1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * NI 16550 UART Driver
4 *
5 * The National Instruments (NI) 16550 is a UART that is compatible with the
6 * TL16C550C and OX16C950B register interfaces, but has additional functions
7 * for RS-485 transceiver control. This driver implements support for the
8 * additional functionality on top of the standard serial8250 core.
9 *
10 * Copyright 2012-2023 National Instruments Corporation
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/bits.h>
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/io.h>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/property.h>
22 #include <linux/serial_core.h>
23 #include <linux/types.h>
24
25 #include "8250.h"
26
27 /* Extra bits in UART_ACR */
28 #define NI16550_ACR_AUTO_DTR_EN BIT(4)
29
30 /* TFS - TX FIFO Size */
31 #define NI16550_TFS_OFFSET 0x0C
32 /* RFS - RX FIFO Size */
33 #define NI16550_RFS_OFFSET 0x0D
34
35 /* PMR - Port Mode Register */
36 #define NI16550_PMR_OFFSET 0x0E
37 /* PMR[1:0] - Port Capabilities */
38 #define NI16550_PMR_CAP_MASK GENMASK(1, 0)
39 #define NI16550_PMR_NOT_IMPL FIELD_PREP(NI16550_PMR_CAP_MASK, 0) /* not implemented */
40 #define NI16550_PMR_CAP_RS232 FIELD_PREP(NI16550_PMR_CAP_MASK, 1) /* RS-232 capable */
41 #define NI16550_PMR_CAP_RS485 FIELD_PREP(NI16550_PMR_CAP_MASK, 2) /* RS-485 capable */
42 #define NI16550_PMR_CAP_DUAL FIELD_PREP(NI16550_PMR_CAP_MASK, 3) /* dual-port */
43 /* PMR[4] - Interface Mode */
44 #define NI16550_PMR_MODE_MASK GENMASK(4, 4)
45 #define NI16550_PMR_MODE_RS232 FIELD_PREP(NI16550_PMR_MODE_MASK, 0) /* currently 232 */
46 #define NI16550_PMR_MODE_RS485 FIELD_PREP(NI16550_PMR_MODE_MASK, 1) /* currently 485 */
47
48 /* PCR - Port Control Register */
49 /*
50 * Wire Mode | Tx enabled? | Rx enabled?
51 * ---------------|----------------------|--------------------------
52 * PCR_RS422 | Always | Always
53 * PCR_ECHO_RS485 | When DTR asserted | Always
54 * PCR_DTR_RS485 | When DTR asserted | Disabled when TX enabled
55 * PCR_AUTO_RS485 | When data in TX FIFO | Disabled when TX enabled
56 */
57 #define NI16550_PCR_OFFSET 0x0F
58 #define NI16550_PCR_WIRE_MODE_MASK GENMASK(1, 0)
59 #define NI16550_PCR_RS422 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 0)
60 #define NI16550_PCR_ECHO_RS485 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 1)
61 #define NI16550_PCR_DTR_RS485 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 2)
62 #define NI16550_PCR_AUTO_RS485 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 3)
63 #define NI16550_PCR_TXVR_ENABLE_BIT BIT(3)
64 #define NI16550_PCR_RS485_TERMINATION_BIT BIT(6)
65
66 /* flags for ni16550_device_info */
67 #define NI_HAS_PMR BIT(0)
68
69 struct ni16550_device_info {
70 u32 uartclk;
71 u8 prescaler;
72 u8 flags;
73 };
74
75 struct ni16550_data {
76 int line;
77 struct clk *clk;
78 };
79
ni16550_enable_transceivers(struct uart_port * port)80 static int ni16550_enable_transceivers(struct uart_port *port)
81 {
82 u8 pcr;
83
84 pcr = port->serial_in(port, NI16550_PCR_OFFSET);
85 pcr |= NI16550_PCR_TXVR_ENABLE_BIT;
86 dev_dbg(port->dev, "enable transceivers: write pcr: 0x%02x\n", pcr);
87 port->serial_out(port, NI16550_PCR_OFFSET, pcr);
88
89 return 0;
90 }
91
ni16550_disable_transceivers(struct uart_port * port)92 static int ni16550_disable_transceivers(struct uart_port *port)
93 {
94 u8 pcr;
95
96 pcr = serial_port_in(port, NI16550_PCR_OFFSET);
97 pcr &= ~NI16550_PCR_TXVR_ENABLE_BIT;
98 dev_dbg(port->dev, "disable transceivers: write pcr: 0x%02x\n", pcr);
99 serial_port_out(port, NI16550_PCR_OFFSET, pcr);
100
101 return 0;
102 }
103
ni16550_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)104 static int ni16550_rs485_config(struct uart_port *port,
105 struct ktermios *termios,
106 struct serial_rs485 *rs485)
107 {
108 struct uart_8250_port *up = container_of(port, struct uart_8250_port, port);
109 u8 pcr;
110
111 pcr = serial_port_in(port, NI16550_PCR_OFFSET);
112 pcr &= ~NI16550_PCR_WIRE_MODE_MASK;
113
114 if ((rs485->flags & SER_RS485_MODE_RS422) ||
115 !(rs485->flags & SER_RS485_ENABLED)) {
116 /* RS-422 */
117 pcr |= NI16550_PCR_RS422;
118 up->acr &= ~NI16550_ACR_AUTO_DTR_EN;
119 } else {
120 /* RS-485 2-wire Auto */
121 pcr |= NI16550_PCR_AUTO_RS485;
122 up->acr |= NI16550_ACR_AUTO_DTR_EN;
123 }
124
125 dev_dbg(port->dev, "config rs485: write pcr: 0x%02x, acr: %02x\n", pcr, up->acr);
126 serial_port_out(port, NI16550_PCR_OFFSET, pcr);
127 serial_icr_write(up, UART_ACR, up->acr);
128
129 return 0;
130 }
131
is_pmr_rs232_mode(struct uart_8250_port * up)132 static bool is_pmr_rs232_mode(struct uart_8250_port *up)
133 {
134 u8 pmr = serial_in(up, NI16550_PMR_OFFSET);
135 u8 pmr_mode = pmr & NI16550_PMR_MODE_MASK;
136 u8 pmr_cap = pmr & NI16550_PMR_CAP_MASK;
137
138 /*
139 * If the PMR is not implemented, then by default NI UARTs are
140 * connected to RS-485 transceivers
141 */
142 if (pmr_cap == NI16550_PMR_NOT_IMPL)
143 return false;
144
145 if (pmr_cap == NI16550_PMR_CAP_DUAL)
146 /*
147 * If the port is dual-mode capable, then read the mode bit
148 * to know the current mode
149 */
150 return pmr_mode == NI16550_PMR_MODE_RS232;
151 /*
152 * If it is not dual-mode capable, then decide based on the
153 * capability
154 */
155 return pmr_cap == NI16550_PMR_CAP_RS232;
156 }
157
ni16550_config_prescaler(struct uart_8250_port * up,u8 prescaler)158 static void ni16550_config_prescaler(struct uart_8250_port *up,
159 u8 prescaler)
160 {
161 /*
162 * Page in the Enhanced Mode Registers
163 * Sets EFR[4] for Enhanced Mode.
164 */
165 u8 lcr_value;
166 u8 efr_value;
167
168 lcr_value = serial_in(up, UART_LCR);
169 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
170
171 efr_value = serial_in(up, UART_EFR);
172 efr_value |= UART_EFR_ECB;
173
174 serial_out(up, UART_EFR, efr_value);
175
176 /* Page out the Enhanced Mode Registers */
177 serial_out(up, UART_LCR, lcr_value);
178
179 /* Set prescaler to CPR register. */
180 serial_out(up, UART_SCR, UART_CPR);
181 serial_out(up, UART_ICR, prescaler);
182 }
183
184 static const struct serial_rs485 ni16550_rs485_supported = {
185 .flags = SER_RS485_ENABLED | SER_RS485_MODE_RS422 | SER_RS485_RTS_ON_SEND |
186 SER_RS485_RTS_AFTER_SEND,
187 /*
188 * delay_rts_* and RX_DURING_TX are not supported.
189 *
190 * RTS_{ON,AFTER}_SEND are supported, but ignored; the transceiver
191 * is connected in only one way and we don't need userspace to tell
192 * us, but want to retain compatibility with applications that do.
193 */
194 };
195
ni16550_rs485_setup(struct uart_port * port)196 static void ni16550_rs485_setup(struct uart_port *port)
197 {
198 port->rs485_config = ni16550_rs485_config;
199 port->rs485_supported = ni16550_rs485_supported;
200 /*
201 * The hardware comes up by default in 2-wire auto mode and we
202 * set the flags to represent that
203 */
204 port->rs485.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
205 }
206
ni16550_port_startup(struct uart_port * port)207 static int ni16550_port_startup(struct uart_port *port)
208 {
209 int ret;
210
211 ret = serial8250_do_startup(port);
212 if (ret)
213 return ret;
214
215 return ni16550_enable_transceivers(port);
216 }
217
ni16550_port_shutdown(struct uart_port * port)218 static void ni16550_port_shutdown(struct uart_port *port)
219 {
220 ni16550_disable_transceivers(port);
221
222 serial8250_do_shutdown(port);
223 }
224
ni16550_get_regs(struct platform_device * pdev,struct uart_port * port)225 static int ni16550_get_regs(struct platform_device *pdev,
226 struct uart_port *port)
227 {
228 struct resource *regs;
229
230 regs = platform_get_mem_or_io(pdev, 0);
231 if (!regs)
232 return dev_err_probe(&pdev->dev, -EINVAL, "no registers defined\n");
233
234 switch (resource_type(regs)) {
235 case IORESOURCE_IO:
236 port->iotype = UPIO_PORT;
237 port->iobase = regs->start;
238
239 return 0;
240 case IORESOURCE_MEM:
241 port->iotype = UPIO_MEM;
242 port->mapbase = regs->start;
243 port->mapsize = resource_size(regs);
244 port->flags |= UPF_IOREMAP;
245
246 return 0;
247 default:
248 return -EINVAL;
249 }
250 }
251
252 /*
253 * Very old implementations don't have the TFS or RFS registers
254 * defined, so we may read all-0s or all-1s. For such devices,
255 * assume a FIFO size of 128.
256 */
ni16550_read_fifo_size(struct uart_8250_port * uart,int reg)257 static u8 ni16550_read_fifo_size(struct uart_8250_port *uart, int reg)
258 {
259 u8 value = serial_in(uart, reg);
260
261 if (value == 0x00 || value == 0xFF)
262 return 128;
263
264 return value;
265 }
266
ni16550_set_mctrl(struct uart_port * port,unsigned int mctrl)267 static void ni16550_set_mctrl(struct uart_port *port, unsigned int mctrl)
268 {
269 struct uart_8250_port *up = up_to_u8250p(port);
270
271 up->mcr |= UART_MCR_CLKSEL;
272 serial8250_do_set_mctrl(port, mctrl);
273 }
274
ni16550_probe(struct platform_device * pdev)275 static int ni16550_probe(struct platform_device *pdev)
276 {
277 struct uart_8250_port *uart __free(kfree) = NULL;
278 const struct ni16550_device_info *info;
279 struct device *dev = &pdev->dev;
280 unsigned int txfifosz, rxfifosz;
281 struct ni16550_data *data;
282 unsigned int prescaler;
283 const char *portmode;
284 bool rs232_property;
285 int ret;
286
287 uart = kzalloc_obj(*uart);
288 if (!uart)
289 return -ENOMEM;
290
291 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
292 if (!data)
293 return -ENOMEM;
294
295 spin_lock_init(&uart->port.lock);
296
297 ret = ni16550_get_regs(pdev, &uart->port);
298 if (ret < 0)
299 return ret;
300
301 /* early setup so that serial_in()/serial_out() work */
302 serial8250_set_defaults(uart);
303
304 info = device_get_match_data(dev);
305
306 uart->port.dev = dev;
307 uart->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_FIXED_TYPE;
308 uart->port.startup = ni16550_port_startup;
309 uart->port.shutdown = ni16550_port_shutdown;
310
311 /*
312 * Hardware instantiation of FIFO sizes are held in registers.
313 */
314 txfifosz = ni16550_read_fifo_size(uart, NI16550_TFS_OFFSET);
315 rxfifosz = ni16550_read_fifo_size(uart, NI16550_RFS_OFFSET);
316
317 dev_dbg(dev, "NI 16550 has TX FIFO size %u, RX FIFO size %u\n",
318 txfifosz, rxfifosz);
319
320 uart->port.type = PORT_16550A;
321 uart->port.fifosize = txfifosz;
322 uart->tx_loadsz = txfifosz;
323 uart->fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10;
324 uart->capabilities = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR;
325
326 /*
327 * Declaration of the base clock frequency can come from one of:
328 * - static declaration in this driver (for older ACPI IDs)
329 * - a "clock-frequency" ACPI
330 */
331 uart->port.uartclk = info->uartclk;
332
333 ret = uart_read_port_properties(&uart->port);
334 if (ret)
335 return ret;
336
337 if (!uart->port.uartclk) {
338 data->clk = devm_clk_get_enabled(dev, NULL);
339 if (!IS_ERR(data->clk))
340 uart->port.uartclk = clk_get_rate(data->clk);
341 }
342
343 if (!uart->port.uartclk)
344 return dev_err_probe(dev, -ENODEV, "unable to determine clock frequency!\n");
345
346 prescaler = info->prescaler;
347 device_property_read_u32(dev, "clock-prescaler", &prescaler);
348 if (prescaler) {
349 uart->port.set_mctrl = ni16550_set_mctrl;
350 ni16550_config_prescaler(uart, (u8)prescaler);
351 }
352
353 /*
354 * The determination of whether or not this is an RS-485 or RS-232 port
355 * can come from the PMR (if present), otherwise we're solely an RS-485
356 * port.
357 *
358 * This is a device-specific property, and there are old devices in the
359 * field using "transceiver" as an ACPI property, so we have to check
360 * for that as well.
361 */
362 if (!device_property_read_string(dev, "transceiver", &portmode)) {
363 rs232_property = strncmp(portmode, "RS-232", 6) == 0;
364
365 dev_dbg(dev, "port is in %s mode (via device property)\n",
366 rs232_property ? "RS-232" : "RS-485");
367 } else if (info->flags & NI_HAS_PMR) {
368 rs232_property = is_pmr_rs232_mode(uart);
369
370 dev_dbg(dev, "port is in %s mode (via PMR)\n",
371 rs232_property ? "RS-232" : "RS-485");
372 } else {
373 rs232_property = 0;
374
375 dev_dbg(dev, "port is fixed as RS-485\n");
376 }
377
378 if (!rs232_property) {
379 /*
380 * Neither the 'transceiver' property nor the PMR indicate
381 * that this is an RS-232 port, so it must be an RS-485 one.
382 */
383 ni16550_rs485_setup(&uart->port);
384 }
385
386 ret = serial8250_register_8250_port(uart);
387 if (ret < 0)
388 return ret;
389 data->line = ret;
390
391 platform_set_drvdata(pdev, data);
392 return 0;
393 }
394
ni16550_remove(struct platform_device * pdev)395 static void ni16550_remove(struct platform_device *pdev)
396 {
397 struct ni16550_data *data = platform_get_drvdata(pdev);
398
399 serial8250_unregister_port(data->line);
400 }
401
402 /* NI 16550 RS-485 Interface */
403 static const struct ni16550_device_info nic7750 = {
404 .uartclk = 33333333,
405 };
406
407 /* NI CVS-145x RS-485 Interface */
408 static const struct ni16550_device_info nic7772 = {
409 .uartclk = 1843200,
410 .flags = NI_HAS_PMR,
411 };
412
413 /* NI cRIO-904x RS-485 Interface */
414 static const struct ni16550_device_info nic792b = {
415 /* Sets UART clock rate to 22.222 MHz with 1.125 prescale */
416 .uartclk = 22222222,
417 .prescaler = 0x09,
418 };
419
420 /* NI sbRIO 96x8 RS-232/485 Interfaces */
421 static const struct ni16550_device_info nic7a69 = {
422 /* Set UART clock rate to 29.629 MHz with 1.125 prescale */
423 .uartclk = 29629629,
424 .prescaler = 0x09,
425 };
426
427 static const struct acpi_device_id ni16550_acpi_match[] = {
428 { "NIC7750", (kernel_ulong_t)&nic7750 },
429 { "NIC7772", (kernel_ulong_t)&nic7772 },
430 { "NIC792B", (kernel_ulong_t)&nic792b },
431 { "NIC7A69", (kernel_ulong_t)&nic7a69 },
432 { }
433 };
434 MODULE_DEVICE_TABLE(acpi, ni16550_acpi_match);
435
436 static struct platform_driver ni16550_driver = {
437 .driver = {
438 .name = "ni16550",
439 .acpi_match_table = ni16550_acpi_match,
440 },
441 .probe = ni16550_probe,
442 .remove = ni16550_remove,
443 };
444
445 module_platform_driver(ni16550_driver);
446
447 MODULE_AUTHOR("Emerson Electric Co.");
448 MODULE_DESCRIPTION("NI 16550 Driver");
449 MODULE_LICENSE("GPL");
450