1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/types.h>
30 #include <machine/npx.h>
31
32 #include "fenv.h"
33
34 const fenv_t __fe_dfl_env = {
35 __INITIAL_NPXCW__,
36 0x0000,
37 0x0000,
38 0x1f80,
39 0xffffffff,
40 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
41 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff }
42 };
43
44 enum __sse_support __has_sse =
45 #ifdef __SSE__
46 __SSE_YES;
47 #else
48 __SSE_UNK;
49 #endif
50
51 #define getfl(x) __asm __volatile("pushfl\n\tpopl %0" : "=mr" (*(x)))
52 #define setfl(x) __asm __volatile("pushl %0\n\tpopfl" : : "g" (x))
53 #define cpuid_dx(x) __asm __volatile("pushl %%ebx\n\tmovl $1, %%eax\n\t" \
54 "cpuid\n\tpopl %%ebx" \
55 : "=d" (*(x)) : : "eax", "ecx")
56
57 /*
58 * Test for SSE support on this processor. We need to do this because
59 * we need to use ldmxcsr/stmxcsr to get correct results if any part
60 * of the program was compiled to use SSE floating-point, but we can't
61 * use SSE on older processors.
62 */
63 int
__test_sse(void)64 __test_sse(void)
65 {
66 int flag, nflag;
67 int dx_features;
68
69 /* Am I a 486? */
70 getfl(&flag);
71 nflag = flag ^ 0x200000;
72 setfl(nflag);
73 getfl(&nflag);
74 if (flag != nflag) {
75 /* Not a 486, so CPUID should work. */
76 cpuid_dx(&dx_features);
77 if (dx_features & 0x2000000) {
78 __has_sse = __SSE_YES;
79 return (1);
80 }
81 }
82 __has_sse = __SSE_NO;
83 return (0);
84 }
85
86 int
87 (feclearexcept)(int excepts)
88 {
89 return (__feclearexcept_int(excepts));
90 }
91
92 int
93 (fegetexceptflag)(fexcept_t *flagp, int excepts)
94 {
95 return (__fegetexceptflag_int(flagp, excepts));
96 }
97
98 int
fesetexceptflag(const fexcept_t * flagp,int excepts)99 fesetexceptflag(const fexcept_t *flagp, int excepts)
100 {
101 fenv_t env;
102 __uint32_t mxcsr;
103
104 __fnstenv(&env);
105 env.__status &= ~excepts;
106 env.__status |= *flagp & excepts;
107 __fldenv(&env);
108
109 if (__HAS_SSE()) {
110 __stmxcsr(&mxcsr);
111 mxcsr &= ~excepts;
112 mxcsr |= *flagp & excepts;
113 __ldmxcsr(&mxcsr);
114 }
115
116 return (0);
117 }
118
119 int
feraiseexcept(int excepts)120 feraiseexcept(int excepts)
121 {
122 fexcept_t ex = excepts;
123
124 fesetexceptflag(&ex, excepts);
125 __fwait();
126 return (0);
127 }
128
129 int
130 (fetestexcept)(int excepts)
131 {
132 return (__fetestexcept_int(excepts));
133 }
134
135 int
136 (fegetround)(void)
137 {
138 return (__fegetround_int());
139 }
140
141 int
142 (fesetround)(int round)
143 {
144 return (__fesetround_int(round));
145 }
146
147 int
fegetenv(fenv_t * envp)148 fegetenv(fenv_t *envp)
149 {
150 __uint32_t mxcsr;
151
152 __fnstenv(envp);
153 /*
154 * fnstenv masks all exceptions, so we need to restore
155 * the old control word to avoid this side effect.
156 */
157 __fldcw(&envp->__control);
158 if (__HAS_SSE()) {
159 __stmxcsr(&mxcsr);
160 __set_mxcsr(*envp, mxcsr);
161 }
162 return (0);
163 }
164
165 int
feholdexcept(fenv_t * envp)166 feholdexcept(fenv_t *envp)
167 {
168 __uint32_t mxcsr;
169
170 __fnstenv(envp);
171 __fnclex();
172 if (__HAS_SSE()) {
173 __stmxcsr(&mxcsr);
174 __set_mxcsr(*envp, mxcsr);
175 mxcsr &= ~FE_ALL_EXCEPT;
176 mxcsr |= FE_ALL_EXCEPT << _SSE_EMASK_SHIFT;
177 __ldmxcsr(&mxcsr);
178 }
179 return (0);
180 }
181
182 int
183 (fesetenv)(const fenv_t *envp)
184 {
185 return (__fesetenv_int(envp));
186 }
187
188 int
feupdateenv(const fenv_t * envp)189 feupdateenv(const fenv_t *envp)
190 {
191 __uint32_t mxcsr;
192 __uint16_t status;
193
194 __fnstsw(&status);
195 if (__HAS_SSE())
196 __stmxcsr(&mxcsr);
197 else
198 mxcsr = 0;
199 fesetenv(envp);
200 feraiseexcept((mxcsr | status) & FE_ALL_EXCEPT);
201 return (0);
202 }
203
204 int
__feenableexcept(int mask)205 __feenableexcept(int mask)
206 {
207 __uint32_t mxcsr, omask;
208 __uint16_t control;
209
210 mask &= FE_ALL_EXCEPT;
211 __fnstcw(&control);
212 if (__HAS_SSE())
213 __stmxcsr(&mxcsr);
214 else
215 mxcsr = 0;
216 omask = ~(control | mxcsr >> _SSE_EMASK_SHIFT) & FE_ALL_EXCEPT;
217 control &= ~mask;
218 __fldcw(&control);
219 if (__HAS_SSE()) {
220 mxcsr &= ~(mask << _SSE_EMASK_SHIFT);
221 __ldmxcsr(&mxcsr);
222 }
223 return (omask);
224 }
225
226 int
__fedisableexcept(int mask)227 __fedisableexcept(int mask)
228 {
229 __uint32_t mxcsr, omask;
230 __uint16_t control;
231
232 mask &= FE_ALL_EXCEPT;
233 __fnstcw(&control);
234 if (__HAS_SSE())
235 __stmxcsr(&mxcsr);
236 else
237 mxcsr = 0;
238 omask = ~(control | mxcsr >> _SSE_EMASK_SHIFT) & FE_ALL_EXCEPT;
239 control |= mask;
240 __fldcw(&control);
241 if (__HAS_SSE()) {
242 mxcsr |= mask << _SSE_EMASK_SHIFT;
243 __ldmxcsr(&mxcsr);
244 }
245 return (omask);
246 }
247
248 __weak_reference(__feenableexcept, feenableexcept);
249 __weak_reference(__fedisableexcept, fedisableexcept);
250