1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #include <linux/ieee80211.h>
8 #include <linux/kernel.h>
9 #include <linux/skbuff.h>
10 #include <crypto/hash.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "debugfs_htt_stats.h"
14 #include "debugfs_sta.h"
15 #include "hal_desc.h"
16 #include "hw.h"
17 #include "dp_rx.h"
18 #include "hal_rx.h"
19 #include "dp_tx.h"
20 #include "peer.h"
21
22 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23
24 static inline
ath11k_dp_rx_h_80211_hdr(struct ath11k_base * ab,struct hal_rx_desc * desc)25 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
26 {
27 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
28 }
29
30 static inline
ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base * ab,struct hal_rx_desc * desc)31 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
32 struct hal_rx_desc *desc)
33 {
34 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
35 return HAL_ENCRYPT_TYPE_OPEN;
36
37 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
38 }
39
ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base * ab,struct hal_rx_desc * desc)40 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
41 struct hal_rx_desc *desc)
42 {
43 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
44 }
45
46 static inline
ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base * ab,struct hal_rx_desc * desc)47 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab,
48 struct hal_rx_desc *desc)
49 {
50 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc);
51 }
52
53 static inline
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base * ab,struct hal_rx_desc * desc)54 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
55 struct hal_rx_desc *desc)
56 {
57 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
58 }
59
60 static inline
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)61 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
62 struct hal_rx_desc *desc)
63 {
64 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
65 }
66
ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)67 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
68 struct hal_rx_desc *desc)
69 {
70 return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
71 }
72
ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base * ab,struct sk_buff * skb)73 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
74 struct sk_buff *skb)
75 {
76 struct ieee80211_hdr *hdr;
77
78 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
79 return ieee80211_has_morefrags(hdr->frame_control);
80 }
81
ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base * ab,struct sk_buff * skb)82 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
83 struct sk_buff *skb)
84 {
85 struct ieee80211_hdr *hdr;
86
87 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
88 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
89 }
90
ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base * ab,struct hal_rx_desc * desc)91 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
92 struct hal_rx_desc *desc)
93 {
94 return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
95 }
96
ath11k_dp_rx_get_attention(struct ath11k_base * ab,struct hal_rx_desc * desc)97 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
98 struct hal_rx_desc *desc)
99 {
100 return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
101 }
102
ath11k_dp_rx_h_attn_msdu_done(struct rx_attention * attn)103 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
104 {
105 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
106 __le32_to_cpu(attn->info2));
107 }
108
ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention * attn)109 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
110 {
111 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
112 __le32_to_cpu(attn->info1));
113 }
114
ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention * attn)115 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
116 {
117 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
118 __le32_to_cpu(attn->info1));
119 }
120
ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention * attn)121 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
122 {
123 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
124 __le32_to_cpu(attn->info2)) ==
125 RX_DESC_DECRYPT_STATUS_CODE_OK);
126 }
127
ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention * attn)128 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
129 {
130 u32 info = __le32_to_cpu(attn->info1);
131 u32 errmap = 0;
132
133 if (info & RX_ATTENTION_INFO1_FCS_ERR)
134 errmap |= DP_RX_MPDU_ERR_FCS;
135
136 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
137 errmap |= DP_RX_MPDU_ERR_DECRYPT;
138
139 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
140 errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
141
142 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
143 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
144
145 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
146 errmap |= DP_RX_MPDU_ERR_OVERFLOW;
147
148 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
149 errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
150
151 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
152 errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
153
154 return errmap;
155 }
156
ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base * ab,struct hal_rx_desc * desc)157 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
158 struct hal_rx_desc *desc)
159 {
160 struct rx_attention *rx_attention;
161 u32 errmap;
162
163 rx_attention = ath11k_dp_rx_get_attention(ab, desc);
164 errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
165
166 return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
167 }
168
ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc)169 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
170 struct hal_rx_desc *desc)
171 {
172 return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
173 }
174
ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base * ab,struct hal_rx_desc * desc)175 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
176 struct hal_rx_desc *desc)
177 {
178 return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
179 }
180
ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base * ab,struct hal_rx_desc * desc)181 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
182 struct hal_rx_desc *desc)
183 {
184 return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
185 }
186
ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base * ab,struct hal_rx_desc * desc)187 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
188 struct hal_rx_desc *desc)
189 {
190 return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
191 }
192
ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base * ab,struct hal_rx_desc * desc)193 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
194 struct hal_rx_desc *desc)
195 {
196 return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
197 }
198
ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base * ab,struct hal_rx_desc * desc)199 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
200 struct hal_rx_desc *desc)
201 {
202 return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
203 }
204
ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base * ab,struct hal_rx_desc * desc)205 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
206 struct hal_rx_desc *desc)
207 {
208 return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
209 }
210
ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base * ab,struct hal_rx_desc * desc)211 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
212 struct hal_rx_desc *desc)
213 {
214 return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
215 }
216
ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base * ab,struct hal_rx_desc * desc)217 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
218 struct hal_rx_desc *desc)
219 {
220 return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
221 }
222
ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base * ab,struct hal_rx_desc * desc)223 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
224 struct hal_rx_desc *desc)
225 {
226 return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
227 }
228
ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)229 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
230 struct hal_rx_desc *desc)
231 {
232 return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
233 }
234
ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)235 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
236 struct hal_rx_desc *desc)
237 {
238 return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
239 }
240
ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)241 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
242 struct hal_rx_desc *fdesc,
243 struct hal_rx_desc *ldesc)
244 {
245 ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
246 }
247
ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention * attn)248 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
249 {
250 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
251 __le32_to_cpu(attn->info1));
252 }
253
ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)254 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
255 struct hal_rx_desc *rx_desc)
256 {
257 u8 *rx_pkt_hdr;
258
259 rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
260
261 return rx_pkt_hdr;
262 }
263
ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)264 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
265 struct hal_rx_desc *rx_desc)
266 {
267 u32 tlv_tag;
268
269 tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
270
271 return tlv_tag == HAL_RX_MPDU_START;
272 }
273
ath11k_dp_rxdesc_get_ppduid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)274 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
275 struct hal_rx_desc *rx_desc)
276 {
277 return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
278 }
279
ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc,u16 len)280 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
281 struct hal_rx_desc *desc,
282 u16 len)
283 {
284 ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
285 }
286
ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base * ab,struct hal_rx_desc * desc)287 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
288 struct hal_rx_desc *desc)
289 {
290 struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
291
292 return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
293 (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
294 __le32_to_cpu(attn->info1)));
295 }
296
ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)297 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
298 struct hal_rx_desc *desc)
299 {
300 return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
301 }
302
ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base * ab,struct hal_rx_desc * desc)303 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
304 struct hal_rx_desc *desc)
305 {
306 return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
307 }
308
ath11k_dp_service_mon_ring(struct timer_list * t)309 static void ath11k_dp_service_mon_ring(struct timer_list *t)
310 {
311 struct ath11k_base *ab = timer_container_of(ab, t, mon_reap_timer);
312 int i;
313
314 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
315 ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
316
317 mod_timer(&ab->mon_reap_timer, jiffies +
318 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
319 }
320
ath11k_dp_purge_mon_ring(struct ath11k_base * ab)321 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
322 {
323 int i, reaped = 0;
324 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
325
326 do {
327 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
328 reaped += ath11k_dp_rx_process_mon_rings(ab, i,
329 NULL,
330 DP_MON_SERVICE_BUDGET);
331
332 /* nothing more to reap */
333 if (reaped < DP_MON_SERVICE_BUDGET)
334 return 0;
335
336 } while (time_before(jiffies, timeout));
337
338 ath11k_warn(ab, "dp mon ring purge timeout");
339
340 return -ETIMEDOUT;
341 }
342
343 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)344 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
345 struct dp_rxdma_ring *rx_ring,
346 int req_entries,
347 enum hal_rx_buf_return_buf_manager mgr)
348 {
349 struct hal_srng *srng;
350 u32 *desc;
351 struct sk_buff *skb;
352 int num_free;
353 int num_remain;
354 int buf_id;
355 u32 cookie;
356 dma_addr_t paddr;
357
358 req_entries = min(req_entries, rx_ring->bufs_max);
359
360 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
361
362 spin_lock_bh(&srng->lock);
363
364 ath11k_hal_srng_access_begin(ab, srng);
365
366 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
367 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
368 req_entries = num_free;
369
370 req_entries = min(num_free, req_entries);
371 num_remain = req_entries;
372
373 while (num_remain > 0) {
374 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
375 DP_RX_BUFFER_ALIGN_SIZE);
376 if (!skb)
377 break;
378
379 if (!IS_ALIGNED((unsigned long)skb->data,
380 DP_RX_BUFFER_ALIGN_SIZE)) {
381 skb_pull(skb,
382 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
383 skb->data);
384 }
385
386 paddr = dma_map_single(ab->dev, skb->data,
387 skb->len + skb_tailroom(skb),
388 DMA_FROM_DEVICE);
389 if (dma_mapping_error(ab->dev, paddr))
390 goto fail_free_skb;
391
392 spin_lock_bh(&rx_ring->idr_lock);
393 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
394 (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
395 spin_unlock_bh(&rx_ring->idr_lock);
396 if (buf_id <= 0)
397 goto fail_dma_unmap;
398
399 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
400 if (!desc)
401 goto fail_idr_remove;
402
403 ATH11K_SKB_RXCB(skb)->paddr = paddr;
404
405 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
406 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
407
408 num_remain--;
409
410 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
411 }
412
413 ath11k_hal_srng_access_end(ab, srng);
414
415 spin_unlock_bh(&srng->lock);
416
417 return req_entries - num_remain;
418
419 fail_idr_remove:
420 spin_lock_bh(&rx_ring->idr_lock);
421 idr_remove(&rx_ring->bufs_idr, buf_id);
422 spin_unlock_bh(&rx_ring->idr_lock);
423 fail_dma_unmap:
424 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
425 DMA_FROM_DEVICE);
426 fail_free_skb:
427 dev_kfree_skb_any(skb);
428
429 ath11k_hal_srng_access_end(ab, srng);
430
431 spin_unlock_bh(&srng->lock);
432
433 return req_entries - num_remain;
434 }
435
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)436 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
437 struct dp_rxdma_ring *rx_ring)
438 {
439 struct sk_buff *skb;
440 int buf_id;
441
442 spin_lock_bh(&rx_ring->idr_lock);
443 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
444 idr_remove(&rx_ring->bufs_idr, buf_id);
445 /* TODO: Understand where internal driver does this dma_unmap
446 * of rxdma_buffer.
447 */
448 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
449 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
450 dev_kfree_skb_any(skb);
451 }
452
453 idr_destroy(&rx_ring->bufs_idr);
454 spin_unlock_bh(&rx_ring->idr_lock);
455
456 return 0;
457 }
458
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)459 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
460 {
461 struct ath11k_pdev_dp *dp = &ar->dp;
462 struct ath11k_base *ab = ar->ab;
463 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
464 int i;
465
466 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
467
468 rx_ring = &dp->rxdma_mon_buf_ring;
469 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
470
471 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
472 rx_ring = &dp->rx_mon_status_refill_ring[i];
473 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
474 }
475
476 return 0;
477 }
478
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)479 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
480 struct dp_rxdma_ring *rx_ring,
481 u32 ringtype)
482 {
483 struct ath11k_pdev_dp *dp = &ar->dp;
484 int num_entries;
485
486 num_entries = rx_ring->refill_buf_ring.size /
487 ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
488
489 rx_ring->bufs_max = num_entries;
490 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
491 ar->ab->hw_params.hal_params->rx_buf_rbm);
492 return 0;
493 }
494
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)495 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
496 {
497 struct ath11k_pdev_dp *dp = &ar->dp;
498 struct ath11k_base *ab = ar->ab;
499 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
500 int i;
501
502 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
503
504 if (ar->ab->hw_params.rxdma1_enable) {
505 rx_ring = &dp->rxdma_mon_buf_ring;
506 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
507 }
508
509 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
510 rx_ring = &dp->rx_mon_status_refill_ring[i];
511 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
512 }
513
514 return 0;
515 }
516
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)517 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
518 {
519 struct ath11k_pdev_dp *dp = &ar->dp;
520 struct ath11k_base *ab = ar->ab;
521 int i;
522
523 ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
524
525 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
526 if (ab->hw_params.rx_mac_buf_ring)
527 ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
528
529 ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
530 ath11k_dp_srng_cleanup(ab,
531 &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
532 }
533
534 ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
535 }
536
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)537 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
538 {
539 struct ath11k_dp *dp = &ab->dp;
540 int i;
541
542 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
543 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
544 }
545
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)546 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
547 {
548 struct ath11k_dp *dp = &ab->dp;
549 int ret;
550 int i;
551
552 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
553 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
554 HAL_REO_DST, i, 0,
555 DP_REO_DST_RING_SIZE);
556 if (ret) {
557 ath11k_warn(ab, "failed to setup reo_dst_ring\n");
558 goto err_reo_cleanup;
559 }
560 }
561
562 return 0;
563
564 err_reo_cleanup:
565 ath11k_dp_pdev_reo_cleanup(ab);
566
567 return ret;
568 }
569
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)570 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
571 {
572 struct ath11k_pdev_dp *dp = &ar->dp;
573 struct ath11k_base *ab = ar->ab;
574 struct dp_srng *srng = NULL;
575 int i;
576 int ret;
577
578 ret = ath11k_dp_srng_setup(ar->ab,
579 &dp->rx_refill_buf_ring.refill_buf_ring,
580 HAL_RXDMA_BUF, 0,
581 dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
582 if (ret) {
583 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
584 return ret;
585 }
586
587 if (ar->ab->hw_params.rx_mac_buf_ring) {
588 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
589 ret = ath11k_dp_srng_setup(ar->ab,
590 &dp->rx_mac_buf_ring[i],
591 HAL_RXDMA_BUF, 1,
592 dp->mac_id + i, 1024);
593 if (ret) {
594 ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
595 i);
596 return ret;
597 }
598 }
599 }
600
601 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
602 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
603 HAL_RXDMA_DST, 0, dp->mac_id + i,
604 DP_RXDMA_ERR_DST_RING_SIZE);
605 if (ret) {
606 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
607 return ret;
608 }
609 }
610
611 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
612 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
613 ret = ath11k_dp_srng_setup(ar->ab,
614 srng,
615 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
616 DP_RXDMA_MON_STATUS_RING_SIZE);
617 if (ret) {
618 ath11k_warn(ar->ab,
619 "failed to setup rx_mon_status_refill_ring %d\n", i);
620 return ret;
621 }
622 }
623
624 /* if rxdma1_enable is false, then it doesn't need
625 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
626 * and rxdma_mon_desc_ring.
627 * init reap timer for QCA6390.
628 */
629 if (!ar->ab->hw_params.rxdma1_enable) {
630 //init mon status buffer reap timer
631 timer_setup(&ar->ab->mon_reap_timer,
632 ath11k_dp_service_mon_ring, 0);
633 return 0;
634 }
635
636 ret = ath11k_dp_srng_setup(ar->ab,
637 &dp->rxdma_mon_buf_ring.refill_buf_ring,
638 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
639 DP_RXDMA_MONITOR_BUF_RING_SIZE);
640 if (ret) {
641 ath11k_warn(ar->ab,
642 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
643 return ret;
644 }
645
646 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
647 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
648 DP_RXDMA_MONITOR_DST_RING_SIZE);
649 if (ret) {
650 ath11k_warn(ar->ab,
651 "failed to setup HAL_RXDMA_MONITOR_DST\n");
652 return ret;
653 }
654
655 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
656 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
657 DP_RXDMA_MONITOR_DESC_RING_SIZE);
658 if (ret) {
659 ath11k_warn(ar->ab,
660 "failed to setup HAL_RXDMA_MONITOR_DESC\n");
661 return ret;
662 }
663
664 return 0;
665 }
666
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)667 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
668 {
669 struct ath11k_dp *dp = &ab->dp;
670 struct dp_reo_cmd *cmd, *tmp;
671 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
672 struct dp_rx_tid *rx_tid;
673
674 spin_lock_bh(&dp->reo_cmd_lock);
675 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
676 list_del(&cmd->list);
677 rx_tid = &cmd->data;
678 if (rx_tid->vaddr_unaligned) {
679 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
680 rx_tid->vaddr_unaligned,
681 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
682 rx_tid->vaddr_unaligned = NULL;
683 }
684 kfree(cmd);
685 }
686
687 list_for_each_entry_safe(cmd_cache, tmp_cache,
688 &dp->reo_cmd_cache_flush_list, list) {
689 list_del(&cmd_cache->list);
690 dp->reo_cmd_cache_flush_count--;
691 rx_tid = &cmd_cache->data;
692 if (rx_tid->vaddr_unaligned) {
693 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
694 rx_tid->vaddr_unaligned,
695 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
696 rx_tid->vaddr_unaligned = NULL;
697 }
698 kfree(cmd_cache);
699 }
700 spin_unlock_bh(&dp->reo_cmd_lock);
701 }
702
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)703 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
704 enum hal_reo_cmd_status status)
705 {
706 struct dp_rx_tid *rx_tid = ctx;
707
708 if (status != HAL_REO_CMD_SUCCESS)
709 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
710 rx_tid->tid, status);
711 if (rx_tid->vaddr_unaligned) {
712 dma_free_noncoherent(dp->ab->dev, rx_tid->unaligned_size,
713 rx_tid->vaddr_unaligned,
714 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
715 rx_tid->vaddr_unaligned = NULL;
716 }
717 }
718
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)719 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
720 struct dp_rx_tid *rx_tid)
721 {
722 struct ath11k_hal_reo_cmd cmd = {};
723 unsigned long tot_desc_sz, desc_sz;
724 int ret;
725
726 tot_desc_sz = rx_tid->size;
727 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
728
729 while (tot_desc_sz > desc_sz) {
730 tot_desc_sz -= desc_sz;
731 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
732 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
733 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
734 HAL_REO_CMD_FLUSH_CACHE, &cmd,
735 NULL);
736 if (ret)
737 ath11k_warn(ab,
738 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
739 rx_tid->tid, ret);
740 }
741
742 memset(&cmd, 0, sizeof(cmd));
743 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
744 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
745 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
746 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
747 HAL_REO_CMD_FLUSH_CACHE,
748 &cmd, ath11k_dp_reo_cmd_free);
749 if (ret) {
750 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
751 rx_tid->tid, ret);
752 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
753 rx_tid->vaddr_unaligned,
754 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
755 rx_tid->vaddr_unaligned = NULL;
756 }
757 }
758
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)759 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
760 enum hal_reo_cmd_status status)
761 {
762 struct ath11k_base *ab = dp->ab;
763 struct dp_rx_tid *rx_tid = ctx;
764 struct dp_reo_cache_flush_elem *elem, *tmp;
765
766 if (status == HAL_REO_CMD_DRAIN) {
767 goto free_desc;
768 } else if (status != HAL_REO_CMD_SUCCESS) {
769 /* Shouldn't happen! Cleanup in case of other failure? */
770 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
771 rx_tid->tid, status);
772 return;
773 }
774
775 elem = kzalloc_obj(*elem, GFP_ATOMIC);
776 if (!elem)
777 goto free_desc;
778
779 elem->ts = jiffies;
780 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
781
782 spin_lock_bh(&dp->reo_cmd_lock);
783 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
784 dp->reo_cmd_cache_flush_count++;
785
786 /* Flush and invalidate aged REO desc from HW cache */
787 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
788 list) {
789 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
790 time_after(jiffies, elem->ts +
791 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
792 list_del(&elem->list);
793 dp->reo_cmd_cache_flush_count--;
794 spin_unlock_bh(&dp->reo_cmd_lock);
795
796 ath11k_dp_reo_cache_flush(ab, &elem->data);
797 kfree(elem);
798 spin_lock_bh(&dp->reo_cmd_lock);
799 }
800 }
801 spin_unlock_bh(&dp->reo_cmd_lock);
802
803 return;
804 free_desc:
805 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
806 rx_tid->vaddr_unaligned,
807 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
808 rx_tid->vaddr_unaligned = NULL;
809 }
810
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)811 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
812 struct ath11k_peer *peer, u8 tid)
813 {
814 struct ath11k_hal_reo_cmd cmd = {};
815 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
816 int ret;
817
818 if (!rx_tid->active)
819 return;
820
821 rx_tid->active = false;
822
823 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
824 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
825 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
826 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
827 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
828 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
829 ath11k_dp_rx_tid_del_func);
830 if (ret) {
831 if (ret != -ESHUTDOWN)
832 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
833 tid, ret);
834 dma_free_noncoherent(ar->ab->dev, rx_tid->unaligned_size,
835 rx_tid->vaddr_unaligned,
836 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
837 rx_tid->vaddr_unaligned = NULL;
838 }
839
840 rx_tid->paddr = 0;
841 rx_tid->paddr_unaligned = 0;
842 rx_tid->size = 0;
843 rx_tid->unaligned_size = 0;
844 }
845
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)846 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
847 u32 *link_desc,
848 enum hal_wbm_rel_bm_act action)
849 {
850 struct ath11k_dp *dp = &ab->dp;
851 struct hal_srng *srng;
852 u32 *desc;
853 int ret = 0;
854
855 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
856
857 spin_lock_bh(&srng->lock);
858
859 ath11k_hal_srng_access_begin(ab, srng);
860
861 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
862 if (!desc) {
863 ret = -ENOBUFS;
864 goto exit;
865 }
866
867 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
868 action);
869
870 exit:
871 ath11k_hal_srng_access_end(ab, srng);
872
873 spin_unlock_bh(&srng->lock);
874
875 return ret;
876 }
877
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)878 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
879 {
880 struct ath11k_base *ab = rx_tid->ab;
881
882 lockdep_assert_held(&ab->base_lock);
883
884 if (rx_tid->dst_ring_desc) {
885 if (rel_link_desc)
886 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
887 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
888 kfree(rx_tid->dst_ring_desc);
889 rx_tid->dst_ring_desc = NULL;
890 }
891
892 rx_tid->cur_sn = 0;
893 rx_tid->last_frag_no = 0;
894 rx_tid->rx_frag_bitmap = 0;
895 __skb_queue_purge(&rx_tid->rx_frags);
896 }
897
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)898 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
899 {
900 struct dp_rx_tid *rx_tid;
901 int i;
902
903 lockdep_assert_held(&ar->ab->base_lock);
904
905 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
906 rx_tid = &peer->rx_tid[i];
907
908 spin_unlock_bh(&ar->ab->base_lock);
909 timer_delete_sync(&rx_tid->frag_timer);
910 spin_lock_bh(&ar->ab->base_lock);
911
912 ath11k_dp_rx_frags_cleanup(rx_tid, true);
913 }
914 }
915
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)916 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
917 {
918 struct dp_rx_tid *rx_tid;
919 int i;
920
921 lockdep_assert_held(&ar->ab->base_lock);
922
923 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
924 rx_tid = &peer->rx_tid[i];
925
926 ath11k_peer_rx_tid_delete(ar, peer, i);
927 ath11k_dp_rx_frags_cleanup(rx_tid, true);
928
929 spin_unlock_bh(&ar->ab->base_lock);
930 timer_delete_sync(&rx_tid->frag_timer);
931 spin_lock_bh(&ar->ab->base_lock);
932 }
933 }
934
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)935 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
936 struct ath11k_peer *peer,
937 struct dp_rx_tid *rx_tid,
938 u32 ba_win_sz, u16 ssn,
939 bool update_ssn)
940 {
941 struct ath11k_hal_reo_cmd cmd = {};
942 int ret;
943
944 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
945 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
946 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
947 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
948 cmd.ba_window_size = ba_win_sz;
949
950 if (update_ssn) {
951 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
952 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
953 }
954
955 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
956 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
957 NULL);
958 if (ret) {
959 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
960 rx_tid->tid, ret);
961 return ret;
962 }
963
964 rx_tid->ba_win_sz = ba_win_sz;
965
966 return 0;
967 }
968
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)969 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
970 const u8 *peer_mac, int vdev_id, u8 tid)
971 {
972 struct ath11k_peer *peer;
973 struct dp_rx_tid *rx_tid;
974
975 spin_lock_bh(&ab->base_lock);
976
977 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
978 if (!peer) {
979 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
980 goto unlock_exit;
981 }
982
983 rx_tid = &peer->rx_tid[tid];
984 if (!rx_tid->active)
985 goto unlock_exit;
986
987 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size, rx_tid->vaddr_unaligned,
988 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
989 rx_tid->vaddr_unaligned = NULL;
990
991 rx_tid->active = false;
992
993 unlock_exit:
994 spin_unlock_bh(&ab->base_lock);
995 }
996
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)997 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
998 u8 tid, u32 ba_win_sz, u16 ssn,
999 enum hal_pn_type pn_type)
1000 {
1001 struct ath11k_base *ab = ar->ab;
1002 struct ath11k_peer *peer;
1003 struct dp_rx_tid *rx_tid;
1004 u32 hw_desc_sz, *vaddr;
1005 void *vaddr_unaligned;
1006 dma_addr_t paddr;
1007 int ret;
1008
1009 spin_lock_bh(&ab->base_lock);
1010
1011 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1012 if (!peer) {
1013 ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n",
1014 peer_mac);
1015 spin_unlock_bh(&ab->base_lock);
1016 return -ENOENT;
1017 }
1018
1019 rx_tid = &peer->rx_tid[tid];
1020 /* Update the tid queue if it is already setup */
1021 if (rx_tid->active) {
1022 paddr = rx_tid->paddr;
1023 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1024 ba_win_sz, ssn, true);
1025 spin_unlock_bh(&ab->base_lock);
1026 if (ret) {
1027 ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d",
1028 peer_mac, tid, ret);
1029 return ret;
1030 }
1031
1032 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1033 peer_mac, paddr,
1034 tid, 1, ba_win_sz);
1035 if (ret)
1036 ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n",
1037 peer_mac, tid, ret);
1038 return ret;
1039 }
1040
1041 rx_tid->tid = tid;
1042
1043 rx_tid->ba_win_sz = ba_win_sz;
1044
1045 /* TODO: Optimize the memory allocation for qos tid based on
1046 * the actual BA window size in REO tid update path.
1047 */
1048 if (tid == HAL_DESC_REO_NON_QOS_TID)
1049 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1050 else
1051 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1052
1053 rx_tid->unaligned_size = hw_desc_sz + HAL_LINK_DESC_ALIGN - 1;
1054 vaddr_unaligned = dma_alloc_noncoherent(ab->dev, rx_tid->unaligned_size, &paddr,
1055 DMA_BIDIRECTIONAL, GFP_ATOMIC);
1056 if (!vaddr_unaligned) {
1057 spin_unlock_bh(&ab->base_lock);
1058 return -ENOMEM;
1059 }
1060
1061 rx_tid->vaddr_unaligned = vaddr_unaligned;
1062 vaddr = PTR_ALIGN(vaddr_unaligned, HAL_LINK_DESC_ALIGN);
1063 rx_tid->paddr_unaligned = paddr;
1064 rx_tid->paddr = rx_tid->paddr_unaligned + ((unsigned long)vaddr -
1065 (unsigned long)rx_tid->vaddr_unaligned);
1066 ath11k_hal_reo_qdesc_setup(vaddr, tid, ba_win_sz, ssn, pn_type);
1067 rx_tid->size = hw_desc_sz;
1068 rx_tid->active = true;
1069
1070 /* After dma_alloc_noncoherent, vaddr is being modified for reo qdesc setup.
1071 * Since these changes are not reflected in the device, driver now needs to
1072 * explicitly call dma_sync_single_for_device.
1073 */
1074 dma_sync_single_for_device(ab->dev, rx_tid->paddr,
1075 rx_tid->size,
1076 DMA_TO_DEVICE);
1077 spin_unlock_bh(&ab->base_lock);
1078
1079 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, rx_tid->paddr,
1080 tid, 1, ba_win_sz);
1081 if (ret) {
1082 ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n",
1083 peer_mac, tid, ret);
1084 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1085 }
1086
1087 return ret;
1088 }
1089
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1090 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1091 struct ieee80211_ampdu_params *params)
1092 {
1093 struct ath11k_base *ab = ar->ab;
1094 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1095 int vdev_id = arsta->arvif->vdev_id;
1096 int ret;
1097
1098 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1099 params->tid, params->buf_size,
1100 params->ssn, arsta->pn_type);
1101 if (ret)
1102 ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1103
1104 return ret;
1105 }
1106
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1107 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1108 struct ieee80211_ampdu_params *params)
1109 {
1110 struct ath11k_base *ab = ar->ab;
1111 struct ath11k_peer *peer;
1112 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1113 struct dp_rx_tid *rx_tid;
1114 int vdev_id = arsta->arvif->vdev_id;
1115 int ret;
1116
1117 spin_lock_bh(&ab->base_lock);
1118
1119 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1120 if (!peer) {
1121 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1122 spin_unlock_bh(&ab->base_lock);
1123 return -ENOENT;
1124 }
1125
1126 rx_tid = &peer->rx_tid[params->tid];
1127
1128 if (!rx_tid->active) {
1129 spin_unlock_bh(&ab->base_lock);
1130 return 0;
1131 }
1132
1133 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid, 1, 0, false);
1134 spin_unlock_bh(&ab->base_lock);
1135 if (ret) {
1136 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1137 params->tid, ret);
1138 return ret;
1139 }
1140
1141 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1142 params->sta->addr,
1143 rx_tid->paddr,
1144 params->tid, 1, 1);
1145 if (ret)
1146 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1147 ret);
1148
1149 return ret;
1150 }
1151
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1152 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1153 const u8 *peer_addr,
1154 enum set_key_cmd key_cmd,
1155 struct ieee80211_key_conf *key)
1156 {
1157 struct ath11k *ar = arvif->ar;
1158 struct ath11k_base *ab = ar->ab;
1159 struct ath11k_hal_reo_cmd cmd = {};
1160 struct ath11k_peer *peer;
1161 struct dp_rx_tid *rx_tid;
1162 u8 tid;
1163 int ret = 0;
1164
1165 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1166 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1167 * for now.
1168 */
1169 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1170 return 0;
1171
1172 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1173 cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1174 HAL_REO_CMD_UPD0_PN_SIZE |
1175 HAL_REO_CMD_UPD0_PN_VALID |
1176 HAL_REO_CMD_UPD0_PN_CHECK |
1177 HAL_REO_CMD_UPD0_SVLD;
1178
1179 switch (key->cipher) {
1180 case WLAN_CIPHER_SUITE_TKIP:
1181 case WLAN_CIPHER_SUITE_CCMP:
1182 case WLAN_CIPHER_SUITE_CCMP_256:
1183 case WLAN_CIPHER_SUITE_GCMP:
1184 case WLAN_CIPHER_SUITE_GCMP_256:
1185 if (key_cmd == SET_KEY) {
1186 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1187 cmd.pn_size = 48;
1188 }
1189 break;
1190 default:
1191 break;
1192 }
1193
1194 spin_lock_bh(&ab->base_lock);
1195
1196 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1197 if (!peer) {
1198 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1199 spin_unlock_bh(&ab->base_lock);
1200 return -ENOENT;
1201 }
1202
1203 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1204 rx_tid = &peer->rx_tid[tid];
1205 if (!rx_tid->active)
1206 continue;
1207 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1208 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1209 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1210 HAL_REO_CMD_UPDATE_RX_QUEUE,
1211 &cmd, NULL);
1212 if (ret) {
1213 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1214 tid, ret);
1215 break;
1216 }
1217 }
1218
1219 spin_unlock_bh(&ab->base_lock);
1220
1221 return ret;
1222 }
1223
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1224 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1225 u16 peer_id)
1226 {
1227 int i;
1228
1229 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1230 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1231 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1232 return i;
1233 } else {
1234 return i;
1235 }
1236 }
1237
1238 return -EINVAL;
1239 }
1240
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1241 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1242 u16 tag, u16 len, const void *ptr,
1243 void *data)
1244 {
1245 struct htt_ppdu_stats_info *ppdu_info;
1246 struct htt_ppdu_user_stats *user_stats;
1247 int cur_user;
1248 u16 peer_id;
1249
1250 ppdu_info = data;
1251
1252 switch (tag) {
1253 case HTT_PPDU_STATS_TAG_COMMON:
1254 if (len < sizeof(struct htt_ppdu_stats_common)) {
1255 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1256 len, tag);
1257 return -EINVAL;
1258 }
1259 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1260 sizeof(struct htt_ppdu_stats_common));
1261 break;
1262 case HTT_PPDU_STATS_TAG_USR_RATE:
1263 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1264 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1265 len, tag);
1266 return -EINVAL;
1267 }
1268
1269 #if defined(__linux__)
1270 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1271 #elif defined(__FreeBSD__)
1272 peer_id = ((const struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1273 #endif
1274 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1275 peer_id);
1276 if (cur_user < 0)
1277 return -EINVAL;
1278 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1279 user_stats->peer_id = peer_id;
1280 user_stats->is_valid_peer_id = true;
1281 memcpy((void *)&user_stats->rate, ptr,
1282 sizeof(struct htt_ppdu_stats_user_rate));
1283 user_stats->tlv_flags |= BIT(tag);
1284 break;
1285 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1286 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1287 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1288 len, tag);
1289 return -EINVAL;
1290 }
1291
1292 #if defined(__linux__)
1293 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1294 #elif defined(__FreeBSD__)
1295 peer_id = ((const struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1296 #endif
1297 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1298 peer_id);
1299 if (cur_user < 0)
1300 return -EINVAL;
1301 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1302 user_stats->peer_id = peer_id;
1303 user_stats->is_valid_peer_id = true;
1304 memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1305 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1306 user_stats->tlv_flags |= BIT(tag);
1307 break;
1308 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1309 if (len <
1310 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1311 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1312 len, tag);
1313 return -EINVAL;
1314 }
1315
1316 peer_id =
1317 #if defined(__linux__)
1318 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1319 #elif defined(__FreeBSD__)
1320 ((const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1321 #endif
1322 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1323 peer_id);
1324 if (cur_user < 0)
1325 return -EINVAL;
1326 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1327 user_stats->peer_id = peer_id;
1328 user_stats->is_valid_peer_id = true;
1329 memcpy((void *)&user_stats->ack_ba, ptr,
1330 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1331 user_stats->tlv_flags |= BIT(tag);
1332 break;
1333 }
1334 return 0;
1335 }
1336
1337 #if defined(__linux__)
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1338 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1339 #elif defined(__FreeBSD__)
1340 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const u8 *ptr, size_t len,
1341 #endif
1342 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1343 const void *ptr, void *data),
1344 void *data)
1345 {
1346 const struct htt_tlv *tlv;
1347 #if defined(__linux__)
1348 const void *begin = ptr;
1349 #elif defined(__FreeBSD__)
1350 const u8 *begin = ptr;
1351 #endif
1352 u16 tlv_tag, tlv_len;
1353 int ret = -EINVAL;
1354
1355 while (len > 0) {
1356 if (len < sizeof(*tlv)) {
1357 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1358 ptr - begin, len, sizeof(*tlv));
1359 return -EINVAL;
1360 }
1361 #if defined(__linux__)
1362 tlv = (struct htt_tlv *)ptr;
1363 #elif defined(__FreeBSD__)
1364 tlv = (const struct htt_tlv *)(const void *)ptr;
1365 #endif
1366 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1367 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1368 ptr += sizeof(*tlv);
1369 len -= sizeof(*tlv);
1370
1371 if (tlv_len > len) {
1372 ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1373 tlv_tag, ptr - begin, len, tlv_len);
1374 return -EINVAL;
1375 }
1376 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1377 if (ret == -ENOMEM)
1378 return ret;
1379
1380 ptr += tlv_len;
1381 len -= tlv_len;
1382 }
1383 return 0;
1384 }
1385
1386 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1387 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1388 struct htt_ppdu_stats *ppdu_stats, u8 user)
1389 {
1390 struct ath11k_base *ab = ar->ab;
1391 struct ath11k_peer *peer;
1392 struct ieee80211_sta *sta;
1393 struct ath11k_sta *arsta;
1394 struct htt_ppdu_stats_user_rate *user_rate;
1395 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1396 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1397 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1398 int ret;
1399 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1400 u32 succ_bytes = 0;
1401 u16 rate = 0, succ_pkts = 0;
1402 u32 tx_duration = 0;
1403 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1404 bool is_ampdu = false;
1405
1406 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1407 return;
1408
1409 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1410 is_ampdu =
1411 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1412
1413 if (usr_stats->tlv_flags &
1414 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1415 succ_bytes = usr_stats->ack_ba.success_bytes;
1416 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1417 usr_stats->ack_ba.info);
1418 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1419 usr_stats->ack_ba.info);
1420 }
1421
1422 if (common->fes_duration_us)
1423 tx_duration = common->fes_duration_us;
1424
1425 user_rate = &usr_stats->rate;
1426 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1427 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1428 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1429 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1430 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1431 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1432
1433 /* Note: If host configured fixed rates and in some other special
1434 * cases, the broadcast/management frames are sent in different rates.
1435 * Firmware rate's control to be skipped for this?
1436 */
1437
1438 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1439 ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
1440 return;
1441 }
1442
1443 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1444 ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
1445 return;
1446 }
1447
1448 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1449 ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1450 mcs, nss);
1451 return;
1452 }
1453
1454 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1455 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1456 flags,
1457 &rate_idx,
1458 &rate);
1459 if (ret < 0)
1460 return;
1461 }
1462
1463 rcu_read_lock();
1464 spin_lock_bh(&ab->base_lock);
1465 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1466
1467 if (!peer || !peer->sta) {
1468 spin_unlock_bh(&ab->base_lock);
1469 rcu_read_unlock();
1470 return;
1471 }
1472
1473 sta = peer->sta;
1474 arsta = ath11k_sta_to_arsta(sta);
1475
1476 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1477
1478 switch (flags) {
1479 case WMI_RATE_PREAMBLE_OFDM:
1480 arsta->txrate.legacy = rate;
1481 break;
1482 case WMI_RATE_PREAMBLE_CCK:
1483 arsta->txrate.legacy = rate;
1484 break;
1485 case WMI_RATE_PREAMBLE_HT:
1486 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1487 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1488 if (sgi)
1489 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1490 break;
1491 case WMI_RATE_PREAMBLE_VHT:
1492 arsta->txrate.mcs = mcs;
1493 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1494 if (sgi)
1495 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1496 break;
1497 case WMI_RATE_PREAMBLE_HE:
1498 arsta->txrate.mcs = mcs;
1499 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1500 arsta->txrate.he_dcm = dcm;
1501 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
1502 arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
1503 ((user_rate->ru_end -
1504 user_rate->ru_start) + 1);
1505 break;
1506 }
1507
1508 arsta->txrate.nss = nss;
1509
1510 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1511 arsta->tx_duration += tx_duration;
1512 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1513
1514 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1515 * So skip peer stats update for mgmt packets.
1516 */
1517 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1518 memset(peer_stats, 0, sizeof(*peer_stats));
1519 peer_stats->succ_pkts = succ_pkts;
1520 peer_stats->succ_bytes = succ_bytes;
1521 peer_stats->is_ampdu = is_ampdu;
1522 peer_stats->duration = tx_duration;
1523 peer_stats->ba_fails =
1524 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1525 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1526
1527 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1528 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1529 }
1530
1531 spin_unlock_bh(&ab->base_lock);
1532 rcu_read_unlock();
1533 }
1534
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1535 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1536 struct htt_ppdu_stats *ppdu_stats)
1537 {
1538 u8 user;
1539
1540 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1541 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1542 }
1543
1544 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1545 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1546 u32 ppdu_id)
1547 {
1548 struct htt_ppdu_stats_info *ppdu_info;
1549
1550 lockdep_assert_held(&ar->data_lock);
1551
1552 if (!list_empty(&ar->ppdu_stats_info)) {
1553 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1554 if (ppdu_info->ppdu_id == ppdu_id)
1555 return ppdu_info;
1556 }
1557
1558 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1559 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1560 typeof(*ppdu_info), list);
1561 list_del(&ppdu_info->list);
1562 ar->ppdu_stat_list_depth--;
1563 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1564 kfree(ppdu_info);
1565 }
1566 }
1567
1568 ppdu_info = kzalloc_obj(*ppdu_info, GFP_ATOMIC);
1569 if (!ppdu_info)
1570 return NULL;
1571
1572 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1573 ar->ppdu_stat_list_depth++;
1574
1575 return ppdu_info;
1576 }
1577
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1578 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1579 struct sk_buff *skb)
1580 {
1581 struct ath11k_htt_ppdu_stats_msg *msg;
1582 struct htt_ppdu_stats_info *ppdu_info;
1583 struct ath11k *ar;
1584 int ret;
1585 u8 pdev_id;
1586 u32 ppdu_id, len;
1587
1588 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1589 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1590 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1591 ppdu_id = msg->ppdu_id;
1592
1593 rcu_read_lock();
1594 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1595 if (!ar) {
1596 ret = -EINVAL;
1597 goto out;
1598 }
1599
1600 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1601 trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1602
1603 spin_lock_bh(&ar->data_lock);
1604 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1605 if (!ppdu_info) {
1606 ret = -EINVAL;
1607 goto out_unlock_data;
1608 }
1609
1610 ppdu_info->ppdu_id = ppdu_id;
1611 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1612 ath11k_htt_tlv_ppdu_stats_parse,
1613 (void *)ppdu_info);
1614 if (ret) {
1615 ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1616 goto out_unlock_data;
1617 }
1618
1619 out_unlock_data:
1620 spin_unlock_bh(&ar->data_lock);
1621
1622 out:
1623 rcu_read_unlock();
1624
1625 return ret;
1626 }
1627
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1628 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1629 {
1630 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1631 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1632 struct ath11k *ar;
1633 u8 pdev_id;
1634
1635 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1636
1637 rcu_read_lock();
1638
1639 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1640 if (!ar) {
1641 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1642 goto out;
1643 }
1644
1645 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1646 ar->ab->pktlog_defs_checksum);
1647
1648 out:
1649 rcu_read_unlock();
1650 }
1651
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1652 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1653 struct sk_buff *skb)
1654 {
1655 u32 *data = (u32 *)skb->data;
1656 u8 pdev_id, ring_type, ring_id, pdev_idx;
1657 u16 hp, tp;
1658 u32 backpressure_time;
1659 struct ath11k_bp_stats *bp_stats;
1660
1661 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1662 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1663 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1664 ++data;
1665
1666 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1667 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1668 ++data;
1669
1670 backpressure_time = *data;
1671
1672 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1673 pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1674
1675 if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1676 if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1677 return;
1678
1679 bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1680 } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1681 pdev_idx = DP_HW2SW_MACID(pdev_id);
1682
1683 if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1684 return;
1685
1686 bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1687 } else {
1688 ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1689 ring_type);
1690 return;
1691 }
1692
1693 spin_lock_bh(&ab->base_lock);
1694 bp_stats->hp = hp;
1695 bp_stats->tp = tp;
1696 bp_stats->count++;
1697 bp_stats->jiffies = jiffies;
1698 spin_unlock_bh(&ab->base_lock);
1699 }
1700
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1701 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1702 struct sk_buff *skb)
1703 {
1704 struct ath11k_dp *dp = &ab->dp;
1705 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1706 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1707 u16 peer_id;
1708 u8 vdev_id;
1709 u8 mac_addr[ETH_ALEN];
1710 u16 peer_mac_h16;
1711 u16 ast_hash;
1712 u16 hw_peer_id;
1713
1714 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1715
1716 switch (type) {
1717 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1718 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1719 resp->version_msg.version);
1720 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1721 resp->version_msg.version);
1722 complete(&dp->htt_tgt_version_received);
1723 break;
1724 case HTT_T2H_MSG_TYPE_PEER_MAP:
1725 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1726 resp->peer_map_ev.info);
1727 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1728 resp->peer_map_ev.info);
1729 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1730 resp->peer_map_ev.info1);
1731 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1732 peer_mac_h16, mac_addr);
1733 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1734 break;
1735 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1736 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1737 resp->peer_map_ev.info);
1738 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1739 resp->peer_map_ev.info);
1740 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1741 resp->peer_map_ev.info1);
1742 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1743 peer_mac_h16, mac_addr);
1744 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1745 resp->peer_map_ev.info2);
1746 hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1747 resp->peer_map_ev.info1);
1748 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1749 hw_peer_id);
1750 break;
1751 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1752 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1753 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1754 resp->peer_unmap_ev.info);
1755 ath11k_peer_unmap_event(ab, peer_id);
1756 break;
1757 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1758 ath11k_htt_pull_ppdu_stats(ab, skb);
1759 break;
1760 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1761 ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1762 break;
1763 case HTT_T2H_MSG_TYPE_PKTLOG:
1764 ath11k_htt_pktlog(ab, skb);
1765 break;
1766 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1767 ath11k_htt_backpressure_event_handler(ab, skb);
1768 break;
1769 default:
1770 ath11k_warn(ab, "htt event %d not handled\n", type);
1771 break;
1772 }
1773
1774 dev_kfree_skb_any(skb);
1775 }
1776
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1777 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1778 struct sk_buff_head *msdu_list,
1779 struct sk_buff *first, struct sk_buff *last,
1780 u8 l3pad_bytes, int msdu_len)
1781 {
1782 struct ath11k_base *ab = ar->ab;
1783 struct sk_buff *skb;
1784 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1785 int buf_first_hdr_len, buf_first_len;
1786 struct hal_rx_desc *ldesc;
1787 int space_extra, rem_len, buf_len;
1788 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1789
1790 /* As the msdu is spread across multiple rx buffers,
1791 * find the offset to the start of msdu for computing
1792 * the length of the msdu in the first buffer.
1793 */
1794 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1795 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1796
1797 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1798 skb_put(first, buf_first_hdr_len + msdu_len);
1799 skb_pull(first, buf_first_hdr_len);
1800 return 0;
1801 }
1802
1803 ldesc = (struct hal_rx_desc *)last->data;
1804 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1805 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1806
1807 /* MSDU spans over multiple buffers because the length of the MSDU
1808 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1809 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1810 */
1811 skb_put(first, DP_RX_BUFFER_SIZE);
1812 skb_pull(first, buf_first_hdr_len);
1813
1814 /* When an MSDU spread over multiple buffers attention, MSDU_END and
1815 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1816 */
1817 ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1818
1819 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1820 if (space_extra > 0 &&
1821 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1822 /* Free up all buffers of the MSDU */
1823 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1824 rxcb = ATH11K_SKB_RXCB(skb);
1825 if (!rxcb->is_continuation) {
1826 dev_kfree_skb_any(skb);
1827 break;
1828 }
1829 dev_kfree_skb_any(skb);
1830 }
1831 return -ENOMEM;
1832 }
1833
1834 rem_len = msdu_len - buf_first_len;
1835 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1836 rxcb = ATH11K_SKB_RXCB(skb);
1837 if (rxcb->is_continuation)
1838 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1839 else
1840 buf_len = rem_len;
1841
1842 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1843 WARN_ON_ONCE(1);
1844 dev_kfree_skb_any(skb);
1845 return -EINVAL;
1846 }
1847
1848 skb_put(skb, buf_len + hal_rx_desc_sz);
1849 skb_pull(skb, hal_rx_desc_sz);
1850 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1851 buf_len);
1852 dev_kfree_skb_any(skb);
1853
1854 rem_len -= buf_len;
1855 if (!rxcb->is_continuation)
1856 break;
1857 }
1858
1859 return 0;
1860 }
1861
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1862 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1863 struct sk_buff *first)
1864 {
1865 struct sk_buff *skb;
1866 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1867
1868 if (!rxcb->is_continuation)
1869 return first;
1870
1871 skb_queue_walk(msdu_list, skb) {
1872 rxcb = ATH11K_SKB_RXCB(skb);
1873 if (!rxcb->is_continuation)
1874 return skb;
1875 }
1876
1877 return NULL;
1878 }
1879
ath11k_dp_rx_h_csum_offload(struct ath11k * ar,struct sk_buff * msdu)1880 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1881 {
1882 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1883 struct rx_attention *rx_attention;
1884 bool ip_csum_fail, l4_csum_fail;
1885
1886 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1887 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1888 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1889
1890 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1891 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1892 }
1893
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1894 int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, enum hal_encrypt_type enctype)
1895 {
1896 switch (enctype) {
1897 case HAL_ENCRYPT_TYPE_OPEN:
1898 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1899 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1900 return 0;
1901 case HAL_ENCRYPT_TYPE_CCMP_128:
1902 return IEEE80211_CCMP_MIC_LEN;
1903 case HAL_ENCRYPT_TYPE_CCMP_256:
1904 return IEEE80211_CCMP_256_MIC_LEN;
1905 case HAL_ENCRYPT_TYPE_GCMP_128:
1906 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1907 return IEEE80211_GCMP_MIC_LEN;
1908 case HAL_ENCRYPT_TYPE_WEP_40:
1909 case HAL_ENCRYPT_TYPE_WEP_104:
1910 case HAL_ENCRYPT_TYPE_WEP_128:
1911 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1912 case HAL_ENCRYPT_TYPE_WAPI:
1913 break;
1914 }
1915
1916 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1917 return 0;
1918 }
1919
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1920 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1921 enum hal_encrypt_type enctype)
1922 {
1923 switch (enctype) {
1924 case HAL_ENCRYPT_TYPE_OPEN:
1925 return 0;
1926 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1927 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1928 return IEEE80211_TKIP_IV_LEN;
1929 case HAL_ENCRYPT_TYPE_CCMP_128:
1930 return IEEE80211_CCMP_HDR_LEN;
1931 case HAL_ENCRYPT_TYPE_CCMP_256:
1932 return IEEE80211_CCMP_256_HDR_LEN;
1933 case HAL_ENCRYPT_TYPE_GCMP_128:
1934 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1935 return IEEE80211_GCMP_HDR_LEN;
1936 case HAL_ENCRYPT_TYPE_WEP_40:
1937 case HAL_ENCRYPT_TYPE_WEP_104:
1938 case HAL_ENCRYPT_TYPE_WEP_128:
1939 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1940 case HAL_ENCRYPT_TYPE_WAPI:
1941 break;
1942 }
1943
1944 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1945 return 0;
1946 }
1947
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1948 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1949 enum hal_encrypt_type enctype)
1950 {
1951 switch (enctype) {
1952 case HAL_ENCRYPT_TYPE_OPEN:
1953 case HAL_ENCRYPT_TYPE_CCMP_128:
1954 case HAL_ENCRYPT_TYPE_CCMP_256:
1955 case HAL_ENCRYPT_TYPE_GCMP_128:
1956 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1957 return 0;
1958 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1959 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1960 return IEEE80211_TKIP_ICV_LEN;
1961 case HAL_ENCRYPT_TYPE_WEP_40:
1962 case HAL_ENCRYPT_TYPE_WEP_104:
1963 case HAL_ENCRYPT_TYPE_WEP_128:
1964 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1965 case HAL_ENCRYPT_TYPE_WAPI:
1966 break;
1967 }
1968
1969 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1970 return 0;
1971 }
1972
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1973 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1974 struct sk_buff *msdu,
1975 u8 *first_hdr,
1976 enum hal_encrypt_type enctype,
1977 struct ieee80211_rx_status *status)
1978 {
1979 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1980 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1981 struct ieee80211_hdr *hdr;
1982 size_t hdr_len;
1983 u8 da[ETH_ALEN];
1984 u8 sa[ETH_ALEN];
1985 u16 qos_ctl = 0;
1986 u8 *qos;
1987
1988 /* copy SA & DA and pull decapped header */
1989 hdr = (struct ieee80211_hdr *)msdu->data;
1990 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1991 ether_addr_copy(da, ieee80211_get_DA(hdr));
1992 ether_addr_copy(sa, ieee80211_get_SA(hdr));
1993 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1994
1995 if (rxcb->is_first_msdu) {
1996 /* original 802.11 header is valid for the first msdu
1997 * hence we can reuse the same header
1998 */
1999 hdr = (struct ieee80211_hdr *)first_hdr;
2000 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2001
2002 /* Each A-MSDU subframe will be reported as a separate MSDU,
2003 * so strip the A-MSDU bit from QoS Ctl.
2004 */
2005 if (ieee80211_is_data_qos(hdr->frame_control)) {
2006 qos = ieee80211_get_qos_ctl(hdr);
2007 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
2008 }
2009 } else {
2010 /* Rebuild qos header if this is a middle/last msdu */
2011 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
2012
2013 /* Reset the order bit as the HT_Control header is stripped */
2014 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
2015
2016 qos_ctl = rxcb->tid;
2017
2018 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
2019 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
2020
2021 /* TODO Add other QoS ctl fields when required */
2022
2023 /* copy decap header before overwriting for reuse below */
2024 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2025 }
2026
2027 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2028 memcpy(skb_push(msdu,
2029 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2030 #if defined(__linux__)
2031 (void *)hdr + hdr_len,
2032 #elif defined(__FreeBSD__)
2033 (u8 *)hdr + hdr_len,
2034 #endif
2035 ath11k_dp_rx_crypto_param_len(ar, enctype));
2036 }
2037
2038 if (!rxcb->is_first_msdu) {
2039 memcpy(skb_push(msdu,
2040 IEEE80211_QOS_CTL_LEN), &qos_ctl,
2041 IEEE80211_QOS_CTL_LEN);
2042 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2043 return;
2044 }
2045
2046 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2047
2048 /* original 802.11 header has a different DA and in
2049 * case of 4addr it may also have different SA
2050 */
2051 hdr = (struct ieee80211_hdr *)msdu->data;
2052 ether_addr_copy(ieee80211_get_DA(hdr), da);
2053 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2054 }
2055
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2056 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2057 enum hal_encrypt_type enctype,
2058 struct ieee80211_rx_status *status,
2059 bool decrypted)
2060 {
2061 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2062 struct ieee80211_hdr *hdr;
2063 size_t hdr_len;
2064 size_t crypto_len;
2065
2066 if (!rxcb->is_first_msdu ||
2067 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2068 WARN_ON_ONCE(1);
2069 return;
2070 }
2071
2072 skb_trim(msdu, msdu->len - FCS_LEN);
2073
2074 if (!decrypted)
2075 return;
2076
2077 hdr = (void *)msdu->data;
2078
2079 /* Tail */
2080 if (status->flag & RX_FLAG_IV_STRIPPED) {
2081 skb_trim(msdu, msdu->len -
2082 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2083
2084 skb_trim(msdu, msdu->len -
2085 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2086 } else {
2087 /* MIC */
2088 if (status->flag & RX_FLAG_MIC_STRIPPED)
2089 skb_trim(msdu, msdu->len -
2090 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2091
2092 /* ICV */
2093 if (status->flag & RX_FLAG_ICV_STRIPPED)
2094 skb_trim(msdu, msdu->len -
2095 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2096 }
2097
2098 /* MMIC */
2099 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2100 !ieee80211_has_morefrags(hdr->frame_control) &&
2101 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2102 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2103
2104 /* Head */
2105 if (status->flag & RX_FLAG_IV_STRIPPED) {
2106 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2107 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2108
2109 #if defined(__linux__)
2110 memmove((void *)msdu->data + crypto_len,
2111 (void *)msdu->data, hdr_len);
2112 #elif defined(__FreeBSD__)
2113 memmove((u8 *)msdu->data + crypto_len,
2114 (u8 *)msdu->data, hdr_len);
2115 #endif
2116 skb_pull(msdu, crypto_len);
2117 }
2118 }
2119
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2120 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2121 struct sk_buff *msdu,
2122 enum hal_encrypt_type enctype)
2123 {
2124 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2125 struct ieee80211_hdr *hdr;
2126 size_t hdr_len, crypto_len;
2127 #if defined(__linux__)
2128 void *rfc1042;
2129 #elif defined(__FreeBSD__)
2130 u8 *rfc1042;
2131 #endif
2132 bool is_amsdu;
2133
2134 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2135 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2136 #if defined(__linux__)
2137 rfc1042 = hdr;
2138 #elif defined(__FreeBSD__)
2139 rfc1042 = (void *)hdr;
2140 #endif
2141
2142 if (rxcb->is_first_msdu) {
2143 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2144 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2145
2146 rfc1042 += hdr_len + crypto_len;
2147 }
2148
2149 if (is_amsdu)
2150 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2151
2152 return rfc1042;
2153 }
2154
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2155 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2156 struct sk_buff *msdu,
2157 u8 *first_hdr,
2158 enum hal_encrypt_type enctype,
2159 struct ieee80211_rx_status *status)
2160 {
2161 struct ieee80211_hdr *hdr;
2162 struct ethhdr *eth;
2163 size_t hdr_len;
2164 u8 da[ETH_ALEN];
2165 u8 sa[ETH_ALEN];
2166 void *rfc1042;
2167
2168 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2169 if (WARN_ON_ONCE(!rfc1042))
2170 return;
2171
2172 /* pull decapped header and copy SA & DA */
2173 eth = (struct ethhdr *)msdu->data;
2174 ether_addr_copy(da, eth->h_dest);
2175 ether_addr_copy(sa, eth->h_source);
2176 skb_pull(msdu, sizeof(struct ethhdr));
2177
2178 /* push rfc1042/llc/snap */
2179 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2180 sizeof(struct ath11k_dp_rfc1042_hdr));
2181
2182 /* push original 802.11 header */
2183 hdr = (struct ieee80211_hdr *)first_hdr;
2184 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2185
2186 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2187 memcpy(skb_push(msdu,
2188 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2189 #if defined(__linux__)
2190 (void *)hdr + hdr_len,
2191 #elif defined(__FreeBSD__)
2192 (u8 *)hdr + hdr_len,
2193 #endif
2194 ath11k_dp_rx_crypto_param_len(ar, enctype));
2195 }
2196
2197 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2198
2199 /* original 802.11 header has a different DA and in
2200 * case of 4addr it may also have different SA
2201 */
2202 hdr = (struct ieee80211_hdr *)msdu->data;
2203 ether_addr_copy(ieee80211_get_DA(hdr), da);
2204 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2205 }
2206
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2207 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2208 struct hal_rx_desc *rx_desc,
2209 enum hal_encrypt_type enctype,
2210 struct ieee80211_rx_status *status,
2211 bool decrypted)
2212 {
2213 u8 *first_hdr;
2214 u8 decap;
2215 struct ethhdr *ehdr;
2216
2217 first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2218 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2219
2220 switch (decap) {
2221 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2222 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2223 enctype, status);
2224 break;
2225 case DP_RX_DECAP_TYPE_RAW:
2226 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2227 decrypted);
2228 break;
2229 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2230 ehdr = (struct ethhdr *)msdu->data;
2231
2232 /* mac80211 allows fast path only for authorized STA */
2233 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2234 ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2235 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2236 enctype, status);
2237 break;
2238 }
2239
2240 /* PN for mcast packets will be validated in mac80211;
2241 * remove eth header and add 802.11 header.
2242 */
2243 if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2244 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2245 enctype, status);
2246 break;
2247 case DP_RX_DECAP_TYPE_8023:
2248 /* TODO: Handle undecap for these formats */
2249 break;
2250 }
2251 }
2252
2253 static struct ath11k_peer *
ath11k_dp_rx_h_find_peer(struct ath11k_base * ab,struct sk_buff * msdu)2254 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2255 {
2256 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2257 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2258 struct ath11k_peer *peer = NULL;
2259
2260 lockdep_assert_held(&ab->base_lock);
2261
2262 if (rxcb->peer_id)
2263 peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2264
2265 if (peer)
2266 return peer;
2267
2268 if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2269 return NULL;
2270
2271 peer = ath11k_peer_find_by_addr(ab,
2272 ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2273 return peer;
2274 }
2275
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2276 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2277 struct sk_buff *msdu,
2278 struct hal_rx_desc *rx_desc,
2279 struct ieee80211_rx_status *rx_status)
2280 {
2281 bool fill_crypto_hdr;
2282 enum hal_encrypt_type enctype;
2283 bool is_decrypted = false;
2284 struct ath11k_skb_rxcb *rxcb;
2285 struct ieee80211_hdr *hdr;
2286 struct ath11k_peer *peer;
2287 struct rx_attention *rx_attention;
2288 u32 err_bitmap;
2289
2290 /* PN for multicast packets will be checked in mac80211 */
2291 rxcb = ATH11K_SKB_RXCB(msdu);
2292 fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2293 rxcb->is_mcbc = fill_crypto_hdr;
2294
2295 if (rxcb->is_mcbc) {
2296 rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2297 rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2298 }
2299
2300 spin_lock_bh(&ar->ab->base_lock);
2301 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2302 if (peer) {
2303 if (rxcb->is_mcbc)
2304 enctype = peer->sec_type_grp;
2305 else
2306 enctype = peer->sec_type;
2307 } else {
2308 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2309 }
2310 spin_unlock_bh(&ar->ab->base_lock);
2311
2312 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2313 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2314 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2315 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2316
2317 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2318 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2319 RX_FLAG_MMIC_ERROR |
2320 RX_FLAG_DECRYPTED |
2321 RX_FLAG_IV_STRIPPED |
2322 RX_FLAG_MMIC_STRIPPED);
2323
2324 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2325 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2326 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2327 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2328
2329 if (is_decrypted) {
2330 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2331
2332 if (fill_crypto_hdr)
2333 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2334 RX_FLAG_ICV_STRIPPED;
2335 else
2336 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2337 RX_FLAG_PN_VALIDATED;
2338 }
2339
2340 ath11k_dp_rx_h_csum_offload(ar, msdu);
2341 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2342 enctype, rx_status, is_decrypted);
2343
2344 if (!is_decrypted || fill_crypto_hdr)
2345 return;
2346
2347 if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2348 DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2349 hdr = (void *)msdu->data;
2350 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2351 }
2352 }
2353
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2354 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2355 struct ieee80211_rx_status *rx_status)
2356 {
2357 struct ieee80211_supported_band *sband;
2358 enum rx_msdu_start_pkt_type pkt_type;
2359 u8 bw;
2360 u8 rate_mcs, nss;
2361 u8 sgi;
2362 bool is_cck, is_ldpc;
2363
2364 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2365 bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2366 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2367 nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2368 sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2369
2370 switch (pkt_type) {
2371 case RX_MSDU_START_PKT_TYPE_11A:
2372 case RX_MSDU_START_PKT_TYPE_11B:
2373 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2374 sband = &ar->mac.sbands[rx_status->band];
2375 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2376 is_cck);
2377 break;
2378 case RX_MSDU_START_PKT_TYPE_11N:
2379 rx_status->encoding = RX_ENC_HT;
2380 if (rate_mcs > ATH11K_HT_MCS_MAX) {
2381 ath11k_warn(ar->ab,
2382 "Received with invalid mcs in HT mode %d\n",
2383 rate_mcs);
2384 break;
2385 }
2386 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2387 if (sgi)
2388 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2389 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2390 break;
2391 case RX_MSDU_START_PKT_TYPE_11AC:
2392 rx_status->encoding = RX_ENC_VHT;
2393 rx_status->rate_idx = rate_mcs;
2394 if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2395 ath11k_warn(ar->ab,
2396 "Received with invalid mcs in VHT mode %d\n",
2397 rate_mcs);
2398 break;
2399 }
2400 rx_status->nss = nss;
2401 if (sgi)
2402 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2403 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2404 is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc);
2405 if (is_ldpc)
2406 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2407 break;
2408 case RX_MSDU_START_PKT_TYPE_11AX:
2409 rx_status->rate_idx = rate_mcs;
2410 if (rate_mcs > ATH11K_HE_MCS_MAX) {
2411 ath11k_warn(ar->ab,
2412 "Received with invalid mcs in HE mode %d\n",
2413 rate_mcs);
2414 break;
2415 }
2416 rx_status->encoding = RX_ENC_HE;
2417 rx_status->nss = nss;
2418 rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
2419 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2420 break;
2421 }
2422 }
2423
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2424 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2425 struct ieee80211_rx_status *rx_status)
2426 {
2427 u8 channel_num;
2428 u32 center_freq, meta_data;
2429 struct ieee80211_channel *channel;
2430
2431 rx_status->freq = 0;
2432 rx_status->rate_idx = 0;
2433 rx_status->nss = 0;
2434 rx_status->encoding = RX_ENC_LEGACY;
2435 rx_status->bw = RATE_INFO_BW_20;
2436
2437 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2438
2439 meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2440 channel_num = meta_data;
2441 center_freq = meta_data >> 16;
2442
2443 if (center_freq >= ATH11K_MIN_6G_FREQ &&
2444 center_freq <= ATH11K_MAX_6G_FREQ) {
2445 rx_status->band = NL80211_BAND_6GHZ;
2446 rx_status->freq = center_freq;
2447 } else if (channel_num >= 1 && channel_num <= 14) {
2448 rx_status->band = NL80211_BAND_2GHZ;
2449 } else if (channel_num >= 36 && channel_num <= 177) {
2450 rx_status->band = NL80211_BAND_5GHZ;
2451 } else {
2452 spin_lock_bh(&ar->data_lock);
2453 channel = ar->rx_channel;
2454 if (channel) {
2455 rx_status->band = channel->band;
2456 channel_num =
2457 ieee80211_frequency_to_channel(channel->center_freq);
2458 }
2459 spin_unlock_bh(&ar->data_lock);
2460 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2461 rx_desc, sizeof(struct hal_rx_desc));
2462 }
2463
2464 if (rx_status->band != NL80211_BAND_6GHZ)
2465 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2466 rx_status->band);
2467
2468 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2469 }
2470
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2471 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2472 struct sk_buff *msdu,
2473 struct ieee80211_rx_status *status)
2474 {
2475 static const struct ieee80211_radiotap_he known = {
2476 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2477 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2478 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2479 };
2480 struct ieee80211_rx_status *rx_status;
2481 struct ieee80211_radiotap_he *he = NULL;
2482 struct ieee80211_sta *pubsta = NULL;
2483 struct ath11k_peer *peer;
2484 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2485 u8 decap = DP_RX_DECAP_TYPE_RAW;
2486 bool is_mcbc = rxcb->is_mcbc;
2487 bool is_eapol = rxcb->is_eapol;
2488
2489 if (status->encoding == RX_ENC_HE &&
2490 !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2491 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2492 he = skb_push(msdu, sizeof(known));
2493 memcpy(he, &known, sizeof(known));
2494 status->flag |= RX_FLAG_RADIOTAP_HE;
2495 }
2496
2497 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2498 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2499
2500 spin_lock_bh(&ar->ab->base_lock);
2501 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2502 if (peer && peer->sta)
2503 pubsta = peer->sta;
2504 spin_unlock_bh(&ar->ab->base_lock);
2505
2506 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2507 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2508 msdu,
2509 msdu->len,
2510 peer ? peer->addr : NULL,
2511 rxcb->tid,
2512 is_mcbc ? "mcast" : "ucast",
2513 rxcb->seq_no,
2514 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2515 (status->encoding == RX_ENC_HT) ? "ht" : "",
2516 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2517 (status->encoding == RX_ENC_HE) ? "he" : "",
2518 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2519 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2520 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2521 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2522 status->rate_idx,
2523 status->nss,
2524 status->freq,
2525 status->band, status->flag,
2526 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2527 !!(status->flag & RX_FLAG_MMIC_ERROR),
2528 !!(status->flag & RX_FLAG_AMSDU_MORE));
2529
2530 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2531 msdu->data, msdu->len);
2532
2533 rx_status = IEEE80211_SKB_RXCB(msdu);
2534 *rx_status = *status;
2535
2536 /* TODO: trace rx packet */
2537
2538 /* PN for multicast packets are not validate in HW,
2539 * so skip 802.3 rx path
2540 * Also, fast_rx expects the STA to be authorized, hence
2541 * eapol packets are sent in slow path.
2542 */
2543 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2544 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2545 rx_status->flag |= RX_FLAG_8023;
2546
2547 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2548 }
2549
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2550 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2551 struct sk_buff *msdu,
2552 struct sk_buff_head *msdu_list,
2553 struct ieee80211_rx_status *rx_status)
2554 {
2555 struct ath11k_base *ab = ar->ab;
2556 struct hal_rx_desc *rx_desc, *lrx_desc;
2557 struct rx_attention *rx_attention;
2558 struct ath11k_skb_rxcb *rxcb;
2559 struct sk_buff *last_buf;
2560 u8 l3_pad_bytes;
2561 u8 *hdr_status;
2562 u16 msdu_len;
2563 int ret;
2564 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2565
2566 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2567 if (!last_buf) {
2568 ath11k_warn(ab,
2569 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2570 ret = -EIO;
2571 goto free_out;
2572 }
2573
2574 rx_desc = (struct hal_rx_desc *)msdu->data;
2575 if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2576 ath11k_warn(ar->ab, "msdu len not valid\n");
2577 ret = -EIO;
2578 goto free_out;
2579 }
2580
2581 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2582 rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2583 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2584 ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2585 ret = -EIO;
2586 goto free_out;
2587 }
2588
2589 rxcb = ATH11K_SKB_RXCB(msdu);
2590 rxcb->rx_desc = rx_desc;
2591 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2592 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2593
2594 if (rxcb->is_frag) {
2595 skb_pull(msdu, hal_rx_desc_sz);
2596 } else if (!rxcb->is_continuation) {
2597 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2598 hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2599 ret = -EINVAL;
2600 ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2601 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2602 sizeof(struct ieee80211_hdr));
2603 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2604 sizeof(struct hal_rx_desc));
2605 goto free_out;
2606 }
2607 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2608 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2609 } else {
2610 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2611 msdu, last_buf,
2612 l3_pad_bytes, msdu_len);
2613 if (ret) {
2614 ath11k_warn(ab,
2615 "failed to coalesce msdu rx buffer%d\n", ret);
2616 goto free_out;
2617 }
2618 }
2619
2620 ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2621 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2622
2623 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2624
2625 return 0;
2626
2627 free_out:
2628 return ret;
2629 }
2630
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int mac_id)2631 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2632 struct napi_struct *napi,
2633 struct sk_buff_head *msdu_list,
2634 int mac_id)
2635 {
2636 struct sk_buff *msdu;
2637 struct ath11k *ar;
2638 struct ieee80211_rx_status rx_status = {};
2639 int ret;
2640
2641 if (skb_queue_empty(msdu_list))
2642 return;
2643
2644 if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
2645 __skb_queue_purge(msdu_list);
2646 return;
2647 }
2648
2649 ar = ab->pdevs[mac_id].ar;
2650 if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
2651 __skb_queue_purge(msdu_list);
2652 return;
2653 }
2654
2655 while ((msdu = __skb_dequeue(msdu_list))) {
2656 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2657 if (unlikely(ret)) {
2658 ath11k_dbg(ab, ATH11K_DBG_DATA,
2659 "Unable to process msdu %d", ret);
2660 dev_kfree_skb_any(msdu);
2661 continue;
2662 }
2663
2664 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2665 }
2666 }
2667
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2668 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2669 struct napi_struct *napi, int budget)
2670 {
2671 struct ath11k_dp *dp = &ab->dp;
2672 struct dp_rxdma_ring *rx_ring;
2673 int num_buffs_reaped[MAX_RADIOS] = {};
2674 struct sk_buff_head msdu_list[MAX_RADIOS];
2675 struct ath11k_skb_rxcb *rxcb;
2676 int total_msdu_reaped = 0;
2677 struct hal_srng *srng;
2678 struct sk_buff *msdu;
2679 bool done = false;
2680 int buf_id, mac_id;
2681 struct ath11k *ar;
2682 struct hal_reo_dest_ring *desc;
2683 enum hal_reo_dest_ring_push_reason push_reason;
2684 u32 cookie;
2685 int i;
2686
2687 for (i = 0; i < MAX_RADIOS; i++)
2688 __skb_queue_head_init(&msdu_list[i]);
2689
2690 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2691
2692 spin_lock_bh(&srng->lock);
2693
2694 try_again:
2695 ath11k_hal_srng_access_begin(ab, srng);
2696
2697 while (likely(desc =
2698 (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
2699 srng))) {
2700 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2701 desc->buf_addr_info.info1);
2702 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2703 cookie);
2704 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2705
2706 if (unlikely(buf_id == 0))
2707 continue;
2708
2709 ar = ab->pdevs[mac_id].ar;
2710 rx_ring = &ar->dp.rx_refill_buf_ring;
2711 spin_lock_bh(&rx_ring->idr_lock);
2712 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2713 if (unlikely(!msdu)) {
2714 ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2715 buf_id);
2716 spin_unlock_bh(&rx_ring->idr_lock);
2717 continue;
2718 }
2719
2720 idr_remove(&rx_ring->bufs_idr, buf_id);
2721 spin_unlock_bh(&rx_ring->idr_lock);
2722
2723 rxcb = ATH11K_SKB_RXCB(msdu);
2724 dma_unmap_single(ab->dev, rxcb->paddr,
2725 msdu->len + skb_tailroom(msdu),
2726 DMA_FROM_DEVICE);
2727
2728 num_buffs_reaped[mac_id]++;
2729
2730 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2731 desc->info0);
2732 if (unlikely(push_reason !=
2733 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
2734 dev_kfree_skb_any(msdu);
2735 ab->soc_stats.hal_reo_error[ring_id]++;
2736 continue;
2737 }
2738
2739 rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 &
2740 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2741 rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 &
2742 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2743 rxcb->is_continuation = !!(desc->rx_msdu_info.info0 &
2744 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2745 rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2746 desc->rx_mpdu_info.meta_data);
2747 rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2748 desc->rx_mpdu_info.info0);
2749 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2750 desc->info0);
2751
2752 rxcb->mac_id = mac_id;
2753 __skb_queue_tail(&msdu_list[mac_id], msdu);
2754
2755 if (rxcb->is_continuation) {
2756 done = false;
2757 } else {
2758 total_msdu_reaped++;
2759 done = true;
2760 }
2761
2762 if (total_msdu_reaped >= budget)
2763 break;
2764 }
2765
2766 /* Hw might have updated the head pointer after we cached it.
2767 * In this case, even though there are entries in the ring we'll
2768 * get rx_desc NULL. Give the read another try with updated cached
2769 * head pointer so that we can reap complete MPDU in the current
2770 * rx processing.
2771 */
2772 if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
2773 ath11k_hal_srng_access_end(ab, srng);
2774 goto try_again;
2775 }
2776
2777 ath11k_hal_srng_access_end(ab, srng);
2778
2779 spin_unlock_bh(&srng->lock);
2780
2781 if (unlikely(!total_msdu_reaped))
2782 goto exit;
2783
2784 for (i = 0; i < ab->num_radios; i++) {
2785 if (!num_buffs_reaped[i])
2786 continue;
2787
2788 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
2789
2790 ar = ab->pdevs[i].ar;
2791 rx_ring = &ar->dp.rx_refill_buf_ring;
2792
2793 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2794 ab->hw_params.hal_params->rx_buf_rbm);
2795 }
2796 exit:
2797 return total_msdu_reaped;
2798 }
2799
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2800 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2801 struct hal_rx_mon_ppdu_info *ppdu_info)
2802 {
2803 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2804 u32 num_msdu;
2805 int i;
2806
2807 if (!rx_stats)
2808 return;
2809
2810 arsta->rssi_comb = ppdu_info->rssi_comb;
2811 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
2812
2813 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2814 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2815
2816 rx_stats->num_msdu += num_msdu;
2817 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2818 ppdu_info->tcp_ack_msdu_count;
2819 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2820 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2821
2822 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2823 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2824 ppdu_info->nss = 1;
2825 ppdu_info->mcs = HAL_RX_MAX_MCS;
2826 ppdu_info->tid = IEEE80211_NUM_TIDS;
2827 }
2828
2829 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2830 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2831
2832 if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2833 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2834
2835 if (ppdu_info->gi < HAL_RX_GI_MAX)
2836 rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2837
2838 if (ppdu_info->bw < HAL_RX_BW_MAX)
2839 rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2840
2841 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2842 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2843
2844 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2845 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2846
2847 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2848 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2849
2850 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2851 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2852
2853 if (ppdu_info->is_stbc)
2854 rx_stats->stbc_count += num_msdu;
2855
2856 if (ppdu_info->beamformed)
2857 rx_stats->beamformed_count += num_msdu;
2858
2859 if (ppdu_info->num_mpdu_fcs_ok > 1)
2860 rx_stats->ampdu_msdu_count += num_msdu;
2861 else
2862 rx_stats->non_ampdu_msdu_count += num_msdu;
2863
2864 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2865 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2866 rx_stats->dcm_count += ppdu_info->dcm;
2867 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2868
2869 BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
2870 ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
2871
2872 for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
2873 arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
2874
2875 rx_stats->rx_duration += ppdu_info->rx_duration;
2876 arsta->rx_duration = rx_stats->rx_duration;
2877 }
2878
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2879 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2880 struct dp_rxdma_ring *rx_ring,
2881 int *buf_id)
2882 {
2883 struct sk_buff *skb;
2884 dma_addr_t paddr;
2885
2886 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2887 DP_RX_BUFFER_ALIGN_SIZE);
2888
2889 if (!skb)
2890 goto fail_alloc_skb;
2891
2892 if (!IS_ALIGNED((unsigned long)skb->data,
2893 DP_RX_BUFFER_ALIGN_SIZE)) {
2894 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2895 skb->data);
2896 }
2897
2898 paddr = dma_map_single(ab->dev, skb->data,
2899 skb->len + skb_tailroom(skb),
2900 DMA_FROM_DEVICE);
2901 if (unlikely(dma_mapping_error(ab->dev, paddr)))
2902 goto fail_free_skb;
2903
2904 spin_lock_bh(&rx_ring->idr_lock);
2905 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2906 rx_ring->bufs_max, GFP_ATOMIC);
2907 spin_unlock_bh(&rx_ring->idr_lock);
2908 if (*buf_id < 0)
2909 goto fail_dma_unmap;
2910
2911 ATH11K_SKB_RXCB(skb)->paddr = paddr;
2912 return skb;
2913
2914 fail_dma_unmap:
2915 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2916 DMA_FROM_DEVICE);
2917 fail_free_skb:
2918 dev_kfree_skb_any(skb);
2919 fail_alloc_skb:
2920 return NULL;
2921 }
2922
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2923 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2924 struct dp_rxdma_ring *rx_ring,
2925 int req_entries,
2926 enum hal_rx_buf_return_buf_manager mgr)
2927 {
2928 struct hal_srng *srng;
2929 u32 *desc;
2930 struct sk_buff *skb;
2931 int num_free;
2932 int num_remain;
2933 int buf_id;
2934 u32 cookie;
2935 dma_addr_t paddr;
2936
2937 req_entries = min(req_entries, rx_ring->bufs_max);
2938
2939 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2940
2941 spin_lock_bh(&srng->lock);
2942
2943 ath11k_hal_srng_access_begin(ab, srng);
2944
2945 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2946
2947 req_entries = min(num_free, req_entries);
2948 num_remain = req_entries;
2949
2950 while (num_remain > 0) {
2951 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2952 &buf_id);
2953 if (!skb)
2954 break;
2955 paddr = ATH11K_SKB_RXCB(skb)->paddr;
2956
2957 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2958 if (!desc)
2959 goto fail_desc_get;
2960
2961 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2962 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2963
2964 num_remain--;
2965
2966 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2967 }
2968
2969 ath11k_hal_srng_access_end(ab, srng);
2970
2971 spin_unlock_bh(&srng->lock);
2972
2973 return req_entries - num_remain;
2974
2975 fail_desc_get:
2976 spin_lock_bh(&rx_ring->idr_lock);
2977 idr_remove(&rx_ring->bufs_idr, buf_id);
2978 spin_unlock_bh(&rx_ring->idr_lock);
2979 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2980 DMA_FROM_DEVICE);
2981 dev_kfree_skb_any(skb);
2982 ath11k_hal_srng_access_end(ab, srng);
2983 spin_unlock_bh(&srng->lock);
2984
2985 return req_entries - num_remain;
2986 }
2987
2988 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
2989
2990 static void
ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data * pmon,struct hal_tlv_hdr * tlv)2991 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
2992 struct hal_tlv_hdr *tlv)
2993 {
2994 struct hal_rx_ppdu_start *ppdu_start;
2995 u16 ppdu_id_diff, ppdu_id, tlv_len;
2996 u8 *ptr;
2997
2998 /* PPDU id is part of second tlv, move ptr to second tlv */
2999 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
3000 ptr = (u8 *)tlv;
3001 ptr += sizeof(*tlv) + tlv_len;
3002 tlv = (struct hal_tlv_hdr *)ptr;
3003
3004 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
3005 return;
3006
3007 ptr += sizeof(*tlv);
3008 ppdu_start = (struct hal_rx_ppdu_start *)ptr;
3009 ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
3010 __le32_to_cpu(ppdu_start->info0));
3011
3012 if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
3013 pmon->buf_state = DP_MON_STATUS_LEAD;
3014 ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
3015 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
3016 pmon->buf_state = DP_MON_STATUS_LAG;
3017 } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
3018 pmon->buf_state = DP_MON_STATUS_LAG;
3019 ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
3020 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
3021 pmon->buf_state = DP_MON_STATUS_LEAD;
3022 }
3023 }
3024
3025 static enum dp_mon_status_buf_state
ath11k_dp_rx_mon_buf_done(struct ath11k_base * ab,struct hal_srng * srng,struct dp_rxdma_ring * rx_ring)3026 ath11k_dp_rx_mon_buf_done(struct ath11k_base *ab, struct hal_srng *srng,
3027 struct dp_rxdma_ring *rx_ring)
3028 {
3029 struct ath11k_skb_rxcb *rxcb;
3030 struct hal_tlv_hdr *tlv;
3031 struct sk_buff *skb;
3032 void *status_desc;
3033 dma_addr_t paddr;
3034 u32 cookie;
3035 int buf_id;
3036 u8 rbm;
3037
3038 status_desc = ath11k_hal_srng_src_next_peek(ab, srng);
3039 if (!status_desc)
3040 return DP_MON_STATUS_NO_DMA;
3041
3042 ath11k_hal_rx_buf_addr_info_get(status_desc, &paddr, &cookie, &rbm);
3043
3044 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3045
3046 spin_lock_bh(&rx_ring->idr_lock);
3047 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3048 spin_unlock_bh(&rx_ring->idr_lock);
3049
3050 if (!skb)
3051 return DP_MON_STATUS_NO_DMA;
3052
3053 rxcb = ATH11K_SKB_RXCB(skb);
3054 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3055 skb->len + skb_tailroom(skb),
3056 DMA_FROM_DEVICE);
3057
3058 tlv = (struct hal_tlv_hdr *)skb->data;
3059 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_STATUS_BUFFER_DONE)
3060 return DP_MON_STATUS_NO_DMA;
3061
3062 return DP_MON_STATUS_REPLINISH;
3063 }
3064
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)3065 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
3066 int *budget, struct sk_buff_head *skb_list)
3067 {
3068 struct ath11k *ar;
3069 const struct ath11k_hw_hal_params *hal_params;
3070 enum dp_mon_status_buf_state reap_status;
3071 struct ath11k_pdev_dp *dp;
3072 struct dp_rxdma_ring *rx_ring;
3073 struct ath11k_mon_data *pmon;
3074 struct hal_srng *srng;
3075 void *rx_mon_status_desc;
3076 struct sk_buff *skb;
3077 struct ath11k_skb_rxcb *rxcb;
3078 struct hal_tlv_hdr *tlv;
3079 u32 cookie;
3080 int buf_id, srng_id;
3081 dma_addr_t paddr;
3082 u8 rbm;
3083 int num_buffs_reaped = 0;
3084
3085 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
3086 dp = &ar->dp;
3087 pmon = &dp->mon_data;
3088 srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
3089 rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
3090
3091 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
3092
3093 spin_lock_bh(&srng->lock);
3094
3095 ath11k_hal_srng_access_begin(ab, srng);
3096 while (*budget) {
3097 *budget -= 1;
3098 rx_mon_status_desc =
3099 ath11k_hal_srng_src_peek(ab, srng);
3100 if (!rx_mon_status_desc) {
3101 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3102 break;
3103 }
3104
3105 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3106 &cookie, &rbm);
3107 if (paddr) {
3108 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3109
3110 spin_lock_bh(&rx_ring->idr_lock);
3111 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3112 spin_unlock_bh(&rx_ring->idr_lock);
3113
3114 if (!skb) {
3115 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3116 buf_id);
3117 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3118 goto move_next;
3119 }
3120
3121 rxcb = ATH11K_SKB_RXCB(skb);
3122
3123 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3124 skb->len + skb_tailroom(skb),
3125 DMA_FROM_DEVICE);
3126
3127 tlv = (struct hal_tlv_hdr *)skb->data;
3128 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3129 HAL_RX_STATUS_BUFFER_DONE) {
3130 ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n",
3131 FIELD_GET(HAL_TLV_HDR_TAG,
3132 tlv->tl), buf_id);
3133 /* RxDMA status done bit might not be set even
3134 * though tp is moved by HW.
3135 */
3136
3137 /* If done status is missing:
3138 * 1. As per MAC team's suggestion,
3139 * when HP + 1 entry is peeked and if DMA
3140 * is not done and if HP + 2 entry's DMA done
3141 * is set. skip HP + 1 entry and
3142 * start processing in next interrupt.
3143 * 2. If HP + 2 entry's DMA done is not set,
3144 * poll onto HP + 1 entry DMA done to be set.
3145 * Check status for same buffer for next time
3146 * dp_rx_mon_status_srng_process
3147 */
3148
3149 reap_status = ath11k_dp_rx_mon_buf_done(ab, srng,
3150 rx_ring);
3151 if (reap_status == DP_MON_STATUS_NO_DMA)
3152 continue;
3153
3154 spin_lock_bh(&rx_ring->idr_lock);
3155 idr_remove(&rx_ring->bufs_idr, buf_id);
3156 spin_unlock_bh(&rx_ring->idr_lock);
3157
3158 dma_unmap_single(ab->dev, rxcb->paddr,
3159 skb->len + skb_tailroom(skb),
3160 DMA_FROM_DEVICE);
3161
3162 dev_kfree_skb_any(skb);
3163 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3164 goto move_next;
3165 }
3166
3167 spin_lock_bh(&rx_ring->idr_lock);
3168 idr_remove(&rx_ring->bufs_idr, buf_id);
3169 spin_unlock_bh(&rx_ring->idr_lock);
3170 if (ab->hw_params.full_monitor_mode) {
3171 ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
3172 if (paddr == pmon->mon_status_paddr)
3173 pmon->buf_state = DP_MON_STATUS_MATCH;
3174 }
3175
3176 dma_unmap_single(ab->dev, rxcb->paddr,
3177 skb->len + skb_tailroom(skb),
3178 DMA_FROM_DEVICE);
3179
3180 __skb_queue_tail(skb_list, skb);
3181 } else {
3182 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3183 }
3184 move_next:
3185 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3186 &buf_id);
3187
3188 if (!skb) {
3189 hal_params = ab->hw_params.hal_params;
3190 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3191 hal_params->rx_buf_rbm);
3192 num_buffs_reaped++;
3193 break;
3194 }
3195 rxcb = ATH11K_SKB_RXCB(skb);
3196
3197 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3198 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3199
3200 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3201 cookie,
3202 ab->hw_params.hal_params->rx_buf_rbm);
3203 ath11k_hal_srng_src_get_next_entry(ab, srng);
3204 num_buffs_reaped++;
3205 }
3206 ath11k_hal_srng_access_end(ab, srng);
3207 spin_unlock_bh(&srng->lock);
3208
3209 return num_buffs_reaped;
3210 }
3211
ath11k_dp_rx_frag_timer(struct timer_list * timer)3212 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3213 {
3214 struct dp_rx_tid *rx_tid = timer_container_of(rx_tid, timer,
3215 frag_timer);
3216
3217 spin_lock_bh(&rx_tid->ab->base_lock);
3218 if (rx_tid->last_frag_no &&
3219 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3220 spin_unlock_bh(&rx_tid->ab->base_lock);
3221 return;
3222 }
3223 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3224 spin_unlock_bh(&rx_tid->ab->base_lock);
3225 }
3226
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3227 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3228 {
3229 struct ath11k_base *ab = ar->ab;
3230 struct crypto_shash *tfm;
3231 struct ath11k_peer *peer;
3232 struct dp_rx_tid *rx_tid;
3233 int i;
3234
3235 tfm = crypto_alloc_shash("michael_mic", 0, 0);
3236 if (IS_ERR(tfm)) {
3237 ath11k_warn(ab, "failed to allocate michael_mic shash: %ld\n",
3238 PTR_ERR(tfm));
3239 return PTR_ERR(tfm);
3240 }
3241
3242 spin_lock_bh(&ab->base_lock);
3243
3244 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3245 if (!peer) {
3246 ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3247 spin_unlock_bh(&ab->base_lock);
3248 crypto_free_shash(tfm);
3249 return -ENOENT;
3250 }
3251
3252 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3253 rx_tid = &peer->rx_tid[i];
3254 rx_tid->ab = ab;
3255 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3256 skb_queue_head_init(&rx_tid->rx_frags);
3257 }
3258
3259 peer->tfm_mmic = tfm;
3260 peer->dp_setup_done = true;
3261 spin_unlock_bh(&ab->base_lock);
3262
3263 return 0;
3264 }
3265
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3266 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3267 struct ieee80211_hdr *hdr, u8 *data,
3268 size_t data_len, u8 *mic)
3269 {
3270 SHASH_DESC_ON_STACK(desc, tfm);
3271 u8 mic_hdr[16] = {};
3272 u8 tid = 0;
3273 int ret;
3274
3275 if (!tfm)
3276 return -EINVAL;
3277
3278 desc->tfm = tfm;
3279
3280 ret = crypto_shash_setkey(tfm, key, 8);
3281 if (ret)
3282 goto out;
3283
3284 ret = crypto_shash_init(desc);
3285 if (ret)
3286 goto out;
3287
3288 /* TKIP MIC header */
3289 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3290 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3291 if (ieee80211_is_data_qos(hdr->frame_control))
3292 tid = ieee80211_get_tid(hdr);
3293 mic_hdr[12] = tid;
3294
3295 ret = crypto_shash_update(desc, mic_hdr, 16);
3296 if (ret)
3297 goto out;
3298 ret = crypto_shash_update(desc, data, data_len);
3299 if (ret)
3300 goto out;
3301 ret = crypto_shash_final(desc, mic);
3302 out:
3303 shash_desc_zero(desc);
3304 return ret;
3305 }
3306
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3307 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3308 struct sk_buff *msdu)
3309 {
3310 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3311 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3312 struct ieee80211_key_conf *key_conf;
3313 struct ieee80211_hdr *hdr;
3314 u8 mic[IEEE80211_CCMP_MIC_LEN];
3315 int head_len, tail_len, ret;
3316 size_t data_len;
3317 u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3318 u8 *key, *data;
3319 u8 key_idx;
3320
3321 if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3322 HAL_ENCRYPT_TYPE_TKIP_MIC)
3323 return 0;
3324
3325 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3326 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3327 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3328 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3329
3330 if (!is_multicast_ether_addr(hdr->addr1))
3331 key_idx = peer->ucast_keyidx;
3332 else
3333 key_idx = peer->mcast_keyidx;
3334
3335 key_conf = peer->keys[key_idx];
3336
3337 data = msdu->data + head_len;
3338 data_len = msdu->len - head_len - tail_len;
3339 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3340
3341 ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3342 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3343 goto mic_fail;
3344
3345 return 0;
3346
3347 mic_fail:
3348 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3349 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3350
3351 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3352 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3353 skb_pull(msdu, hal_rx_desc_sz);
3354
3355 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3356 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3357 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3358 ieee80211_rx(ar->hw, msdu);
3359 return -EINVAL;
3360 }
3361
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3362 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3363 enum hal_encrypt_type enctype, u32 flags)
3364 {
3365 struct ieee80211_hdr *hdr;
3366 size_t hdr_len;
3367 size_t crypto_len;
3368 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3369
3370 if (!flags)
3371 return;
3372
3373 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3374
3375 if (flags & RX_FLAG_MIC_STRIPPED)
3376 skb_trim(msdu, msdu->len -
3377 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3378
3379 if (flags & RX_FLAG_ICV_STRIPPED)
3380 skb_trim(msdu, msdu->len -
3381 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3382
3383 if (flags & RX_FLAG_IV_STRIPPED) {
3384 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3385 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3386
3387 #if defined(__linux__)
3388 memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3389 (void *)msdu->data + hal_rx_desc_sz, hdr_len);
3390 #elif defined(__FreeBSD__)
3391 memmove((u8 *)msdu->data + hal_rx_desc_sz + crypto_len,
3392 (u8 *)msdu->data + hal_rx_desc_sz, hdr_len);
3393 #endif
3394 skb_pull(msdu, crypto_len);
3395 }
3396 }
3397
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3398 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3399 struct ath11k_peer *peer,
3400 struct dp_rx_tid *rx_tid,
3401 struct sk_buff **defrag_skb)
3402 {
3403 struct hal_rx_desc *rx_desc;
3404 struct sk_buff *skb, *first_frag, *last_frag;
3405 struct ieee80211_hdr *hdr;
3406 struct rx_attention *rx_attention;
3407 enum hal_encrypt_type enctype;
3408 bool is_decrypted = false;
3409 int msdu_len = 0;
3410 int extra_space;
3411 u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3412
3413 first_frag = skb_peek(&rx_tid->rx_frags);
3414 last_frag = skb_peek_tail(&rx_tid->rx_frags);
3415
3416 skb_queue_walk(&rx_tid->rx_frags, skb) {
3417 flags = 0;
3418 rx_desc = (struct hal_rx_desc *)skb->data;
3419 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3420
3421 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3422 if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3423 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3424 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3425 }
3426
3427 if (is_decrypted) {
3428 if (skb != first_frag)
3429 flags |= RX_FLAG_IV_STRIPPED;
3430 if (skb != last_frag)
3431 flags |= RX_FLAG_ICV_STRIPPED |
3432 RX_FLAG_MIC_STRIPPED;
3433 }
3434
3435 /* RX fragments are always raw packets */
3436 if (skb != last_frag)
3437 skb_trim(skb, skb->len - FCS_LEN);
3438 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3439
3440 if (skb != first_frag)
3441 skb_pull(skb, hal_rx_desc_sz +
3442 ieee80211_hdrlen(hdr->frame_control));
3443 msdu_len += skb->len;
3444 }
3445
3446 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3447 if (extra_space > 0 &&
3448 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3449 return -ENOMEM;
3450
3451 __skb_unlink(first_frag, &rx_tid->rx_frags);
3452 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3453 skb_put_data(first_frag, skb->data, skb->len);
3454 dev_kfree_skb_any(skb);
3455 }
3456
3457 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3458 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3459 ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3460
3461 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3462 first_frag = NULL;
3463
3464 *defrag_skb = first_frag;
3465 return 0;
3466 }
3467
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3468 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3469 struct sk_buff *defrag_skb)
3470 {
3471 struct ath11k_base *ab = ar->ab;
3472 struct ath11k_pdev_dp *dp = &ar->dp;
3473 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3474 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3475 struct hal_reo_entrance_ring *reo_ent_ring;
3476 struct hal_reo_dest_ring *reo_dest_ring;
3477 struct dp_link_desc_bank *link_desc_banks;
3478 struct hal_rx_msdu_link *msdu_link;
3479 struct hal_rx_msdu_details *msdu0;
3480 struct hal_srng *srng;
3481 dma_addr_t paddr;
3482 u32 desc_bank, msdu_info, mpdu_info;
3483 u32 dst_idx, cookie, hal_rx_desc_sz;
3484 int ret, buf_id;
3485
3486 hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3487 link_desc_banks = ab->dp.link_desc_banks;
3488 reo_dest_ring = rx_tid->dst_ring_desc;
3489
3490 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3491 #if defined(__linux__)
3492 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3493 #elif defined(__FreeBSD__)
3494 msdu_link = (struct hal_rx_msdu_link *)((u8 *)link_desc_banks[desc_bank].vaddr +
3495 #endif
3496 (paddr - link_desc_banks[desc_bank].paddr));
3497 msdu0 = &msdu_link->msdu_link[0];
3498 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3499 memset(msdu0, 0, sizeof(*msdu0));
3500
3501 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3502 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3503 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3504 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3505 defrag_skb->len - hal_rx_desc_sz) |
3506 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3507 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3508 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3509 msdu0->rx_msdu_info.info0 = msdu_info;
3510
3511 /* change msdu len in hal rx desc */
3512 ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3513
3514 paddr = dma_map_single(ab->dev, defrag_skb->data,
3515 defrag_skb->len + skb_tailroom(defrag_skb),
3516 DMA_TO_DEVICE);
3517 if (dma_mapping_error(ab->dev, paddr))
3518 return -ENOMEM;
3519
3520 spin_lock_bh(&rx_refill_ring->idr_lock);
3521 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3522 rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3523 spin_unlock_bh(&rx_refill_ring->idr_lock);
3524 if (buf_id < 0) {
3525 ret = -ENOMEM;
3526 goto err_unmap_dma;
3527 }
3528
3529 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3530 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3531 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3532
3533 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
3534 ab->hw_params.hal_params->rx_buf_rbm);
3535
3536 /* Fill mpdu details into reo entrance ring */
3537 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3538
3539 spin_lock_bh(&srng->lock);
3540 ath11k_hal_srng_access_begin(ab, srng);
3541
3542 reo_ent_ring = (struct hal_reo_entrance_ring *)
3543 ath11k_hal_srng_src_get_next_entry(ab, srng);
3544 if (!reo_ent_ring) {
3545 ath11k_hal_srng_access_end(ab, srng);
3546 spin_unlock_bh(&srng->lock);
3547 ret = -ENOSPC;
3548 goto err_free_idr;
3549 }
3550 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3551
3552 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3553 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3554 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3555
3556 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3557 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3558 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3559 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3560 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3561 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3562 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3563
3564 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3565 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3566 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3567 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3568 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3569 reo_dest_ring->info0)) |
3570 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3571 ath11k_hal_srng_access_end(ab, srng);
3572 spin_unlock_bh(&srng->lock);
3573
3574 return 0;
3575
3576 err_free_idr:
3577 spin_lock_bh(&rx_refill_ring->idr_lock);
3578 idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3579 spin_unlock_bh(&rx_refill_ring->idr_lock);
3580 err_unmap_dma:
3581 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3582 DMA_TO_DEVICE);
3583 return ret;
3584 }
3585
ath11k_dp_rx_h_cmp_frags(struct ath11k * ar,struct sk_buff * a,struct sk_buff * b)3586 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3587 struct sk_buff *a, struct sk_buff *b)
3588 {
3589 int frag1, frag2;
3590
3591 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3592 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3593
3594 return frag1 - frag2;
3595 }
3596
ath11k_dp_rx_h_sort_frags(struct ath11k * ar,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3597 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3598 struct sk_buff_head *frag_list,
3599 struct sk_buff *cur_frag)
3600 {
3601 struct sk_buff *skb;
3602 int cmp;
3603
3604 skb_queue_walk(frag_list, skb) {
3605 cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3606 if (cmp < 0)
3607 continue;
3608 __skb_queue_before(frag_list, skb, cur_frag);
3609 return;
3610 }
3611 __skb_queue_tail(frag_list, cur_frag);
3612 }
3613
ath11k_dp_rx_h_get_pn(struct ath11k * ar,struct sk_buff * skb)3614 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3615 {
3616 struct ieee80211_hdr *hdr;
3617 u64 pn = 0;
3618 u8 *ehdr;
3619 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3620
3621 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3622 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3623
3624 pn = ehdr[0];
3625 pn |= (u64)ehdr[1] << 8;
3626 pn |= (u64)ehdr[4] << 16;
3627 pn |= (u64)ehdr[5] << 24;
3628 pn |= (u64)ehdr[6] << 32;
3629 pn |= (u64)ehdr[7] << 40;
3630
3631 return pn;
3632 }
3633
3634 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3635 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3636 {
3637 enum hal_encrypt_type encrypt_type;
3638 struct sk_buff *first_frag, *skb;
3639 struct hal_rx_desc *desc;
3640 u64 last_pn;
3641 u64 cur_pn;
3642
3643 first_frag = skb_peek(&rx_tid->rx_frags);
3644 desc = (struct hal_rx_desc *)first_frag->data;
3645
3646 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3647 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3648 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3649 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3650 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3651 return true;
3652
3653 last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3654 skb_queue_walk(&rx_tid->rx_frags, skb) {
3655 if (skb == first_frag)
3656 continue;
3657
3658 cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3659 if (cur_pn != last_pn + 1)
3660 return false;
3661 last_pn = cur_pn;
3662 }
3663 return true;
3664 }
3665
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3666 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3667 struct sk_buff *msdu,
3668 u32 *ring_desc)
3669 {
3670 struct ath11k_base *ab = ar->ab;
3671 struct hal_rx_desc *rx_desc;
3672 struct ath11k_peer *peer;
3673 struct dp_rx_tid *rx_tid;
3674 struct sk_buff *defrag_skb = NULL;
3675 u32 peer_id;
3676 u16 seqno, frag_no;
3677 u8 tid;
3678 int ret = 0;
3679 bool more_frags;
3680 bool is_mcbc;
3681
3682 rx_desc = (struct hal_rx_desc *)msdu->data;
3683 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3684 tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3685 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3686 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3687 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3688 is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3689
3690 /* Multicast/Broadcast fragments are not expected */
3691 if (is_mcbc)
3692 return -EINVAL;
3693
3694 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3695 !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3696 tid > IEEE80211_NUM_TIDS)
3697 return -EINVAL;
3698
3699 /* received unfragmented packet in reo
3700 * exception ring, this shouldn't happen
3701 * as these packets typically come from
3702 * reo2sw srngs.
3703 */
3704 if (WARN_ON_ONCE(!frag_no && !more_frags))
3705 return -EINVAL;
3706
3707 spin_lock_bh(&ab->base_lock);
3708 peer = ath11k_peer_find_by_id(ab, peer_id);
3709 if (!peer) {
3710 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3711 peer_id);
3712 ret = -ENOENT;
3713 goto out_unlock;
3714 }
3715 if (!peer->dp_setup_done) {
3716 ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3717 peer->addr, peer_id);
3718 ret = -ENOENT;
3719 goto out_unlock;
3720 }
3721
3722 rx_tid = &peer->rx_tid[tid];
3723
3724 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3725 skb_queue_empty(&rx_tid->rx_frags)) {
3726 /* Flush stored fragments and start a new sequence */
3727 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3728 rx_tid->cur_sn = seqno;
3729 }
3730
3731 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3732 /* Fragment already present */
3733 ret = -EINVAL;
3734 goto out_unlock;
3735 }
3736
3737 if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap)))
3738 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3739 else
3740 ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3741
3742 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3743 if (!more_frags)
3744 rx_tid->last_frag_no = frag_no;
3745
3746 if (frag_no == 0) {
3747 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3748 sizeof(*rx_tid->dst_ring_desc),
3749 GFP_ATOMIC);
3750 if (!rx_tid->dst_ring_desc) {
3751 ret = -ENOMEM;
3752 goto out_unlock;
3753 }
3754 } else {
3755 ath11k_dp_rx_link_desc_return(ab, ring_desc,
3756 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3757 }
3758
3759 if (!rx_tid->last_frag_no ||
3760 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3761 mod_timer(&rx_tid->frag_timer, jiffies +
3762 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3763 goto out_unlock;
3764 }
3765
3766 spin_unlock_bh(&ab->base_lock);
3767 timer_delete_sync(&rx_tid->frag_timer);
3768 spin_lock_bh(&ab->base_lock);
3769
3770 peer = ath11k_peer_find_by_id(ab, peer_id);
3771 if (!peer)
3772 goto err_frags_cleanup;
3773
3774 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3775 goto err_frags_cleanup;
3776
3777 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3778 goto err_frags_cleanup;
3779
3780 if (!defrag_skb)
3781 goto err_frags_cleanup;
3782
3783 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3784 goto err_frags_cleanup;
3785
3786 ath11k_dp_rx_frags_cleanup(rx_tid, false);
3787 goto out_unlock;
3788
3789 err_frags_cleanup:
3790 dev_kfree_skb_any(defrag_skb);
3791 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3792 out_unlock:
3793 spin_unlock_bh(&ab->base_lock);
3794 return ret;
3795 }
3796
3797 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3798 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3799 {
3800 struct ath11k_pdev_dp *dp = &ar->dp;
3801 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3802 struct sk_buff *msdu;
3803 struct ath11k_skb_rxcb *rxcb;
3804 struct hal_rx_desc *rx_desc;
3805 u8 *hdr_status;
3806 u16 msdu_len;
3807 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3808
3809 spin_lock_bh(&rx_ring->idr_lock);
3810 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3811 if (!msdu) {
3812 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3813 buf_id);
3814 spin_unlock_bh(&rx_ring->idr_lock);
3815 return -EINVAL;
3816 }
3817
3818 idr_remove(&rx_ring->bufs_idr, buf_id);
3819 spin_unlock_bh(&rx_ring->idr_lock);
3820
3821 rxcb = ATH11K_SKB_RXCB(msdu);
3822 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3823 msdu->len + skb_tailroom(msdu),
3824 DMA_FROM_DEVICE);
3825
3826 if (drop) {
3827 dev_kfree_skb_any(msdu);
3828 return 0;
3829 }
3830
3831 rcu_read_lock();
3832 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3833 dev_kfree_skb_any(msdu);
3834 goto exit;
3835 }
3836
3837 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3838 dev_kfree_skb_any(msdu);
3839 goto exit;
3840 }
3841
3842 rx_desc = (struct hal_rx_desc *)msdu->data;
3843 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3844 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3845 hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3846 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3847 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3848 sizeof(struct ieee80211_hdr));
3849 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3850 sizeof(struct hal_rx_desc));
3851 dev_kfree_skb_any(msdu);
3852 goto exit;
3853 }
3854
3855 skb_put(msdu, hal_rx_desc_sz + msdu_len);
3856
3857 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3858 dev_kfree_skb_any(msdu);
3859 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3860 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3861 }
3862 exit:
3863 rcu_read_unlock();
3864 return 0;
3865 }
3866
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3867 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3868 int budget)
3869 {
3870 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3871 struct dp_link_desc_bank *link_desc_banks;
3872 enum hal_rx_buf_return_buf_manager rbm;
3873 int tot_n_bufs_reaped, quota, ret, i;
3874 int n_bufs_reaped[MAX_RADIOS] = {};
3875 struct dp_rxdma_ring *rx_ring;
3876 struct dp_srng *reo_except;
3877 u32 desc_bank, num_msdus;
3878 struct hal_srng *srng;
3879 struct ath11k_dp *dp;
3880 void *link_desc_va;
3881 int buf_id, mac_id;
3882 struct ath11k *ar;
3883 dma_addr_t paddr;
3884 u32 *desc;
3885 bool is_frag;
3886 u8 drop = 0;
3887
3888 tot_n_bufs_reaped = 0;
3889 quota = budget;
3890
3891 dp = &ab->dp;
3892 reo_except = &dp->reo_except_ring;
3893 link_desc_banks = dp->link_desc_banks;
3894
3895 srng = &ab->hal.srng_list[reo_except->ring_id];
3896
3897 spin_lock_bh(&srng->lock);
3898
3899 ath11k_hal_srng_access_begin(ab, srng);
3900
3901 while (budget &&
3902 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3903 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3904
3905 ab->soc_stats.err_ring_pkts++;
3906 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3907 &desc_bank);
3908 if (ret) {
3909 ath11k_warn(ab, "failed to parse error reo desc %d\n",
3910 ret);
3911 continue;
3912 }
3913 #if defined(__linux__)
3914 link_desc_va = link_desc_banks[desc_bank].vaddr +
3915 #elif defined(__FreeBSD__)
3916 link_desc_va = (u8 *)link_desc_banks[desc_bank].vaddr +
3917 #endif
3918 (paddr - link_desc_banks[desc_bank].paddr);
3919 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3920 &rbm);
3921 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3922 rbm != HAL_RX_BUF_RBM_SW1_BM &&
3923 rbm != HAL_RX_BUF_RBM_SW3_BM) {
3924 ab->soc_stats.invalid_rbm++;
3925 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3926 ath11k_dp_rx_link_desc_return(ab, desc,
3927 HAL_WBM_REL_BM_ACT_REL_MSDU);
3928 continue;
3929 }
3930
3931 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3932
3933 /* Process only rx fragments with one msdu per link desc below, and drop
3934 * msdu's indicated due to error reasons.
3935 */
3936 if (!is_frag || num_msdus > 1) {
3937 drop = 1;
3938 /* Return the link desc back to wbm idle list */
3939 ath11k_dp_rx_link_desc_return(ab, desc,
3940 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3941 }
3942
3943 for (i = 0; i < num_msdus; i++) {
3944 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3945 msdu_cookies[i]);
3946
3947 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3948 msdu_cookies[i]);
3949
3950 ar = ab->pdevs[mac_id].ar;
3951
3952 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3953 n_bufs_reaped[mac_id]++;
3954 tot_n_bufs_reaped++;
3955 }
3956 }
3957
3958 if (tot_n_bufs_reaped >= quota) {
3959 tot_n_bufs_reaped = quota;
3960 goto exit;
3961 }
3962
3963 budget = quota - tot_n_bufs_reaped;
3964 }
3965
3966 exit:
3967 ath11k_hal_srng_access_end(ab, srng);
3968
3969 spin_unlock_bh(&srng->lock);
3970
3971 for (i = 0; i < ab->num_radios; i++) {
3972 if (!n_bufs_reaped[i])
3973 continue;
3974
3975 ar = ab->pdevs[i].ar;
3976 rx_ring = &ar->dp.rx_refill_buf_ring;
3977
3978 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3979 ab->hw_params.hal_params->rx_buf_rbm);
3980 }
3981
3982 return tot_n_bufs_reaped;
3983 }
3984
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3985 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3986 int msdu_len,
3987 struct sk_buff_head *msdu_list)
3988 {
3989 struct sk_buff *skb, *tmp;
3990 struct ath11k_skb_rxcb *rxcb;
3991 int n_buffs;
3992
3993 n_buffs = DIV_ROUND_UP(msdu_len,
3994 (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3995
3996 skb_queue_walk_safe(msdu_list, skb, tmp) {
3997 rxcb = ATH11K_SKB_RXCB(skb);
3998 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3999 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
4000 if (!n_buffs)
4001 break;
4002 __skb_unlink(skb, msdu_list);
4003 dev_kfree_skb_any(skb);
4004 n_buffs--;
4005 }
4006 }
4007 }
4008
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)4009 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
4010 struct ieee80211_rx_status *status,
4011 struct sk_buff_head *msdu_list)
4012 {
4013 u16 msdu_len;
4014 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4015 struct rx_attention *rx_attention;
4016 u8 l3pad_bytes;
4017 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4018 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4019
4020 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4021
4022 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
4023 /* First buffer will be freed by the caller, so deduct it's length */
4024 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
4025 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
4026 return -EINVAL;
4027 }
4028
4029 rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
4030 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
4031 ath11k_warn(ar->ab,
4032 "msdu_done bit not set in null_q_des processing\n");
4033 __skb_queue_purge(msdu_list);
4034 return -EIO;
4035 }
4036
4037 /* Handle NULL queue descriptor violations arising out a missing
4038 * REO queue for a given peer or a given TID. This typically
4039 * may happen if a packet is received on a QOS enabled TID before the
4040 * ADDBA negotiation for that TID, when the TID queue is setup. Or
4041 * it may also happen for MC/BC frames if they are not routed to the
4042 * non-QOS TID queue, in the absence of any other default TID queue.
4043 * This error can show up both in a REO destination or WBM release ring.
4044 */
4045
4046 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4047 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4048
4049 if (rxcb->is_frag) {
4050 skb_pull(msdu, hal_rx_desc_sz);
4051 } else {
4052 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4053
4054 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
4055 return -EINVAL;
4056
4057 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4058 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4059 }
4060 ath11k_dp_rx_h_ppdu(ar, desc, status);
4061
4062 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
4063
4064 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
4065
4066 /* Please note that caller will having the access to msdu and completing
4067 * rx with mac80211. Need not worry about cleaning up amsdu_list.
4068 */
4069
4070 return 0;
4071 }
4072
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)4073 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
4074 struct ieee80211_rx_status *status,
4075 struct sk_buff_head *msdu_list)
4076 {
4077 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4078 bool drop = false;
4079
4080 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
4081
4082 switch (rxcb->err_code) {
4083 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
4084 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
4085 drop = true;
4086 break;
4087 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
4088 /* TODO: Do not drop PN failed packets in the driver;
4089 * instead, it is good to drop such packets in mac80211
4090 * after incrementing the replay counters.
4091 */
4092 fallthrough;
4093 default:
4094 /* TODO: Review other errors and process them to mac80211
4095 * as appropriate.
4096 */
4097 drop = true;
4098 break;
4099 }
4100
4101 return drop;
4102 }
4103
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4104 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
4105 struct ieee80211_rx_status *status)
4106 {
4107 u16 msdu_len;
4108 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4109 u8 l3pad_bytes;
4110 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4111 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4112
4113 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4114 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4115
4116 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4117 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4118 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4119 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4120
4121 ath11k_dp_rx_h_ppdu(ar, desc, status);
4122
4123 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4124 RX_FLAG_DECRYPTED);
4125
4126 ath11k_dp_rx_h_undecap(ar, msdu, desc,
4127 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4128 }
4129
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4130 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu,
4131 struct ieee80211_rx_status *status)
4132 {
4133 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4134 bool drop = false;
4135
4136 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4137
4138 switch (rxcb->err_code) {
4139 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4140 ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4141 break;
4142 default:
4143 /* TODO: Review other rxdma error code to check if anything is
4144 * worth reporting to mac80211
4145 */
4146 drop = true;
4147 break;
4148 }
4149
4150 return drop;
4151 }
4152
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)4153 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4154 struct napi_struct *napi,
4155 struct sk_buff *msdu,
4156 struct sk_buff_head *msdu_list)
4157 {
4158 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4159 struct ieee80211_rx_status rxs = {};
4160 bool drop = true;
4161
4162 switch (rxcb->err_rel_src) {
4163 case HAL_WBM_REL_SRC_MODULE_REO:
4164 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4165 break;
4166 case HAL_WBM_REL_SRC_MODULE_RXDMA:
4167 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4168 break;
4169 default:
4170 /* msdu will get freed */
4171 break;
4172 }
4173
4174 if (drop) {
4175 dev_kfree_skb_any(msdu);
4176 return;
4177 }
4178
4179 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4180 }
4181
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)4182 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4183 struct napi_struct *napi, int budget)
4184 {
4185 struct ath11k *ar;
4186 struct ath11k_dp *dp = &ab->dp;
4187 struct dp_rxdma_ring *rx_ring;
4188 struct hal_rx_wbm_rel_info err_info;
4189 struct hal_srng *srng;
4190 struct sk_buff *msdu;
4191 struct sk_buff_head msdu_list[MAX_RADIOS];
4192 struct ath11k_skb_rxcb *rxcb;
4193 u32 *rx_desc;
4194 int buf_id, mac_id;
4195 int num_buffs_reaped[MAX_RADIOS] = {};
4196 int total_num_buffs_reaped = 0;
4197 int ret, i;
4198
4199 for (i = 0; i < ab->num_radios; i++)
4200 __skb_queue_head_init(&msdu_list[i]);
4201
4202 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4203
4204 spin_lock_bh(&srng->lock);
4205
4206 ath11k_hal_srng_access_begin(ab, srng);
4207
4208 while (budget) {
4209 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4210 if (!rx_desc)
4211 break;
4212
4213 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4214 if (ret) {
4215 ath11k_warn(ab,
4216 "failed to parse rx error in wbm_rel ring desc %d\n",
4217 ret);
4218 continue;
4219 }
4220
4221 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4222 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4223
4224 ar = ab->pdevs[mac_id].ar;
4225 rx_ring = &ar->dp.rx_refill_buf_ring;
4226
4227 spin_lock_bh(&rx_ring->idr_lock);
4228 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4229 if (!msdu) {
4230 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4231 buf_id, mac_id);
4232 spin_unlock_bh(&rx_ring->idr_lock);
4233 continue;
4234 }
4235
4236 idr_remove(&rx_ring->bufs_idr, buf_id);
4237 spin_unlock_bh(&rx_ring->idr_lock);
4238
4239 rxcb = ATH11K_SKB_RXCB(msdu);
4240 dma_unmap_single(ab->dev, rxcb->paddr,
4241 msdu->len + skb_tailroom(msdu),
4242 DMA_FROM_DEVICE);
4243
4244 num_buffs_reaped[mac_id]++;
4245 total_num_buffs_reaped++;
4246 budget--;
4247
4248 if (err_info.push_reason !=
4249 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4250 dev_kfree_skb_any(msdu);
4251 continue;
4252 }
4253
4254 rxcb->err_rel_src = err_info.err_rel_src;
4255 rxcb->err_code = err_info.err_code;
4256 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4257 __skb_queue_tail(&msdu_list[mac_id], msdu);
4258 }
4259
4260 ath11k_hal_srng_access_end(ab, srng);
4261
4262 spin_unlock_bh(&srng->lock);
4263
4264 if (!total_num_buffs_reaped)
4265 goto done;
4266
4267 for (i = 0; i < ab->num_radios; i++) {
4268 if (!num_buffs_reaped[i])
4269 continue;
4270
4271 ar = ab->pdevs[i].ar;
4272 rx_ring = &ar->dp.rx_refill_buf_ring;
4273
4274 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4275 ab->hw_params.hal_params->rx_buf_rbm);
4276 }
4277
4278 rcu_read_lock();
4279 for (i = 0; i < ab->num_radios; i++) {
4280 if (!rcu_dereference(ab->pdevs_active[i])) {
4281 __skb_queue_purge(&msdu_list[i]);
4282 continue;
4283 }
4284
4285 ar = ab->pdevs[i].ar;
4286
4287 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4288 __skb_queue_purge(&msdu_list[i]);
4289 continue;
4290 }
4291
4292 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4293 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4294 }
4295 rcu_read_unlock();
4296 done:
4297 return total_num_buffs_reaped;
4298 }
4299
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4300 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4301 {
4302 struct ath11k *ar;
4303 struct dp_srng *err_ring;
4304 struct dp_rxdma_ring *rx_ring;
4305 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4306 struct hal_srng *srng;
4307 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4308 enum hal_rx_buf_return_buf_manager rbm;
4309 enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4310 struct ath11k_skb_rxcb *rxcb;
4311 struct sk_buff *skb;
4312 struct hal_reo_entrance_ring *entr_ring;
4313 void *desc;
4314 int num_buf_freed = 0;
4315 int quota = budget;
4316 dma_addr_t paddr;
4317 u32 desc_bank;
4318 void *link_desc_va;
4319 int num_msdus;
4320 int i;
4321 int buf_id;
4322
4323 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4324 err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4325 mac_id)];
4326 rx_ring = &ar->dp.rx_refill_buf_ring;
4327
4328 srng = &ab->hal.srng_list[err_ring->ring_id];
4329
4330 spin_lock_bh(&srng->lock);
4331
4332 ath11k_hal_srng_access_begin(ab, srng);
4333
4334 while (quota-- &&
4335 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4336 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4337
4338 entr_ring = (struct hal_reo_entrance_ring *)desc;
4339 rxdma_err_code =
4340 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4341 entr_ring->info1);
4342 ab->soc_stats.rxdma_error[rxdma_err_code]++;
4343
4344 #if defined(__linux__)
4345 link_desc_va = link_desc_banks[desc_bank].vaddr +
4346 #elif defined(__FreeBSD__)
4347 link_desc_va = (u8 *)link_desc_banks[desc_bank].vaddr +
4348 #endif
4349 (paddr - link_desc_banks[desc_bank].paddr);
4350 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4351 msdu_cookies, &rbm);
4352
4353 for (i = 0; i < num_msdus; i++) {
4354 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4355 msdu_cookies[i]);
4356
4357 spin_lock_bh(&rx_ring->idr_lock);
4358 skb = idr_find(&rx_ring->bufs_idr, buf_id);
4359 if (!skb) {
4360 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4361 buf_id);
4362 spin_unlock_bh(&rx_ring->idr_lock);
4363 continue;
4364 }
4365
4366 idr_remove(&rx_ring->bufs_idr, buf_id);
4367 spin_unlock_bh(&rx_ring->idr_lock);
4368
4369 rxcb = ATH11K_SKB_RXCB(skb);
4370 dma_unmap_single(ab->dev, rxcb->paddr,
4371 skb->len + skb_tailroom(skb),
4372 DMA_FROM_DEVICE);
4373 dev_kfree_skb_any(skb);
4374
4375 num_buf_freed++;
4376 }
4377
4378 ath11k_dp_rx_link_desc_return(ab, desc,
4379 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4380 }
4381
4382 ath11k_hal_srng_access_end(ab, srng);
4383
4384 spin_unlock_bh(&srng->lock);
4385
4386 if (num_buf_freed)
4387 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4388 ab->hw_params.hal_params->rx_buf_rbm);
4389
4390 return budget - quota;
4391 }
4392
ath11k_dp_process_reo_status(struct ath11k_base * ab)4393 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4394 {
4395 struct ath11k_dp *dp = &ab->dp;
4396 struct hal_srng *srng;
4397 struct dp_reo_cmd *cmd, *tmp;
4398 bool found = false;
4399 u32 *reo_desc;
4400 u16 tag;
4401 struct hal_reo_status reo_status;
4402
4403 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4404
4405 memset(&reo_status, 0, sizeof(reo_status));
4406
4407 spin_lock_bh(&srng->lock);
4408
4409 ath11k_hal_srng_access_begin(ab, srng);
4410
4411 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4412 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4413
4414 switch (tag) {
4415 case HAL_REO_GET_QUEUE_STATS_STATUS:
4416 ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4417 &reo_status);
4418 break;
4419 case HAL_REO_FLUSH_QUEUE_STATUS:
4420 ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4421 &reo_status);
4422 break;
4423 case HAL_REO_FLUSH_CACHE_STATUS:
4424 ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4425 &reo_status);
4426 break;
4427 case HAL_REO_UNBLOCK_CACHE_STATUS:
4428 ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4429 &reo_status);
4430 break;
4431 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4432 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4433 &reo_status);
4434 break;
4435 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4436 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4437 &reo_status);
4438 break;
4439 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4440 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4441 &reo_status);
4442 break;
4443 default:
4444 ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4445 continue;
4446 }
4447
4448 spin_lock_bh(&dp->reo_cmd_lock);
4449 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4450 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4451 found = true;
4452 list_del(&cmd->list);
4453 break;
4454 }
4455 }
4456 spin_unlock_bh(&dp->reo_cmd_lock);
4457
4458 if (found) {
4459 cmd->handler(dp, (void *)&cmd->data,
4460 reo_status.uniform_hdr.cmd_status);
4461 kfree(cmd);
4462 }
4463
4464 found = false;
4465 }
4466
4467 ath11k_hal_srng_access_end(ab, srng);
4468
4469 spin_unlock_bh(&srng->lock);
4470 }
4471
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4472 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4473 {
4474 struct ath11k *ar = ab->pdevs[mac_id].ar;
4475
4476 ath11k_dp_rx_pdev_srng_free(ar);
4477 ath11k_dp_rxdma_pdev_buf_free(ar);
4478 }
4479
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4480 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4481 {
4482 struct ath11k *ar = ab->pdevs[mac_id].ar;
4483 struct ath11k_pdev_dp *dp = &ar->dp;
4484 u32 ring_id;
4485 int i;
4486 int ret;
4487
4488 ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4489 if (ret) {
4490 ath11k_warn(ab, "failed to setup rx srngs\n");
4491 return ret;
4492 }
4493
4494 ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4495 if (ret) {
4496 ath11k_warn(ab, "failed to setup rxdma ring\n");
4497 return ret;
4498 }
4499
4500 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4501 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4502 if (ret) {
4503 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4504 ret);
4505 return ret;
4506 }
4507
4508 if (ab->hw_params.rx_mac_buf_ring) {
4509 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4510 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4511 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4512 mac_id + i, HAL_RXDMA_BUF);
4513 if (ret) {
4514 ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4515 i, ret);
4516 return ret;
4517 }
4518 }
4519 }
4520
4521 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4522 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4523 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4524 mac_id + i, HAL_RXDMA_DST);
4525 if (ret) {
4526 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4527 i, ret);
4528 return ret;
4529 }
4530 }
4531
4532 if (!ab->hw_params.rxdma1_enable)
4533 goto config_refill_ring;
4534
4535 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4536 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4537 mac_id, HAL_RXDMA_MONITOR_BUF);
4538 if (ret) {
4539 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4540 ret);
4541 return ret;
4542 }
4543 ret = ath11k_dp_tx_htt_srng_setup(ab,
4544 dp->rxdma_mon_dst_ring.ring_id,
4545 mac_id, HAL_RXDMA_MONITOR_DST);
4546 if (ret) {
4547 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4548 ret);
4549 return ret;
4550 }
4551 ret = ath11k_dp_tx_htt_srng_setup(ab,
4552 dp->rxdma_mon_desc_ring.ring_id,
4553 mac_id, HAL_RXDMA_MONITOR_DESC);
4554 if (ret) {
4555 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4556 ret);
4557 return ret;
4558 }
4559
4560 config_refill_ring:
4561 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4562 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4563 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4564 HAL_RXDMA_MONITOR_STATUS);
4565 if (ret) {
4566 ath11k_warn(ab,
4567 "failed to configure mon_status_refill_ring%d %d\n",
4568 i, ret);
4569 return ret;
4570 }
4571 }
4572
4573 return 0;
4574 }
4575
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4576 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4577 {
4578 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4579 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4580 *total_len -= *frag_len;
4581 } else {
4582 *frag_len = *total_len;
4583 *total_len = 0;
4584 }
4585 }
4586
4587 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4588 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4589 void *p_last_buf_addr_info,
4590 u8 mac_id)
4591 {
4592 struct ath11k_pdev_dp *dp = &ar->dp;
4593 struct dp_srng *dp_srng;
4594 void *hal_srng;
4595 void *src_srng_desc;
4596 int ret = 0;
4597
4598 if (ar->ab->hw_params.rxdma1_enable) {
4599 dp_srng = &dp->rxdma_mon_desc_ring;
4600 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4601 } else {
4602 dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4603 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4604 }
4605
4606 ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4607
4608 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4609
4610 if (src_srng_desc) {
4611 struct ath11k_buffer_addr *src_desc = src_srng_desc;
4612
4613 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4614 } else {
4615 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4616 "Monitor Link Desc Ring %d Full", mac_id);
4617 ret = -ENOMEM;
4618 }
4619
4620 ath11k_hal_srng_access_end(ar->ab, hal_srng);
4621 return ret;
4622 }
4623
4624 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4625 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4626 dma_addr_t *paddr, u32 *sw_cookie,
4627 u8 *rbm,
4628 void **pp_buf_addr_info)
4629 {
4630 struct hal_rx_msdu_link *msdu_link = rx_msdu_link_desc;
4631 struct ath11k_buffer_addr *buf_addr_info;
4632
4633 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4634
4635 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4636
4637 *pp_buf_addr_info = (void *)buf_addr_info;
4638 }
4639
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4640 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4641 {
4642 if (skb->len > len) {
4643 skb_trim(skb, len);
4644 } else {
4645 if (skb_tailroom(skb) < len - skb->len) {
4646 if ((pskb_expand_head(skb, 0,
4647 len - skb->len - skb_tailroom(skb),
4648 GFP_ATOMIC))) {
4649 dev_kfree_skb_any(skb);
4650 return -ENOMEM;
4651 }
4652 }
4653 skb_put(skb, (len - skb->len));
4654 }
4655 return 0;
4656 }
4657
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4658 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4659 void *msdu_link_desc,
4660 struct hal_rx_msdu_list *msdu_list,
4661 u16 *num_msdus)
4662 {
4663 struct hal_rx_msdu_details *msdu_details = NULL;
4664 struct rx_msdu_desc *msdu_desc_info = NULL;
4665 struct hal_rx_msdu_link *msdu_link = NULL;
4666 int i;
4667 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4668 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4669 u8 tmp = 0;
4670
4671 msdu_link = msdu_link_desc;
4672 msdu_details = &msdu_link->msdu_link[0];
4673
4674 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4675 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4676 msdu_details[i].buf_addr_info.info0) == 0) {
4677 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4678 msdu_desc_info->info0 |= last;
4679 break;
4680 }
4681 msdu_desc_info = &msdu_details[i].rx_msdu_info;
4682
4683 if (!i)
4684 msdu_desc_info->info0 |= first;
4685 else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4686 msdu_desc_info->info0 |= last;
4687 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4688 msdu_list->msdu_info[i].msdu_len =
4689 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4690 msdu_list->sw_cookie[i] =
4691 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4692 msdu_details[i].buf_addr_info.info1);
4693 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4694 msdu_details[i].buf_addr_info.info1);
4695 msdu_list->rbm[i] = tmp;
4696 }
4697 *num_msdus = i;
4698 }
4699
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4700 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4701 u32 *rx_bufs_used)
4702 {
4703 u32 ret = 0;
4704
4705 if ((*ppdu_id < msdu_ppdu_id) &&
4706 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4707 *ppdu_id = msdu_ppdu_id;
4708 ret = msdu_ppdu_id;
4709 } else if ((*ppdu_id > msdu_ppdu_id) &&
4710 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4711 /* mon_dst is behind than mon_status
4712 * skip dst_ring and free it
4713 */
4714 *rx_bufs_used += 1;
4715 *ppdu_id = msdu_ppdu_id;
4716 ret = msdu_ppdu_id;
4717 }
4718 return ret;
4719 }
4720
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4721 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4722 bool *is_frag, u32 *total_len,
4723 u32 *frag_len, u32 *msdu_cnt)
4724 {
4725 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4726 if (!*is_frag) {
4727 *total_len = info->msdu_len;
4728 *is_frag = true;
4729 }
4730 ath11k_dp_mon_set_frag_len(total_len,
4731 frag_len);
4732 } else {
4733 if (*is_frag) {
4734 ath11k_dp_mon_set_frag_len(total_len,
4735 frag_len);
4736 } else {
4737 *frag_len = info->msdu_len;
4738 }
4739 *is_frag = false;
4740 *msdu_cnt -= 1;
4741 }
4742 }
4743
4744 /* clang stack usage explodes if this is inlined */
4745 static noinline_for_stack
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4746 u32 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4747 void *ring_entry, struct sk_buff **head_msdu,
4748 struct sk_buff **tail_msdu, u32 *npackets,
4749 u32 *ppdu_id)
4750 {
4751 struct ath11k_pdev_dp *dp = &ar->dp;
4752 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4753 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4754 struct sk_buff *msdu = NULL, *last = NULL;
4755 struct hal_rx_msdu_list msdu_list;
4756 void *p_buf_addr_info, *p_last_buf_addr_info;
4757 struct hal_rx_desc *rx_desc;
4758 void *rx_msdu_link_desc;
4759 dma_addr_t paddr;
4760 u16 num_msdus = 0;
4761 u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4762 u32 rx_bufs_used = 0, i = 0;
4763 u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4764 u32 total_len = 0, frag_len = 0;
4765 bool is_frag, is_first_msdu;
4766 bool drop_mpdu = false;
4767 struct ath11k_skb_rxcb *rxcb;
4768 struct hal_reo_entrance_ring *ent_desc = ring_entry;
4769 int buf_id;
4770 u32 rx_link_buf_info[2];
4771 u8 rbm;
4772
4773 if (!ar->ab->hw_params.rxdma1_enable)
4774 rx_ring = &dp->rx_refill_buf_ring;
4775
4776 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4777 &sw_cookie,
4778 &p_last_buf_addr_info, &rbm,
4779 &msdu_cnt);
4780
4781 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4782 ent_desc->info1) ==
4783 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4784 u8 rxdma_err =
4785 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4786 ent_desc->info1);
4787 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4788 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4789 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4790 drop_mpdu = true;
4791 pmon->rx_mon_stats.dest_mpdu_drop++;
4792 }
4793 }
4794
4795 is_frag = false;
4796 is_first_msdu = true;
4797
4798 do {
4799 if (pmon->mon_last_linkdesc_paddr == paddr) {
4800 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4801 return rx_bufs_used;
4802 }
4803
4804 if (ar->ab->hw_params.rxdma1_enable)
4805 rx_msdu_link_desc =
4806 #if defined(__linux__)
4807 (void *)pmon->link_desc_banks[sw_cookie].vaddr +
4808 #elif defined(__FreeBSD__)
4809 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
4810 #endif
4811 (paddr - pmon->link_desc_banks[sw_cookie].paddr);
4812 else
4813 rx_msdu_link_desc =
4814 #if defined(__linux__)
4815 (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4816 #elif defined(__FreeBSD__)
4817 (u8 *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4818 #endif
4819 (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4820
4821 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4822 &num_msdus);
4823
4824 for (i = 0; i < num_msdus; i++) {
4825 u32 l2_hdr_offset;
4826
4827 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4828 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4829 "i %d last_cookie %d is same\n",
4830 i, pmon->mon_last_buf_cookie);
4831 drop_mpdu = true;
4832 pmon->rx_mon_stats.dup_mon_buf_cnt++;
4833 continue;
4834 }
4835 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4836 msdu_list.sw_cookie[i]);
4837
4838 spin_lock_bh(&rx_ring->idr_lock);
4839 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4840 spin_unlock_bh(&rx_ring->idr_lock);
4841 if (!msdu) {
4842 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4843 "msdu_pop: invalid buf_id %d\n", buf_id);
4844 goto next_msdu;
4845 }
4846 rxcb = ATH11K_SKB_RXCB(msdu);
4847 if (!rxcb->unmapped) {
4848 dma_unmap_single(ar->ab->dev, rxcb->paddr,
4849 msdu->len +
4850 skb_tailroom(msdu),
4851 DMA_FROM_DEVICE);
4852 rxcb->unmapped = 1;
4853 }
4854 if (drop_mpdu) {
4855 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4856 "i %d drop msdu %p *ppdu_id %x\n",
4857 i, msdu, *ppdu_id);
4858 dev_kfree_skb_any(msdu);
4859 msdu = NULL;
4860 goto next_msdu;
4861 }
4862
4863 rx_desc = (struct hal_rx_desc *)msdu->data;
4864
4865 rx_pkt_offset = sizeof(struct hal_rx_desc);
4866 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4867
4868 if (is_first_msdu) {
4869 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4870 drop_mpdu = true;
4871 dev_kfree_skb_any(msdu);
4872 msdu = NULL;
4873 pmon->mon_last_linkdesc_paddr = paddr;
4874 goto next_msdu;
4875 }
4876
4877 msdu_ppdu_id =
4878 ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4879
4880 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4881 ppdu_id,
4882 &rx_bufs_used)) {
4883 if (rx_bufs_used) {
4884 drop_mpdu = true;
4885 dev_kfree_skb_any(msdu);
4886 msdu = NULL;
4887 goto next_msdu;
4888 }
4889 return rx_bufs_used;
4890 }
4891 pmon->mon_last_linkdesc_paddr = paddr;
4892 is_first_msdu = false;
4893 }
4894 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4895 &is_frag, &total_len,
4896 &frag_len, &msdu_cnt);
4897 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4898
4899 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4900
4901 if (!(*head_msdu))
4902 *head_msdu = msdu;
4903 else if (last)
4904 last->next = msdu;
4905
4906 last = msdu;
4907 next_msdu:
4908 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4909 rx_bufs_used++;
4910 spin_lock_bh(&rx_ring->idr_lock);
4911 idr_remove(&rx_ring->bufs_idr, buf_id);
4912 spin_unlock_bh(&rx_ring->idr_lock);
4913 }
4914
4915 ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4916
4917 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4918 &sw_cookie, &rbm,
4919 &p_buf_addr_info);
4920
4921 if (ar->ab->hw_params.rxdma1_enable) {
4922 if (ath11k_dp_rx_monitor_link_desc_return(ar,
4923 p_last_buf_addr_info,
4924 dp->mac_id))
4925 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4926 "dp_rx_monitor_link_desc_return failed");
4927 } else {
4928 ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4929 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4930 }
4931
4932 p_last_buf_addr_info = p_buf_addr_info;
4933
4934 } while (paddr && msdu_cnt);
4935
4936 if (last)
4937 last->next = NULL;
4938
4939 *tail_msdu = msdu;
4940
4941 if (msdu_cnt == 0)
4942 *npackets = 1;
4943
4944 return rx_bufs_used;
4945 }
4946
ath11k_dp_rx_msdus_set_payload(struct ath11k * ar,struct sk_buff * msdu)4947 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4948 {
4949 u32 rx_pkt_offset, l2_hdr_offset;
4950
4951 rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4952 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4953 (struct hal_rx_desc *)msdu->data);
4954 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4955 }
4956
4957 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)4958 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4959 u32 mac_id, struct sk_buff *head_msdu,
4960 struct sk_buff *last_msdu,
4961 struct ieee80211_rx_status *rxs, bool *fcs_err)
4962 {
4963 struct ath11k_base *ab = ar->ab;
4964 struct sk_buff *msdu, *prev_buf;
4965 struct hal_rx_desc *rx_desc;
4966 char *hdr_desc;
4967 u8 *dest, decap_format;
4968 struct ieee80211_hdr_3addr *wh;
4969 struct rx_attention *rx_attention;
4970 u32 err_bitmap;
4971
4972 if (!head_msdu)
4973 goto err_merge_fail;
4974
4975 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4976 rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4977 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
4978
4979 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
4980 *fcs_err = true;
4981
4982 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4983 return NULL;
4984
4985 decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4986
4987 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4988
4989 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4990 ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4991
4992 prev_buf = head_msdu;
4993 msdu = head_msdu->next;
4994
4995 while (msdu) {
4996 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4997
4998 prev_buf = msdu;
4999 msdu = msdu->next;
5000 }
5001
5002 prev_buf->next = NULL;
5003
5004 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
5005 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
5006 u8 qos_pkt = 0;
5007
5008 rx_desc = (struct hal_rx_desc *)head_msdu->data;
5009 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
5010
5011 /* Base size */
5012 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
5013
5014 if (ieee80211_is_data_qos(wh->frame_control))
5015 qos_pkt = 1;
5016
5017 msdu = head_msdu;
5018
5019 while (msdu) {
5020 ath11k_dp_rx_msdus_set_payload(ar, msdu);
5021 if (qos_pkt) {
5022 dest = skb_push(msdu, sizeof(__le16));
5023 if (!dest)
5024 goto err_merge_fail;
5025 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
5026 }
5027 prev_buf = msdu;
5028 msdu = msdu->next;
5029 }
5030 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
5031 if (!dest)
5032 goto err_merge_fail;
5033
5034 ath11k_dbg(ab, ATH11K_DBG_DATA,
5035 "mpdu_buf %p mpdu_buf->len %u",
5036 prev_buf, prev_buf->len);
5037 } else {
5038 ath11k_dbg(ab, ATH11K_DBG_DATA,
5039 "decap format %d is not supported!\n",
5040 decap_format);
5041 goto err_merge_fail;
5042 }
5043
5044 return head_msdu;
5045
5046 err_merge_fail:
5047 return NULL;
5048 }
5049
5050 static void
ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)5051 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
5052 u8 *rtap_buf)
5053 {
5054 u32 rtap_len = 0;
5055
5056 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
5057 rtap_len += 2;
5058
5059 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
5060 rtap_len += 2;
5061
5062 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
5063 rtap_len += 2;
5064
5065 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
5066 rtap_len += 2;
5067
5068 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
5069 rtap_len += 2;
5070
5071 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
5072 }
5073
5074 static void
ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)5075 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
5076 u8 *rtap_buf)
5077 {
5078 u32 rtap_len = 0;
5079
5080 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
5081 rtap_len += 2;
5082
5083 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
5084 rtap_len += 2;
5085
5086 rtap_buf[rtap_len] = rx_status->he_RU[0];
5087 rtap_len += 1;
5088
5089 rtap_buf[rtap_len] = rx_status->he_RU[1];
5090 rtap_len += 1;
5091
5092 rtap_buf[rtap_len] = rx_status->he_RU[2];
5093 rtap_len += 1;
5094
5095 rtap_buf[rtap_len] = rx_status->he_RU[3];
5096 }
5097
ath11k_update_radiotap(struct ath11k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)5098 static void ath11k_update_radiotap(struct ath11k *ar,
5099 struct hal_rx_mon_ppdu_info *ppduinfo,
5100 struct sk_buff *mon_skb,
5101 struct ieee80211_rx_status *rxs)
5102 {
5103 struct ieee80211_supported_band *sband;
5104 u8 *ptr = NULL;
5105
5106 rxs->flag |= RX_FLAG_MACTIME_START;
5107 rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR;
5108
5109 if (ppduinfo->nss)
5110 rxs->nss = ppduinfo->nss;
5111
5112 if (ppduinfo->he_mu_flags) {
5113 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
5114 rxs->encoding = RX_ENC_HE;
5115 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
5116 ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr);
5117 } else if (ppduinfo->he_flags) {
5118 rxs->flag |= RX_FLAG_RADIOTAP_HE;
5119 rxs->encoding = RX_ENC_HE;
5120 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
5121 ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr);
5122 rxs->rate_idx = ppduinfo->rate;
5123 } else if (ppduinfo->vht_flags) {
5124 rxs->encoding = RX_ENC_VHT;
5125 rxs->rate_idx = ppduinfo->rate;
5126 } else if (ppduinfo->ht_flags) {
5127 rxs->encoding = RX_ENC_HT;
5128 rxs->rate_idx = ppduinfo->rate;
5129 } else {
5130 rxs->encoding = RX_ENC_LEGACY;
5131 sband = &ar->mac.sbands[rxs->band];
5132 rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
5133 ppduinfo->cck_flag);
5134 }
5135
5136 rxs->mactime = ppduinfo->tsft;
5137 }
5138
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * tail_msdu,struct napi_struct * napi)5139 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
5140 struct sk_buff *head_msdu,
5141 struct hal_rx_mon_ppdu_info *ppduinfo,
5142 struct sk_buff *tail_msdu,
5143 struct napi_struct *napi)
5144 {
5145 struct ath11k_pdev_dp *dp = &ar->dp;
5146 struct sk_buff *mon_skb, *skb_next, *header;
5147 struct ieee80211_rx_status *rxs = &dp->rx_status;
5148 bool fcs_err = false;
5149
5150 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
5151 tail_msdu, rxs, &fcs_err);
5152
5153 if (!mon_skb)
5154 goto mon_deliver_fail;
5155
5156 header = mon_skb;
5157
5158 rxs->flag = 0;
5159
5160 if (fcs_err)
5161 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
5162
5163 do {
5164 skb_next = mon_skb->next;
5165 if (!skb_next)
5166 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
5167 else
5168 rxs->flag |= RX_FLAG_AMSDU_MORE;
5169
5170 if (mon_skb == header) {
5171 header = NULL;
5172 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
5173 } else {
5174 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
5175 }
5176 rxs->flag |= RX_FLAG_ONLY_MONITOR;
5177 ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs);
5178
5179 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
5180 mon_skb = skb_next;
5181 } while (mon_skb);
5182 rxs->flag = 0;
5183
5184 return 0;
5185
5186 mon_deliver_fail:
5187 mon_skb = head_msdu;
5188 while (mon_skb) {
5189 skb_next = mon_skb->next;
5190 dev_kfree_skb_any(mon_skb);
5191 mon_skb = skb_next;
5192 }
5193 return -EINVAL;
5194 }
5195
5196 /* The destination ring processing is stuck if the destination is not
5197 * moving while status ring moves 16 PPDU. The destination ring processing
5198 * skips this destination ring PPDU as a workaround.
5199 */
5200 #define MON_DEST_RING_STUCK_MAX_CNT 16
5201
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)5202 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
5203 u32 quota, struct napi_struct *napi)
5204 {
5205 struct ath11k_pdev_dp *dp = &ar->dp;
5206 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5207 const struct ath11k_hw_hal_params *hal_params;
5208 void *ring_entry;
5209 struct hal_srng *mon_dst_srng;
5210 u32 ppdu_id;
5211 u32 rx_bufs_used;
5212 u32 ring_id;
5213 struct ath11k_pdev_mon_stats *rx_mon_stats;
5214 u32 npackets = 0;
5215 u32 mpdu_rx_bufs_used;
5216
5217 if (ar->ab->hw_params.rxdma1_enable)
5218 ring_id = dp->rxdma_mon_dst_ring.ring_id;
5219 else
5220 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
5221
5222 mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
5223
5224 spin_lock_bh(&pmon->mon_lock);
5225
5226 spin_lock_bh(&mon_dst_srng->lock);
5227 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5228
5229 ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5230 rx_bufs_used = 0;
5231 rx_mon_stats = &pmon->rx_mon_stats;
5232
5233 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5234 struct sk_buff *head_msdu, *tail_msdu;
5235
5236 head_msdu = NULL;
5237 tail_msdu = NULL;
5238
5239 mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5240 &head_msdu,
5241 &tail_msdu,
5242 &npackets, &ppdu_id);
5243
5244 rx_bufs_used += mpdu_rx_bufs_used;
5245
5246 if (mpdu_rx_bufs_used) {
5247 dp->mon_dest_ring_stuck_cnt = 0;
5248 } else {
5249 dp->mon_dest_ring_stuck_cnt++;
5250 rx_mon_stats->dest_mon_not_reaped++;
5251 }
5252
5253 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
5254 rx_mon_stats->dest_mon_stuck++;
5255 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5256 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
5257 pmon->mon_ppdu_info.ppdu_id, ppdu_id,
5258 dp->mon_dest_ring_stuck_cnt,
5259 rx_mon_stats->dest_mon_not_reaped,
5260 rx_mon_stats->dest_mon_stuck);
5261 pmon->mon_ppdu_info.ppdu_id = ppdu_id;
5262 continue;
5263 }
5264
5265 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5266 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5267 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5268 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
5269 ppdu_id, pmon->mon_ppdu_info.ppdu_id,
5270 rx_mon_stats->dest_mon_not_reaped,
5271 rx_mon_stats->dest_mon_stuck);
5272 break;
5273 }
5274 if (head_msdu && tail_msdu) {
5275 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5276 &pmon->mon_ppdu_info,
5277 tail_msdu, napi);
5278 rx_mon_stats->dest_mpdu_done++;
5279 }
5280
5281 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5282 mon_dst_srng);
5283 }
5284 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5285 spin_unlock_bh(&mon_dst_srng->lock);
5286
5287 spin_unlock_bh(&pmon->mon_lock);
5288
5289 if (rx_bufs_used) {
5290 rx_mon_stats->dest_ppdu_done++;
5291 hal_params = ar->ab->hw_params.hal_params;
5292
5293 if (ar->ab->hw_params.rxdma1_enable)
5294 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5295 &dp->rxdma_mon_buf_ring,
5296 rx_bufs_used,
5297 hal_params->rx_buf_rbm);
5298 else
5299 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5300 &dp->rx_refill_buf_ring,
5301 rx_bufs_used,
5302 hal_params->rx_buf_rbm);
5303 }
5304 }
5305
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5306 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
5307 struct napi_struct *napi, int budget)
5308 {
5309 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5310 enum hal_rx_mon_status hal_status;
5311 struct sk_buff *skb;
5312 struct sk_buff_head skb_list;
5313 struct ath11k_peer *peer;
5314 struct ath11k_sta *arsta;
5315 int num_buffs_reaped = 0;
5316 u32 rx_buf_sz;
5317 u16 log_type;
5318 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data;
5319 struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
5320 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
5321
5322 __skb_queue_head_init(&skb_list);
5323
5324 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
5325 &skb_list);
5326 if (!num_buffs_reaped)
5327 goto exit;
5328
5329 memset(ppdu_info, 0, sizeof(*ppdu_info));
5330 ppdu_info->peer_id = HAL_INVALID_PEERID;
5331
5332 while ((skb = __skb_dequeue(&skb_list))) {
5333 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
5334 log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
5335 rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
5336 } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
5337 log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
5338 rx_buf_sz = DP_RX_BUFFER_SIZE;
5339 } else {
5340 log_type = ATH11K_PKTLOG_TYPE_INVALID;
5341 rx_buf_sz = 0;
5342 }
5343
5344 if (log_type != ATH11K_PKTLOG_TYPE_INVALID)
5345 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5346
5347 memset(ppdu_info, 0, sizeof(*ppdu_info));
5348 ppdu_info->peer_id = HAL_INVALID_PEERID;
5349 hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb);
5350
5351 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5352 pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
5353 hal_status == HAL_TLV_STATUS_PPDU_DONE) {
5354 rx_mon_stats->status_ppdu_done++;
5355 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5356 if (!ab->hw_params.full_monitor_mode) {
5357 ath11k_dp_rx_mon_dest_process(ar, mac_id,
5358 budget, napi);
5359 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5360 }
5361 }
5362
5363 if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
5364 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
5365 dev_kfree_skb_any(skb);
5366 continue;
5367 }
5368
5369 rcu_read_lock();
5370 spin_lock_bh(&ab->base_lock);
5371 peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id);
5372
5373 if (!peer || !peer->sta) {
5374 ath11k_dbg(ab, ATH11K_DBG_DATA,
5375 "failed to find the peer with peer_id %d\n",
5376 ppdu_info->peer_id);
5377 goto next_skb;
5378 }
5379
5380 arsta = ath11k_sta_to_arsta(peer->sta);
5381 ath11k_dp_rx_update_peer_stats(arsta, ppdu_info);
5382
5383 if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
5384 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5385
5386 next_skb:
5387 spin_unlock_bh(&ab->base_lock);
5388 rcu_read_unlock();
5389
5390 dev_kfree_skb_any(skb);
5391 memset(ppdu_info, 0, sizeof(*ppdu_info));
5392 ppdu_info->peer_id = HAL_INVALID_PEERID;
5393 }
5394 exit:
5395 return num_buffs_reaped;
5396 }
5397
5398 static u32
ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k * ar,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,struct hal_sw_mon_ring_entries * sw_mon_entries)5399 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
5400 void *ring_entry, struct sk_buff **head_msdu,
5401 struct sk_buff **tail_msdu,
5402 struct hal_sw_mon_ring_entries *sw_mon_entries)
5403 {
5404 struct ath11k_pdev_dp *dp = &ar->dp;
5405 struct ath11k_mon_data *pmon = &dp->mon_data;
5406 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
5407 struct sk_buff *msdu = NULL, *last = NULL;
5408 struct hal_sw_monitor_ring *sw_desc = ring_entry;
5409 struct hal_rx_msdu_list msdu_list;
5410 struct hal_rx_desc *rx_desc;
5411 struct ath11k_skb_rxcb *rxcb;
5412 void *rx_msdu_link_desc;
5413 void *p_buf_addr_info, *p_last_buf_addr_info;
5414 int buf_id, i = 0;
5415 u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
5416 u32 rx_bufs_used = 0, msdu_cnt = 0;
5417 u32 total_len = 0, frag_len = 0, sw_cookie;
5418 u16 num_msdus = 0;
5419 u8 rxdma_err, rbm;
5420 bool is_frag, is_first_msdu;
5421 bool drop_mpdu = false;
5422
5423 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
5424
5425 sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
5426 sw_mon_entries->end_of_ppdu = false;
5427 sw_mon_entries->drop_ppdu = false;
5428 p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
5429 msdu_cnt = sw_mon_entries->msdu_cnt;
5430
5431 sw_mon_entries->end_of_ppdu =
5432 FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
5433 if (sw_mon_entries->end_of_ppdu)
5434 return rx_bufs_used;
5435
5436 if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
5437 sw_desc->info0) ==
5438 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
5439 rxdma_err =
5440 FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
5441 sw_desc->info0);
5442 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
5443 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
5444 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
5445 pmon->rx_mon_stats.dest_mpdu_drop++;
5446 drop_mpdu = true;
5447 }
5448 }
5449
5450 is_frag = false;
5451 is_first_msdu = true;
5452
5453 do {
5454 rx_msdu_link_desc =
5455 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
5456 (sw_mon_entries->mon_dst_paddr -
5457 pmon->link_desc_banks[sw_cookie].paddr);
5458
5459 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
5460 &num_msdus);
5461
5462 for (i = 0; i < num_msdus; i++) {
5463 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
5464 msdu_list.sw_cookie[i]);
5465
5466 spin_lock_bh(&rx_ring->idr_lock);
5467 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
5468 if (!msdu) {
5469 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5470 "full mon msdu_pop: invalid buf_id %d\n",
5471 buf_id);
5472 spin_unlock_bh(&rx_ring->idr_lock);
5473 goto next_msdu;
5474 }
5475 idr_remove(&rx_ring->bufs_idr, buf_id);
5476 spin_unlock_bh(&rx_ring->idr_lock);
5477
5478 rxcb = ATH11K_SKB_RXCB(msdu);
5479 if (!rxcb->unmapped) {
5480 dma_unmap_single(ar->ab->dev, rxcb->paddr,
5481 msdu->len +
5482 skb_tailroom(msdu),
5483 DMA_FROM_DEVICE);
5484 rxcb->unmapped = 1;
5485 }
5486 if (drop_mpdu) {
5487 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5488 "full mon: i %d drop msdu %p *ppdu_id %x\n",
5489 i, msdu, sw_mon_entries->ppdu_id);
5490 dev_kfree_skb_any(msdu);
5491 msdu_cnt--;
5492 goto next_msdu;
5493 }
5494
5495 rx_desc = (struct hal_rx_desc *)msdu->data;
5496
5497 rx_pkt_offset = sizeof(struct hal_rx_desc);
5498 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
5499
5500 if (is_first_msdu) {
5501 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
5502 drop_mpdu = true;
5503 dev_kfree_skb_any(msdu);
5504 msdu = NULL;
5505 goto next_msdu;
5506 }
5507 is_first_msdu = false;
5508 }
5509
5510 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
5511 &is_frag, &total_len,
5512 &frag_len, &msdu_cnt);
5513
5514 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
5515
5516 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
5517
5518 if (!(*head_msdu))
5519 *head_msdu = msdu;
5520 else if (last)
5521 last->next = msdu;
5522
5523 last = msdu;
5524 next_msdu:
5525 rx_bufs_used++;
5526 }
5527
5528 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
5529 &sw_mon_entries->mon_dst_paddr,
5530 &sw_mon_entries->mon_dst_sw_cookie,
5531 &rbm,
5532 &p_buf_addr_info);
5533
5534 if (ath11k_dp_rx_monitor_link_desc_return(ar,
5535 p_last_buf_addr_info,
5536 dp->mac_id))
5537 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5538 "full mon: dp_rx_monitor_link_desc_return failed\n");
5539
5540 p_last_buf_addr_info = p_buf_addr_info;
5541
5542 } while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
5543
5544 if (last)
5545 last->next = NULL;
5546
5547 *tail_msdu = msdu;
5548
5549 return rx_bufs_used;
5550 }
5551
ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu,struct sk_buff * head,struct sk_buff * tail)5552 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
5553 struct dp_full_mon_mpdu *mon_mpdu,
5554 struct sk_buff *head,
5555 struct sk_buff *tail)
5556 {
5557 mon_mpdu = kzalloc_obj(*mon_mpdu, GFP_ATOMIC);
5558 if (!mon_mpdu)
5559 return -ENOMEM;
5560
5561 list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
5562 mon_mpdu->head = head;
5563 mon_mpdu->tail = tail;
5564
5565 return 0;
5566 }
5567
ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu)5568 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
5569 struct dp_full_mon_mpdu *mon_mpdu)
5570 {
5571 struct dp_full_mon_mpdu *tmp;
5572 struct sk_buff *tmp_msdu, *skb_next;
5573
5574 if (list_empty(&dp->dp_full_mon_mpdu_list))
5575 return;
5576
5577 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5578 list_del(&mon_mpdu->list);
5579
5580 tmp_msdu = mon_mpdu->head;
5581 while (tmp_msdu) {
5582 skb_next = tmp_msdu->next;
5583 dev_kfree_skb_any(tmp_msdu);
5584 tmp_msdu = skb_next;
5585 }
5586
5587 kfree(mon_mpdu);
5588 }
5589 }
5590
ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k * ar,int mac_id,struct ath11k_mon_data * pmon,struct napi_struct * napi)5591 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
5592 int mac_id,
5593 struct ath11k_mon_data *pmon,
5594 struct napi_struct *napi)
5595 {
5596 struct ath11k_pdev_mon_stats *rx_mon_stats;
5597 struct dp_full_mon_mpdu *tmp;
5598 struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
5599 struct sk_buff *head_msdu, *tail_msdu;
5600 struct ath11k_base *ab = ar->ab;
5601 struct ath11k_dp *dp = &ab->dp;
5602 int ret;
5603
5604 rx_mon_stats = &pmon->rx_mon_stats;
5605
5606 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5607 list_del(&mon_mpdu->list);
5608 head_msdu = mon_mpdu->head;
5609 tail_msdu = mon_mpdu->tail;
5610 if (head_msdu && tail_msdu) {
5611 ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
5612 &pmon->mon_ppdu_info,
5613 tail_msdu, napi);
5614 rx_mon_stats->dest_mpdu_done++;
5615 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
5616 }
5617 kfree(mon_mpdu);
5618 }
5619
5620 return ret;
5621 }
5622
5623 static int
ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5624 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
5625 struct napi_struct *napi, int budget)
5626 {
5627 struct ath11k *ar = ab->pdevs[mac_id].ar;
5628 struct ath11k_pdev_dp *dp = &ar->dp;
5629 struct ath11k_mon_data *pmon = &dp->mon_data;
5630 struct hal_sw_mon_ring_entries *sw_mon_entries;
5631 int quota = 0, work = 0, count;
5632
5633 sw_mon_entries = &pmon->sw_mon_entries;
5634
5635 while (pmon->hold_mon_dst_ring) {
5636 quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
5637 napi, 1);
5638 if (pmon->buf_state == DP_MON_STATUS_MATCH) {
5639 count = sw_mon_entries->status_buf_count;
5640 if (count > 1) {
5641 quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
5642 napi, count);
5643 }
5644
5645 ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
5646 pmon, napi);
5647 pmon->hold_mon_dst_ring = false;
5648 } else if (!pmon->mon_status_paddr ||
5649 pmon->buf_state == DP_MON_STATUS_LEAD) {
5650 sw_mon_entries->drop_ppdu = true;
5651 pmon->hold_mon_dst_ring = false;
5652 }
5653
5654 if (!quota)
5655 break;
5656
5657 work += quota;
5658 }
5659
5660 if (sw_mon_entries->drop_ppdu)
5661 ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
5662
5663 return work;
5664 }
5665
ath11k_dp_full_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5666 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
5667 struct napi_struct *napi, int budget)
5668 {
5669 struct ath11k *ar = ab->pdevs[mac_id].ar;
5670 struct ath11k_pdev_dp *dp = &ar->dp;
5671 struct ath11k_mon_data *pmon = &dp->mon_data;
5672 struct hal_sw_mon_ring_entries *sw_mon_entries;
5673 struct ath11k_pdev_mon_stats *rx_mon_stats;
5674 struct sk_buff *head_msdu, *tail_msdu;
5675 struct hal_srng *mon_dst_srng;
5676 void *ring_entry;
5677 u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
5678 int quota = 0, ret;
5679 bool break_dst_ring = false;
5680
5681 spin_lock_bh(&pmon->mon_lock);
5682
5683 sw_mon_entries = &pmon->sw_mon_entries;
5684 rx_mon_stats = &pmon->rx_mon_stats;
5685
5686 if (pmon->hold_mon_dst_ring) {
5687 spin_unlock_bh(&pmon->mon_lock);
5688 goto reap_status_ring;
5689 }
5690
5691 mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
5692 spin_lock_bh(&mon_dst_srng->lock);
5693
5694 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5695 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5696 head_msdu = NULL;
5697 tail_msdu = NULL;
5698
5699 mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
5700 &head_msdu,
5701 &tail_msdu,
5702 sw_mon_entries);
5703 rx_bufs_used += mpdu_rx_bufs_used;
5704
5705 if (!sw_mon_entries->end_of_ppdu) {
5706 if (head_msdu) {
5707 ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
5708 pmon->mon_mpdu,
5709 head_msdu,
5710 tail_msdu);
5711 if (ret)
5712 break_dst_ring = true;
5713 }
5714
5715 goto next_entry;
5716 } else {
5717 if (!sw_mon_entries->ppdu_id &&
5718 !sw_mon_entries->mon_status_paddr) {
5719 break_dst_ring = true;
5720 goto next_entry;
5721 }
5722 }
5723
5724 rx_mon_stats->dest_ppdu_done++;
5725 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5726 pmon->buf_state = DP_MON_STATUS_LAG;
5727 pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
5728 pmon->hold_mon_dst_ring = true;
5729 next_entry:
5730 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5731 mon_dst_srng);
5732 if (break_dst_ring)
5733 break;
5734 }
5735
5736 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5737 spin_unlock_bh(&mon_dst_srng->lock);
5738 spin_unlock_bh(&pmon->mon_lock);
5739
5740 if (rx_bufs_used) {
5741 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5742 &dp->rxdma_mon_buf_ring,
5743 rx_bufs_used,
5744 HAL_RX_BUF_RBM_SW3_BM);
5745 }
5746
5747 reap_status_ring:
5748 quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
5749 napi, budget);
5750
5751 return quota;
5752 }
5753
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5754 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5755 struct napi_struct *napi, int budget)
5756 {
5757 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5758 int ret = 0;
5759
5760 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5761 ab->hw_params.full_monitor_mode)
5762 ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
5763 else
5764 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5765
5766 return ret;
5767 }
5768
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)5769 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5770 {
5771 struct ath11k_pdev_dp *dp = &ar->dp;
5772 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5773
5774 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5775
5776 memset(&pmon->rx_mon_stats, 0,
5777 sizeof(pmon->rx_mon_stats));
5778 return 0;
5779 }
5780
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5781 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5782 {
5783 struct ath11k_pdev_dp *dp = &ar->dp;
5784 struct ath11k_mon_data *pmon = &dp->mon_data;
5785 struct hal_srng *mon_desc_srng = NULL;
5786 struct dp_srng *dp_srng;
5787 int ret = 0;
5788 u32 n_link_desc = 0;
5789
5790 ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5791 if (ret) {
5792 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5793 return ret;
5794 }
5795
5796 /* if rxdma1_enable is false, no need to setup
5797 * rxdma_mon_desc_ring.
5798 */
5799 if (!ar->ab->hw_params.rxdma1_enable)
5800 return 0;
5801
5802 dp_srng = &dp->rxdma_mon_desc_ring;
5803 n_link_desc = dp_srng->size /
5804 ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5805 mon_desc_srng =
5806 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5807
5808 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5809 HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5810 n_link_desc);
5811 if (ret) {
5812 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5813 return ret;
5814 }
5815 pmon->mon_last_linkdesc_paddr = 0;
5816 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5817 spin_lock_init(&pmon->mon_lock);
5818
5819 return 0;
5820 }
5821
ath11k_dp_mon_link_free(struct ath11k * ar)5822 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5823 {
5824 struct ath11k_pdev_dp *dp = &ar->dp;
5825 struct ath11k_mon_data *pmon = &dp->mon_data;
5826
5827 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5828 HAL_RXDMA_MONITOR_DESC,
5829 &dp->rxdma_mon_desc_ring);
5830 return 0;
5831 }
5832
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5833 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5834 {
5835 ath11k_dp_mon_link_free(ar);
5836 return 0;
5837 }
5838
ath11k_dp_rx_pktlog_start(struct ath11k_base * ab)5839 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5840 {
5841 /* start reap timer */
5842 mod_timer(&ab->mon_reap_timer,
5843 jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5844
5845 return 0;
5846 }
5847
ath11k_dp_rx_pktlog_stop(struct ath11k_base * ab,bool stop_timer)5848 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5849 {
5850 int ret;
5851
5852 if (stop_timer)
5853 timer_delete_sync(&ab->mon_reap_timer);
5854
5855 /* reap all the monitor related rings */
5856 ret = ath11k_dp_purge_mon_ring(ab);
5857 if (ret) {
5858 ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5859 return ret;
5860 }
5861
5862 return 0;
5863 }
5864