1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2017
4 *
5 * Authors: Philippe Cornu <philippe.cornu@st.com>
6 * Yannick Fertre <yannick.fertre@st.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regulator/consumer.h>
17
18 #include <video/mipi_display.h>
19
20 #include <drm/bridge/dw_mipi_dsi.h>
21 #include <drm/drm_mipi_dsi.h>
22 #include <drm/drm_print.h>
23
24 #define HWVER_130 0x31333000 /* IP version 1.30 */
25 #define HWVER_131 0x31333100 /* IP version 1.31 */
26
27 /* DSI digital registers & bit definitions */
28 #define DSI_VERSION 0x00
29 #define VERSION GENMASK(31, 8)
30
31 /* DSI wrapper registers & bit definitions */
32 /* Note: registers are named as in the Reference Manual */
33 #define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */
34 #define WCFGR_DSIM BIT(0) /* DSI Mode */
35 #define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */
36
37 #define DSI_WCR 0x0404 /* Wrapper Control Reg */
38 #define WCR_DSIEN BIT(3) /* DSI ENable */
39
40 #define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */
41 #define WISR_PLLLS BIT(8) /* PLL Lock Status */
42 #define WISR_RRS BIT(12) /* Regulator Ready Status */
43
44 #define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */
45 #define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */
46 #define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
47
48 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
49 #define WRPCR_PLLEN BIT(0) /* PLL ENable */
50 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
51 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
52 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
53 #define WRPCR_REGEN BIT(24) /* REGulator ENable */
54 #define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */
55 #define IDF_MIN 1
56 #define IDF_MAX 7
57 #define NDIV_MIN 10
58 #define NDIV_MAX 125
59 #define ODF_MIN 1
60 #define ODF_MAX 8
61
62 /* dsi color format coding according to the datasheet */
63 enum dsi_color {
64 DSI_RGB565_CONF1,
65 DSI_RGB565_CONF2,
66 DSI_RGB565_CONF3,
67 DSI_RGB666_CONF1,
68 DSI_RGB666_CONF2,
69 DSI_RGB888,
70 };
71
72 #define LANE_MIN_KBPS 31250
73 #define LANE_MAX_KBPS 500000
74
75 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
76 #define SLEEP_US 1000
77 #define TIMEOUT_US 200000
78
79 struct dw_mipi_dsi_stm {
80 void __iomem *base;
81 struct device *dev;
82 struct clk *pllref_clk;
83 struct clk *pclk;
84 struct clk_hw txbyte_clk;
85 struct dw_mipi_dsi *dsi;
86 struct dw_mipi_dsi_plat_data pdata;
87 u32 hw_version;
88 int lane_min_kbps;
89 int lane_max_kbps;
90 struct regulator *vdd_supply;
91 };
92
dsi_write(struct dw_mipi_dsi_stm * dsi,u32 reg,u32 val)93 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
94 {
95 writel(val, dsi->base + reg);
96 }
97
dsi_read(struct dw_mipi_dsi_stm * dsi,u32 reg)98 static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg)
99 {
100 return readl(dsi->base + reg);
101 }
102
dsi_set(struct dw_mipi_dsi_stm * dsi,u32 reg,u32 mask)103 static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
104 {
105 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
106 }
107
dsi_clear(struct dw_mipi_dsi_stm * dsi,u32 reg,u32 mask)108 static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
109 {
110 dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
111 }
112
dsi_update_bits(struct dw_mipi_dsi_stm * dsi,u32 reg,u32 mask,u32 val)113 static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg,
114 u32 mask, u32 val)
115 {
116 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
117 }
118
dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)119 static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
120 {
121 switch (fmt) {
122 case MIPI_DSI_FMT_RGB888:
123 return DSI_RGB888;
124 case MIPI_DSI_FMT_RGB666:
125 return DSI_RGB666_CONF2;
126 case MIPI_DSI_FMT_RGB666_PACKED:
127 return DSI_RGB666_CONF1;
128 case MIPI_DSI_FMT_RGB565:
129 return DSI_RGB565_CONF1;
130 default:
131 DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
132 }
133 return DSI_RGB888;
134 }
135
dsi_pll_get_clkout_khz(int clkin_khz,int idf,int ndiv,int odf)136 static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
137 {
138 int divisor = idf * odf;
139
140 /* prevent from division by 0 */
141 if (!divisor)
142 return 0;
143
144 return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor);
145 }
146
dsi_pll_get_params(struct dw_mipi_dsi_stm * dsi,int clkin_khz,int clkout_khz,int * idf,int * ndiv,int * odf)147 static int dsi_pll_get_params(struct dw_mipi_dsi_stm *dsi,
148 int clkin_khz, int clkout_khz,
149 int *idf, int *ndiv, int *odf)
150 {
151 int i, o, n, n_min, n_max;
152 int fvco_min, fvco_max, delta, best_delta; /* all in khz */
153
154 /* Early checks preventing division by 0 & odd results */
155 if (clkin_khz <= 0 || clkout_khz <= 0)
156 return -EINVAL;
157
158 fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;
159 fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;
160
161 best_delta = 1000000; /* big started value (1000000khz) */
162
163 for (i = IDF_MIN; i <= IDF_MAX; i++) {
164 /* Compute ndiv range according to Fvco */
165 n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
166 n_max = (fvco_max * i) / (2 * clkin_khz);
167
168 /* No need to continue idf loop if we reach ndiv max */
169 if (n_min >= NDIV_MAX)
170 break;
171
172 /* Clamp ndiv to valid values */
173 if (n_min < NDIV_MIN)
174 n_min = NDIV_MIN;
175 if (n_max > NDIV_MAX)
176 n_max = NDIV_MAX;
177
178 for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
179 n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
180 /* Check ndiv according to vco range */
181 if (n < n_min || n > n_max)
182 continue;
183 /* Check if new delta is better & saves parameters */
184 delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
185 clkout_khz;
186 if (delta < 0)
187 delta = -delta;
188 if (delta < best_delta) {
189 *idf = i;
190 *ndiv = n;
191 *odf = o;
192 best_delta = delta;
193 }
194 /* fast return in case of "perfect result" */
195 if (!delta)
196 return 0;
197 }
198 }
199
200 return 0;
201 }
202
203 #define clk_to_dw_mipi_dsi_stm(clk) \
204 container_of(clk, struct dw_mipi_dsi_stm, txbyte_clk)
205
dw_mipi_dsi_clk_disable(struct clk_hw * clk)206 static void dw_mipi_dsi_clk_disable(struct clk_hw *clk)
207 {
208 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(clk);
209
210 DRM_DEBUG_DRIVER("\n");
211
212 /* Disable the DSI PLL */
213 dsi_clear(dsi, DSI_WRPCR, WRPCR_PLLEN);
214
215 /* Disable the regulator */
216 dsi_clear(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
217 }
218
dw_mipi_dsi_clk_enable(struct clk_hw * clk)219 static int dw_mipi_dsi_clk_enable(struct clk_hw *clk)
220 {
221 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(clk);
222 u32 val;
223 int ret;
224
225 DRM_DEBUG_DRIVER("\n");
226
227 /* Enable the regulator */
228 dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
229 ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val & WISR_RRS,
230 SLEEP_US, TIMEOUT_US);
231 if (ret)
232 DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
233
234 /* Enable the DSI PLL & wait for its lock */
235 dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
236 ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
237 SLEEP_US, TIMEOUT_US);
238 if (ret)
239 DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
240
241 return 0;
242 }
243
dw_mipi_dsi_clk_is_enabled(struct clk_hw * hw)244 static int dw_mipi_dsi_clk_is_enabled(struct clk_hw *hw)
245 {
246 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
247
248 return dsi_read(dsi, DSI_WRPCR) & WRPCR_PLLEN;
249 }
250
dw_mipi_dsi_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)251 static unsigned long dw_mipi_dsi_clk_recalc_rate(struct clk_hw *hw,
252 unsigned long parent_rate)
253 {
254 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
255 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
256 u32 val;
257
258 DRM_DEBUG_DRIVER("\n");
259
260 pll_in_khz = (unsigned int)(parent_rate / 1000);
261
262 val = dsi_read(dsi, DSI_WRPCR);
263
264 idf = (val & WRPCR_IDF) >> 11;
265 if (!idf)
266 idf = 1;
267 ndiv = (val & WRPCR_NDIV) >> 2;
268 odf = int_pow(2, (val & WRPCR_ODF) >> 16);
269
270 /* Get the adjusted pll out value */
271 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
272
273 return (unsigned long)pll_out_khz * 1000;
274 }
275
dw_mipi_dsi_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)276 static int dw_mipi_dsi_clk_determine_rate(struct clk_hw *hw,
277 struct clk_rate_request *req)
278 {
279 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
280 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
281 int ret;
282
283 DRM_DEBUG_DRIVER("\n");
284
285 pll_in_khz = (unsigned int)(req->best_parent_rate / 1000);
286
287 /* Compute best pll parameters */
288 idf = 0;
289 ndiv = 0;
290 odf = 0;
291
292 ret = dsi_pll_get_params(dsi, pll_in_khz, req->rate / 1000,
293 &idf, &ndiv, &odf);
294 if (ret)
295 DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
296
297 /* Get the adjusted pll out value */
298 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
299
300 req->rate = pll_out_khz * 1000;
301
302 return 0;
303 }
304
dw_mipi_dsi_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)305 static int dw_mipi_dsi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
306 unsigned long parent_rate)
307 {
308 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
309 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
310 int ret;
311 u32 val;
312
313 DRM_DEBUG_DRIVER("\n");
314
315 pll_in_khz = (unsigned int)(parent_rate / 1000);
316
317 /* Compute best pll parameters */
318 idf = 0;
319 ndiv = 0;
320 odf = 0;
321
322 ret = dsi_pll_get_params(dsi, pll_in_khz, rate / 1000, &idf, &ndiv, &odf);
323 if (ret)
324 DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
325
326 /* Get the adjusted pll out value */
327 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
328
329 /* Set the PLL division factors */
330 dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
331 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
332
333 /* Compute uix4 & set the bit period in high-speed mode */
334 val = 4000000 / pll_out_khz;
335 dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
336
337 return 0;
338 }
339
dw_mipi_dsi_clk_unregister(void * data)340 static void dw_mipi_dsi_clk_unregister(void *data)
341 {
342 struct dw_mipi_dsi_stm *dsi = data;
343
344 DRM_DEBUG_DRIVER("\n");
345
346 of_clk_del_provider(dsi->dev->of_node);
347 clk_hw_unregister(&dsi->txbyte_clk);
348 }
349
350 static const struct clk_ops dw_mipi_dsi_stm_clk_ops = {
351 .enable = dw_mipi_dsi_clk_enable,
352 .disable = dw_mipi_dsi_clk_disable,
353 .is_enabled = dw_mipi_dsi_clk_is_enabled,
354 .recalc_rate = dw_mipi_dsi_clk_recalc_rate,
355 .determine_rate = dw_mipi_dsi_clk_determine_rate,
356 .set_rate = dw_mipi_dsi_clk_set_rate,
357 };
358
359 static struct clk_init_data cdata_init = {
360 .name = "ck_dsi_phy",
361 .ops = &dw_mipi_dsi_stm_clk_ops,
362 .parent_names = (const char * []) {"ck_hse"},
363 .num_parents = 1,
364 };
365
dw_mipi_dsi_clk_register(struct dw_mipi_dsi_stm * dsi,struct device * dev)366 static int dw_mipi_dsi_clk_register(struct dw_mipi_dsi_stm *dsi,
367 struct device *dev)
368 {
369 struct device_node *node = dev->of_node;
370 int ret;
371
372 DRM_DEBUG_DRIVER("Registering clk\n");
373
374 dsi->txbyte_clk.init = &cdata_init;
375
376 ret = clk_hw_register(dev, &dsi->txbyte_clk);
377 if (ret)
378 return ret;
379
380 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get,
381 &dsi->txbyte_clk);
382 if (ret)
383 clk_hw_unregister(&dsi->txbyte_clk);
384
385 return ret;
386 }
387
dw_mipi_dsi_phy_init(void * priv_data)388 static int dw_mipi_dsi_phy_init(void *priv_data)
389 {
390 struct dw_mipi_dsi_stm *dsi = priv_data;
391 int ret;
392
393 ret = clk_prepare_enable(dsi->txbyte_clk.clk);
394 return ret;
395 }
396
dw_mipi_dsi_phy_power_on(void * priv_data)397 static void dw_mipi_dsi_phy_power_on(void *priv_data)
398 {
399 struct dw_mipi_dsi_stm *dsi = priv_data;
400
401 DRM_DEBUG_DRIVER("\n");
402
403 /* Enable the DSI wrapper */
404 dsi_set(dsi, DSI_WCR, WCR_DSIEN);
405 }
406
dw_mipi_dsi_phy_power_off(void * priv_data)407 static void dw_mipi_dsi_phy_power_off(void *priv_data)
408 {
409 struct dw_mipi_dsi_stm *dsi = priv_data;
410
411 DRM_DEBUG_DRIVER("\n");
412
413 clk_disable_unprepare(dsi->txbyte_clk.clk);
414
415 /* Disable the DSI wrapper */
416 dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
417 }
418
419 static int
dw_mipi_dsi_get_lane_mbps(void * priv_data,const struct drm_display_mode * mode,unsigned long mode_flags,u32 lanes,u32 format,unsigned int * lane_mbps)420 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
421 unsigned long mode_flags, u32 lanes, u32 format,
422 unsigned int *lane_mbps)
423 {
424 struct dw_mipi_dsi_stm *dsi = priv_data;
425 unsigned int pll_in_khz, pll_out_khz;
426 int ret, bpp;
427
428 pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
429
430 /* Compute requested pll out */
431 bpp = mipi_dsi_pixel_format_to_bpp(format);
432 pll_out_khz = mode->clock * bpp / lanes;
433
434 /* Add 20% to pll out to be higher than pixel bw (burst mode only) */
435 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
436 pll_out_khz = (pll_out_khz * 12) / 10;
437
438 if (pll_out_khz > dsi->lane_max_kbps) {
439 pll_out_khz = dsi->lane_max_kbps;
440 DRM_WARN("Warning max phy mbps is used\n");
441 }
442 if (pll_out_khz < dsi->lane_min_kbps) {
443 pll_out_khz = dsi->lane_min_kbps;
444 DRM_WARN("Warning min phy mbps is used\n");
445 }
446
447 ret = clk_set_rate((dsi->txbyte_clk.clk), pll_out_khz * 1000);
448 if (ret)
449 DRM_DEBUG_DRIVER("ERROR Could not set rate of %d to %s clk->name",
450 pll_out_khz, clk_hw_get_name(&dsi->txbyte_clk));
451
452 /* Select video mode by resetting DSIM bit */
453 dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
454
455 /* Select the color coding */
456 dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
457 dsi_color_from_mipi(format) << 1);
458
459 *lane_mbps = pll_out_khz / 1000;
460
461 DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
462 pll_in_khz, pll_out_khz, *lane_mbps);
463
464 return 0;
465 }
466
467 #define DSI_PHY_DELAY(fp, vp, mbps) DIV_ROUND_UP((fp) * (mbps) + 1000 * (vp), 8000)
468
469 static int
dw_mipi_dsi_phy_get_timing(void * priv_data,unsigned int lane_mbps,struct dw_mipi_dsi_dphy_timing * timing)470 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
471 struct dw_mipi_dsi_dphy_timing *timing)
472 {
473 /*
474 * From STM32MP157 datasheet, valid for STM32F469, STM32F7x9, STM32H747
475 * phy_clkhs2lp_time = (272+136*UI)/(8*UI)
476 * phy_clklp2hs_time = (512+40*UI)/(8*UI)
477 * phy_hs2lp_time = (192+64*UI)/(8*UI)
478 * phy_lp2hs_time = (256+32*UI)/(8*UI)
479 */
480 timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps);
481 timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps);
482 timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps);
483 timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps);
484
485 return 0;
486 }
487
488 #define CLK_TOLERANCE_HZ 50
489
490 static enum drm_mode_status
dw_mipi_dsi_stm_mode_valid(void * priv_data,const struct drm_display_mode * mode,unsigned long mode_flags,u32 lanes,u32 format)491 dw_mipi_dsi_stm_mode_valid(void *priv_data,
492 const struct drm_display_mode *mode,
493 unsigned long mode_flags, u32 lanes, u32 format)
494 {
495 struct dw_mipi_dsi_stm *dsi = priv_data;
496 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
497 int ret, bpp;
498
499 bpp = mipi_dsi_pixel_format_to_bpp(format);
500 if (bpp < 0)
501 return MODE_BAD;
502
503 /* Compute requested pll out */
504 pll_out_khz = mode->clock * bpp / lanes;
505
506 if (pll_out_khz > dsi->lane_max_kbps)
507 return MODE_CLOCK_HIGH;
508
509 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
510 /* Add 20% to pll out to be higher than pixel bw */
511 pll_out_khz = (pll_out_khz * 12) / 10;
512 } else {
513 if (pll_out_khz < dsi->lane_min_kbps)
514 return MODE_CLOCK_LOW;
515 }
516
517 /* Compute best pll parameters */
518 idf = 0;
519 ndiv = 0;
520 odf = 0;
521 pll_in_khz = clk_get_rate(dsi->pllref_clk) / 1000;
522 ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz, &idf, &ndiv, &odf);
523 if (ret) {
524 DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
525 return MODE_ERROR;
526 }
527
528 if (!(mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
529 unsigned int px_clock_hz, target_px_clock_hz, lane_mbps;
530 int dsi_short_packet_size_px, hfp, hsync, hbp, delay_to_lp;
531 struct dw_mipi_dsi_dphy_timing dphy_timing;
532
533 /* Get the adjusted pll out value */
534 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
535
536 px_clock_hz = DIV_ROUND_CLOSEST_ULL(1000ULL * pll_out_khz * lanes, bpp);
537 target_px_clock_hz = mode->clock * 1000;
538 /*
539 * Filter modes according to the clock value, particularly useful for
540 * hdmi modes that require precise pixel clocks.
541 */
542 if (px_clock_hz < target_px_clock_hz - CLK_TOLERANCE_HZ ||
543 px_clock_hz > target_px_clock_hz + CLK_TOLERANCE_HZ)
544 return MODE_CLOCK_RANGE;
545
546 /* sync packets are codes as DSI short packets (4 bytes) */
547 dsi_short_packet_size_px = DIV_ROUND_UP(4 * BITS_PER_BYTE, bpp);
548
549 hfp = mode->hsync_start - mode->hdisplay;
550 hsync = mode->hsync_end - mode->hsync_start;
551 hbp = mode->htotal - mode->hsync_end;
552
553 /* hsync must be longer than 4 bytes HSS packets */
554 if (hsync < dsi_short_packet_size_px)
555 return MODE_HSYNC_NARROW;
556
557 if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
558 /* HBP must be longer than 4 bytes HSE packets */
559 if (hbp < dsi_short_packet_size_px)
560 return MODE_HSYNC_NARROW;
561 hbp -= dsi_short_packet_size_px;
562 } else {
563 /* With sync events HBP extends in the hsync */
564 hbp += hsync - dsi_short_packet_size_px;
565 }
566
567 lane_mbps = pll_out_khz / 1000;
568 ret = dw_mipi_dsi_phy_get_timing(priv_data, lane_mbps, &dphy_timing);
569 if (ret)
570 return MODE_ERROR;
571 /*
572 * In non-burst mode DSI has to enter in LP during HFP
573 * (horizontal front porch) or HBP (horizontal back porch) to
574 * resync with LTDC pixel clock.
575 */
576 delay_to_lp = DIV_ROUND_UP((dphy_timing.data_hs2lp + dphy_timing.data_lp2hs) *
577 lanes * BITS_PER_BYTE, bpp);
578 if (hfp < delay_to_lp && hbp < delay_to_lp)
579 return MODE_HSYNC;
580 }
581
582 return MODE_OK;
583 }
584
585 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
586 .init = dw_mipi_dsi_phy_init,
587 .power_on = dw_mipi_dsi_phy_power_on,
588 .power_off = dw_mipi_dsi_phy_power_off,
589 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
590 .get_timing = dw_mipi_dsi_phy_get_timing,
591 };
592
593 static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
594 .max_data_lanes = 2,
595 .mode_valid = dw_mipi_dsi_stm_mode_valid,
596 .phy_ops = &dw_mipi_dsi_stm_phy_ops,
597 };
598
599 static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = {
600 { .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, },
601 { },
602 };
603 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids);
604
dw_mipi_dsi_stm_probe(struct platform_device * pdev)605 static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
606 {
607 struct device *dev = &pdev->dev;
608 struct dw_mipi_dsi_stm *dsi;
609 const struct dw_mipi_dsi_plat_data *pdata = of_device_get_match_data(dev);
610 int ret;
611
612 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
613 if (!dsi)
614 return -ENOMEM;
615
616 dsi->base = devm_platform_ioremap_resource(pdev, 0);
617 if (IS_ERR(dsi->base)) {
618 ret = PTR_ERR(dsi->base);
619 DRM_ERROR("Unable to get dsi registers %d\n", ret);
620 return ret;
621 }
622
623 dsi->vdd_supply = devm_regulator_get(dev, "phy-dsi");
624 if (IS_ERR(dsi->vdd_supply)) {
625 ret = PTR_ERR(dsi->vdd_supply);
626 dev_err_probe(dev, ret, "Failed to request regulator\n");
627 return ret;
628 }
629
630 ret = regulator_enable(dsi->vdd_supply);
631 if (ret) {
632 DRM_ERROR("Failed to enable regulator: %d\n", ret);
633 return ret;
634 }
635
636 dsi->pllref_clk = devm_clk_get(dev, "ref");
637 if (IS_ERR(dsi->pllref_clk)) {
638 ret = PTR_ERR(dsi->pllref_clk);
639 dev_err_probe(dev, ret, "Unable to get pll reference clock\n");
640 goto err_clk_get;
641 }
642
643 ret = clk_prepare_enable(dsi->pllref_clk);
644 if (ret) {
645 DRM_ERROR("Failed to enable pllref_clk: %d\n", ret);
646 goto err_clk_get;
647 }
648
649 dsi->pclk = devm_clk_get(dev, "pclk");
650 if (IS_ERR(dsi->pclk)) {
651 ret = PTR_ERR(dsi->pclk);
652 DRM_ERROR("Unable to get peripheral clock: %d\n", ret);
653 goto err_dsi_probe;
654 }
655
656 ret = clk_prepare_enable(dsi->pclk);
657 if (ret) {
658 DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
659 goto err_dsi_probe;
660 }
661
662 dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
663 clk_disable_unprepare(dsi->pclk);
664
665 if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
666 ret = -ENODEV;
667 DRM_ERROR("bad dsi hardware version\n");
668 goto err_dsi_probe;
669 }
670
671 /* set lane capabilities according to hw version */
672 dsi->lane_min_kbps = LANE_MIN_KBPS;
673 dsi->lane_max_kbps = LANE_MAX_KBPS;
674 if (dsi->hw_version == HWVER_131) {
675 dsi->lane_min_kbps *= 2;
676 dsi->lane_max_kbps *= 2;
677 }
678
679 dsi->pdata = *pdata;
680 dsi->pdata.base = dsi->base;
681 dsi->pdata.priv_data = dsi;
682
683 dsi->pdata.max_data_lanes = 2;
684 dsi->pdata.phy_ops = &dw_mipi_dsi_stm_phy_ops;
685
686 platform_set_drvdata(pdev, dsi);
687
688 dsi->dsi = dw_mipi_dsi_probe(pdev, &dsi->pdata);
689 if (IS_ERR(dsi->dsi)) {
690 ret = PTR_ERR(dsi->dsi);
691 dev_err_probe(dev, ret, "Failed to initialize mipi dsi host\n");
692 goto err_dsi_probe;
693 }
694
695 /*
696 * We need to wait for the generic bridge to probe before enabling and
697 * register the internal pixel clock.
698 */
699 ret = clk_prepare_enable(dsi->pclk);
700 if (ret) {
701 DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
702 goto err_dsi_probe;
703 }
704
705 ret = dw_mipi_dsi_clk_register(dsi, dev);
706 if (ret) {
707 DRM_ERROR("Failed to register DSI pixel clock: %d\n", ret);
708 clk_disable_unprepare(dsi->pclk);
709 goto err_dsi_probe;
710 }
711
712 clk_disable_unprepare(dsi->pclk);
713
714 return 0;
715
716 err_dsi_probe:
717 clk_disable_unprepare(dsi->pllref_clk);
718 err_clk_get:
719 regulator_disable(dsi->vdd_supply);
720
721 return ret;
722 }
723
dw_mipi_dsi_stm_remove(struct platform_device * pdev)724 static void dw_mipi_dsi_stm_remove(struct platform_device *pdev)
725 {
726 struct dw_mipi_dsi_stm *dsi = platform_get_drvdata(pdev);
727
728 dw_mipi_dsi_remove(dsi->dsi);
729 clk_disable_unprepare(dsi->pllref_clk);
730 dw_mipi_dsi_clk_unregister(dsi);
731 regulator_disable(dsi->vdd_supply);
732 }
733
dw_mipi_dsi_stm_suspend(struct device * dev)734 static int dw_mipi_dsi_stm_suspend(struct device *dev)
735 {
736 struct dw_mipi_dsi_stm *dsi = dev_get_drvdata(dev);
737
738 DRM_DEBUG_DRIVER("\n");
739
740 clk_disable_unprepare(dsi->pllref_clk);
741 clk_disable_unprepare(dsi->pclk);
742 regulator_disable(dsi->vdd_supply);
743
744 return 0;
745 }
746
dw_mipi_dsi_stm_resume(struct device * dev)747 static int dw_mipi_dsi_stm_resume(struct device *dev)
748 {
749 struct dw_mipi_dsi_stm *dsi = dev_get_drvdata(dev);
750 int ret;
751
752 DRM_DEBUG_DRIVER("\n");
753
754 ret = regulator_enable(dsi->vdd_supply);
755 if (ret) {
756 DRM_ERROR("Failed to enable regulator: %d\n", ret);
757 return ret;
758 }
759
760 ret = clk_prepare_enable(dsi->pclk);
761 if (ret) {
762 regulator_disable(dsi->vdd_supply);
763 DRM_ERROR("Failed to enable pclk: %d\n", ret);
764 return ret;
765 }
766
767 ret = clk_prepare_enable(dsi->pllref_clk);
768 if (ret) {
769 clk_disable_unprepare(dsi->pclk);
770 regulator_disable(dsi->vdd_supply);
771 DRM_ERROR("Failed to enable pllref_clk: %d\n", ret);
772 return ret;
773 }
774
775 return 0;
776 }
777
778 static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = {
779 SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend,
780 dw_mipi_dsi_stm_resume)
781 RUNTIME_PM_OPS(dw_mipi_dsi_stm_suspend,
782 dw_mipi_dsi_stm_resume, NULL)
783 };
784
785 static struct platform_driver dw_mipi_dsi_stm_driver = {
786 .probe = dw_mipi_dsi_stm_probe,
787 .remove = dw_mipi_dsi_stm_remove,
788 .driver = {
789 .of_match_table = dw_mipi_dsi_stm_dt_ids,
790 .name = "stm32-display-dsi",
791 .pm = &dw_mipi_dsi_stm_pm_ops,
792 },
793 };
794
795 module_platform_driver(dw_mipi_dsi_stm_driver);
796
797 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
798 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
799 MODULE_DESCRIPTION("STMicroelectronics DW MIPI DSI host controller driver");
800 MODULE_LICENSE("GPL v2");
801