1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2025 MediaTek Inc.
3
4 /*
5 * Library for MediaTek External Interrupt Support
6 *
7 * Author: Maoguang Meng <maoguang.meng@mediatek.com>
8 * Sean Wang <sean.wang@mediatek.com>
9 * Hao Chang <ot_chhao.chang@mediatek.com>
10 * Qingliang Li <qingliang.li@mediatek.com>
11 *
12 */
13
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/module.h>
23 #include <linux/of_irq.h>
24 #include <linux/platform_device.h>
25
26 #include "mtk-eint.h"
27
28 #define MTK_EINT_EDGE_SENSITIVE 0
29 #define MTK_EINT_LEVEL_SENSITIVE 1
30 #define MTK_EINT_DBNC_SET_DBNC_BITS 4
31 #define MTK_EINT_DBNC_MAX 16
32 #define MTK_EINT_DBNC_RST_BIT (0x1 << 1)
33 #define MTK_EINT_DBNC_SET_EN (0x1 << 0)
34
35 static const struct mtk_eint_regs mtk_generic_eint_regs = {
36 .stat = 0x000,
37 .ack = 0x040,
38 .mask = 0x080,
39 .mask_set = 0x0c0,
40 .mask_clr = 0x100,
41 .sens = 0x140,
42 .sens_set = 0x180,
43 .sens_clr = 0x1c0,
44 .soft = 0x200,
45 .soft_set = 0x240,
46 .soft_clr = 0x280,
47 .pol = 0x300,
48 .pol_set = 0x340,
49 .pol_clr = 0x380,
50 .dom_en = 0x400,
51 .dbnc_ctrl = 0x500,
52 .dbnc_set = 0x600,
53 .dbnc_clr = 0x700,
54 };
55
56 const unsigned int debounce_time_mt2701[] = {
57 500, 1000, 16000, 32000, 64000, 128000, 256000, 0
58 };
59 EXPORT_SYMBOL_GPL(debounce_time_mt2701);
60
61 const unsigned int debounce_time_mt6765[] = {
62 125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
63 };
64 EXPORT_SYMBOL_GPL(debounce_time_mt6765);
65
66 const unsigned int debounce_time_mt6795[] = {
67 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
68 };
69 EXPORT_SYMBOL_GPL(debounce_time_mt6795);
70
71 const unsigned int debounce_time_mt6878[] = {
72 156, 313, 625, 1250, 20000, 40000, 80000, 160000, 320000, 640000, 0
73 };
74 EXPORT_SYMBOL_GPL(debounce_time_mt6878);
75
mtk_eint_get_offset(struct mtk_eint * eint,unsigned int eint_num,unsigned int offset)76 static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
77 unsigned int eint_num,
78 unsigned int offset)
79 {
80 unsigned int idx = eint->pins[eint_num].index;
81 unsigned int inst = eint->pins[eint_num].instance;
82 void __iomem *reg;
83
84 reg = eint->base[inst] + offset + (idx / 32 * 4);
85
86 return reg;
87 }
88
mtk_eint_can_en_debounce(struct mtk_eint * eint,unsigned int eint_num)89 static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint,
90 unsigned int eint_num)
91 {
92 unsigned int sens;
93 unsigned int bit = BIT(eint->pins[eint_num].index % 32);
94 void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
95 eint->regs->sens);
96
97 if (readl(reg) & bit)
98 sens = MTK_EINT_LEVEL_SENSITIVE;
99 else
100 sens = MTK_EINT_EDGE_SENSITIVE;
101
102 if (eint->pins[eint_num].debounce && sens != MTK_EINT_EDGE_SENSITIVE)
103 return 1;
104 else
105 return 0;
106 }
107
mtk_eint_flip_edge(struct mtk_eint * eint,int hwirq)108 static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq)
109 {
110 int start_level, curr_level;
111 unsigned int reg_offset;
112 unsigned int mask = BIT(eint->pins[hwirq].index & 0x1f);
113 unsigned int port = (eint->pins[hwirq].index >> 5) & eint->hw->port_mask;
114 void __iomem *reg = eint->base[eint->pins[hwirq].instance] + (port << 2);
115
116 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);
117
118 do {
119 start_level = curr_level;
120 if (start_level)
121 reg_offset = eint->regs->pol_clr;
122 else
123 reg_offset = eint->regs->pol_set;
124 writel(mask, reg + reg_offset);
125
126 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl,
127 hwirq);
128 } while (start_level != curr_level);
129
130 return start_level;
131 }
132
mtk_eint_mask(struct irq_data * d)133 static void mtk_eint_mask(struct irq_data *d)
134 {
135 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
136 unsigned int idx = eint->pins[d->hwirq].index;
137 unsigned int inst = eint->pins[d->hwirq].instance;
138 unsigned int mask = BIT(idx & 0x1f);
139 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
140 eint->regs->mask_set);
141
142 eint->cur_mask[inst][idx >> 5] &= ~mask;
143
144 writel(mask, reg);
145 }
146
mtk_eint_unmask(struct irq_data * d)147 static void mtk_eint_unmask(struct irq_data *d)
148 {
149 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
150 unsigned int idx = eint->pins[d->hwirq].index;
151 unsigned int inst = eint->pins[d->hwirq].instance;
152 unsigned int mask = BIT(idx & 0x1f);
153 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
154 eint->regs->mask_clr);
155
156 eint->cur_mask[inst][idx >> 5] |= mask;
157
158 writel(mask, reg);
159
160 if (eint->pins[d->hwirq].dual_edge)
161 mtk_eint_flip_edge(eint, d->hwirq);
162 }
163
mtk_eint_get_mask(struct mtk_eint * eint,unsigned int eint_num)164 static unsigned int mtk_eint_get_mask(struct mtk_eint *eint,
165 unsigned int eint_num)
166 {
167 unsigned int bit = BIT(eint->pins[eint_num].index % 32);
168 void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
169 eint->regs->mask);
170
171 return !!(readl(reg) & bit);
172 }
173
mtk_eint_ack(struct irq_data * d)174 static void mtk_eint_ack(struct irq_data *d)
175 {
176 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
177 unsigned int mask = BIT(eint->pins[d->hwirq].index & 0x1f);
178 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
179 eint->regs->ack);
180
181 writel(mask, reg);
182 }
183
mtk_eint_set_type(struct irq_data * d,unsigned int type)184 static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
185 {
186 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
187 bool masked;
188 unsigned int mask = BIT(eint->pins[d->hwirq].index & 0x1f);
189 void __iomem *reg;
190
191 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
192 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
193 dev_err(eint->dev,
194 "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
195 d->irq, d->hwirq, type);
196 return -EINVAL;
197 }
198
199 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
200 eint->pins[d->hwirq].dual_edge = 1;
201 else
202 eint->pins[d->hwirq].dual_edge = 0;
203
204 if (!mtk_eint_get_mask(eint, d->hwirq)) {
205 mtk_eint_mask(d);
206 masked = false;
207 } else {
208 masked = true;
209 }
210
211 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
212 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
213 writel(mask, reg);
214 } else {
215 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set);
216 writel(mask, reg);
217 }
218
219 if (type & IRQ_TYPE_EDGE_BOTH) {
220 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);
221 writel(mask, reg);
222 } else {
223 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set);
224 writel(mask, reg);
225 }
226
227 mtk_eint_ack(d);
228 if (!masked)
229 mtk_eint_unmask(d);
230
231 return 0;
232 }
233
mtk_eint_irq_set_wake(struct irq_data * d,unsigned int on)234 static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
235 {
236 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
237 unsigned int idx = eint->pins[d->hwirq].index;
238 unsigned int inst = eint->pins[d->hwirq].instance;
239 unsigned int shift = idx & 0x1f;
240 unsigned int port = idx >> 5;
241
242 if (on)
243 eint->wake_mask[inst][port] |= BIT(shift);
244 else
245 eint->wake_mask[inst][port] &= ~BIT(shift);
246
247 return 0;
248 }
249
mtk_eint_chip_write_mask(const struct mtk_eint * eint,unsigned int ** buf)250 static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
251 unsigned int **buf)
252 {
253 int inst, port, port_num;
254 void __iomem *reg;
255
256 for (inst = 0; inst < eint->nbase; inst++) {
257 port_num = DIV_ROUND_UP(eint->base_pin_num[inst], 32);
258 for (port = 0; port < port_num; port++) {
259 reg = eint->base[inst] + (port << 2);
260 writel_relaxed(~buf[inst][port], reg + eint->regs->mask_set);
261 writel_relaxed(buf[inst][port], reg + eint->regs->mask_clr);
262 }
263 }
264 }
265
mtk_eint_irq_request_resources(struct irq_data * d)266 static int mtk_eint_irq_request_resources(struct irq_data *d)
267 {
268 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
269 struct gpio_chip *gpio_c;
270 unsigned int gpio_n;
271 int err;
272
273 err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq,
274 &gpio_n, &gpio_c);
275 if (err < 0) {
276 dev_err(eint->dev, "Can not find pin\n");
277 return err;
278 }
279
280 err = gpiochip_lock_as_irq(gpio_c, gpio_n);
281 if (err < 0) {
282 dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n",
283 irqd_to_hwirq(d));
284 return err;
285 }
286
287 err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq);
288 if (err < 0) {
289 dev_err(eint->dev, "Can not eint mode\n");
290 return err;
291 }
292
293 return 0;
294 }
295
mtk_eint_irq_release_resources(struct irq_data * d)296 static void mtk_eint_irq_release_resources(struct irq_data *d)
297 {
298 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
299 struct gpio_chip *gpio_c;
300 unsigned int gpio_n;
301
302 eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n,
303 &gpio_c);
304
305 gpiochip_unlock_as_irq(gpio_c, gpio_n);
306 }
307
308 static struct irq_chip mtk_eint_irq_chip = {
309 .name = "mt-eint",
310 .irq_disable = mtk_eint_mask,
311 .irq_mask = mtk_eint_mask,
312 .irq_unmask = mtk_eint_unmask,
313 .irq_ack = mtk_eint_ack,
314 .irq_set_type = mtk_eint_set_type,
315 .irq_set_wake = mtk_eint_irq_set_wake,
316 .irq_request_resources = mtk_eint_irq_request_resources,
317 .irq_release_resources = mtk_eint_irq_release_resources,
318 };
319
mtk_eint_hw_init(struct mtk_eint * eint)320 static unsigned int mtk_eint_hw_init(struct mtk_eint *eint)
321 {
322 void __iomem *dom_reg, *mask_reg;
323 unsigned int i, j;
324
325 for (i = 0; i < eint->nbase; i++) {
326 dom_reg = eint->base[i] + eint->regs->dom_en;
327 mask_reg = eint->base[i] + eint->regs->mask_set;
328 for (j = 0; j < eint->base_pin_num[i]; j += 32) {
329 writel(0xffffffff, dom_reg);
330 writel(0xffffffff, mask_reg);
331 dom_reg += 4;
332 mask_reg += 4;
333 }
334 }
335
336 return 0;
337 }
338
339 static inline void
mtk_eint_debounce_process(struct mtk_eint * eint,int index)340 mtk_eint_debounce_process(struct mtk_eint *eint, int index)
341 {
342 unsigned int rst, ctrl_offset;
343 unsigned int bit, dbnc;
344 unsigned int inst = eint->pins[index].instance;
345 unsigned int idx = eint->pins[index].index;
346
347 ctrl_offset = (idx / 4) * 4 + eint->regs->dbnc_ctrl;
348 dbnc = readl(eint->base[inst] + ctrl_offset);
349 bit = MTK_EINT_DBNC_SET_EN << ((idx % 4) * 8);
350 if ((bit & dbnc) > 0) {
351 ctrl_offset = (idx / 4) * 4 + eint->regs->dbnc_set;
352 rst = MTK_EINT_DBNC_RST_BIT << ((idx % 4) * 8);
353 writel(rst, eint->base[inst] + ctrl_offset);
354 }
355 }
356
mtk_eint_irq_handler(struct irq_desc * desc)357 static void mtk_eint_irq_handler(struct irq_desc *desc)
358 {
359 struct irq_chip *chip = irq_desc_get_chip(desc);
360 struct mtk_eint *eint = irq_desc_get_handler_data(desc);
361 unsigned int i, j, port, status, shift, mask, eint_num;
362 void __iomem *reg;
363 int dual_edge, start_level, curr_level;
364
365 chained_irq_enter(chip, desc);
366 for (i = 0; i < eint->nbase; i++) {
367 for (j = 0; j < eint->base_pin_num[i]; j += 32) {
368 port = j >> 5;
369 status = readl(eint->base[i] + port * 4 + eint->regs->stat);
370 while (status) {
371 shift = __ffs(status);
372 status &= ~BIT(shift);
373 mask = BIT(shift);
374 eint_num = eint->pin_list[i][shift + j];
375
376 /*
377 * If we get an interrupt on pin that was only required
378 * for wake (but no real interrupt requested), mask the
379 * interrupt (as would mtk_eint_resume do anyway later
380 * in the resume sequence).
381 */
382 if (eint->wake_mask[i][port] & mask &&
383 !(eint->cur_mask[i][port] & mask)) {
384 reg = mtk_eint_get_offset(eint, eint_num,
385 eint->regs->mask_set);
386 writel_relaxed(mask, reg);
387 }
388
389 dual_edge = eint->pins[eint_num].dual_edge;
390 if (dual_edge) {
391 /*
392 * Clear soft-irq in case we raised it last
393 * time.
394 */
395 reg = mtk_eint_get_offset(eint, eint_num,
396 eint->regs->soft_clr);
397 writel(mask, reg);
398
399 start_level =
400 eint->gpio_xlate->get_gpio_state(eint->pctl,
401 eint_num);
402 }
403
404 generic_handle_domain_irq(eint->domain, eint_num);
405
406 if (dual_edge) {
407 curr_level = mtk_eint_flip_edge(eint, eint_num);
408
409 /*
410 * If level changed, we might lost one edge
411 * interrupt, raised it through soft-irq.
412 */
413 if (start_level != curr_level) {
414 reg = mtk_eint_get_offset(eint, eint_num,
415 eint->regs->soft_set);
416 writel(mask, reg);
417 }
418 }
419
420 if (eint->pins[eint_num].debounce)
421 mtk_eint_debounce_process(eint, eint_num);
422 }
423 }
424 }
425 chained_irq_exit(chip, desc);
426 }
427
mtk_eint_do_suspend(struct mtk_eint * eint)428 int mtk_eint_do_suspend(struct mtk_eint *eint)
429 {
430 mtk_eint_chip_write_mask(eint, eint->wake_mask);
431
432 return 0;
433 }
434 EXPORT_SYMBOL_GPL(mtk_eint_do_suspend);
435
mtk_eint_do_resume(struct mtk_eint * eint)436 int mtk_eint_do_resume(struct mtk_eint *eint)
437 {
438 mtk_eint_chip_write_mask(eint, eint->cur_mask);
439
440 return 0;
441 }
442 EXPORT_SYMBOL_GPL(mtk_eint_do_resume);
443
mtk_eint_set_debounce(struct mtk_eint * eint,unsigned long eint_num,unsigned int debounce)444 int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num,
445 unsigned int debounce)
446 {
447 int virq, eint_offset;
448 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
449 dbnc;
450 unsigned int inst = eint->pins[eint_num].instance;
451 unsigned int idx = eint->pins[eint_num].index;
452 struct irq_data *d;
453
454 if (!eint->hw->db_time)
455 return -EOPNOTSUPP;
456
457 virq = irq_find_mapping(eint->domain, eint_num);
458 eint_offset = (idx % 4) * 8;
459 d = irq_get_irq_data(virq);
460
461 set_offset = (idx / 4) * 4 + eint->regs->dbnc_set;
462 clr_offset = (idx / 4) * 4 + eint->regs->dbnc_clr;
463
464 if (!mtk_eint_can_en_debounce(eint, eint_num))
465 return -EINVAL;
466
467 dbnc = eint->num_db_time;
468 for (i = 0; i < eint->num_db_time; i++) {
469 if (debounce <= eint->hw->db_time[i]) {
470 dbnc = i;
471 break;
472 }
473 }
474
475 if (!mtk_eint_get_mask(eint, eint_num)) {
476 mtk_eint_mask(d);
477 unmask = 1;
478 } else {
479 unmask = 0;
480 }
481
482 clr_bit = 0xff << eint_offset;
483 writel(clr_bit, eint->base[inst] + clr_offset);
484
485 bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) <<
486 eint_offset;
487 rst = MTK_EINT_DBNC_RST_BIT << eint_offset;
488 writel(rst | bit, eint->base[inst] + set_offset);
489
490 /*
491 * Delay a while (more than 2T) to wait for hw debounce counter reset
492 * work correctly.
493 */
494 udelay(1);
495 if (unmask == 1)
496 mtk_eint_unmask(d);
497
498 return 0;
499 }
500 EXPORT_SYMBOL_GPL(mtk_eint_set_debounce);
501
mtk_eint_find_irq(struct mtk_eint * eint,unsigned long eint_n)502 int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
503 {
504 int irq;
505
506 irq = irq_find_mapping(eint->domain, eint_n);
507 if (!irq)
508 return -EINVAL;
509
510 return irq;
511 }
512 EXPORT_SYMBOL_GPL(mtk_eint_find_irq);
513
mtk_eint_teardown(void * data)514 static void mtk_eint_teardown(void *data)
515 {
516 struct mtk_eint *eint = data;
517 unsigned int i, virq;
518
519 /* Detach the demux handler so it can no longer reference freed data. */
520 irq_set_chained_handler_and_data(eint->irq, NULL, NULL);
521
522 /* Wait for any in-flight handler to finish before tearing down. */
523 synchronize_irq(eint->irq);
524
525 /* Dispose of all child mappings before the domain is removed. */
526 for (i = 0; i < eint->hw->ap_num; i++) {
527 virq = irq_find_mapping(eint->domain, i);
528 if (virq)
529 irq_dispose_mapping(virq);
530 }
531
532 irq_domain_remove(eint->domain);
533 }
534
mtk_eint_do_init(struct mtk_eint * eint,struct mtk_eint_pin * eint_pin)535 int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin)
536 {
537 unsigned int size, i, port, virq, inst = 0;
538
539 /* If clients don't assign a specific regs, let's use generic one */
540 if (!eint->regs)
541 eint->regs = &mtk_generic_eint_regs;
542
543 eint->base_pin_num = devm_kmalloc_array(eint->dev, eint->nbase, sizeof(u16),
544 GFP_KERNEL | __GFP_ZERO);
545 if (!eint->base_pin_num)
546 return -ENOMEM;
547
548 if (eint_pin) {
549 eint->pins = eint_pin;
550 for (i = 0; i < eint->hw->ap_num; i++) {
551 inst = eint->pins[i].instance;
552 if (inst >= eint->nbase)
553 continue;
554 eint->base_pin_num[inst]++;
555 }
556 } else {
557 size = eint->hw->ap_num * sizeof(struct mtk_eint_pin);
558 eint->pins = devm_kmalloc(eint->dev, size, GFP_KERNEL);
559 if (!eint->pins)
560 goto err_pins;
561
562 eint->base_pin_num[inst] = eint->hw->ap_num;
563 for (i = 0; i < eint->hw->ap_num; i++) {
564 eint->pins[i].instance = inst;
565 eint->pins[i].index = i;
566 eint->pins[i].debounce = (i < eint->hw->db_cnt) ? 1 : 0;
567 }
568 }
569
570 eint->pin_list = devm_kcalloc(eint->dev, eint->nbase,
571 sizeof(*eint->pin_list), GFP_KERNEL);
572 if (!eint->pin_list)
573 goto err_pin_list;
574
575 eint->wake_mask = devm_kcalloc(eint->dev, eint->nbase,
576 sizeof(*eint->wake_mask), GFP_KERNEL);
577 if (!eint->wake_mask)
578 goto err_wake_mask;
579
580 eint->cur_mask = devm_kcalloc(eint->dev, eint->nbase,
581 sizeof(*eint->cur_mask), GFP_KERNEL);
582 if (!eint->cur_mask)
583 goto err_cur_mask;
584
585 for (i = 0; i < eint->nbase; i++) {
586 eint->pin_list[i] = devm_kzalloc(eint->dev,
587 eint->base_pin_num[i] * sizeof(**eint->pin_list),
588 GFP_KERNEL);
589 port = DIV_ROUND_UP(eint->base_pin_num[i], 32);
590 eint->wake_mask[i] = devm_kzalloc(eint->dev,
591 port * sizeof(**eint->wake_mask),
592 GFP_KERNEL);
593 eint->cur_mask[i] = devm_kzalloc(eint->dev,
594 port * sizeof(**eint->cur_mask),
595 GFP_KERNEL);
596 if (!eint->pin_list[i] || !eint->wake_mask[i] || !eint->cur_mask[i])
597 goto err_eint;
598 }
599
600 eint->domain = irq_domain_create_linear(dev_fwnode(eint->dev), eint->hw->ap_num,
601 &irq_domain_simple_ops, NULL);
602 if (!eint->domain)
603 goto err_eint;
604
605 if (eint->hw->db_time) {
606 for (i = 0; i < MTK_EINT_DBNC_MAX; i++)
607 if (eint->hw->db_time[i] == 0)
608 break;
609 eint->num_db_time = i;
610 }
611
612 mtk_eint_hw_init(eint);
613 for (i = 0; i < eint->hw->ap_num; i++) {
614 inst = eint->pins[i].instance;
615 if (inst >= eint->nbase)
616 continue;
617 eint->pin_list[inst][eint->pins[i].index] = i;
618 virq = irq_create_mapping(eint->domain, i);
619 irq_set_chip_and_handler(virq, &mtk_eint_irq_chip,
620 handle_level_irq);
621 irq_set_chip_data(virq, eint);
622 }
623
624 irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler,
625 eint);
626
627 return devm_add_action_or_reset(eint->dev, mtk_eint_teardown, eint);
628
629 err_eint:
630 for (i = 0; i < eint->nbase; i++) {
631 devm_kfree(eint->dev, eint->cur_mask[i]);
632 devm_kfree(eint->dev, eint->wake_mask[i]);
633 devm_kfree(eint->dev, eint->pin_list[i]);
634 }
635 devm_kfree(eint->dev, eint->cur_mask);
636 err_cur_mask:
637 devm_kfree(eint->dev, eint->wake_mask);
638 err_wake_mask:
639 devm_kfree(eint->dev, eint->pin_list);
640 err_pin_list:
641 if (!eint_pin)
642 devm_kfree(eint->dev, eint->pins);
643 err_pins:
644 devm_kfree(eint->dev, eint->base_pin_num);
645 return -ENOMEM;
646 }
647 EXPORT_SYMBOL_GPL(mtk_eint_do_init);
648
649 MODULE_LICENSE("GPL v2");
650 MODULE_DESCRIPTION("MediaTek EINT Driver");
651