1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitops.h>
7 #include <linux/completion.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/iio/adc/qcom-vadc-common.h>
11 #include <linux/iio/iio.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/log2.h>
15 #include <linux/math64.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/property.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21
22 #include <dt-bindings/iio/qcom,spmi-vadc.h>
23
24 #define ADC5_USR_REVISION1 0x0
25 #define ADC5_USR_STATUS1 0x8
26 #define ADC5_USR_STATUS1_CONV_FAULT BIT(7)
27 #define ADC5_USR_STATUS1_REQ_STS BIT(1)
28 #define ADC5_USR_STATUS1_EOC BIT(0)
29 #define ADC5_USR_STATUS1_REQ_STS_EOC_MASK 0x3
30
31 #define ADC5_USR_STATUS2 0x9
32 #define ADC5_USR_STATUS2_CONV_SEQ_MASK 0x70
33 #define ADC5_USR_STATUS2_CONV_SEQ_MASK_SHIFT 0x5
34
35 #define ADC5_USR_IBAT_MEAS 0xf
36 #define ADC5_USR_IBAT_MEAS_SUPPORTED BIT(0)
37
38 #define ADC5_USR_DIG_PARAM 0x42
39 #define ADC5_USR_DIG_PARAM_CAL_VAL BIT(6)
40 #define ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT 6
41 #define ADC5_USR_DIG_PARAM_CAL_SEL 0x30
42 #define ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT 4
43 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL 0xc
44 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT 2
45
46 #define ADC5_USR_FAST_AVG_CTL 0x43
47 #define ADC5_USR_FAST_AVG_CTL_EN BIT(7)
48 #define ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK 0x7
49
50 #define ADC5_USR_CH_SEL_CTL 0x44
51
52 #define ADC5_USR_DELAY_CTL 0x45
53 #define ADC5_USR_HW_SETTLE_DELAY_MASK 0xf
54
55 #define ADC5_USR_EN_CTL1 0x46
56 #define ADC5_USR_EN_CTL1_ADC_EN BIT(7)
57
58 #define ADC5_USR_CONV_REQ 0x47
59 #define ADC5_USR_CONV_REQ_REQ BIT(7)
60
61 #define ADC5_USR_DATA0 0x50
62
63 #define ADC5_USR_DATA1 0x51
64
65 #define ADC5_USR_IBAT_DATA0 0x52
66
67 #define ADC5_USR_IBAT_DATA1 0x53
68
69 #define ADC_CHANNEL_OFFSET 0x8
70 #define ADC_CHANNEL_MASK GENMASK(7, 0)
71
72 /*
73 * Conversion time varies based on the decimation, clock rate, fast average
74 * samples and measurements queued across different VADC peripherals.
75 * Set the timeout to a max of 100ms.
76 */
77 #define ADC5_CONV_TIME_MIN_US 263
78 #define ADC5_CONV_TIME_MAX_US 264
79 #define ADC5_CONV_TIME_RETRY 400
80 #define ADC5_CONV_TIMEOUT msecs_to_jiffies(100)
81
82 /* Digital version >= 5.3 supports hw_settle_2 */
83 #define ADC5_HW_SETTLE_DIFF_MINOR 3
84 #define ADC5_HW_SETTLE_DIFF_MAJOR 5
85
86 /* For PMIC7 */
87 #define ADC_APP_SID 0x40
88 #define ADC_APP_SID_MASK GENMASK(3, 0)
89 #define ADC7_CONV_TIMEOUT msecs_to_jiffies(10)
90
91 enum adc5_cal_method {
92 ADC5_NO_CAL = 0,
93 ADC5_RATIOMETRIC_CAL,
94 ADC5_ABSOLUTE_CAL
95 };
96
97 enum adc5_cal_val {
98 ADC5_TIMER_CAL = 0,
99 ADC5_NEW_CAL
100 };
101
102 /**
103 * struct adc5_channel_prop - ADC channel property.
104 * @channel: channel number, refer to the channel list.
105 * @cal_method: calibration method.
106 * @cal_val: calibration value
107 * @decimation: sampling rate supported for the channel.
108 * @sid: slave id of PMIC owning the channel, for PMIC7.
109 * @prescale: channel scaling performed on the input signal.
110 * @hw_settle_time: the time between AMUX being configured and the
111 * start of conversion.
112 * @avg_samples: ability to provide single result from the ADC
113 * that is an average of multiple measurements.
114 * @scale_fn_type: Represents the scaling function to convert voltage
115 * physical units desired by the client for the channel.
116 * @channel_name: Channel name used in device tree.
117 */
118 struct adc5_channel_prop {
119 unsigned int channel;
120 enum adc5_cal_method cal_method;
121 enum adc5_cal_val cal_val;
122 unsigned int decimation;
123 unsigned int sid;
124 unsigned int prescale;
125 unsigned int hw_settle_time;
126 unsigned int avg_samples;
127 enum vadc_scale_fn_type scale_fn_type;
128 const char *channel_name;
129 };
130
131 /**
132 * struct adc5_chip - ADC private structure.
133 * @regmap: SPMI ADC5 peripheral register map field.
134 * @dev: SPMI ADC5 device.
135 * @base: base address for the ADC peripheral.
136 * @nchannels: number of ADC channels.
137 * @chan_props: array of ADC channel properties.
138 * @iio_chans: array of IIO channels specification.
139 * @poll_eoc: use polling instead of interrupt.
140 * @complete: ADC result notification after interrupt is received.
141 * @lock: ADC lock for access to the peripheral.
142 * @data: software configuration data.
143 */
144 struct adc5_chip {
145 struct regmap *regmap;
146 struct device *dev;
147 u16 base;
148 unsigned int nchannels;
149 struct adc5_channel_prop *chan_props;
150 struct iio_chan_spec *iio_chans;
151 bool poll_eoc;
152 struct completion complete;
153 struct mutex lock;
154 const struct adc5_data *data;
155 };
156
adc5_read(struct adc5_chip * adc,u16 offset,u8 * data,int len)157 static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len)
158 {
159 return regmap_bulk_read(adc->regmap, adc->base + offset, data, len);
160 }
161
adc5_write(struct adc5_chip * adc,u16 offset,u8 * data,int len)162 static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len)
163 {
164 return regmap_bulk_write(adc->regmap, adc->base + offset, data, len);
165 }
166
adc5_masked_write(struct adc5_chip * adc,u16 offset,u8 mask,u8 val)167 static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val)
168 {
169 return regmap_update_bits(adc->regmap, adc->base + offset, mask, val);
170 }
171
adc5_read_voltage_data(struct adc5_chip * adc,u16 * data)172 static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data)
173 {
174 int ret;
175 u8 rslt_lsb, rslt_msb;
176
177 ret = adc5_read(adc, ADC5_USR_DATA0, &rslt_lsb, sizeof(rslt_lsb));
178 if (ret)
179 return ret;
180
181 ret = adc5_read(adc, ADC5_USR_DATA1, &rslt_msb, sizeof(rslt_lsb));
182 if (ret)
183 return ret;
184
185 *data = (rslt_msb << 8) | rslt_lsb;
186
187 if (*data == ADC5_USR_DATA_CHECK) {
188 dev_err(adc->dev, "Invalid data:0x%x\n", *data);
189 return -EINVAL;
190 }
191
192 dev_dbg(adc->dev, "voltage raw code:0x%x\n", *data);
193
194 return 0;
195 }
196
adc5_poll_wait_eoc(struct adc5_chip * adc)197 static int adc5_poll_wait_eoc(struct adc5_chip *adc)
198 {
199 unsigned int count, retry = ADC5_CONV_TIME_RETRY;
200 u8 status1;
201 int ret;
202
203 for (count = 0; count < retry; count++) {
204 ret = adc5_read(adc, ADC5_USR_STATUS1, &status1,
205 sizeof(status1));
206 if (ret)
207 return ret;
208
209 status1 &= ADC5_USR_STATUS1_REQ_STS_EOC_MASK;
210 if (status1 == ADC5_USR_STATUS1_EOC)
211 return 0;
212
213 usleep_range(ADC5_CONV_TIME_MIN_US, ADC5_CONV_TIME_MAX_US);
214 }
215
216 return -ETIMEDOUT;
217 }
218
adc5_update_dig_param(struct adc5_chip * adc,struct adc5_channel_prop * prop,u8 * data)219 static void adc5_update_dig_param(struct adc5_chip *adc,
220 struct adc5_channel_prop *prop, u8 *data)
221 {
222 /* Update calibration value */
223 *data &= ~ADC5_USR_DIG_PARAM_CAL_VAL;
224 *data |= (prop->cal_val << ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT);
225
226 /* Update calibration select */
227 *data &= ~ADC5_USR_DIG_PARAM_CAL_SEL;
228 *data |= (prop->cal_method << ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT);
229
230 /* Update decimation ratio select */
231 *data &= ~ADC5_USR_DIG_PARAM_DEC_RATIO_SEL;
232 *data |= (prop->decimation << ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT);
233 }
234
adc5_configure(struct adc5_chip * adc,struct adc5_channel_prop * prop)235 static int adc5_configure(struct adc5_chip *adc,
236 struct adc5_channel_prop *prop)
237 {
238 int ret;
239 u8 buf[6];
240
241 /* Read registers 0x42 through 0x46 */
242 ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
243 if (ret)
244 return ret;
245
246 /* Digital param selection */
247 adc5_update_dig_param(adc, prop, &buf[0]);
248
249 /* Update fast average sample value */
250 buf[1] &= (u8) ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
251 buf[1] |= prop->avg_samples;
252
253 /* Select ADC channel */
254 buf[2] = prop->channel;
255
256 /* Select HW settle delay for channel */
257 buf[3] &= (u8) ~ADC5_USR_HW_SETTLE_DELAY_MASK;
258 buf[3] |= prop->hw_settle_time;
259
260 /* Select ADC enable */
261 buf[4] |= ADC5_USR_EN_CTL1_ADC_EN;
262
263 /* Select CONV request */
264 buf[5] |= ADC5_USR_CONV_REQ_REQ;
265
266 if (!adc->poll_eoc)
267 reinit_completion(&adc->complete);
268
269 return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
270 }
271
adc7_configure(struct adc5_chip * adc,struct adc5_channel_prop * prop)272 static int adc7_configure(struct adc5_chip *adc,
273 struct adc5_channel_prop *prop)
274 {
275 int ret;
276 u8 conv_req = 0, buf[4];
277
278 ret = adc5_masked_write(adc, ADC_APP_SID, ADC_APP_SID_MASK, prop->sid);
279 if (ret)
280 return ret;
281
282 ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
283 if (ret)
284 return ret;
285
286 /* Digital param selection */
287 adc5_update_dig_param(adc, prop, &buf[0]);
288
289 /* Update fast average sample value */
290 buf[1] &= ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
291 buf[1] |= prop->avg_samples;
292
293 /* Select ADC channel */
294 buf[2] = prop->channel;
295
296 /* Select HW settle delay for channel */
297 buf[3] &= ~ADC5_USR_HW_SETTLE_DELAY_MASK;
298 buf[3] |= prop->hw_settle_time;
299
300 /* Select CONV request */
301 conv_req = ADC5_USR_CONV_REQ_REQ;
302
303 if (!adc->poll_eoc)
304 reinit_completion(&adc->complete);
305
306 ret = adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
307 if (ret)
308 return ret;
309
310 return adc5_write(adc, ADC5_USR_CONV_REQ, &conv_req, 1);
311 }
312
adc5_do_conversion(struct adc5_chip * adc,struct adc5_channel_prop * prop,struct iio_chan_spec const * chan,u16 * data_volt,u16 * data_cur)313 static int adc5_do_conversion(struct adc5_chip *adc,
314 struct adc5_channel_prop *prop,
315 struct iio_chan_spec const *chan,
316 u16 *data_volt, u16 *data_cur)
317 {
318 int ret;
319
320 mutex_lock(&adc->lock);
321
322 ret = adc5_configure(adc, prop);
323 if (ret) {
324 dev_err(adc->dev, "ADC configure failed with %d\n", ret);
325 goto unlock;
326 }
327
328 if (adc->poll_eoc) {
329 ret = adc5_poll_wait_eoc(adc);
330 if (ret) {
331 dev_err(adc->dev, "EOC bit not set\n");
332 goto unlock;
333 }
334 } else {
335 ret = wait_for_completion_timeout(&adc->complete,
336 ADC5_CONV_TIMEOUT);
337 if (!ret) {
338 dev_dbg(adc->dev, "Did not get completion timeout.\n");
339 ret = adc5_poll_wait_eoc(adc);
340 if (ret) {
341 dev_err(adc->dev, "EOC bit not set\n");
342 goto unlock;
343 }
344 }
345 }
346
347 ret = adc5_read_voltage_data(adc, data_volt);
348 unlock:
349 mutex_unlock(&adc->lock);
350
351 return ret;
352 }
353
adc7_do_conversion(struct adc5_chip * adc,struct adc5_channel_prop * prop,struct iio_chan_spec const * chan,u16 * data_volt,u16 * data_cur)354 static int adc7_do_conversion(struct adc5_chip *adc,
355 struct adc5_channel_prop *prop,
356 struct iio_chan_spec const *chan,
357 u16 *data_volt, u16 *data_cur)
358 {
359 int ret;
360 u8 status;
361
362 mutex_lock(&adc->lock);
363
364 ret = adc7_configure(adc, prop);
365 if (ret) {
366 dev_err(adc->dev, "ADC configure failed with %d\n", ret);
367 goto unlock;
368 }
369
370 /* No support for polling mode at present */
371 wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT);
372
373 ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1);
374 if (ret)
375 goto unlock;
376
377 if (status & ADC5_USR_STATUS1_CONV_FAULT) {
378 dev_err(adc->dev, "Unexpected conversion fault\n");
379 ret = -EIO;
380 goto unlock;
381 }
382
383 ret = adc5_read_voltage_data(adc, data_volt);
384
385 unlock:
386 mutex_unlock(&adc->lock);
387
388 return ret;
389 }
390
391 typedef int (*adc_do_conversion)(struct adc5_chip *adc,
392 struct adc5_channel_prop *prop,
393 struct iio_chan_spec const *chan,
394 u16 *data_volt, u16 *data_cur);
395
adc5_isr(int irq,void * dev_id)396 static irqreturn_t adc5_isr(int irq, void *dev_id)
397 {
398 struct adc5_chip *adc = dev_id;
399
400 complete(&adc->complete);
401
402 return IRQ_HANDLED;
403 }
404
adc5_fwnode_xlate(struct iio_dev * indio_dev,const struct fwnode_reference_args * iiospec)405 static int adc5_fwnode_xlate(struct iio_dev *indio_dev,
406 const struct fwnode_reference_args *iiospec)
407 {
408 struct adc5_chip *adc = iio_priv(indio_dev);
409 int i;
410
411 for (i = 0; i < adc->nchannels; i++)
412 if (adc->chan_props[i].channel == iiospec->args[0])
413 return i;
414
415 return -EINVAL;
416 }
417
adc7_fwnode_xlate(struct iio_dev * indio_dev,const struct fwnode_reference_args * iiospec)418 static int adc7_fwnode_xlate(struct iio_dev *indio_dev,
419 const struct fwnode_reference_args *iiospec)
420 {
421 struct adc5_chip *adc = iio_priv(indio_dev);
422 int i, v_channel;
423
424 for (i = 0; i < adc->nchannels; i++) {
425 v_channel = (adc->chan_props[i].sid << ADC_CHANNEL_OFFSET) |
426 adc->chan_props[i].channel;
427 if (v_channel == iiospec->args[0])
428 return i;
429 }
430
431 return -EINVAL;
432 }
433
adc_read_raw_common(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask,adc_do_conversion do_conv)434 static int adc_read_raw_common(struct iio_dev *indio_dev,
435 struct iio_chan_spec const *chan, int *val, int *val2,
436 long mask, adc_do_conversion do_conv)
437 {
438 struct adc5_chip *adc = iio_priv(indio_dev);
439 struct adc5_channel_prop *prop;
440 u16 adc_code_volt, adc_code_cur;
441 int ret;
442
443 prop = &adc->chan_props[chan->address];
444
445 switch (mask) {
446 case IIO_CHAN_INFO_PROCESSED:
447 ret = do_conv(adc, prop, chan,
448 &adc_code_volt, &adc_code_cur);
449 if (ret)
450 return ret;
451
452 ret = qcom_adc5_hw_scale(prop->scale_fn_type,
453 prop->prescale,
454 adc->data,
455 adc_code_volt, val);
456 if (ret)
457 return ret;
458
459 return IIO_VAL_INT;
460 default:
461 return -EINVAL;
462 }
463 }
464
adc5_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)465 static int adc5_read_raw(struct iio_dev *indio_dev,
466 struct iio_chan_spec const *chan, int *val, int *val2,
467 long mask)
468 {
469 return adc_read_raw_common(indio_dev, chan, val, val2,
470 mask, adc5_do_conversion);
471 }
472
adc7_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)473 static int adc7_read_raw(struct iio_dev *indio_dev,
474 struct iio_chan_spec const *chan, int *val, int *val2,
475 long mask)
476 {
477 return adc_read_raw_common(indio_dev, chan, val, val2,
478 mask, adc7_do_conversion);
479 }
480
481 static const struct iio_info adc5_info = {
482 .read_raw = adc5_read_raw,
483 .fwnode_xlate = adc5_fwnode_xlate,
484 };
485
486 static const struct iio_info adc7_info = {
487 .read_raw = adc7_read_raw,
488 .fwnode_xlate = adc7_fwnode_xlate,
489 };
490
491 struct adc5_channels {
492 const char *datasheet_name;
493 unsigned int prescale_index;
494 enum iio_chan_type type;
495 long info_mask;
496 enum vadc_scale_fn_type scale_fn_type;
497 };
498
499 /* In these definitions, _pre refers to an index into adc5_prescale_ratios. */
500 #define ADC5_CHAN(_dname, _type, _mask, _pre, _scale) \
501 { \
502 .datasheet_name = _dname, \
503 .prescale_index = _pre, \
504 .type = _type, \
505 .info_mask = _mask, \
506 .scale_fn_type = _scale, \
507 }, \
508
509 #define ADC5_CHAN_TEMP(_dname, _pre, _scale) \
510 ADC5_CHAN(_dname, IIO_TEMP, \
511 BIT(IIO_CHAN_INFO_PROCESSED), \
512 _pre, _scale) \
513
514 #define ADC5_CHAN_VOLT(_dname, _pre, _scale) \
515 ADC5_CHAN(_dname, IIO_VOLTAGE, \
516 BIT(IIO_CHAN_INFO_PROCESSED), \
517 _pre, _scale) \
518
519 static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = {
520 [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
521 SCALE_HW_CALIB_DEFAULT)
522 [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
523 SCALE_HW_CALIB_DEFAULT)
524 [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
525 SCALE_HW_CALIB_DEFAULT)
526 [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
527 SCALE_HW_CALIB_DEFAULT)
528 [ADC5_VCOIN] = ADC5_CHAN_VOLT("vcoin", 1,
529 SCALE_HW_CALIB_DEFAULT)
530 [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
531 SCALE_HW_CALIB_PMIC_THERM)
532 [ADC5_USB_IN_I] = ADC5_CHAN_VOLT("usb_in_i_uv", 0,
533 SCALE_HW_CALIB_DEFAULT)
534 [ADC5_USB_IN_V_16] = ADC5_CHAN_VOLT("usb_in_v_div_16", 8,
535 SCALE_HW_CALIB_DEFAULT)
536 [ADC5_CHG_TEMP] = ADC5_CHAN_TEMP("chg_temp", 0,
537 SCALE_HW_CALIB_PM5_CHG_TEMP)
538 /* Charger prescales SBUx and MID_CHG to fit within 1.8V upper unit */
539 [ADC5_SBUx] = ADC5_CHAN_VOLT("chg_sbux", 1,
540 SCALE_HW_CALIB_DEFAULT)
541 [ADC5_MID_CHG_DIV6] = ADC5_CHAN_VOLT("chg_mid_chg", 3,
542 SCALE_HW_CALIB_DEFAULT)
543 [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm", 0,
544 SCALE_HW_CALIB_XOTHERM)
545 [ADC5_BAT_ID_100K_PU] = ADC5_CHAN_TEMP("bat_id", 0,
546 SCALE_HW_CALIB_DEFAULT)
547 [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
548 SCALE_HW_CALIB_THERM_100K_PULLUP)
549 [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
550 SCALE_HW_CALIB_THERM_100K_PULLUP)
551 [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
552 SCALE_HW_CALIB_THERM_100K_PULLUP)
553 [ADC5_AMUX_THM2] = ADC5_CHAN_TEMP("amux_thm2", 0,
554 SCALE_HW_CALIB_PM5_SMB_TEMP)
555 [ADC5_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_100k_pu", 0,
556 SCALE_HW_CALIB_THERM_100K_PULLUP)
557 [ADC5_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_100k_pu", 0,
558 SCALE_HW_CALIB_THERM_100K_PULLUP)
559 [ADC5_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_100k_pu", 0,
560 SCALE_HW_CALIB_THERM_100K_PULLUP)
561 [ADC5_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_100k_pu", 0,
562 SCALE_HW_CALIB_THERM_100K_PULLUP)
563 };
564
565 static const struct adc5_channels adc7_chans_pmic[ADC5_MAX_CHANNEL] = {
566 [ADC7_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
567 SCALE_HW_CALIB_DEFAULT)
568 [ADC7_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
569 SCALE_HW_CALIB_DEFAULT)
570 [ADC7_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
571 SCALE_HW_CALIB_DEFAULT)
572 [ADC7_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3,
573 SCALE_HW_CALIB_DEFAULT)
574 [ADC7_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
575 SCALE_HW_CALIB_PMIC_THERM_PM7)
576 [ADC7_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0,
577 SCALE_HW_CALIB_THERM_100K_PU_PM7)
578 [ADC7_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0,
579 SCALE_HW_CALIB_THERM_100K_PU_PM7)
580 [ADC7_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0,
581 SCALE_HW_CALIB_THERM_100K_PU_PM7)
582 [ADC7_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0,
583 SCALE_HW_CALIB_THERM_100K_PU_PM7)
584 [ADC7_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0,
585 SCALE_HW_CALIB_THERM_100K_PU_PM7)
586 [ADC7_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0,
587 SCALE_HW_CALIB_THERM_100K_PU_PM7)
588 [ADC7_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_pu2", 0,
589 SCALE_HW_CALIB_THERM_100K_PU_PM7)
590 [ADC7_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_pu2", 0,
591 SCALE_HW_CALIB_THERM_100K_PU_PM7)
592 [ADC7_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_pu2", 0,
593 SCALE_HW_CALIB_THERM_100K_PU_PM7)
594 [ADC7_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_pu2", 0,
595 SCALE_HW_CALIB_THERM_100K_PU_PM7)
596 };
597
598 static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = {
599 [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
600 SCALE_HW_CALIB_DEFAULT)
601 [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
602 SCALE_HW_CALIB_DEFAULT)
603 [ADC5_VREF_VADC] = ADC5_CHAN_VOLT("vref_vadc", 0,
604 SCALE_HW_CALIB_DEFAULT)
605 [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
606 SCALE_HW_CALIB_DEFAULT)
607 [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
608 SCALE_HW_CALIB_DEFAULT)
609 [ADC5_VCOIN] = ADC5_CHAN_VOLT("vcoin", 1,
610 SCALE_HW_CALIB_DEFAULT)
611 [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
612 SCALE_HW_CALIB_PMIC_THERM)
613 [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
614 SCALE_HW_CALIB_THERM_100K_PULLUP)
615 [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
616 SCALE_HW_CALIB_THERM_100K_PULLUP)
617 [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
618 SCALE_HW_CALIB_THERM_100K_PULLUP)
619 [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 0,
620 SCALE_HW_CALIB_THERM_100K_PULLUP)
621 [ADC5_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_100k_pu", 0,
622 SCALE_HW_CALIB_THERM_100K_PULLUP)
623 [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm_100k_pu", 0,
624 SCALE_HW_CALIB_THERM_100K_PULLUP)
625 };
626
adc5_get_fw_channel_data(struct adc5_chip * adc,struct adc5_channel_prop * prop,struct fwnode_handle * fwnode,const struct adc5_data * data)627 static int adc5_get_fw_channel_data(struct adc5_chip *adc,
628 struct adc5_channel_prop *prop,
629 struct fwnode_handle *fwnode,
630 const struct adc5_data *data)
631 {
632 const char *channel_name;
633 char *name;
634 u32 chan, value, varr[2];
635 u32 sid = 0;
636 int ret;
637 struct device *dev = adc->dev;
638
639 name = devm_kasprintf(dev, GFP_KERNEL, "%pfwP", fwnode);
640 if (!name)
641 return -ENOMEM;
642
643 /* Cut the address part */
644 name[strchrnul(name, '@') - name] = '\0';
645
646 ret = fwnode_property_read_u32(fwnode, "reg", &chan);
647 if (ret) {
648 dev_err(dev, "invalid channel number %s\n", name);
649 return ret;
650 }
651
652 /* Value read from "reg" is virtual channel number */
653
654 /* virtual channel number = sid << 8 | channel number */
655
656 if (adc->data->info == &adc7_info) {
657 sid = chan >> ADC_CHANNEL_OFFSET;
658 chan = chan & ADC_CHANNEL_MASK;
659 }
660
661 if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA) {
662 dev_err(dev, "%s invalid channel number %d\n", name, chan);
663 return -EINVAL;
664 }
665
666 /* the channel has DT description */
667 prop->channel = chan;
668 prop->sid = sid;
669
670 ret = fwnode_property_read_string(fwnode, "label", &channel_name);
671 if (ret)
672 channel_name = data->adc_chans[chan].datasheet_name;
673
674 prop->channel_name = channel_name;
675
676 ret = fwnode_property_read_u32(fwnode, "qcom,decimation", &value);
677 if (!ret) {
678 ret = qcom_adc5_decimation_from_dt(value, data->decimation);
679 if (ret < 0) {
680 dev_err(dev, "%02x invalid decimation %d\n",
681 chan, value);
682 return ret;
683 }
684 prop->decimation = ret;
685 } else {
686 prop->decimation = ADC5_DECIMATION_DEFAULT;
687 }
688
689 ret = fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, 2);
690 if (!ret) {
691 ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
692 if (ret < 0) {
693 dev_err(dev, "%02x invalid pre-scaling <%d %d>\n",
694 chan, varr[0], varr[1]);
695 return ret;
696 }
697 prop->prescale = ret;
698 } else {
699 prop->prescale =
700 adc->data->adc_chans[prop->channel].prescale_index;
701 }
702
703 ret = fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value);
704 if (!ret) {
705 u8 dig_version[2];
706
707 ret = adc5_read(adc, ADC5_USR_REVISION1, dig_version,
708 sizeof(dig_version));
709 if (ret) {
710 dev_err(dev, "Invalid dig version read %d\n", ret);
711 return ret;
712 }
713
714 dev_dbg(dev, "dig_ver:minor:%d, major:%d\n", dig_version[0],
715 dig_version[1]);
716 /* Digital controller >= 5.3 have hw_settle_2 option */
717 if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR &&
718 dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) ||
719 adc->data->info == &adc7_info)
720 ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_2);
721 else
722 ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1);
723
724 if (ret < 0) {
725 dev_err(dev, "%02x invalid hw-settle-time %d us\n",
726 chan, value);
727 return ret;
728 }
729 prop->hw_settle_time = ret;
730 } else {
731 prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
732 }
733
734 ret = fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value);
735 if (!ret) {
736 ret = qcom_adc5_avg_samples_from_dt(value);
737 if (ret < 0) {
738 dev_err(dev, "%02x invalid avg-samples %d\n",
739 chan, value);
740 return ret;
741 }
742 prop->avg_samples = ret;
743 } else {
744 prop->avg_samples = VADC_DEF_AVG_SAMPLES;
745 }
746
747 if (fwnode_property_read_bool(fwnode, "qcom,ratiometric"))
748 prop->cal_method = ADC5_RATIOMETRIC_CAL;
749 else
750 prop->cal_method = ADC5_ABSOLUTE_CAL;
751
752 /*
753 * Default to using timer calibration. Using a fresh calibration value
754 * for every conversion will increase the overall time for a request.
755 */
756 prop->cal_val = ADC5_TIMER_CAL;
757
758 dev_dbg(dev, "%02x name %s\n", chan, name);
759
760 return 0;
761 }
762
763 static const struct adc5_data adc5_data_pmic = {
764 .full_scale_code_volt = 0x70e4,
765 .full_scale_code_cur = 0x2710,
766 .adc_chans = adc5_chans_pmic,
767 .info = &adc5_info,
768 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
769 {250, 420, 840},
770 .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
771 {15, 100, 200, 300, 400, 500, 600, 700,
772 800, 900, 1, 2, 4, 6, 8, 10},
773 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
774 {15, 100, 200, 300, 400, 500, 600, 700,
775 1, 2, 4, 8, 16, 32, 64, 128},
776 };
777
778 static const struct adc5_data adc7_data_pmic = {
779 .full_scale_code_volt = 0x70e4,
780 .adc_chans = adc7_chans_pmic,
781 .info = &adc7_info,
782 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
783 {85, 340, 1360},
784 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
785 {15, 100, 200, 300, 400, 500, 600, 700,
786 1000, 2000, 4000, 8000, 16000, 32000,
787 64000, 128000},
788 };
789
790 static const struct adc5_data adc5_data_pmic_rev2 = {
791 .full_scale_code_volt = 0x4000,
792 .full_scale_code_cur = 0x1800,
793 .adc_chans = adc5_chans_rev2,
794 .info = &adc5_info,
795 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
796 {256, 512, 1024},
797 .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
798 {0, 100, 200, 300, 400, 500, 600, 700,
799 800, 900, 1, 2, 4, 6, 8, 10},
800 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
801 {15, 100, 200, 300, 400, 500, 600, 700,
802 1, 2, 4, 8, 16, 32, 64, 128},
803 };
804
805 static const struct of_device_id adc5_match_table[] = {
806 {
807 .compatible = "qcom,spmi-adc5",
808 .data = &adc5_data_pmic,
809 },
810 {
811 .compatible = "qcom,spmi-adc7",
812 .data = &adc7_data_pmic,
813 },
814 {
815 .compatible = "qcom,spmi-adc-rev2",
816 .data = &adc5_data_pmic_rev2,
817 },
818 { }
819 };
820 MODULE_DEVICE_TABLE(of, adc5_match_table);
821
adc5_get_fw_data(struct adc5_chip * adc)822 static int adc5_get_fw_data(struct adc5_chip *adc)
823 {
824 const struct adc5_channels *adc_chan;
825 struct iio_chan_spec *iio_chan;
826 struct adc5_channel_prop prop, *chan_props;
827 unsigned int index = 0;
828 int ret;
829
830 adc->nchannels = device_get_child_node_count(adc->dev);
831 if (!adc->nchannels)
832 return dev_err_probe(adc->dev, -EINVAL, "no channels defined\n");
833
834 adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
835 sizeof(*adc->iio_chans), GFP_KERNEL);
836 if (!adc->iio_chans)
837 return -ENOMEM;
838
839 adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
840 sizeof(*adc->chan_props), GFP_KERNEL);
841 if (!adc->chan_props)
842 return -ENOMEM;
843
844 chan_props = adc->chan_props;
845 iio_chan = adc->iio_chans;
846 adc->data = device_get_match_data(adc->dev);
847 if (!adc->data)
848 adc->data = &adc5_data_pmic;
849
850 device_for_each_child_node_scoped(adc->dev, child) {
851 ret = adc5_get_fw_channel_data(adc, &prop, child, adc->data);
852 if (ret)
853 return ret;
854
855 prop.scale_fn_type =
856 adc->data->adc_chans[prop.channel].scale_fn_type;
857 *chan_props = prop;
858 adc_chan = &adc->data->adc_chans[prop.channel];
859
860 iio_chan->channel = prop.channel;
861 iio_chan->datasheet_name = adc_chan->datasheet_name;
862 iio_chan->extend_name = prop.channel_name;
863 iio_chan->info_mask_separate = adc_chan->info_mask;
864 iio_chan->type = adc_chan->type;
865 iio_chan->address = index;
866 iio_chan++;
867 chan_props++;
868 index++;
869 }
870
871 return 0;
872 }
873
adc5_probe(struct platform_device * pdev)874 static int adc5_probe(struct platform_device *pdev)
875 {
876 struct device *dev = &pdev->dev;
877 struct iio_dev *indio_dev;
878 struct adc5_chip *adc;
879 struct regmap *regmap;
880 int ret, irq_eoc;
881 u32 reg;
882
883 regmap = dev_get_regmap(dev->parent, NULL);
884 if (!regmap)
885 return -ENODEV;
886
887 ret = device_property_read_u32(dev, "reg", ®);
888 if (ret < 0)
889 return ret;
890
891 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
892 if (!indio_dev)
893 return -ENOMEM;
894
895 adc = iio_priv(indio_dev);
896 adc->regmap = regmap;
897 adc->dev = dev;
898 adc->base = reg;
899
900 init_completion(&adc->complete);
901 mutex_init(&adc->lock);
902
903 ret = adc5_get_fw_data(adc);
904 if (ret)
905 return ret;
906
907 irq_eoc = platform_get_irq(pdev, 0);
908 if (irq_eoc < 0) {
909 if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL)
910 return irq_eoc;
911 adc->poll_eoc = true;
912 } else {
913 ret = devm_request_irq(dev, irq_eoc, adc5_isr, 0,
914 "pm-adc5", adc);
915 if (ret)
916 return ret;
917 }
918
919 indio_dev->name = pdev->name;
920 indio_dev->modes = INDIO_DIRECT_MODE;
921 indio_dev->info = adc->data->info;
922 indio_dev->channels = adc->iio_chans;
923 indio_dev->num_channels = adc->nchannels;
924
925 return devm_iio_device_register(dev, indio_dev);
926 }
927
928 static struct platform_driver adc5_driver = {
929 .driver = {
930 .name = "qcom-spmi-adc5",
931 .of_match_table = adc5_match_table,
932 },
933 .probe = adc5_probe,
934 };
935 module_platform_driver(adc5_driver);
936
937 MODULE_ALIAS("platform:qcom-spmi-adc5");
938 MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 ADC driver");
939 MODULE_LICENSE("GPL v2");
940