1 /* 2 * Copyright (c) 2025 Arm Ltd 3 * 4 * SPDX-License-Identifier: BSD-2-Clause 5 */ 6 7 #ifndef _ARM64_GICV5VAR_H_ 8 #define _ARM64_GICV5VAR_H_ 9 10 DECLARE_CLASS(gicv5_driver); 11 12 struct gicv5_irqsrc; 13 struct gicv5_irs_irqspec; 14 15 enum gicv5_irq_space { 16 GICv5_INVALID, 17 /* GICv5 interrupt types so they are the same values as in the spec */ 18 GICv5_PPI, 19 GICv5_LPI, 20 GICv5_SPI, 21 }; 22 23 /* 24 * Shared between the IRS and ITS 25 */ 26 struct gicv5_base_irqsrc { 27 struct intr_irqsrc gbi_isrc; 28 enum gicv5_irq_space gbi_space; 29 bool gbi_ipi; 30 uint32_t gbi_irq; 31 }; 32 33 struct gicv5_irs; 34 35 struct gicv5_softc { 36 device_t gic_dev; 37 struct intr_pic *gic_pic; 38 39 struct gicv5_irqsrc *gic_ppi_irqs; 40 struct gicv5_irqsrc *gic_irs_irqs; 41 struct gicv5_irqsrc *gic_ipi_irqs; 42 struct gicv5_irs **gic_irs; 43 44 device_t *gic_children; 45 46 u_int gic_bus; 47 bool gic_coherent; 48 u_int gic_nirs; 49 u_int gic_spi_count; 50 u_int gic_nchildren; 51 /* Number of LPIs, including IPIs */ 52 u_int gic_nlpis; 53 }; 54 55 struct gicv5_devinfo { 56 struct resource_list di_rl; 57 struct gicv5_irs *di_irs; 58 }; 59 60 #define GICV5_IVAR_LPI_START 5000 61 62 __BUS_ACCESSOR(gicv5, lpi_start, GICV5, LPI_START, u_int); 63 64 void gicv5_attach(device_t); 65 bool gicv5_add_child(device_t, struct gicv5_devinfo *); 66 int gicv5_intr(void *); 67 68 void gicv5_irs_init(device_t, u_int, cpuset_t *); 69 void gicv5_irs_extend_ist(device_t, device_t, u_int); 70 71 #endif /* _ARM64_GICV5VAR_H_ */ 72