1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dm_services.h"
6 #include "dc.h"
7
8 #include "dcn32/dcn32_init.h"
9 #include "dcn401/dcn401_init.h"
10
11 #include "resource.h"
12 #include "include/irq_service_interface.h"
13 #include "dcn401_resource.h"
14
15 #include "dcn20/dcn20_resource.h"
16 #include "dcn30/dcn30_resource.h"
17 #include "dcn32/dcn32_resource.h"
18 #include "dcn321/dcn321_resource.h"
19
20 #include "dcn10/dcn10_ipp.h"
21 #include "dcn401/dcn401_hubbub.h"
22 #include "dcn401/dcn401_mpc.h"
23 #include "dcn401/dcn401_hubp.h"
24 #include "irq/dcn401/irq_service_dcn401.h"
25 #include "dcn401/dcn401_dpp.h"
26 #include "dcn401/dcn401_optc.h"
27 #include "dcn20/dcn20_hwseq.h"
28 #include "dcn30/dcn30_hwseq.h"
29 #include "dce110/dce110_hwseq.h"
30 #include "dcn20/dcn20_opp.h"
31 #include "dcn401/dcn401_dsc.h"
32 #include "dcn30/dcn30_vpg.h"
33 #include "dcn31/dcn31_vpg.h"
34 #include "dcn30/dcn30_afmt.h"
35 #include "dcn30/dcn30_dio_stream_encoder.h"
36 #include "dcn401/dcn401_dio_stream_encoder.h"
37 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
38 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
39 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
40 #include "dcn31/dcn31_apg.h"
41 #include "dcn31/dcn31_dio_link_encoder.h"
42 #include "dcn401/dcn401_dio_link_encoder.h"
43 #include "dcn10/dcn10_link_encoder.h"
44 #include "dcn321/dcn321_dio_link_encoder.h"
45 #include "dce/dce_clock_source.h"
46 #include "dce/dce_audio.h"
47 #include "dce/dce_hwseq.h"
48 #include "clk_mgr.h"
49 #include "virtual/virtual_stream_encoder.h"
50 #include "dml/display_mode_vba.h"
51 #include "dcn401/dcn401_dccg.h"
52 #include "dcn10/dcn10_resource.h"
53 #include "link.h"
54 #include "link_enc_cfg.h"
55 #include "dcn31/dcn31_panel_cntl.h"
56
57 #include "dcn30/dcn30_dwb.h"
58 #include "dcn32/dcn32_mmhubbub.h"
59
60 #include "dcn/dcn_4_1_0_offset.h"
61 #include "dcn/dcn_4_1_0_sh_mask.h"
62 #include "nbif/nbif_6_3_1_offset.h"
63
64 #include "reg_helper.h"
65 #include "dce/dmub_abm.h"
66 #include "dce/dmub_psr.h"
67 #include "dce/dce_aux.h"
68 #include "dce/dce_i2c.h"
69
70 #include "dml/dcn30/display_mode_vba_30.h"
71 #include "vm_helper.h"
72 #include "dcn20/dcn20_vmid.h"
73
74 #include "dc_state_priv.h"
75
76 #include "dml2/dml2_wrapper.h"
77
78 #define DC_LOGGER_INIT(logger)
79
80 enum dcn401_clk_src_array_id {
81 DCN401_CLK_SRC_PLL0,
82 DCN401_CLK_SRC_PLL1,
83 DCN401_CLK_SRC_PLL2,
84 DCN401_CLK_SRC_PLL3,
85 //DCN401_CLK_SRC_PLL4,
86 DCN401_CLK_SRC_TOTAL
87 };
88
89 /* begin *********************
90 * macros to expend register list macro defined in HW object header file
91 */
92
93 /* DCN */
94 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
95
96 #define BASE(seg) BASE_INNER(seg)
97
98 #define SR(reg_name)\
99 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
100 reg ## reg_name
101 #define SR_ARR(reg_name, id)\
102 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
103 reg ## reg_name
104 #define SR_ARR_INIT(reg_name, id, value)\
105 REG_STRUCT[id].reg_name = value
106
107 #define SRI(reg_name, block, id)\
108 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
109 reg ## block ## id ## _ ## reg_name
110
111 #define SRI_ARR(reg_name, block, id)\
112 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
113 reg ## block ## id ## _ ## reg_name
114
115 /*
116 * Used when a reg_name would otherwise begin with an integer
117 */
118 #define SRI_ARR_US(reg_name, block, id)\
119 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \
120 reg ## block ## id ## reg_name
121 #define SR_ARR_I2C(reg_name, id) \
122 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
123
124 #define SRI_ARR_I2C(reg_name, block, id)\
125 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
126 reg ## block ## id ## _ ## reg_name
127
128 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
129 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 reg ## block ## id ## _ ## reg_name
131
132 #define SRI2(reg_name, block, id)\
133 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
134 reg ## reg_name
135 #define SRI2_ARR(reg_name, block, id)\
136 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
137 reg ## reg_name
138
139 #define SRIR(var_name, reg_name, block, id)\
140 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
141 reg ## block ## id ## _ ## reg_name
142
143 #define SRII(reg_name, block, id)\
144 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
145 reg ## block ## id ## _ ## reg_name
146
147 #define SRII_ARR_2(reg_name, block, id, inst)\
148 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
149 reg ## block ## id ## _ ## reg_name
150
151 #define SRII_MPC_RMU(reg_name, block, id)\
152 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
153 reg ## block ## id ## _ ## reg_name
154
155 #define SRII_DWB(reg_name, temp_name, block, id)\
156 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
157 reg ## block ## id ## _ ## temp_name
158
159 #define DCCG_SRII(reg_name, block, id)\
160 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
161 reg ## block ## id ## _ ## reg_name
162
163 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
164 .field_name = reg_name ## __ ## field_name ## post_fix
165
166 #define VUPDATE_SRII(reg_name, block, id)\
167 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
168 reg ## reg_name ## _ ## block ## id
169
170 /* NBIO */
171 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
172
173 #define NBIO_BASE(seg) \
174 NBIO_BASE_INNER(seg)
175
176 #define NBIO_SR(reg_name)\
177 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
178 regBIF_BX0_ ## reg_name
179 #define NBIO_SR_ARR(reg_name, id)\
180 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
181 regBIF_BX0_ ## reg_name
182
183 #define CTX ctx
184 #define REG(reg_name) \
185 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
186
187 static struct bios_registers bios_regs;
188
189 #define bios_regs_init() \
190 NBIO_SR(BIOS_SCRATCH_3),\
191 NBIO_SR(BIOS_SCRATCH_6)
192
193 #define clk_src_regs_init(index, pllid)\
194 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
195
196 static struct dce110_clk_src_regs clk_src_regs[5];
197
198 static const struct dce110_clk_src_shift cs_shift = {
199 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
200 };
201
202 static const struct dce110_clk_src_mask cs_mask = {
203 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
204 };
205
206 #define abm_regs_init(id)\
207 ABM_DCN401_REG_LIST_RI(id)
208
209 static struct dce_abm_registers abm_regs[4];
210
211 static const struct dce_abm_shift abm_shift = {
212 ABM_MASK_SH_LIST_DCN401(__SHIFT)
213 };
214
215 static const struct dce_abm_mask abm_mask = {
216 ABM_MASK_SH_LIST_DCN401(_MASK)
217 };
218
219 #define audio_regs_init(id)\
220 AUD_COMMON_REG_LIST_RI(id)
221
222 static struct dce_audio_registers audio_regs[5];
223
224 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
225 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
226 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
227 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
228
229 static const struct dce_audio_shift audio_shift = {
230 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
231 };
232
233 static const struct dce_audio_mask audio_mask = {
234 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
235 };
236
237 #define vpg_regs_init(id)\
238 VPG_DCN401_REG_LIST_RI(id)
239
240 static struct dcn31_vpg_registers vpg_regs[9];
241
242 static const struct dcn31_vpg_shift vpg_shift = {
243 DCN31_VPG_MASK_SH_LIST(__SHIFT)
244 };
245
246 static const struct dcn31_vpg_mask vpg_mask = {
247 DCN31_VPG_MASK_SH_LIST(_MASK)
248 };
249
250 #define afmt_regs_init(id)\
251 AFMT_DCN3_REG_LIST_RI(id)
252
253 static struct dcn30_afmt_registers afmt_regs[5];
254
255 static const struct dcn30_afmt_shift afmt_shift = {
256 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
257 };
258
259 static const struct dcn30_afmt_mask afmt_mask = {
260 DCN3_AFMT_MASK_SH_LIST(_MASK)
261 };
262
263 #define apg_regs_init(id)\
264 APG_DCN31_REG_LIST_RI(id)
265
266 static struct dcn31_apg_registers apg_regs[4];
267
268 static const struct dcn31_apg_shift apg_shift = {
269 DCN31_APG_MASK_SH_LIST(__SHIFT)
270 };
271
272 static const struct dcn31_apg_mask apg_mask = {
273 DCN31_APG_MASK_SH_LIST(_MASK)
274 };
275
276 #define stream_enc_regs_init(id)\
277 SE_DCN4_01_REG_LIST_RI(id)
278
279 static struct dcn10_stream_enc_registers stream_enc_regs[4];
280
281 static const struct dcn10_stream_encoder_shift se_shift = {
282 SE_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
283 };
284
285 static const struct dcn10_stream_encoder_mask se_mask = {
286 SE_COMMON_MASK_SH_LIST_DCN401(_MASK)
287 };
288
289 #define aux_regs_init(id)\
290 DCN2_AUX_REG_LIST_RI(id)
291
292 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
293
294 #define hpd_regs_init(id)\
295 HPD_REG_LIST_RI(id)
296
297 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
298
299 #define link_regs_init(id, phyid)\
300 LE_DCN401_REG_LIST_RI(id)
301
302 static struct dcn10_link_enc_registers link_enc_regs[4];
303
304
305 static const struct dcn10_link_enc_shift le_shift = {
306 LINK_ENCODER_MASK_SH_LIST_DCN401(__SHIFT)
307 };
308
309
310 static const struct dcn10_link_enc_mask le_mask = {
311 LINK_ENCODER_MASK_SH_LIST_DCN401(_MASK)
312 };
313
314
315 #define hpo_dp_stream_encoder_reg_init(id)\
316 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
317
318 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
319
320 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
321 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
322 };
323
324 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
325 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
326 };
327
328
329 #define hpo_dp_link_encoder_reg_init(id)\
330 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
331 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
332 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
333 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
334 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
335
336 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4];
337
338 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
339 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
340 };
341
342 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
343 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
344 };
345
346 #define dpp_regs_init(id)\
347 DPP_REG_LIST_DCN401_COMMON_RI(id)
348
349 static struct dcn401_dpp_registers dpp_regs[4];
350
351 static const struct dcn401_dpp_shift tf_shift = {
352 DPP_REG_LIST_SH_MASK_DCN401_COMMON(__SHIFT)
353 };
354
355 static const struct dcn401_dpp_mask tf_mask = {
356 DPP_REG_LIST_SH_MASK_DCN401_COMMON(_MASK)
357 };
358
359 #define opp_regs_init(id)\
360 OPP_REG_LIST_DCN401_RI(id)
361
362 static struct dcn20_opp_registers opp_regs[4];
363
364 static const struct dcn20_opp_shift opp_shift = {
365 OPP_MASK_SH_LIST_DCN20(__SHIFT)
366 };
367
368 static const struct dcn20_opp_mask opp_mask = {
369 OPP_MASK_SH_LIST_DCN20(_MASK)
370 };
371
372 #define aux_engine_regs_init(id) \
373 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
374 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
375 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
376 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)
377
378 static struct dce110_aux_registers aux_engine_regs[5];
379
380 static const struct dce110_aux_registers_shift aux_shift = {
381 DCN_AUX_MASK_SH_LIST(__SHIFT)
382 };
383
384 static const struct dce110_aux_registers_mask aux_mask = {
385 DCN_AUX_MASK_SH_LIST(_MASK)
386 };
387
388 #define dwbc_regs_dcn401_init(id)\
389 DWBC_COMMON_REG_LIST_DCN30_RI(id)
390
391 static struct dcn30_dwbc_registers dwbc401_regs[1];
392
393 static const struct dcn30_dwbc_shift dwbc401_shift = {
394 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
395 };
396
397 static const struct dcn30_dwbc_mask dwbc401_mask = {
398 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
399 };
400
401
402 #define mcif_wb_regs_dcn3_init(id)\
403 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
404
405 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
406
407 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
408 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
409 };
410
411 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
412 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
413 };
414
415 #define dsc_regs_init(id)\
416 DSC_REG_LIST_DCN401_RI(id)
417
418 static struct dcn401_dsc_registers dsc_regs[4];
419
420 static const struct dcn401_dsc_shift dsc_shift = {
421 DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)
422 };
423
424 static const struct dcn401_dsc_mask dsc_mask = {
425 DSC_REG_LIST_SH_MASK_DCN401(_MASK)
426 };
427
428 static struct dcn401_mpc_registers mpc_regs;
429
430 #define dcn_mpc_regs_init()\
431 MPC_REG_LIST_DCN4_01_RI(0),\
432 MPC_REG_LIST_DCN4_01_RI(1),\
433 MPC_REG_LIST_DCN4_01_RI(2),\
434 MPC_REG_LIST_DCN4_01_RI(3),\
435 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
436 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
437 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
438 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
439 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
440
441 static const struct dcn401_mpc_shift mpc_shift = {
442 MPC_COMMON_MASK_SH_LIST_DCN4_01(__SHIFT)
443 };
444
445 static const struct dcn401_mpc_mask mpc_mask = {
446 MPC_COMMON_MASK_SH_LIST_DCN4_01(_MASK)
447 };
448
449 #define optc_regs_init(id)\
450 OPTC_COMMON_REG_LIST_DCN401_RI(id)
451
452 static struct dcn_optc_registers optc_regs[4];
453
454 static const struct dcn_optc_shift optc_shift = {
455 OPTC_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
456 };
457
458 static const struct dcn_optc_mask optc_mask = {
459 OPTC_COMMON_MASK_SH_LIST_DCN401(_MASK)
460 };
461
462 #define hubp_regs_init(id)\
463 HUBP_REG_LIST_DCN401_RI(id)
464
465 static struct dcn_hubp2_registers hubp_regs[4];
466
467 static const struct dcn_hubp2_shift hubp_shift = {
468 HUBP_MASK_SH_LIST_DCN401(__SHIFT)
469 };
470
471 static const struct dcn_hubp2_mask hubp_mask = {
472 HUBP_MASK_SH_LIST_DCN401(_MASK)
473 };
474
475 static struct dcn_hubbub_registers hubbub_reg;
476 #define hubbub_reg_init()\
477 HUBBUB_REG_LIST_DCN4_01_RI(0)
478
479 static const struct dcn_hubbub_shift hubbub_shift = {
480 HUBBUB_MASK_SH_LIST_DCN4_01(__SHIFT)
481 };
482
483 static const struct dcn_hubbub_mask hubbub_mask = {
484 HUBBUB_MASK_SH_LIST_DCN4_01(_MASK)
485 };
486
487 static struct dccg_registers dccg_regs;
488
489 #define dccg_regs_init()\
490 DCCG_REG_LIST_DCN401_RI()
491
492 static const struct dccg_shift dccg_shift = {
493 DCCG_MASK_SH_LIST_DCN401(__SHIFT)
494 };
495
496 static const struct dccg_mask dccg_mask = {
497 DCCG_MASK_SH_LIST_DCN401(_MASK)
498 };
499
500 #define SRII2(reg_name_pre, reg_name_post, id)\
501 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
502 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
503 reg ## reg_name_pre ## id ## _ ## reg_name_post
504
505
506 #define HWSEQ_DCN401_REG_LIST()\
507 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
508 SR(DIO_MEM_PWR_CTRL), \
509 SR(ODM_MEM_PWR_CTRL3), \
510 SR(MMHUBBUB_MEM_PWR_CNTL), \
511 SR(DCCG_GATE_DISABLE_CNTL), \
512 SR(DCCG_GATE_DISABLE_CNTL2), \
513 SR(DCFCLK_CNTL),\
514 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
515 SRII(PIXEL_RATE_CNTL, OTG, 0), \
516 SRII(PIXEL_RATE_CNTL, OTG, 1),\
517 SRII(PIXEL_RATE_CNTL, OTG, 2),\
518 SRII(PIXEL_RATE_CNTL, OTG, 3),\
519 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
520 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
521 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
522 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
523 SR(MICROSECOND_TIME_BASE_DIV), \
524 SR(MILLISECOND_TIME_BASE_DIV), \
525 SR(DISPCLK_FREQ_CHANGE_CNTL), \
526 SR(RBBMIF_TIMEOUT_DIS), \
527 SR(RBBMIF_TIMEOUT_DIS_2), \
528 SR(DCHUBBUB_CRC_CTRL), \
529 SR(DPP_TOP0_DPP_CRC_CTRL), \
530 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
531 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
532 SR(MPC_CRC_CTRL), \
533 SR(MPC_CRC_RESULT_GB), \
534 SR(MPC_CRC_RESULT_C), \
535 SR(MPC_CRC_RESULT_AR), \
536 SR(DOMAIN0_PG_CONFIG), \
537 SR(DOMAIN1_PG_CONFIG), \
538 SR(DOMAIN2_PG_CONFIG), \
539 SR(DOMAIN3_PG_CONFIG), \
540 SR(DOMAIN16_PG_CONFIG), \
541 SR(DOMAIN17_PG_CONFIG), \
542 SR(DOMAIN18_PG_CONFIG), \
543 SR(DOMAIN19_PG_CONFIG), \
544 SR(DOMAIN22_PG_CONFIG), \
545 SR(DOMAIN23_PG_CONFIG), \
546 SR(DOMAIN24_PG_CONFIG), \
547 SR(DOMAIN25_PG_CONFIG), \
548 SR(DOMAIN0_PG_STATUS), \
549 SR(DOMAIN1_PG_STATUS), \
550 SR(DOMAIN2_PG_STATUS), \
551 SR(DOMAIN3_PG_STATUS), \
552 SR(DOMAIN16_PG_STATUS), \
553 SR(DOMAIN17_PG_STATUS), \
554 SR(DOMAIN18_PG_STATUS), \
555 SR(DOMAIN19_PG_STATUS), \
556 SR(DOMAIN22_PG_STATUS), \
557 SR(DOMAIN23_PG_STATUS), \
558 SR(DOMAIN24_PG_STATUS), \
559 SR(DOMAIN25_PG_STATUS), \
560 SR(DC_IP_REQUEST_CNTL), \
561 SR(AZALIA_AUDIO_DTO), \
562 SR(HPO_TOP_HW_CONTROL),\
563 SR(AZALIA_CONTROLLER_CLOCK_GATING)
564
565 static struct dce_hwseq_registers hwseq_reg;
566
567 #define hwseq_reg_init()\
568 HWSEQ_DCN401_REG_LIST()
569
570 #define HWSEQ_DCN401_MASK_SH_LIST(mask_sh)\
571 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
572 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
573 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
574 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
575 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
576 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
577 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
578 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
579 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
580 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
581 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
582 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
583 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
584 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
585 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
586 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
587 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
588 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
589 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
590 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
591 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
592 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
593 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
594 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
595 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
596 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
597 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
598 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
599 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
600 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
601 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
602 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
603 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
604 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
605 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
606 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
607 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
608 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
609 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
610 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
611 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
612 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \
613 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
614 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)
615
616 static const struct dce_hwseq_shift hwseq_shift = {
617 HWSEQ_DCN401_MASK_SH_LIST(__SHIFT)
618 };
619
620 static const struct dce_hwseq_mask hwseq_mask = {
621 HWSEQ_DCN401_MASK_SH_LIST(_MASK)
622 };
623
624 #define vmid_regs_init(id)\
625 DCN20_VMID_REG_LIST_RI(id)
626
627 static struct dcn_vmid_registers vmid_regs[16];
628
629 static const struct dcn20_vmid_shift vmid_shifts = {
630 DCN20_VMID_MASK_SH_LIST(__SHIFT)
631 };
632
633 static const struct dcn20_vmid_mask vmid_masks = {
634 DCN20_VMID_MASK_SH_LIST(_MASK)
635 };
636
637 static const struct resource_caps res_cap_dcn4_01 = {
638 .num_timing_generator = 4,
639 .num_opp = 4,
640 .num_video_plane = 4,
641 .num_audio = 4,
642 .num_stream_encoder = 4,
643 .num_hpo_dp_stream_encoder = 4,
644 .num_hpo_dp_link_encoder = 4,
645 .num_pll = 4,
646 .num_dwb = 1,
647 .num_ddc = 4,
648 .num_vmid = 16,
649 .num_mpc_3dlut = 4,
650 .num_dsc = 4,
651 };
652
653 static const struct dc_plane_cap plane_cap = {
654 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
655 .per_pixel_alpha = true,
656
657 .pixel_format_support = {
658 .argb8888 = true,
659 .nv12 = true,
660 .fp16 = true,
661 .p010 = true,
662 .ayuv = false,
663 },
664
665 .max_upscale_factor = {
666 .argb8888 = 16000,
667 .nv12 = 16000,
668 .fp16 = 16000
669 },
670
671 // 6:1 downscaling ratio: 1000/6 = 166.666
672 .max_downscale_factor = {
673 .argb8888 = 167,
674 .nv12 = 167,
675 .fp16 = 167
676 },
677 64,
678 64
679 };
680
681 static const struct dc_debug_options debug_defaults_drv = {
682 .disable_dmcu = true,
683 .force_abm_enable = false,
684 .clock_trace = true,
685 .disable_pplib_clock_request = false,
686 .pipe_split_policy = MPC_SPLIT_AVOID,
687 .force_single_disp_pipe_split = false,
688 .disable_dcc = DCC_ENABLE,
689 .vsr_support = true,
690 .performance_trace = false,
691 .max_downscale_src_width = 7680,/*upto 8K*/
692 .disable_pplib_wm_range = false,
693 .scl_reset_length10 = true,
694 .sanity_checks = false,
695 .underflow_assert_delay_us = 0xFFFFFFFF,
696 .dwb_fi_phase = -1, // -1 = disable,
697 .dmub_command_table = true,
698 .enable_mem_low_power = {
699 .bits = {
700 .vga = false,
701 .i2c = false,
702 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
703 .dscl = false,
704 .cm = false,
705 .mpc = false,
706 .optc = true,
707 }
708 },
709 .use_max_lb = true,
710 .force_disable_subvp = false,
711 .exit_idle_opt_for_cursor_updates = true,
712 .using_dml2 = true,
713 .using_dml21 = true,
714 .enable_single_display_2to1_odm_policy = true,
715
716 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
717 .enable_double_buffered_dsc_pg_support = true,
718 .enable_dp_dig_pixel_rate_div_policy = 1,
719 .allow_sw_cursor_fallback = false,
720 .alloc_extra_way_for_cursor = true,
721 .min_prefetch_in_strobe_ns = 60000, // 60us
722 .disable_unbounded_requesting = false,
723 .enable_legacy_fast_update = false,
724 .dcc_meta_propagation_delay_us = 10,
725 .fams_version = {
726 .minor = 1,
727 .major = 2,
728 }, //v2.1
729 .fams2_config = {
730 .bits = {
731 .enable = true,
732 .enable_offload_flip = true,
733 .enable_stall_recovery = true,
734 }
735 },
736 .force_cositing = CHROMA_COSITING_NONE + 1,
737 };
738
dcn401_aux_engine_create(struct dc_context * ctx,uint32_t inst)739 static struct dce_aux *dcn401_aux_engine_create(
740 struct dc_context *ctx,
741 uint32_t inst)
742 {
743 struct aux_engine_dce110 *aux_engine =
744 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
745
746 if (!aux_engine)
747 return NULL;
748
749 #undef REG_STRUCT
750 #define REG_STRUCT aux_engine_regs
751 aux_engine_regs_init(0),
752 aux_engine_regs_init(1),
753 aux_engine_regs_init(2),
754 aux_engine_regs_init(3);
755
756 dce110_aux_engine_construct(aux_engine, ctx, inst,
757 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
758 &aux_engine_regs[inst],
759 &aux_mask,
760 &aux_shift,
761 ctx->dc->caps.extended_aux_timeout_support);
762
763 return &aux_engine->base;
764 }
765 #define i2c_inst_regs_init(id)\
766 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
767
768 static struct dce_i2c_registers i2c_hw_regs[5];
769
770 static const struct dce_i2c_shift i2c_shifts = {
771 I2C_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
772 };
773
774 static const struct dce_i2c_mask i2c_masks = {
775 I2C_COMMON_MASK_SH_LIST_DCN401(_MASK)
776 };
777
dcn401_i2c_hw_create(struct dc_context * ctx,uint32_t inst)778 static struct dce_i2c_hw *dcn401_i2c_hw_create(
779 struct dc_context *ctx,
780 uint32_t inst)
781 {
782 struct dce_i2c_hw *dce_i2c_hw =
783 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
784
785 if (!dce_i2c_hw)
786 return NULL;
787
788 #undef REG_STRUCT
789 #define REG_STRUCT i2c_hw_regs
790 i2c_inst_regs_init(1),
791 i2c_inst_regs_init(2),
792 i2c_inst_regs_init(3),
793 i2c_inst_regs_init(4);
794
795 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
796 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
797
798 return dce_i2c_hw;
799 }
800
dcn401_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)801 static struct clock_source *dcn401_clock_source_create(
802 struct dc_context *ctx,
803 struct dc_bios *bios,
804 enum clock_source_id id,
805 const struct dce110_clk_src_regs *regs,
806 bool dp_clk_src)
807 {
808 struct dce110_clk_src *clk_src =
809 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
810
811 if (!clk_src)
812 return NULL;
813
814 if (dcn401_clk_src_construct(clk_src, ctx, bios, id,
815 regs, &cs_shift, &cs_mask)) {
816 clk_src->base.dp_clk_src = dp_clk_src;
817 return &clk_src->base;
818 }
819
820 kfree(clk_src);
821 BREAK_TO_DEBUGGER();
822 return NULL;
823 }
824
dcn401_hubbub_create(struct dc_context * ctx)825 static struct hubbub *dcn401_hubbub_create(struct dc_context *ctx)
826 {
827 int i;
828
829 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
830 GFP_KERNEL);
831
832 if (!hubbub2)
833 return NULL;
834
835
836 #undef REG_STRUCT
837 #define REG_STRUCT hubbub_reg
838 hubbub_reg_init();
839
840 #undef REG_STRUCT
841 #define REG_STRUCT vmid_regs
842 vmid_regs_init(0),
843 vmid_regs_init(1),
844 vmid_regs_init(2),
845 vmid_regs_init(3),
846 vmid_regs_init(4),
847 vmid_regs_init(5),
848 vmid_regs_init(6),
849 vmid_regs_init(7),
850 vmid_regs_init(8),
851 vmid_regs_init(9),
852 vmid_regs_init(10),
853 vmid_regs_init(11),
854 vmid_regs_init(12),
855 vmid_regs_init(13),
856 vmid_regs_init(14),
857 vmid_regs_init(15);
858
859 hubbub401_construct(hubbub2, ctx,
860 &hubbub_reg,
861 &hubbub_shift,
862 &hubbub_mask,
863 DCN4_01_DEFAULT_DET_SIZE, //nominal (default) detile buffer size in kbytes,
864 8, //dml2 ip_params_st.pixel_chunk_size_kbytes
865 DCN4_01_CRB_SIZE_KB); //dml2 ip_params_st.config_return_buffer_size_in_kbytes
866
867 for (i = 0; i < res_cap_dcn4_01.num_vmid; i++) {
868 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
869
870 vmid->ctx = ctx;
871
872 vmid->regs = &vmid_regs[i];
873 vmid->shifts = &vmid_shifts;
874 vmid->masks = &vmid_masks;
875 }
876
877 return &hubbub2->base;
878 }
879
dcn401_hubp_create(struct dc_context * ctx,uint32_t inst)880 static struct hubp *dcn401_hubp_create(
881 struct dc_context *ctx,
882 uint32_t inst)
883 {
884 struct dcn20_hubp *hubp2 =
885 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
886
887 if (!hubp2)
888 return NULL;
889
890 #undef REG_STRUCT
891 #define REG_STRUCT hubp_regs
892 hubp_regs_init(0),
893 hubp_regs_init(1),
894 hubp_regs_init(2),
895 hubp_regs_init(3);
896
897 if (hubp401_construct(hubp2, ctx, inst,
898 &hubp_regs[inst], &hubp_shift, &hubp_mask))
899 return &hubp2->base;
900
901 BREAK_TO_DEBUGGER();
902 kfree(hubp2);
903 return NULL;
904 }
905
dcn401_dpp_destroy(struct dpp ** dpp)906 static void dcn401_dpp_destroy(struct dpp **dpp)
907 {
908 kfree(TO_DCN401_DPP(*dpp));
909 *dpp = NULL;
910 }
911
dcn401_dpp_create(struct dc_context * ctx,uint32_t inst)912 static struct dpp *dcn401_dpp_create(
913 struct dc_context *ctx,
914 uint32_t inst)
915 {
916 struct dcn401_dpp *dpp401 =
917 kzalloc(sizeof(struct dcn401_dpp), GFP_KERNEL);
918
919 if (!dpp401)
920 return NULL;
921
922 #undef REG_STRUCT
923 #define REG_STRUCT dpp_regs
924 dpp_regs_init(0),
925 dpp_regs_init(1),
926 dpp_regs_init(2),
927 dpp_regs_init(3);
928
929 if (dpp401_construct(dpp401, ctx, inst,
930 &dpp_regs[inst], &tf_shift, &tf_mask))
931 return &dpp401->base;
932
933 BREAK_TO_DEBUGGER();
934 kfree(dpp401);
935 return NULL;
936 }
937
dcn401_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)938 static struct mpc *dcn401_mpc_create(
939 struct dc_context *ctx,
940 int num_mpcc,
941 int num_rmu)
942 {
943 struct dcn401_mpc *mpc401 = kzalloc(sizeof(struct dcn401_mpc),
944 GFP_KERNEL);
945
946 if (!mpc401)
947 return NULL;
948
949 #undef REG_STRUCT
950 #define REG_STRUCT mpc_regs
951 dcn_mpc_regs_init();
952
953 dcn401_mpc_construct(mpc401, ctx,
954 &mpc_regs,
955 &mpc_shift,
956 &mpc_mask,
957 num_mpcc,
958 num_rmu);
959
960 return &mpc401->base;
961 }
962
dcn401_opp_create(struct dc_context * ctx,uint32_t inst)963 static struct output_pixel_processor *dcn401_opp_create(
964 struct dc_context *ctx, uint32_t inst)
965 {
966 struct dcn20_opp *opp4 =
967 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
968
969 if (!opp4) {
970 BREAK_TO_DEBUGGER();
971 return NULL;
972 }
973
974 #undef REG_STRUCT
975 #define REG_STRUCT opp_regs
976 opp_regs_init(0),
977 opp_regs_init(1),
978 opp_regs_init(2),
979 opp_regs_init(3);
980
981 dcn20_opp_construct(opp4, ctx, inst,
982 &opp_regs[inst], &opp_shift, &opp_mask);
983 return &opp4->base;
984 }
985
986
dcn401_timing_generator_create(struct dc_context * ctx,uint32_t instance)987 static struct timing_generator *dcn401_timing_generator_create(
988 struct dc_context *ctx,
989 uint32_t instance)
990 {
991 struct optc *tgn10 =
992 kzalloc(sizeof(struct optc), GFP_KERNEL);
993
994 if (!tgn10)
995 return NULL;
996 #undef REG_STRUCT
997 #define REG_STRUCT optc_regs
998 optc_regs_init(0),
999 optc_regs_init(1),
1000 optc_regs_init(2),
1001 optc_regs_init(3);
1002
1003 tgn10->base.inst = instance;
1004 tgn10->base.ctx = ctx;
1005
1006 tgn10->tg_regs = &optc_regs[instance];
1007 tgn10->tg_shift = &optc_shift;
1008 tgn10->tg_mask = &optc_mask;
1009
1010 dcn401_timing_generator_init(tgn10);
1011
1012 return &tgn10->base;
1013 }
1014
1015 static const struct encoder_feature_support link_enc_feature = {
1016 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1017 .max_hdmi_pixel_clock = 600000,
1018 .hdmi_ycbcr420_supported = true,
1019 .dp_ycbcr420_supported = true,
1020 .fec_supported = true,
1021 .flags.bits.IS_HBR2_CAPABLE = true,
1022 .flags.bits.IS_HBR3_CAPABLE = true,
1023 .flags.bits.IS_TPS3_CAPABLE = true,
1024 .flags.bits.IS_TPS4_CAPABLE = true
1025 };
1026
dcn401_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1027 static struct link_encoder *dcn401_link_encoder_create(
1028 struct dc_context *ctx,
1029 const struct encoder_init_data *enc_init_data)
1030 {
1031 struct dcn20_link_encoder *enc20 =
1032 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1033
1034 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1035 return NULL;
1036
1037 #undef REG_STRUCT
1038 #define REG_STRUCT link_enc_aux_regs
1039 aux_regs_init(0),
1040 aux_regs_init(1),
1041 aux_regs_init(2),
1042 aux_regs_init(3);
1043
1044 #undef REG_STRUCT
1045 #define REG_STRUCT link_enc_hpd_regs
1046 hpd_regs_init(0),
1047 hpd_regs_init(1),
1048 hpd_regs_init(2),
1049 hpd_regs_init(3);
1050 #undef REG_STRUCT
1051 #define REG_STRUCT link_enc_regs
1052 link_regs_init(0, A),
1053 link_regs_init(1, B),
1054 link_regs_init(2, C),
1055 link_regs_init(3, D);
1056
1057 dcn401_link_encoder_construct(enc20,
1058 enc_init_data,
1059 &link_enc_feature,
1060 &link_enc_regs[enc_init_data->transmitter],
1061 &link_enc_aux_regs[enc_init_data->channel - 1],
1062 &link_enc_hpd_regs[enc_init_data->hpd_source],
1063 &le_shift,
1064 &le_mask);
1065 return &enc20->enc10.base;
1066 }
1067
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1068 static void read_dce_straps(
1069 struct dc_context *ctx,
1070 struct resource_straps *straps)
1071 {
1072 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1073 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1074
1075 }
1076
dcn401_create_audio(struct dc_context * ctx,unsigned int inst)1077 static struct audio *dcn401_create_audio(
1078 struct dc_context *ctx, unsigned int inst)
1079 {
1080
1081 #undef REG_STRUCT
1082 #define REG_STRUCT audio_regs
1083 audio_regs_init(0),
1084 audio_regs_init(1),
1085 audio_regs_init(2),
1086 audio_regs_init(3),
1087 audio_regs_init(4);
1088
1089 return dce_audio_create(ctx, inst,
1090 &audio_regs[inst], &audio_shift, &audio_mask);
1091 }
1092
dcn401_vpg_create(struct dc_context * ctx,uint32_t inst)1093 static struct vpg *dcn401_vpg_create(
1094 struct dc_context *ctx,
1095 uint32_t inst)
1096 {
1097 struct dcn31_vpg *vpg4 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1098
1099 if (!vpg4)
1100 return NULL;
1101
1102
1103 #undef REG_STRUCT
1104 #define REG_STRUCT vpg_regs
1105 vpg_regs_init(0),
1106 vpg_regs_init(1),
1107 vpg_regs_init(2),
1108 vpg_regs_init(3),
1109 vpg_regs_init(4),
1110 vpg_regs_init(5),
1111 vpg_regs_init(6),
1112 vpg_regs_init(7),
1113 vpg_regs_init(8);
1114
1115 vpg31_construct(vpg4, ctx, inst,
1116 &vpg_regs[inst],
1117 &vpg_shift,
1118 &vpg_mask);
1119
1120 return &vpg4->base;
1121 }
1122
dcn401_afmt_create(struct dc_context * ctx,uint32_t inst)1123 static struct afmt *dcn401_afmt_create(
1124 struct dc_context *ctx,
1125 uint32_t inst)
1126 {
1127 struct dcn30_afmt *afmt401 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1128
1129 if (!afmt401)
1130 return NULL;
1131
1132 #undef REG_STRUCT
1133 #define REG_STRUCT afmt_regs
1134 afmt_regs_init(0),
1135 afmt_regs_init(1),
1136 afmt_regs_init(2),
1137 afmt_regs_init(3),
1138 afmt_regs_init(4);
1139
1140 afmt3_construct(afmt401, ctx, inst,
1141 &afmt_regs[inst],
1142 &afmt_shift,
1143 &afmt_mask);
1144
1145 return &afmt401->base;
1146 }
1147
dcn401_apg_create(struct dc_context * ctx,uint32_t inst)1148 static struct apg *dcn401_apg_create(
1149 struct dc_context *ctx,
1150 uint32_t inst)
1151 {
1152 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1153
1154 if (!apg31)
1155 return NULL;
1156
1157 #undef REG_STRUCT
1158 #define REG_STRUCT apg_regs
1159 apg_regs_init(0),
1160 apg_regs_init(1),
1161 apg_regs_init(2),
1162 apg_regs_init(3);
1163
1164 apg31_construct(apg31, ctx, inst,
1165 &apg_regs[inst],
1166 &apg_shift,
1167 &apg_mask);
1168
1169 return &apg31->base;
1170 }
1171
dcn401_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1172 static struct stream_encoder *dcn401_stream_encoder_create(
1173 enum engine_id eng_id,
1174 struct dc_context *ctx)
1175 {
1176 struct dcn10_stream_encoder *enc1;
1177 struct vpg *vpg;
1178 struct afmt *afmt;
1179 int vpg_inst;
1180 int afmt_inst;
1181
1182 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1183 if (eng_id <= ENGINE_ID_DIGF) {
1184 vpg_inst = eng_id;
1185 afmt_inst = eng_id;
1186 } else
1187 return NULL;
1188
1189 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1190 vpg = dcn401_vpg_create(ctx, vpg_inst);
1191 afmt = dcn401_afmt_create(ctx, afmt_inst);
1192
1193 if (!enc1 || !vpg || !afmt || eng_id >= ARRAY_SIZE(stream_enc_regs)) {
1194 kfree(enc1);
1195 kfree(vpg);
1196 kfree(afmt);
1197 return NULL;
1198 }
1199 #undef REG_STRUCT
1200 #define REG_STRUCT stream_enc_regs
1201 stream_enc_regs_init(0),
1202 stream_enc_regs_init(1),
1203 stream_enc_regs_init(2),
1204 stream_enc_regs_init(3);
1205 //stream_enc_regs_init(4);
1206
1207 dcn401_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1208 eng_id, vpg, afmt,
1209 &stream_enc_regs[eng_id],
1210 &se_shift, &se_mask);
1211 return &enc1->base;
1212 }
1213
dcn401_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1214 static struct hpo_dp_stream_encoder *dcn401_hpo_dp_stream_encoder_create(
1215 enum engine_id eng_id,
1216 struct dc_context *ctx)
1217 {
1218 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1219 struct vpg *vpg;
1220 struct apg *apg;
1221 uint32_t hpo_dp_inst;
1222 uint32_t vpg_inst;
1223 uint32_t apg_inst;
1224
1225 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1226 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1227
1228 /* Mapping of VPG register blocks to HPO DP block instance:
1229 * VPG[6] -> HPO_DP[0]
1230 * VPG[7] -> HPO_DP[1]
1231 * VPG[8] -> HPO_DP[2]
1232 * VPG[9] -> HPO_DP[3]
1233 */
1234 vpg_inst = hpo_dp_inst + 5;
1235
1236 /* Mapping of APG register blocks to HPO DP block instance:
1237 * APG[0] -> HPO_DP[0]
1238 * APG[1] -> HPO_DP[1]
1239 * APG[2] -> HPO_DP[2]
1240 * APG[3] -> HPO_DP[3]
1241 */
1242 apg_inst = hpo_dp_inst;
1243
1244 /* allocate HPO stream encoder and create VPG sub-block */
1245 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1246 vpg = dcn401_vpg_create(ctx, vpg_inst);
1247 apg = dcn401_apg_create(ctx, apg_inst);
1248
1249 if (!hpo_dp_enc31 || !vpg || !apg) {
1250 kfree(hpo_dp_enc31);
1251 kfree(vpg);
1252 kfree(apg);
1253 return NULL;
1254 }
1255
1256 #undef REG_STRUCT
1257 #define REG_STRUCT hpo_dp_stream_enc_regs
1258 hpo_dp_stream_encoder_reg_init(0),
1259 hpo_dp_stream_encoder_reg_init(1),
1260 hpo_dp_stream_encoder_reg_init(2),
1261 hpo_dp_stream_encoder_reg_init(3);
1262
1263 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1264 hpo_dp_inst, eng_id, vpg, apg,
1265 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1266 &hpo_dp_se_shift, &hpo_dp_se_mask);
1267
1268 return &hpo_dp_enc31->base;
1269 }
1270
dcn401_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1271 static struct hpo_dp_link_encoder *dcn401_hpo_dp_link_encoder_create(
1272 uint8_t inst,
1273 struct dc_context *ctx)
1274 {
1275 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1276
1277 /* allocate HPO link encoder */
1278 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1279 if (!hpo_dp_enc31)
1280 return NULL; /* out of memory */
1281
1282 #undef REG_STRUCT
1283 #define REG_STRUCT hpo_dp_link_enc_regs
1284 hpo_dp_link_encoder_reg_init(0),
1285 hpo_dp_link_encoder_reg_init(1),
1286 hpo_dp_link_encoder_reg_init(2),
1287 hpo_dp_link_encoder_reg_init(3);
1288
1289 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1290 &hpo_dp_link_enc_regs[inst],
1291 &hpo_dp_le_shift, &hpo_dp_le_mask);
1292
1293 return &hpo_dp_enc31->base;
1294 }
1295
dcn401_calc_num_avail_chans_for_mall(struct dc * dc,unsigned int num_chans)1296 static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans)
1297 {
1298 unsigned int num_available_chans = 1;
1299
1300 /* channels for MALL must be a power of 2 */
1301 while (num_chans > 1) {
1302 num_available_chans = (num_available_chans << 1);
1303 num_chans = (num_chans >> 1);
1304 }
1305
1306 /* cannot be odd */
1307 num_available_chans &= ~1;
1308
1309 /* clamp to max available channels for MALL per ASIC */
1310 if (ASICREV_IS_GC_12_0_0_A0(dc->ctx->asic_id.hw_internal_rev)) {
1311 num_available_chans = num_available_chans > 16 ? 16 : num_available_chans;
1312 } else if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) {
1313 num_available_chans = num_available_chans > 8 ? 8 : num_available_chans;
1314 }
1315
1316 return num_available_chans;
1317 }
1318
dcn401_hwseq_create(struct dc_context * ctx)1319 static struct dce_hwseq *dcn401_hwseq_create(
1320 struct dc_context *ctx)
1321 {
1322 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1323
1324 #undef REG_STRUCT
1325 #define REG_STRUCT hwseq_reg
1326 hwseq_reg_init();
1327
1328 if (hws) {
1329 hws->ctx = ctx;
1330 hws->regs = &hwseq_reg;
1331 hws->shifts = &hwseq_shift;
1332 hws->masks = &hwseq_mask;
1333 }
1334
1335 return hws;
1336 }
1337 static const struct resource_create_funcs res_create_funcs = {
1338 .read_dce_straps = read_dce_straps,
1339 .create_audio = dcn401_create_audio,
1340 .create_stream_encoder = dcn401_stream_encoder_create,
1341 .create_hpo_dp_stream_encoder = dcn401_hpo_dp_stream_encoder_create,
1342 .create_hpo_dp_link_encoder = dcn401_hpo_dp_link_encoder_create,
1343 .create_hwseq = dcn401_hwseq_create,
1344 };
1345
dcn401_dsc_destroy(struct display_stream_compressor ** dsc)1346 static void dcn401_dsc_destroy(struct display_stream_compressor **dsc)
1347 {
1348 kfree(container_of(*dsc, struct dcn401_dsc, base));
1349 *dsc = NULL;
1350 }
1351
dcn401_resource_destruct(struct dcn401_resource_pool * pool)1352 static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
1353 {
1354 unsigned int i;
1355
1356 for (i = 0; i < pool->base.stream_enc_count; i++) {
1357 if (pool->base.stream_enc[i] != NULL) {
1358 if (pool->base.stream_enc[i]->vpg != NULL) {
1359 kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1360 pool->base.stream_enc[i]->vpg = NULL;
1361 }
1362 if (pool->base.stream_enc[i]->afmt != NULL) {
1363 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1364 pool->base.stream_enc[i]->afmt = NULL;
1365 }
1366 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1367 pool->base.stream_enc[i] = NULL;
1368 }
1369 }
1370
1371 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1372 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1373 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1374 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1375 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1376 }
1377 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1378 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1379 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1380 }
1381 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1382 pool->base.hpo_dp_stream_enc[i] = NULL;
1383 }
1384 }
1385
1386 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1387 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1388 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1389 pool->base.hpo_dp_link_enc[i] = NULL;
1390 }
1391 }
1392
1393 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1394 if (pool->base.dscs[i] != NULL)
1395 dcn401_dsc_destroy(&pool->base.dscs[i]);
1396 }
1397
1398 if (pool->base.mpc != NULL) {
1399 kfree(TO_DCN20_MPC(pool->base.mpc));
1400 pool->base.mpc = NULL;
1401 }
1402 if (pool->base.hubbub != NULL) {
1403 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1404 pool->base.hubbub = NULL;
1405 }
1406 for (i = 0; i < pool->base.pipe_count; i++) {
1407 if (pool->base.dpps[i] != NULL)
1408 dcn401_dpp_destroy(&pool->base.dpps[i]);
1409
1410 if (pool->base.ipps[i] != NULL)
1411 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1412
1413 if (pool->base.hubps[i] != NULL) {
1414 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1415 pool->base.hubps[i] = NULL;
1416 }
1417
1418 if (pool->base.irqs != NULL) {
1419 dal_irq_service_destroy(&pool->base.irqs);
1420 }
1421 }
1422
1423 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1424 if (pool->base.engines[i] != NULL)
1425 dce110_engine_destroy(&pool->base.engines[i]);
1426 if (pool->base.hw_i2cs[i] != NULL) {
1427 kfree(pool->base.hw_i2cs[i]);
1428 pool->base.hw_i2cs[i] = NULL;
1429 }
1430 if (pool->base.sw_i2cs[i] != NULL) {
1431 kfree(pool->base.sw_i2cs[i]);
1432 pool->base.sw_i2cs[i] = NULL;
1433 }
1434 }
1435
1436 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1437 if (pool->base.opps[i] != NULL)
1438 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1439 }
1440
1441 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1442 if (pool->base.timing_generators[i] != NULL) {
1443 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1444 pool->base.timing_generators[i] = NULL;
1445 }
1446 }
1447
1448 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1449 if (pool->base.dwbc[i] != NULL) {
1450 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1451 pool->base.dwbc[i] = NULL;
1452 }
1453 if (pool->base.mcif_wb[i] != NULL) {
1454 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1455 pool->base.mcif_wb[i] = NULL;
1456 }
1457 }
1458
1459 for (i = 0; i < pool->base.audio_count; i++) {
1460 if (pool->base.audios[i])
1461 dce_aud_destroy(&pool->base.audios[i]);
1462 }
1463
1464 for (i = 0; i < pool->base.clk_src_count; i++) {
1465 if (pool->base.clock_sources[i] != NULL) {
1466 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1467 pool->base.clock_sources[i] = NULL;
1468 }
1469 }
1470
1471 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1472 if (pool->base.mpc_lut[i] != NULL) {
1473 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1474 pool->base.mpc_lut[i] = NULL;
1475 }
1476 if (pool->base.mpc_shaper[i] != NULL) {
1477 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1478 pool->base.mpc_shaper[i] = NULL;
1479 }
1480 }
1481
1482 if (pool->base.dp_clock_source != NULL) {
1483 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1484 pool->base.dp_clock_source = NULL;
1485 }
1486
1487 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1488 if (pool->base.multiple_abms[i] != NULL)
1489 dce_abm_destroy(&pool->base.multiple_abms[i]);
1490 }
1491
1492 if (pool->base.psr != NULL)
1493 dmub_psr_destroy(&pool->base.psr);
1494
1495 if (pool->base.dccg != NULL)
1496 dcn_dccg_destroy(&pool->base.dccg);
1497
1498 if (pool->base.oem_device != NULL) {
1499 struct dc *dc = pool->base.oem_device->ctx->dc;
1500
1501 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1502 }
1503 }
1504
1505
dcn401_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1506 static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1507 {
1508 int i;
1509 uint32_t dwb_count = pool->res_cap->num_dwb;
1510
1511 for (i = 0; i < dwb_count; i++) {
1512 struct dcn30_dwbc *dwbc401 = kzalloc(sizeof(struct dcn30_dwbc),
1513 GFP_KERNEL);
1514
1515 if (!dwbc401) {
1516 dm_error("DC: failed to create dwbc401!\n");
1517 return false;
1518 }
1519
1520
1521 #undef REG_STRUCT
1522 #define REG_STRUCT dwbc401_regs
1523 dwbc_regs_dcn401_init(0);
1524
1525 dcn30_dwbc_construct(dwbc401, ctx,
1526 &dwbc401_regs[i],
1527 &dwbc401_shift,
1528 &dwbc401_mask,
1529 i);
1530
1531 pool->dwbc[i] = &dwbc401->base;
1532
1533 }
1534 return true;
1535 }
1536
dcn401_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1537 static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1538 {
1539 int i;
1540 uint32_t dwb_count = pool->res_cap->num_dwb;
1541
1542 for (i = 0; i < dwb_count; i++) {
1543 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1544 GFP_KERNEL);
1545
1546 if (!mcif_wb30) {
1547 dm_error("DC: failed to create mcif_wb30!\n");
1548 return false;
1549 }
1550
1551 #undef REG_STRUCT
1552 #define REG_STRUCT mcif_wb30_regs
1553 mcif_wb_regs_dcn3_init(0);
1554
1555 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1556 &mcif_wb30_regs[i],
1557 &mcif_wb30_shift,
1558 &mcif_wb30_mask,
1559 i);
1560
1561 pool->mcif_wb[i] = &mcif_wb30->base;
1562 }
1563 return true;
1564 }
1565
dcn401_dsc_create(struct dc_context * ctx,uint32_t inst)1566 static struct display_stream_compressor *dcn401_dsc_create(
1567 struct dc_context *ctx, uint32_t inst)
1568 {
1569 struct dcn401_dsc *dsc =
1570 kzalloc(sizeof(struct dcn401_dsc), GFP_KERNEL);
1571
1572 if (!dsc) {
1573 BREAK_TO_DEBUGGER();
1574 return NULL;
1575 }
1576
1577 #undef REG_STRUCT
1578 #define REG_STRUCT dsc_regs
1579 dsc_regs_init(0),
1580 dsc_regs_init(1),
1581 dsc_regs_init(2),
1582 dsc_regs_init(3);
1583
1584 dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1585 dsc401_set_fgcg(dsc,
1586 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1587
1588 //dsc->max_image_width = 6016;
1589 dsc->max_image_width = 5760;
1590
1591 return &dsc->base;
1592 }
1593
dcn401_destroy_resource_pool(struct resource_pool ** pool)1594 static void dcn401_destroy_resource_pool(struct resource_pool **pool)
1595 {
1596 struct dcn401_resource_pool *dcn401_pool = TO_DCN401_RES_POOL(*pool);
1597
1598 dcn401_resource_destruct(dcn401_pool);
1599 kfree(dcn401_pool);
1600 *pool = NULL;
1601 }
1602
1603 static struct dc_cap_funcs cap_funcs = {
1604 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
1605 .get_subvp_en = dcn32_subvp_in_use,
1606 };
1607
dcn401_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1608 static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1609 {
1610 /* re-calculate the available MALL size if required */
1611 if (bw_params->num_channels > 0) {
1612 dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
1613 dc, bw_params->num_channels) *
1614 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1615 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1616 }
1617
1618 DC_FP_START();
1619
1620 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
1621 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1622
1623 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
1624 dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
1625
1626 DC_FP_END();
1627 }
1628
dcn401_patch_unknown_plane_state(struct dc_plane_state * plane_state)1629 enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1630 {
1631 plane_state->tiling_info.gfxversion = DcGfxAddr3;
1632 plane_state->tiling_info.gfx_addr3.swizzle = DC_ADDR3_SW_64KB_2D;
1633 return DC_OK;
1634 }
1635
dcn401_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1636 enum dc_status dcn401_validate_bandwidth(struct dc *dc,
1637 struct dc_state *context,
1638 enum dc_validate_mode validate_mode)
1639 {
1640 unsigned int i;
1641 enum dc_status status = DC_OK;
1642 const struct dc_stream_state *stream;
1643
1644 /* reset cursor limitations on subvp */
1645 for (i = 0; i < context->stream_count; i++) {
1646 stream = context->streams[i];
1647
1648 if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) {
1649 dc_state_set_stream_cursor_subvp_limit(stream, context, false);
1650 }
1651 }
1652
1653 if (dc->debug.using_dml2)
1654 status = dml2_validate(dc, context,
1655 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1656 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1657
1658 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) {
1659 /* check new stream configuration still supports cursor if subvp used */
1660 for (i = 0; i < context->stream_count; i++) {
1661 stream = context->streams[i];
1662
1663 if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM &&
1664 stream->cursor_position.enable &&
1665 !dc_stream_check_cursor_attributes(stream, context, &stream->cursor_attributes)) {
1666 /* hw cursor cannot be supported with subvp active, so disable subvp for now */
1667 dc_state_set_stream_cursor_subvp_limit(stream, context, true);
1668 status = DC_FAIL_HW_CURSOR_SUPPORT;
1669 }
1670 };
1671 }
1672
1673 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) {
1674 /* attempt to validate again with subvp disabled due to cursor */
1675 if (dc->debug.using_dml2)
1676 status = dml2_validate(dc, context,
1677 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1678 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1679 }
1680
1681 return status;
1682 }
1683
dcn401_prepare_mcache_programming(struct dc * dc,struct dc_state * context)1684 void dcn401_prepare_mcache_programming(struct dc *dc,
1685 struct dc_state *context)
1686 {
1687 if (dc->debug.using_dml21)
1688 dml2_prepare_mcache_programming(dc, context,
1689 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);
1690 }
1691
dcn401_build_pipe_pix_clk_params(struct pipe_ctx * pipe_ctx)1692 static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
1693 {
1694 const struct dc_stream_state *stream = pipe_ctx->stream;
1695 struct dc_link *link = stream->link;
1696 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
1697 struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;
1698
1699 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1700
1701 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)
1702 link_enc = link_enc_cfg_get_link_enc(link);
1703 if (link_enc)
1704 pixel_clk_params->encoder_object_id = link_enc->id;
1705
1706 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1707 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1708 /* TODO: un-hardcode*/
1709
1710 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1711
1712 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1713 LINK_RATE_REF_FREQ_IN_KHZ;
1714 pixel_clk_params->flags.ENABLE_SS = 0;
1715 pixel_clk_params->color_depth =
1716 stream->timing.display_color_depth;
1717 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1718 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1719
1720 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1721 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1722
1723 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1724 pixel_clk_params->requested_pix_clk_100hz *= 2;
1725 if (dc_is_tmds_signal(stream->signal) &&
1726 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1727 pixel_clk_params->requested_pix_clk_100hz /= 2;
1728
1729 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1730 pipe_ctx->clock_source,
1731 &pipe_ctx->stream_res.pix_clk_params,
1732 &pipe_ctx->pll_settings);
1733
1734 pixel_clk_params->dio_se_pix_per_cycle = 1;
1735 if (dc_is_tmds_signal(stream->signal) &&
1736 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1737 pixel_clk_params->dio_se_pix_per_cycle = 2;
1738 } else if (dc_is_dp_signal(stream->signal)) {
1739 /* round up to nearest power of 2, or max at 8 pixels per cycle */
1740 if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1741 pixel_clk_params->dio_se_pix_per_cycle = 8;
1742 } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1743 pixel_clk_params->dio_se_pix_per_cycle = 4;
1744 } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1745 pixel_clk_params->dio_se_pix_per_cycle = 2;
1746 } else {
1747 pixel_clk_params->dio_se_pix_per_cycle = 1;
1748 }
1749 }
1750 }
1751
dcn401_get_power_profile(const struct dc_state * context)1752 static int dcn401_get_power_profile(const struct dc_state *context)
1753 {
1754 int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
1755 int dpm_level = 0;
1756
1757 for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
1758 if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 ||
1759 uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1760 break;
1761 if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1762 dpm_level++;
1763 }
1764
1765 return dpm_level;
1766 }
1767
dcn401_get_vstartup_for_pipe(struct pipe_ctx * pipe_ctx)1768 static unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)
1769 {
1770 return pipe_ctx->global_sync.dcn4x.vstartup_lines;
1771 }
1772
1773 static struct resource_funcs dcn401_res_pool_funcs = {
1774 .destroy = dcn401_destroy_resource_pool,
1775 .link_enc_create = dcn401_link_encoder_create,
1776 .link_enc_create_minimal = NULL,
1777 .panel_cntl_create = dcn32_panel_cntl_create,
1778 .validate_bandwidth = dcn401_validate_bandwidth,
1779 .calculate_wm_and_dlg = NULL,
1780 .populate_dml_pipes = NULL,
1781 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1782 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1783 .release_pipe = dcn20_release_pipe,
1784 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1785 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1786 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1787 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1788 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1789 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1790 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1791 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1792 .update_bw_bounding_box = dcn401_update_bw_bounding_box,
1793 .patch_unknown_plane_state = dcn401_patch_unknown_plane_state,
1794 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1795 .add_phantom_pipes = dcn32_add_phantom_pipes,
1796 .prepare_mcache_programming = dcn401_prepare_mcache_programming,
1797 .build_pipe_pix_clk_params = dcn401_build_pipe_pix_clk_params,
1798 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
1799 .get_power_profile = dcn401_get_power_profile,
1800 .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe,
1801 .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size
1802 };
1803
read_pipe_fuses(struct dc_context * ctx)1804 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1805 {
1806 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1807 /* DCN401 support max 4 pipes */
1808 value = value & 0xf;
1809 return value;
1810 }
1811
1812
dcn401_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn401_resource_pool * pool)1813 static bool dcn401_resource_construct(
1814 uint8_t num_virtual_links,
1815 struct dc *dc,
1816 struct dcn401_resource_pool *pool)
1817 {
1818 int i, j;
1819 struct dc_context *ctx = dc->ctx;
1820 struct irq_service_init_data init_data;
1821 struct ddc_service_init_data ddc_init_data = {0};
1822 uint32_t pipe_fuses = 0;
1823 uint32_t num_pipes = 4;
1824
1825 #undef REG_STRUCT
1826 #define REG_STRUCT bios_regs
1827 bios_regs_init();
1828
1829 #undef REG_STRUCT
1830 #define REG_STRUCT clk_src_regs
1831 clk_src_regs_init(0, A),
1832 clk_src_regs_init(1, B),
1833 clk_src_regs_init(2, C),
1834 clk_src_regs_init(3, D);
1835
1836 #undef REG_STRUCT
1837 #define REG_STRUCT abm_regs
1838 abm_regs_init(0),
1839 abm_regs_init(1),
1840 abm_regs_init(2),
1841 abm_regs_init(3);
1842
1843 #undef REG_STRUCT
1844 #define REG_STRUCT dccg_regs
1845 dccg_regs_init();
1846
1847 ctx->dc_bios->regs = &bios_regs;
1848
1849 pool->base.res_cap = &res_cap_dcn4_01;
1850
1851 /* max number of pipes for ASIC before checking for pipe fuses */
1852 num_pipes = pool->base.res_cap->num_timing_generator;
1853 pipe_fuses = read_pipe_fuses(ctx);
1854
1855 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1856 if (pipe_fuses & 1 << i)
1857 num_pipes--;
1858
1859 if (pipe_fuses & 1)
1860 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
1861
1862 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
1863 ASSERT(0); //Entire DCN is harvested!
1864
1865 pool->base.funcs = &dcn401_res_pool_funcs;
1866
1867 /*************************************************
1868 * Resource + asic cap harcoding *
1869 *************************************************/
1870 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1871 pool->base.timing_generator_count = num_pipes;
1872 pool->base.pipe_count = num_pipes;
1873 pool->base.mpcc_count = num_pipes;
1874 dc->caps.max_downscale_ratio = 600;
1875 dc->caps.i2c_speed_in_khz = 95;
1876 dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/
1877 /* used to set cursor pitch, so must be aligned to power of 2 (HW actually supported 78x78) */
1878 dc->caps.max_cursor_size = 64;
1879 dc->caps.max_buffered_cursor_size = 64;
1880 dc->caps.cursor_not_scaled = true;
1881 dc->caps.min_horizontal_blanking_period = 80;
1882 dc->caps.dmdata_alloc_size = 2048;
1883 dc->caps.mall_size_per_mem_channel = 4;
1884 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1885 dc->caps.cache_line_size = 64;
1886 dc->caps.cache_num_ways = 16;
1887
1888 /* Calculate the available MALL space */
1889 dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
1890 dc, dc->ctx->dc_bios->vram_info.num_chans) *
1891 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1892 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1893
1894 dc->caps.subvp_fw_processing_delay_us = 15;
1895 dc->caps.subvp_drr_max_vblank_margin_us = 40;
1896 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
1897 dc->caps.subvp_swath_height_margin_lines = 16;
1898 dc->caps.subvp_pstate_allow_width_us = 20;
1899 dc->caps.subvp_vertical_int_margin_us = 30;
1900 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
1901
1902 dc->caps.max_slave_planes = 3;
1903 dc->caps.max_slave_yuv_planes = 3;
1904 dc->caps.max_slave_rgb_planes = 3;
1905 dc->caps.post_blend_color_processing = true;
1906 dc->caps.force_dp_tps4_for_cp2520 = true;
1907 dc->caps.dp_hpo = true;
1908 dc->caps.dp_hdmi21_pcon_support = true;
1909 dc->caps.edp_dsc_support = true;
1910 dc->caps.extended_aux_timeout_support = true;
1911 dc->caps.dmcub_support = true;
1912 dc->caps.max_v_total = (1 << 15) - 1;
1913 dc->caps.vtotal_limited_by_fp2 = true;
1914
1915 if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))
1916 dc->caps.dcc_plane_width_limit = 7680;
1917
1918 /* Color pipeline capabilities */
1919 dc->caps.color.dpp.dcn_arch = 1;
1920 dc->caps.color.dpp.input_lut_shared = 0;
1921 dc->caps.color.dpp.icsc = 1;
1922 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1923 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1924 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1925 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1926 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1927 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1928 dc->caps.color.dpp.post_csc = 1;
1929 dc->caps.color.dpp.gamma_corr = 1;
1930 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1931
1932 dc->caps.color.dpp.hw_3d_lut = 0;
1933 dc->caps.color.dpp.ogam_ram = 0;
1934 // no OGAM ROM on DCN2 and later ASICs
1935 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1936 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1937 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1938 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1939 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1940 dc->caps.color.dpp.ocsc = 0;
1941
1942 dc->caps.color.mpc.gamut_remap = 1;
1943 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
1944 dc->caps.color.mpc.ogam_ram = 1;
1945 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1946 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1947 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1948 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1949 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1950 dc->caps.color.mpc.ocsc = 1;
1951 dc->caps.color.mpc.preblend = true;
1952 dc->config.use_spl = true;
1953 dc->config.prefer_easf = true;
1954
1955 dc->config.dcn_sharpness_range.sdr_rgb_min = 0;
1956 dc->config.dcn_sharpness_range.sdr_rgb_max = 1750;
1957 dc->config.dcn_sharpness_range.sdr_rgb_mid = 750;
1958 dc->config.dcn_sharpness_range.sdr_yuv_min = 0;
1959 dc->config.dcn_sharpness_range.sdr_yuv_max = 3500;
1960 dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500;
1961 dc->config.dcn_sharpness_range.hdr_rgb_min = 0;
1962 dc->config.dcn_sharpness_range.hdr_rgb_max = 2750;
1963 dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500;
1964
1965 dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0;
1966 dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250;
1967 dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;
1968 dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0;
1969 dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500;
1970 dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;
1971 dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0;
1972 dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750;
1973 dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;
1974
1975 dc->config.dc_mode_clk_limit_support = true;
1976 dc->config.enable_windowed_mpo_odm = true;
1977 dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */
1978
1979 /* read VBIOS LTTPR caps */
1980 {
1981 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1982 enum bp_result bp_query_result;
1983 uint8_t is_vbios_lttpr_enable = 0;
1984
1985 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1986 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1987 }
1988
1989 /* interop bit is implicit */
1990 {
1991 dc->caps.vbios_lttpr_aware = true;
1992 }
1993 }
1994
1995 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1996 dc->debug = debug_defaults_drv;
1997
1998 // Init the vm_helper
1999 if (dc->vm_helper)
2000 vm_helper_init(dc->vm_helper, 16);
2001
2002 /*************************************************
2003 * Create resources *
2004 *************************************************/
2005
2006 /* Clock Sources for Pixel Clock*/
2007 pool->base.clock_sources[DCN401_CLK_SRC_PLL0] =
2008 dcn401_clock_source_create(ctx, ctx->dc_bios,
2009 CLOCK_SOURCE_COMBO_PHY_PLL0,
2010 &clk_src_regs[0], false);
2011 pool->base.clock_sources[DCN401_CLK_SRC_PLL1] =
2012 dcn401_clock_source_create(ctx, ctx->dc_bios,
2013 CLOCK_SOURCE_COMBO_PHY_PLL1,
2014 &clk_src_regs[1], false);
2015 pool->base.clock_sources[DCN401_CLK_SRC_PLL2] =
2016 dcn401_clock_source_create(ctx, ctx->dc_bios,
2017 CLOCK_SOURCE_COMBO_PHY_PLL2,
2018 &clk_src_regs[2], false);
2019 pool->base.clock_sources[DCN401_CLK_SRC_PLL3] =
2020 dcn401_clock_source_create(ctx, ctx->dc_bios,
2021 CLOCK_SOURCE_COMBO_PHY_PLL3,
2022 &clk_src_regs[3], false);
2023 // pool->base.clock_sources[DCN401_CLK_SRC_PLL4] =
2024 // dcn401_clock_source_create(ctx, ctx->dc_bios,
2025 // CLOCK_SOURCE_COMBO_PHY_PLL4,
2026 // &clk_src_regs[4], false);
2027
2028 pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL;
2029
2030 /* todo: not reuse phy_pll registers */
2031 pool->base.dp_clock_source =
2032 dcn401_clock_source_create(ctx, ctx->dc_bios,
2033 CLOCK_SOURCE_ID_DP_DTO,
2034 &clk_src_regs[0], true);
2035
2036 for (i = 0; i < pool->base.clk_src_count; i++) {
2037 if (pool->base.clock_sources[i] == NULL) {
2038 dm_error("DC: failed to create clock sources!\n");
2039 BREAK_TO_DEBUGGER();
2040 goto create_fail;
2041 }
2042 }
2043
2044 /* DCCG */
2045 pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2046 if (pool->base.dccg == NULL) {
2047 dm_error("DC: failed to create dccg!\n");
2048 BREAK_TO_DEBUGGER();
2049 goto create_fail;
2050 }
2051
2052 /* IRQ Service */
2053 init_data.ctx = dc->ctx;
2054 pool->base.irqs = dal_irq_service_dcn401_create(&init_data);
2055 if (!pool->base.irqs)
2056 goto create_fail;
2057
2058 /* HUBBUB */
2059 pool->base.hubbub = dcn401_hubbub_create(ctx);
2060 if (pool->base.hubbub == NULL) {
2061 BREAK_TO_DEBUGGER();
2062 dm_error("DC: failed to create hubbub!\n");
2063 goto create_fail;
2064 }
2065
2066 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2067 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2068
2069 /* if pipe is disabled, skip instance of HW pipe,
2070 * i.e, skip ASIC register instance
2071 */
2072 if (pipe_fuses & 1 << i)
2073 continue;
2074
2075 pool->base.hubps[j] = dcn401_hubp_create(ctx, i);
2076 if (pool->base.hubps[j] == NULL) {
2077 BREAK_TO_DEBUGGER();
2078 dm_error(
2079 "DC: failed to create hubps!\n");
2080 goto create_fail;
2081 }
2082
2083 pool->base.dpps[j] = dcn401_dpp_create(ctx, i);
2084 if (pool->base.dpps[j] == NULL) {
2085 BREAK_TO_DEBUGGER();
2086 dm_error(
2087 "DC: failed to create dpps!\n");
2088 goto create_fail;
2089 }
2090
2091 pool->base.opps[j] = dcn401_opp_create(ctx, i);
2092 if (pool->base.opps[j] == NULL) {
2093 BREAK_TO_DEBUGGER();
2094 dm_error(
2095 "DC: failed to create output pixel processor!\n");
2096 goto create_fail;
2097 }
2098
2099 pool->base.timing_generators[j] = dcn401_timing_generator_create(
2100 ctx, i);
2101 if (pool->base.timing_generators[j] == NULL) {
2102 BREAK_TO_DEBUGGER();
2103 dm_error("DC: failed to create tg!\n");
2104 goto create_fail;
2105 }
2106
2107 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2108 &abm_regs[i],
2109 &abm_shift,
2110 &abm_mask);
2111 if (pool->base.multiple_abms[j] == NULL) {
2112 dm_error("DC: failed to create abm for pipe %d!\n", i);
2113 BREAK_TO_DEBUGGER();
2114 goto create_fail;
2115 }
2116
2117 /* index for resource pool arrays for next valid pipe */
2118 j++;
2119 }
2120
2121 /* PSR */
2122 pool->base.psr = dmub_psr_create(ctx);
2123 if (pool->base.psr == NULL) {
2124 dm_error("DC: failed to create psr obj!\n");
2125 BREAK_TO_DEBUGGER();
2126 goto create_fail;
2127 }
2128
2129 /* MPCCs */
2130 pool->base.mpc = dcn401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2131 if (pool->base.mpc == NULL) {
2132 BREAK_TO_DEBUGGER();
2133 dm_error("DC: failed to create mpc!\n");
2134 goto create_fail;
2135 }
2136
2137 /* DSCs */
2138 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2139 pool->base.dscs[i] = dcn401_dsc_create(ctx, i);
2140 if (pool->base.dscs[i] == NULL) {
2141 BREAK_TO_DEBUGGER();
2142 dm_error("DC: failed to create display stream compressor %d!\n", i);
2143 goto create_fail;
2144 }
2145 }
2146
2147 /* DWB */
2148 if (!dcn401_dwbc_create(ctx, &pool->base)) {
2149 BREAK_TO_DEBUGGER();
2150 dm_error("DC: failed to create dwbc!\n");
2151 goto create_fail;
2152 }
2153
2154 /* MMHUBBUB */
2155 if (!dcn401_mmhubbub_create(ctx, &pool->base)) {
2156 BREAK_TO_DEBUGGER();
2157 dm_error("DC: failed to create mcif_wb!\n");
2158 goto create_fail;
2159 }
2160
2161 /* AUX and I2C */
2162 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2163 pool->base.engines[i] = dcn401_aux_engine_create(ctx, i);
2164 if (pool->base.engines[i] == NULL) {
2165 BREAK_TO_DEBUGGER();
2166 dm_error(
2167 "DC:failed to create aux engine!!\n");
2168 goto create_fail;
2169 }
2170 pool->base.hw_i2cs[i] = dcn401_i2c_hw_create(ctx, i);
2171 if (pool->base.hw_i2cs[i] == NULL) {
2172 BREAK_TO_DEBUGGER();
2173 dm_error(
2174 "DC:failed to create hw i2c!!\n");
2175 goto create_fail;
2176 }
2177 pool->base.sw_i2cs[i] = NULL;
2178 }
2179
2180 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2181 if (!resource_construct(num_virtual_links, dc, &pool->base,
2182 &res_create_funcs))
2183 goto create_fail;
2184
2185 /* HW Sequencer init functions and Plane caps */
2186 dcn401_hw_sequencer_init_functions(dc);
2187
2188 dc->caps.max_planes = pool->base.pipe_count;
2189
2190 for (i = 0; i < dc->caps.max_planes; ++i)
2191 dc->caps.planes[i] = plane_cap;
2192
2193 dc->caps.max_odm_combine_factor = 4;
2194
2195 dc->cap_funcs = cap_funcs;
2196
2197 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2198 ddc_init_data.ctx = dc->ctx;
2199 ddc_init_data.link = NULL;
2200 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2201 ddc_init_data.id.enum_id = 0;
2202 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2203 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2204 } else {
2205 pool->base.oem_device = NULL;
2206 }
2207
2208 //For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided
2209 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2210 dc->config.sdpif_request_limit_words_per_umc = 16;
2211
2212 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2213 dc->dml2_options.use_native_soc_bb_construction = true;
2214 dc->dml2_options.minimize_dispclk_using_odm = true;
2215 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2216 dc->dml2_options.force_tdlut_enable = true;
2217
2218 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2219 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2220 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2221 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2222
2223 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2224 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2225 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2226 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2227
2228 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2229 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2230
2231 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2232 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2233 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2234 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2235 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2236 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2237 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2238
2239 dc->dml2_options.max_segments_per_hubp = 20;
2240 dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;
2241
2242 /* SPL */
2243 dc->caps.scl_caps.sharpener_support = true;
2244
2245 /* init DC limited DML2 options */
2246 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
2247 dc->dml2_dc_power_options.use_clock_dc_limits = true;
2248
2249 return true;
2250
2251 create_fail:
2252
2253 dcn401_resource_destruct(pool);
2254
2255 return false;
2256 }
2257
dcn401_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2258 struct resource_pool *dcn401_create_resource_pool(
2259 const struct dc_init_data *init_data,
2260 struct dc *dc)
2261 {
2262 struct dcn401_resource_pool *pool =
2263 kzalloc(sizeof(struct dcn401_resource_pool), GFP_KERNEL);
2264
2265 if (!pool)
2266 return NULL;
2267
2268 if (dcn401_resource_construct(init_data->num_virtual_links, dc, pool))
2269 return &pool->base;
2270
2271 BREAK_TO_DEBUGGER();
2272 kfree(pool);
2273 return NULL;
2274 }
2275