1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * Copyright 2019 Raptor Engineering, LLC
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <linux/slab.h>
28
29 #include "dm_services.h"
30 #include "dc.h"
31
32 #include "dcn21/dcn21_init.h"
33
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn21/dcn21_resource.h"
38
39 #include "dml/dcn20/dcn20_fpu.h"
40
41 #include "clk_mgr.h"
42 #include "dcn10/dcn10_hubp.h"
43 #include "dcn10/dcn10_ipp.h"
44 #include "dcn20/dcn20_hubbub.h"
45 #include "dcn20/dcn20_mpc.h"
46 #include "dcn20/dcn20_hubp.h"
47 #include "dcn21/dcn21_hubp.h"
48 #include "irq/dcn21/irq_service_dcn21.h"
49 #include "dcn20/dcn20_dpp.h"
50 #include "dcn20/dcn20_optc.h"
51 #include "dcn21/dcn21_hwseq.h"
52 #include "dce110/dce110_hwseq.h"
53 #include "dcn20/dcn20_opp.h"
54 #include "dcn20/dcn20_dsc.h"
55 #include "dcn21/dcn21_link_encoder.h"
56 #include "dcn20/dcn20_stream_encoder.h"
57 #include "dce/dce_clock_source.h"
58 #include "dce/dce_audio.h"
59 #include "dce/dce_hwseq.h"
60 #include "dio/virtual/virtual_stream_encoder.h"
61 #include "dml/display_mode_vba.h"
62 #include "dcn20/dcn20_dccg.h"
63 #include "dcn21/dcn21_dccg.h"
64 #include "dcn21/dcn21_hubbub.h"
65 #include "dcn10/dcn10_resource.h"
66 #include "dce/dce_panel_cntl.h"
67
68 #include "dcn20/dcn20_dwb.h"
69 #include "dcn20/dcn20_mmhubbub.h"
70 #include "dpcs/dpcs_2_1_0_offset.h"
71 #include "dpcs/dpcs_2_1_0_sh_mask.h"
72
73 #include "renoir_ip_offset.h"
74 #include "dcn/dcn_2_1_0_offset.h"
75 #include "dcn/dcn_2_1_0_sh_mask.h"
76
77 #include "nbio/nbio_7_0_offset.h"
78
79 #include "mmhub/mmhub_2_0_0_offset.h"
80 #include "mmhub/mmhub_2_0_0_sh_mask.h"
81
82 #include "reg_helper.h"
83 #include "dce/dce_abm.h"
84 #include "dce/dce_dmcu.h"
85 #include "dce/dce_aux.h"
86 #include "dce/dce_i2c.h"
87 #include "dio/dcn10/dcn10_dio.h"
88 #include "dcn21_resource.h"
89 #include "vm_helper.h"
90 #include "dcn20/dcn20_vmid.h"
91 #include "dce/dmub_psr.h"
92 #include "dce/dmub_abm.h"
93
94 /* begin *********************
95 * macros to expend register list macro defined in HW object header file */
96
97 /* DCN */
98 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
99
100 #define BASE(seg) BASE_INNER(seg)
101
102 #define SR(reg_name)\
103 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
104 mm ## reg_name
105
106 #define SRI(reg_name, block, id)\
107 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
108 mm ## block ## id ## _ ## reg_name
109
110 #define SRIR(var_name, reg_name, block, id)\
111 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
112 mm ## block ## id ## _ ## reg_name
113
114 #define SRII(reg_name, block, id)\
115 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
116 mm ## block ## id ## _ ## reg_name
117
118 #define DCCG_SRII(reg_name, block, id)\
119 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
120 mm ## block ## id ## _ ## reg_name
121
122 #define VUPDATE_SRII(reg_name, block, id)\
123 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
124 mm ## reg_name ## _ ## block ## id
125
126 /* NBIO */
127 #define NBIO_BASE_INNER(seg) \
128 NBIF0_BASE__INST0_SEG ## seg
129
130 #define NBIO_BASE(seg) \
131 NBIO_BASE_INNER(seg)
132
133 #define NBIO_SR(reg_name)\
134 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
135 mm ## reg_name
136
137 /* MMHUB */
138 #define MMHUB_BASE_INNER(seg) \
139 MMHUB_BASE__INST0_SEG ## seg
140
141 #define MMHUB_BASE(seg) \
142 MMHUB_BASE_INNER(seg)
143
144 #define MMHUB_SR(reg_name)\
145 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
146 mmMM ## reg_name
147
148 #define clk_src_regs(index, pllid)\
149 [index] = {\
150 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
151 }
152
153 static const struct dce110_clk_src_regs clk_src_regs[] = {
154 clk_src_regs(0, A),
155 clk_src_regs(1, B),
156 clk_src_regs(2, C),
157 clk_src_regs(3, D),
158 clk_src_regs(4, E),
159 };
160
161 static const struct dce110_clk_src_shift cs_shift = {
162 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
163 };
164
165 static const struct dce110_clk_src_mask cs_mask = {
166 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
167 };
168
169 static const struct bios_registers bios_regs = {
170 NBIO_SR(BIOS_SCRATCH_3),
171 NBIO_SR(BIOS_SCRATCH_6)
172 };
173
174 static const struct dce_dmcu_registers dmcu_regs = {
175 DMCU_DCN20_REG_LIST()
176 };
177
178 static const struct dce_dmcu_shift dmcu_shift = {
179 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
180 };
181
182 static const struct dce_dmcu_mask dmcu_mask = {
183 DMCU_MASK_SH_LIST_DCN10(_MASK)
184 };
185
186 static const struct dce_abm_registers abm_regs = {
187 ABM_DCN20_REG_LIST()
188 };
189
190 static const struct dce_abm_shift abm_shift = {
191 ABM_MASK_SH_LIST_DCN20(__SHIFT)
192 };
193
194 static const struct dce_abm_mask abm_mask = {
195 ABM_MASK_SH_LIST_DCN20(_MASK)
196 };
197
198 #define audio_regs(id)\
199 [id] = {\
200 AUD_COMMON_REG_LIST(id)\
201 }
202
203 static const struct dce_audio_registers audio_regs[] = {
204 audio_regs(0),
205 audio_regs(1),
206 audio_regs(2),
207 audio_regs(3),
208 audio_regs(4),
209 audio_regs(5),
210 };
211
212 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
213 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
214 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
215 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
216
217 static const struct dce_audio_shift audio_shift = {
218 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
219 };
220
221 static const struct dce_audio_mask audio_mask = {
222 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
223 };
224
225 static const struct dccg_registers dccg_regs = {
226 DCCG_COMMON_REG_LIST_DCN_BASE()
227 };
228
229 static const struct dccg_shift dccg_shift = {
230 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
231 };
232
233 static const struct dccg_mask dccg_mask = {
234 DCCG_MASK_SH_LIST_DCN2_1(_MASK)
235 };
236
237 #define opp_regs(id)\
238 [id] = {\
239 OPP_REG_LIST_DCN20(id),\
240 }
241
242 static const struct dcn20_opp_registers opp_regs[] = {
243 opp_regs(0),
244 opp_regs(1),
245 opp_regs(2),
246 opp_regs(3),
247 opp_regs(4),
248 opp_regs(5),
249 };
250
251 static const struct dcn20_opp_shift opp_shift = {
252 OPP_MASK_SH_LIST_DCN20(__SHIFT)
253 };
254
255 static const struct dcn20_opp_mask opp_mask = {
256 OPP_MASK_SH_LIST_DCN20(_MASK)
257 };
258
259 #define tg_regs(id)\
260 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
261
262 static const struct dcn_optc_registers tg_regs[] = {
263 tg_regs(0),
264 tg_regs(1),
265 tg_regs(2),
266 tg_regs(3)
267 };
268
269 static const struct dcn_optc_shift tg_shift = {
270 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
271 };
272
273 static const struct dcn_optc_mask tg_mask = {
274 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
275 };
276
277 static const struct dcn20_mpc_registers mpc_regs = {
278 MPC_REG_LIST_DCN2_0(0),
279 MPC_REG_LIST_DCN2_0(1),
280 MPC_REG_LIST_DCN2_0(2),
281 MPC_REG_LIST_DCN2_0(3),
282 MPC_REG_LIST_DCN2_0(4),
283 MPC_REG_LIST_DCN2_0(5),
284 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
285 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
286 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
287 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
288 MPC_DBG_REG_LIST_DCN2_0()
289 };
290
291 static const struct dcn20_mpc_shift mpc_shift = {
292 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
293 MPC_DEBUG_REG_LIST_SH_DCN20
294 };
295
296 static const struct dcn20_mpc_mask mpc_mask = {
297 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
298 MPC_DEBUG_REG_LIST_MASK_DCN20
299 };
300
301 #define hubp_regs(id)\
302 [id] = {\
303 HUBP_REG_LIST_DCN21(id)\
304 }
305
306 static const struct dcn_hubp2_registers hubp_regs[] = {
307 hubp_regs(0),
308 hubp_regs(1),
309 hubp_regs(2),
310 hubp_regs(3)
311 };
312
313 static const struct dcn_hubp2_shift hubp_shift = {
314 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
315 };
316
317 static const struct dcn_hubp2_mask hubp_mask = {
318 HUBP_MASK_SH_LIST_DCN21(_MASK)
319 };
320
321 static const struct dcn_hubbub_registers hubbub_reg = {
322 HUBBUB_REG_LIST_DCN21()
323 };
324
325 static const struct dcn_hubbub_shift hubbub_shift = {
326 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
327 };
328
329 static const struct dcn_hubbub_mask hubbub_mask = {
330 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
331 };
332
333 static const struct dcn_dio_registers dio_regs = {
334 DIO_REG_LIST_DCN10()
335 };
336
337 static const struct dcn_dio_shift dio_shift = { 0 };
338
339 static const struct dcn_dio_mask dio_mask = { 0 };
340
dcn21_dio_create(struct dc_context * ctx)341 static struct dio *dcn21_dio_create(struct dc_context *ctx)
342 {
343 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
344
345 if (!dio10)
346 return NULL;
347
348 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
349
350 return &dio10->base;
351 }
352
353 #define vmid_regs(id)\
354 [id] = {\
355 DCN20_VMID_REG_LIST(id)\
356 }
357
358 static const struct dcn_vmid_registers vmid_regs[] = {
359 vmid_regs(0),
360 vmid_regs(1),
361 vmid_regs(2),
362 vmid_regs(3),
363 vmid_regs(4),
364 vmid_regs(5),
365 vmid_regs(6),
366 vmid_regs(7),
367 vmid_regs(8),
368 vmid_regs(9),
369 vmid_regs(10),
370 vmid_regs(11),
371 vmid_regs(12),
372 vmid_regs(13),
373 vmid_regs(14),
374 vmid_regs(15)
375 };
376
377 static const struct dcn20_vmid_shift vmid_shifts = {
378 DCN20_VMID_MASK_SH_LIST(__SHIFT)
379 };
380
381 static const struct dcn20_vmid_mask vmid_masks = {
382 DCN20_VMID_MASK_SH_LIST(_MASK)
383 };
384
385 #define dsc_regsDCN20(id)\
386 [id] = {\
387 DSC_REG_LIST_DCN20(id)\
388 }
389
390 static const struct dcn20_dsc_registers dsc_regs[] = {
391 dsc_regsDCN20(0),
392 dsc_regsDCN20(1),
393 dsc_regsDCN20(2),
394 dsc_regsDCN20(3),
395 dsc_regsDCN20(4),
396 dsc_regsDCN20(5)
397 };
398
399 static const struct dcn20_dsc_shift dsc_shift = {
400 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
401 };
402
403 static const struct dcn20_dsc_mask dsc_mask = {
404 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
405 };
406
407 #define ipp_regs(id)\
408 [id] = {\
409 IPP_REG_LIST_DCN20(id),\
410 }
411
412 static const struct dcn10_ipp_registers ipp_regs[] = {
413 ipp_regs(0),
414 ipp_regs(1),
415 ipp_regs(2),
416 ipp_regs(3),
417 };
418
419 static const struct dcn10_ipp_shift ipp_shift = {
420 IPP_MASK_SH_LIST_DCN20(__SHIFT)
421 };
422
423 static const struct dcn10_ipp_mask ipp_mask = {
424 IPP_MASK_SH_LIST_DCN20(_MASK),
425 };
426
427 #define opp_regs(id)\
428 [id] = {\
429 OPP_REG_LIST_DCN20(id),\
430 }
431
432
433 #define aux_engine_regs(id)\
434 [id] = {\
435 AUX_COMMON_REG_LIST0(id), \
436 .AUXN_IMPCAL = 0, \
437 .AUXP_IMPCAL = 0, \
438 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
439 }
440
441 static const struct dce110_aux_registers aux_engine_regs[] = {
442 aux_engine_regs(0),
443 aux_engine_regs(1),
444 aux_engine_regs(2),
445 aux_engine_regs(3),
446 aux_engine_regs(4),
447 };
448
449 #define tf_regs(id)\
450 [id] = {\
451 TF_REG_LIST_DCN20(id),\
452 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
453 }
454
455 static const struct dcn2_dpp_registers tf_regs[] = {
456 tf_regs(0),
457 tf_regs(1),
458 tf_regs(2),
459 tf_regs(3),
460 };
461
462 static const struct dcn2_dpp_shift tf_shift = {
463 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
464 TF_DEBUG_REG_LIST_SH_DCN20
465 };
466
467 static const struct dcn2_dpp_mask tf_mask = {
468 TF_REG_LIST_SH_MASK_DCN20(_MASK),
469 TF_DEBUG_REG_LIST_MASK_DCN20
470 };
471
472 #define stream_enc_regs(id)\
473 [id] = {\
474 SE_DCN2_REG_LIST(id)\
475 }
476
477 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
478 stream_enc_regs(0),
479 stream_enc_regs(1),
480 stream_enc_regs(2),
481 stream_enc_regs(3),
482 stream_enc_regs(4),
483 };
484
485 static const struct dce110_aux_registers_shift aux_shift = {
486 DCN_AUX_MASK_SH_LIST(__SHIFT)
487 };
488
489 static const struct dce110_aux_registers_mask aux_mask = {
490 DCN_AUX_MASK_SH_LIST(_MASK)
491 };
492
493 static const struct dcn10_stream_encoder_shift se_shift = {
494 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
495 };
496
497 static const struct dcn10_stream_encoder_mask se_mask = {
498 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
499 };
500
501 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
502
dcn21_ipp_create(struct dc_context * ctx,uint32_t inst)503 static struct input_pixel_processor *dcn21_ipp_create(
504 struct dc_context *ctx, uint32_t inst)
505 {
506 struct dcn10_ipp *ipp =
507 kzalloc_obj(struct dcn10_ipp);
508
509 if (!ipp) {
510 BREAK_TO_DEBUGGER();
511 return NULL;
512 }
513
514 dcn20_ipp_construct(ipp, ctx, inst,
515 &ipp_regs[inst], &ipp_shift, &ipp_mask);
516 return &ipp->base;
517 }
518
dcn21_dpp_create(struct dc_context * ctx,uint32_t inst)519 static struct dpp *dcn21_dpp_create(
520 struct dc_context *ctx,
521 uint32_t inst)
522 {
523 struct dcn20_dpp *dpp =
524 kzalloc_obj(struct dcn20_dpp);
525
526 if (!dpp)
527 return NULL;
528
529 if (dpp2_construct(dpp, ctx, inst,
530 &tf_regs[inst], &tf_shift, &tf_mask))
531 return &dpp->base;
532
533 BREAK_TO_DEBUGGER();
534 kfree(dpp);
535 return NULL;
536 }
537
dcn21_aux_engine_create(struct dc_context * ctx,uint32_t inst)538 static struct dce_aux *dcn21_aux_engine_create(
539 struct dc_context *ctx,
540 uint32_t inst)
541 {
542 struct aux_engine_dce110 *aux_engine =
543 kzalloc_obj(struct aux_engine_dce110);
544
545 if (!aux_engine)
546 return NULL;
547
548 dce110_aux_engine_construct(aux_engine, ctx, inst,
549 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
550 &aux_engine_regs[inst],
551 &aux_mask,
552 &aux_shift,
553 ctx->dc->caps.extended_aux_timeout_support);
554
555 return &aux_engine->base;
556 }
557
558 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
559
560 static const struct dce_i2c_registers i2c_hw_regs[] = {
561 i2c_inst_regs(1),
562 i2c_inst_regs(2),
563 i2c_inst_regs(3),
564 i2c_inst_regs(4),
565 i2c_inst_regs(5),
566 };
567
568 static const struct dce_i2c_shift i2c_shifts = {
569 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
570 };
571
572 static const struct dce_i2c_mask i2c_masks = {
573 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
574 };
575
dcn21_i2c_hw_create(struct dc_context * ctx,uint32_t inst)576 static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx,
577 uint32_t inst)
578 {
579 struct dce_i2c_hw *dce_i2c_hw =
580 kzalloc_obj(struct dce_i2c_hw);
581
582 if (!dce_i2c_hw)
583 return NULL;
584
585 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
586 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
587
588 return dce_i2c_hw;
589 }
590
591 static const struct resource_caps res_cap_rn = {
592 .num_timing_generator = 4,
593 .num_opp = 4,
594 .num_video_plane = 4,
595 .num_audio = 4, // 4 audio endpoints. 4 audio streams
596 .num_stream_encoder = 5,
597 .num_pll = 5, // maybe 3 because the last two used for USB-c
598 .num_dwb = 1,
599 .num_ddc = 5,
600 .num_vmid = 16,
601 .num_dsc = 3,
602 };
603
604 static const struct dc_plane_cap plane_cap = {
605 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
606 .per_pixel_alpha = true,
607
608 .pixel_format_support = {
609 .argb8888 = true,
610 .nv12 = true,
611 .fp16 = true,
612 .p010 = true
613 },
614
615 .max_upscale_factor = {
616 .argb8888 = 16000,
617 .nv12 = 16000,
618 .fp16 = 16000
619 },
620
621 .max_downscale_factor = {
622 .argb8888 = 250,
623 .nv12 = 250,
624 .fp16 = 250
625 },
626 64,
627 64
628 };
629
630 static const struct dc_debug_options debug_defaults_drv = {
631 .disable_dmcu = false,
632 .force_abm_enable = false,
633 .clock_trace = true,
634 .disable_pplib_clock_request = true,
635 .min_disp_clk_khz = 100000,
636 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
637 .force_single_disp_pipe_split = false,
638 .disable_dcc = DCC_ENABLE,
639 .vsr_support = true,
640 .performance_trace = false,
641 .max_downscale_src_width = 4096,
642 .disable_pplib_wm_range = false,
643 .scl_reset_length10 = true,
644 .sanity_checks = true,
645 .disable_48mhz_pwrdwn = false,
646 .usbc_combo_phy_reset_wa = true,
647 .dmub_command_table = true,
648 .use_max_lb = true,
649 .using_dml2 = false,
650 };
651
652 static const struct dc_check_config config_defaults = {
653 .enable_legacy_fast_update = true,
654 };
655
656 static const struct dc_panel_config panel_config_defaults = {
657 .psr = {
658 .disable_psr = false,
659 .disallow_psrsu = false,
660 .disallow_replay = false,
661 },
662 .ilr = {
663 .optimize_edp_link_rate = true,
664 },
665 };
666
667 enum dcn20_clk_src_array_id {
668 DCN20_CLK_SRC_PLL0,
669 DCN20_CLK_SRC_PLL1,
670 DCN20_CLK_SRC_PLL2,
671 DCN20_CLK_SRC_PLL3,
672 DCN20_CLK_SRC_PLL4,
673 DCN20_CLK_SRC_TOTAL_DCN21
674 };
675
dcn21_resource_destruct(struct dcn21_resource_pool * pool)676 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
677 {
678 unsigned int i;
679
680 for (i = 0; i < pool->base.stream_enc_count; i++) {
681 if (pool->base.stream_enc[i] != NULL) {
682 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
683 pool->base.stream_enc[i] = NULL;
684 }
685 }
686
687 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
688 if (pool->base.dscs[i] != NULL)
689 dcn20_dsc_destroy(&pool->base.dscs[i]);
690 }
691
692 if (pool->base.mpc != NULL) {
693 kfree(TO_DCN20_MPC(pool->base.mpc));
694 pool->base.mpc = NULL;
695 }
696 if (pool->base.hubbub != NULL) {
697 kfree(pool->base.hubbub);
698 pool->base.hubbub = NULL;
699 }
700
701 if (pool->base.dio != NULL) {
702 kfree(TO_DCN10_DIO(pool->base.dio));
703 pool->base.dio = NULL;
704 }
705
706 for (i = 0; i < pool->base.pipe_count; i++) {
707 if (pool->base.dpps[i] != NULL)
708 dcn20_dpp_destroy(&pool->base.dpps[i]);
709
710 if (pool->base.ipps[i] != NULL)
711 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
712
713 if (pool->base.hubps[i] != NULL) {
714 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
715 pool->base.hubps[i] = NULL;
716 }
717
718 if (pool->base.irqs != NULL)
719 dal_irq_service_destroy(&pool->base.irqs);
720 }
721
722 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
723 if (pool->base.engines[i] != NULL)
724 dce110_engine_destroy(&pool->base.engines[i]);
725 if (pool->base.hw_i2cs[i] != NULL) {
726 kfree(pool->base.hw_i2cs[i]);
727 pool->base.hw_i2cs[i] = NULL;
728 }
729 if (pool->base.sw_i2cs[i] != NULL) {
730 kfree(pool->base.sw_i2cs[i]);
731 pool->base.sw_i2cs[i] = NULL;
732 }
733 }
734
735 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
736 if (pool->base.opps[i] != NULL)
737 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
738 }
739
740 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
741 if (pool->base.timing_generators[i] != NULL) {
742 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
743 pool->base.timing_generators[i] = NULL;
744 }
745 }
746
747 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
748 if (pool->base.dwbc[i] != NULL) {
749 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
750 pool->base.dwbc[i] = NULL;
751 }
752 if (pool->base.mcif_wb[i] != NULL) {
753 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
754 pool->base.mcif_wb[i] = NULL;
755 }
756 }
757
758 for (i = 0; i < pool->base.audio_count; i++) {
759 if (pool->base.audios[i])
760 dce_aud_destroy(&pool->base.audios[i]);
761 }
762
763 for (i = 0; i < pool->base.clk_src_count; i++) {
764 if (pool->base.clock_sources[i] != NULL) {
765 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
766 pool->base.clock_sources[i] = NULL;
767 }
768 }
769
770 if (pool->base.dp_clock_source != NULL) {
771 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
772 pool->base.dp_clock_source = NULL;
773 }
774
775 if (pool->base.abm != NULL) {
776 if (pool->base.abm->ctx->dc->config.disable_dmcu)
777 dmub_abm_destroy(&pool->base.abm);
778 else
779 dce_abm_destroy(&pool->base.abm);
780 }
781
782 if (pool->base.dmcu != NULL)
783 dce_dmcu_destroy(&pool->base.dmcu);
784
785 if (pool->base.psr != NULL)
786 dmub_psr_destroy(&pool->base.psr);
787
788 if (pool->base.dccg != NULL)
789 dcn_dccg_destroy(&pool->base.dccg);
790
791 if (pool->base.pp_smu != NULL)
792 dcn21_pp_smu_destroy(&pool->base.pp_smu);
793 }
794
dcn21_fast_validate_bw(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * pipe_cnt_out,int * pipe_split_from,int * vlevel_out,enum dc_validate_mode validate_mode,bool allow_self_refresh_only)795 bool dcn21_fast_validate_bw(struct dc *dc,
796 struct dc_state *context,
797 display_e2e_pipe_params_st *pipes,
798 int *pipe_cnt_out,
799 int *pipe_split_from,
800 int *vlevel_out,
801 enum dc_validate_mode validate_mode,
802 bool allow_self_refresh_only)
803 {
804 bool out = false;
805 int split[MAX_PIPES] = { 0 };
806 bool merge[MAX_PIPES] = { false };
807 int pipe_cnt, i, pipe_idx, vlevel;
808
809 ASSERT(pipes);
810 if (!pipes)
811 return false;
812
813 dcn20_merge_pipes_for_validate(dc, context);
814
815 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
816
817 *pipe_cnt_out = pipe_cnt;
818
819 if (!pipe_cnt) {
820 out = true;
821 goto validate_out;
822 }
823 /*
824 * DML favors voltage over p-state, but we're more interested in
825 * supporting p-state over voltage. We can't support p-state in
826 * prefetch mode > 0 so try capping the prefetch mode to start.
827 */
828 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
829 dm_allow_self_refresh_and_mclk_switch;
830 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
831
832 if (vlevel > context->bw_ctx.dml.soc.num_states) {
833
834 if (allow_self_refresh_only) {
835 /*
836 * If mode is unsupported or there's still no p-state support then
837 * fall back to favoring voltage.
838 *
839 * We don't actually support prefetch mode 2, so require that we
840 * at least support prefetch mode 1.
841 */
842 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
843 dm_allow_self_refresh;
844 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
845 if (vlevel > context->bw_ctx.dml.soc.num_states)
846 goto validate_fail;
847 } else {
848 goto validate_fail;
849 }
850 }
851
852 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
853
854 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
855 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
856 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
857 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
858
859 if (!pipe->stream)
860 continue;
861
862 /* We only support full screen mpo with ODM */
863 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
864 && pipe->plane_state && mpo_pipe
865 && memcmp(&mpo_pipe->plane_state->clip_rect,
866 &pipe->stream->src,
867 sizeof(struct rect)) != 0) {
868 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
869 goto validate_fail;
870 }
871 pipe_idx++;
872 }
873
874 /*initialize pipe_just_split_from to invalid idx*/
875 for (i = 0; i < MAX_PIPES; i++)
876 pipe_split_from[i] = -1;
877
878 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
879 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
880 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
881
882 if (!pipe->stream || pipe_split_from[i] >= 0)
883 continue;
884
885 pipe_idx++;
886
887 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
888 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
889 ASSERT(hsplit_pipe);
890 if (!dcn20_split_stream_for_odm(
891 dc, &context->res_ctx,
892 pipe, hsplit_pipe))
893 goto validate_fail;
894 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
895 dcn20_build_mapped_resource(dc, context, pipe->stream);
896 }
897
898 if (!pipe->plane_state)
899 continue;
900 /* Skip 2nd half of already split pipe */
901 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
902 continue;
903
904 if (split[i] == 2) {
905 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
906 /* pipe not split previously needs split */
907 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
908 ASSERT(hsplit_pipe);
909 if (!hsplit_pipe) {
910 DC_FP_START();
911 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
912 DC_FP_END();
913 continue;
914 }
915 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
916 if (!dcn20_split_stream_for_odm(
917 dc, &context->res_ctx,
918 pipe, hsplit_pipe))
919 goto validate_fail;
920 dcn20_build_mapped_resource(dc, context, pipe->stream);
921 } else {
922 dcn20_split_stream_for_mpc(
923 &context->res_ctx, dc->res_pool,
924 pipe, hsplit_pipe);
925 resource_build_scaling_params(pipe);
926 resource_build_scaling_params(hsplit_pipe);
927 }
928 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
929 }
930 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
931 /* merge should already have been done */
932 ASSERT(0);
933 }
934 }
935 /* Actual dsc count per stream dsc validation*/
936 if (!dcn20_validate_dsc(dc, context)) {
937 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
938 DML_FAIL_DSC_VALIDATION_FAILURE;
939 goto validate_fail;
940 }
941
942 *vlevel_out = vlevel;
943
944 out = true;
945 goto validate_out;
946
947 validate_fail:
948 out = false;
949
950 validate_out:
951 return out;
952 }
953
954 /*
955 * Some of the functions further below use the FPU, so we need to wrap this
956 * with DC_FP_START()/DC_FP_END(). Use the same approach as for
957 * dcn20_validate_bandwidth in dcn20_resource.c.
958 */
dcn21_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)959 static enum dc_status dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
960 enum dc_validate_mode validate_mode)
961 {
962 bool voltage_supported;
963 display_e2e_pipe_params_st *pipes;
964
965 pipes = kzalloc_objs(display_e2e_pipe_params_st,
966 dc->res_pool->pipe_count);
967 if (!pipes)
968 return DC_FAIL_BANDWIDTH_VALIDATE;
969
970 DC_FP_START();
971 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, validate_mode, pipes);
972 DC_FP_END();
973
974 kfree(pipes);
975 return voltage_supported ? DC_OK : DC_NOT_SUPPORTED;
976 }
977
dcn21_destroy_resource_pool(struct resource_pool ** pool)978 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
979 {
980 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
981
982 dcn21_resource_destruct(dcn21_pool);
983 kfree(dcn21_pool);
984 *pool = NULL;
985 }
986
dcn21_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)987 static struct clock_source *dcn21_clock_source_create(
988 struct dc_context *ctx,
989 struct dc_bios *bios,
990 enum clock_source_id id,
991 const struct dce110_clk_src_regs *regs,
992 bool dp_clk_src)
993 {
994 struct dce110_clk_src *clk_src =
995 kzalloc_obj(struct dce110_clk_src);
996
997 if (!clk_src)
998 return NULL;
999
1000 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1001 regs, &cs_shift, &cs_mask)) {
1002 clk_src->base.dp_clk_src = dp_clk_src;
1003 return &clk_src->base;
1004 }
1005
1006 kfree(clk_src);
1007 BREAK_TO_DEBUGGER();
1008 return NULL;
1009 }
1010
dcn21_hubp_create(struct dc_context * ctx,uint32_t inst)1011 static struct hubp *dcn21_hubp_create(
1012 struct dc_context *ctx,
1013 uint32_t inst)
1014 {
1015 struct dcn21_hubp *hubp21 =
1016 kzalloc_obj(struct dcn21_hubp);
1017
1018 if (!hubp21)
1019 return NULL;
1020
1021 if (hubp21_construct(hubp21, ctx, inst,
1022 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1023 return &hubp21->base;
1024
1025 BREAK_TO_DEBUGGER();
1026 kfree(hubp21);
1027 return NULL;
1028 }
1029
dcn21_hubbub_create(struct dc_context * ctx)1030 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1031 {
1032 int i;
1033
1034 struct dcn20_hubbub *hubbub = kzalloc_obj(struct dcn20_hubbub);
1035
1036 if (!hubbub)
1037 return NULL;
1038
1039 hubbub21_construct(hubbub, ctx,
1040 &hubbub_reg,
1041 &hubbub_shift,
1042 &hubbub_mask);
1043
1044 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1045 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1046
1047 vmid->ctx = ctx;
1048
1049 vmid->regs = &vmid_regs[i];
1050 vmid->shifts = &vmid_shifts;
1051 vmid->masks = &vmid_masks;
1052 }
1053 hubbub->num_vmid = res_cap_rn.num_vmid;
1054
1055 return &hubbub->base;
1056 }
1057
dcn21_opp_create(struct dc_context * ctx,uint32_t inst)1058 static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx,
1059 uint32_t inst)
1060 {
1061 struct dcn20_opp *opp =
1062 kzalloc_obj(struct dcn20_opp);
1063
1064 if (!opp) {
1065 BREAK_TO_DEBUGGER();
1066 return NULL;
1067 }
1068
1069 dcn20_opp_construct(opp, ctx, inst,
1070 &opp_regs[inst], &opp_shift, &opp_mask);
1071 return &opp->base;
1072 }
1073
dcn21_timing_generator_create(struct dc_context * ctx,uint32_t instance)1074 static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx,
1075 uint32_t instance)
1076 {
1077 struct optc *tgn10 =
1078 kzalloc_obj(struct optc);
1079
1080 if (!tgn10)
1081 return NULL;
1082
1083 tgn10->base.inst = instance;
1084 tgn10->base.ctx = ctx;
1085
1086 tgn10->tg_regs = &tg_regs[instance];
1087 tgn10->tg_shift = &tg_shift;
1088 tgn10->tg_mask = &tg_mask;
1089
1090 dcn20_timing_generator_init(tgn10);
1091
1092 return &tgn10->base;
1093 }
1094
dcn21_mpc_create(struct dc_context * ctx)1095 static struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1096 {
1097 struct dcn20_mpc *mpc20 = kzalloc_obj(struct dcn20_mpc);
1098
1099 if (!mpc20)
1100 return NULL;
1101
1102 dcn20_mpc_construct(mpc20, ctx,
1103 &mpc_regs,
1104 &mpc_shift,
1105 &mpc_mask,
1106 6);
1107
1108 return &mpc20->base;
1109 }
1110
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1111 static void read_dce_straps(
1112 struct dc_context *ctx,
1113 struct resource_straps *straps)
1114 {
1115 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1116 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1117
1118 }
1119
1120
dcn21_dsc_create(struct dc_context * ctx,uint32_t inst)1121 static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx,
1122 uint32_t inst)
1123 {
1124 struct dcn20_dsc *dsc =
1125 kzalloc_obj(struct dcn20_dsc);
1126
1127 if (!dsc) {
1128 BREAK_TO_DEBUGGER();
1129 return NULL;
1130 }
1131
1132 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1133 return &dsc->base;
1134 }
1135
dcn21_pp_smu_create(struct dc_context * ctx)1136 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1137 {
1138 struct pp_smu_funcs *pp_smu = kzalloc_obj(*pp_smu);
1139
1140 if (!pp_smu)
1141 return pp_smu;
1142
1143 dm_pp_get_funcs(ctx, pp_smu);
1144
1145 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1146 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1147
1148
1149 return pp_smu;
1150 }
1151
dcn21_pp_smu_destroy(struct pp_smu_funcs ** pp_smu)1152 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1153 {
1154 if (pp_smu && *pp_smu) {
1155 kfree(*pp_smu);
1156 *pp_smu = NULL;
1157 }
1158 }
1159
dcn21_create_audio(struct dc_context * ctx,unsigned int inst)1160 static struct audio *dcn21_create_audio(
1161 struct dc_context *ctx, unsigned int inst)
1162 {
1163 return dce_audio_create(ctx, inst,
1164 &audio_regs[inst], &audio_shift, &audio_mask);
1165 }
1166
1167 static struct dc_cap_funcs cap_funcs = {
1168 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1169 };
1170
dcn21_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1171 static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id,
1172 struct dc_context *ctx)
1173 {
1174 struct dcn10_stream_encoder *enc1 =
1175 kzalloc_obj(struct dcn10_stream_encoder);
1176
1177 if (!enc1)
1178 return NULL;
1179
1180 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1181 &stream_enc_regs[eng_id],
1182 &se_shift, &se_mask);
1183
1184 return &enc1->base;
1185 }
1186
1187 static const struct dce_hwseq_registers hwseq_reg = {
1188 HWSEQ_DCN21_REG_LIST()
1189 };
1190
1191 static const struct dce_hwseq_shift hwseq_shift = {
1192 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1193 };
1194
1195 static const struct dce_hwseq_mask hwseq_mask = {
1196 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1197 };
1198
dcn21_hwseq_create(struct dc_context * ctx)1199 static struct dce_hwseq *dcn21_hwseq_create(
1200 struct dc_context *ctx)
1201 {
1202 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1203
1204 if (hws) {
1205 hws->ctx = ctx;
1206 hws->regs = &hwseq_reg;
1207 hws->shifts = &hwseq_shift;
1208 hws->masks = &hwseq_mask;
1209 hws->wa.DEGVIDCN21 = true;
1210 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1211 }
1212 return hws;
1213 }
1214
1215 static const struct resource_create_funcs res_create_funcs = {
1216 .read_dce_straps = read_dce_straps,
1217 .create_audio = dcn21_create_audio,
1218 .create_stream_encoder = dcn21_stream_encoder_create,
1219 .create_hwseq = dcn21_hwseq_create,
1220 };
1221
1222 static const struct encoder_feature_support link_enc_feature = {
1223 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1224 .max_hdmi_pixel_clock = 600000,
1225 .hdmi_ycbcr420_supported = true,
1226 .dp_ycbcr420_supported = true,
1227 .fec_supported = true,
1228 .flags.bits.IS_HBR2_CAPABLE = true,
1229 .flags.bits.IS_HBR3_CAPABLE = true,
1230 .flags.bits.IS_TPS3_CAPABLE = true,
1231 .flags.bits.IS_TPS4_CAPABLE = true
1232 };
1233
1234
1235 #define link_regs(id, phyid)\
1236 [id] = {\
1237 LE_DCN2_REG_LIST(id), \
1238 UNIPHY_DCN2_REG_LIST(phyid), \
1239 DPCS_DCN21_REG_LIST(id), \
1240 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1241 }
1242
1243 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1244 link_regs(0, A),
1245 link_regs(1, B),
1246 link_regs(2, C),
1247 link_regs(3, D),
1248 link_regs(4, E),
1249 };
1250
1251 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1252 { DCN_PANEL_CNTL_REG_LIST() }
1253 };
1254
1255 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1256 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1257 };
1258
1259 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1260 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1261 };
1262
1263 #define aux_regs(id)\
1264 [id] = {\
1265 DCN2_AUX_REG_LIST(id)\
1266 }
1267
1268 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1269 aux_regs(0),
1270 aux_regs(1),
1271 aux_regs(2),
1272 aux_regs(3),
1273 aux_regs(4)
1274 };
1275
1276 #define hpd_regs(id)\
1277 [id] = {\
1278 HPD_REG_LIST(id)\
1279 }
1280
1281 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1282 hpd_regs(0),
1283 hpd_regs(1),
1284 hpd_regs(2),
1285 hpd_regs(3),
1286 hpd_regs(4)
1287 };
1288
1289 static const struct dcn10_link_enc_shift le_shift = {
1290 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1291 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1292 };
1293
1294 static const struct dcn10_link_enc_mask le_mask = {
1295 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1296 DPCS_DCN21_MASK_SH_LIST(_MASK)
1297 };
1298
map_transmitter_id_to_phy_instance(enum transmitter transmitter)1299 static int map_transmitter_id_to_phy_instance(
1300 enum transmitter transmitter)
1301 {
1302 switch (transmitter) {
1303 case TRANSMITTER_UNIPHY_A:
1304 return 0;
1305 break;
1306 case TRANSMITTER_UNIPHY_B:
1307 return 1;
1308 break;
1309 case TRANSMITTER_UNIPHY_C:
1310 return 2;
1311 break;
1312 case TRANSMITTER_UNIPHY_D:
1313 return 3;
1314 break;
1315 case TRANSMITTER_UNIPHY_E:
1316 return 4;
1317 break;
1318 default:
1319 ASSERT(0);
1320 return 0;
1321 }
1322 }
1323
dcn21_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1324 static struct link_encoder *dcn21_link_encoder_create(
1325 struct dc_context *ctx,
1326 const struct encoder_init_data *enc_init_data)
1327 {
1328 (void)ctx;
1329 struct dcn21_link_encoder *enc21 =
1330 kzalloc_obj(struct dcn21_link_encoder);
1331 int link_regs_id;
1332
1333 if (!enc21 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1334 return NULL;
1335
1336 link_regs_id =
1337 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1338
1339 dcn21_link_encoder_construct(enc21,
1340 enc_init_data,
1341 &link_enc_feature,
1342 &link_enc_regs[link_regs_id],
1343 &link_enc_aux_regs[enc_init_data->channel - 1],
1344 &link_enc_hpd_regs[enc_init_data->hpd_source],
1345 &le_shift,
1346 &le_mask);
1347
1348 return &enc21->enc10.base;
1349 }
1350
dcn21_panel_cntl_create(const struct panel_cntl_init_data * init_data)1351 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1352 {
1353 struct dce_panel_cntl *panel_cntl =
1354 kzalloc_obj(struct dce_panel_cntl);
1355
1356 if (!panel_cntl)
1357 return NULL;
1358
1359 dce_panel_cntl_construct(panel_cntl,
1360 init_data,
1361 &panel_cntl_regs[init_data->inst],
1362 &panel_cntl_shift,
1363 &panel_cntl_mask);
1364
1365 return &panel_cntl->base;
1366 }
1367
dcn21_get_panel_config_defaults(struct dc_panel_config * panel_config)1368 static void dcn21_get_panel_config_defaults(struct dc_panel_config *panel_config)
1369 {
1370 *panel_config = panel_config_defaults;
1371 }
1372
1373 #define CTX ctx
1374
1375 #define REG(reg_name) \
1376 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1377
read_pipe_fuses(struct dc_context * ctx)1378 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1379 {
1380 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1381 /* RV1 support max 4 pipes */
1382 value = value & 0xf;
1383 return value;
1384 }
1385
dcn21_patch_unknown_plane_state(struct dc_plane_state * plane_state)1386 static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1387 {
1388 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1389 plane_state->dcc.enable = 1;
1390 /* align to our worst case block width */
1391 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1392 }
1393
1394 return dcn20_patch_unknown_plane_state(plane_state);
1395 }
1396
dcn21_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1397 static void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1398 {
1399 DC_FP_START();
1400 dcn21_update_bw_bounding_box_fpu(dc, bw_params);
1401 DC_FP_END();
1402 }
1403
1404 static const struct resource_funcs dcn21_res_pool_funcs = {
1405 .destroy = dcn21_destroy_resource_pool,
1406 .link_enc_create = dcn21_link_encoder_create,
1407 .panel_cntl_create = dcn21_panel_cntl_create,
1408 .validate_bandwidth = dcn21_validate_bandwidth,
1409 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1410 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1411 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1412 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1413 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1414 .release_pipe = dcn20_release_pipe,
1415 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1416 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1417 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1418 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1419 .update_bw_bounding_box = dcn21_update_bw_bounding_box,
1420 .get_panel_config_defaults = dcn21_get_panel_config_defaults,
1421 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1422 .get_default_tiling_info = dcn10_get_default_tiling_info
1423 };
1424
dcn21_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn21_resource_pool * pool)1425 static bool dcn21_resource_construct(
1426 uint8_t num_virtual_links,
1427 struct dc *dc,
1428 struct dcn21_resource_pool *pool)
1429 {
1430 int i, j;
1431 struct dc_context *ctx = dc->ctx;
1432 struct irq_service_init_data init_data;
1433 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1434 uint32_t num_pipes = 0;
1435
1436 ctx->dc_bios->regs = &bios_regs;
1437
1438 pool->base.res_cap = &res_cap_rn;
1439
1440 pool->base.funcs = &dcn21_res_pool_funcs;
1441
1442 /*************************************************
1443 * Resource + asic cap harcoding *
1444 *************************************************/
1445 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1446
1447 /* max pipe num for ASIC before check pipe fuses */
1448 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1449
1450 dc->caps.max_downscale_ratio = 200;
1451 dc->caps.i2c_speed_in_khz = 100;
1452 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1453 dc->caps.max_cursor_size = 256;
1454 dc->caps.min_horizontal_blanking_period = 80;
1455 dc->caps.dmdata_alloc_size = 2048;
1456
1457 dc->caps.max_slave_planes = 3;
1458 dc->caps.max_slave_yuv_planes = 3;
1459 dc->caps.max_slave_rgb_planes = 3;
1460 dc->caps.post_blend_color_processing = true;
1461 dc->caps.force_dp_tps4_for_cp2520 = true;
1462 dc->caps.extended_aux_timeout_support = true;
1463 dc->caps.dmcub_support = true;
1464 dc->caps.is_apu = true;
1465
1466 /* Color pipeline capabilities */
1467 dc->caps.color.dpp.dcn_arch = 1;
1468 dc->caps.color.dpp.input_lut_shared = 0;
1469 dc->caps.color.dpp.icsc = 1;
1470 dc->caps.color.dpp.dgam_ram = 1;
1471 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1472 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1473 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1474 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1475 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1476 dc->caps.color.dpp.post_csc = 0;
1477 dc->caps.color.dpp.gamma_corr = 0;
1478 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1479
1480 dc->caps.color.dpp.hw_3d_lut = 1;
1481 dc->caps.color.dpp.ogam_ram = 1;
1482 // no OGAM ROM on DCN2
1483 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1484 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1485 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1486 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1487 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1488 dc->caps.color.dpp.ocsc = 0;
1489
1490 dc->caps.color.mpc.gamut_remap = 0;
1491 dc->caps.color.mpc.num_3dluts = 0;
1492 dc->caps.color.mpc.shared_3d_lut = 0;
1493 dc->caps.color.mpc.ogam_ram = 1;
1494 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1495 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1496 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1497 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1498 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1499 dc->caps.color.mpc.ocsc = 1;
1500
1501 dc->caps.dp_hdmi21_pcon_support = true;
1502 dc->check_config = config_defaults;
1503
1504 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1505 dc->debug = debug_defaults_drv;
1506
1507 // Init the vm_helper
1508 if (dc->vm_helper)
1509 vm_helper_init(dc->vm_helper, 16);
1510
1511 /*************************************************
1512 * Create resources *
1513 *************************************************/
1514
1515 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1516 dcn21_clock_source_create(ctx, ctx->dc_bios,
1517 CLOCK_SOURCE_COMBO_PHY_PLL0,
1518 &clk_src_regs[0], false);
1519 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1520 dcn21_clock_source_create(ctx, ctx->dc_bios,
1521 CLOCK_SOURCE_COMBO_PHY_PLL1,
1522 &clk_src_regs[1], false);
1523 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1524 dcn21_clock_source_create(ctx, ctx->dc_bios,
1525 CLOCK_SOURCE_COMBO_PHY_PLL2,
1526 &clk_src_regs[2], false);
1527 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
1528 dcn21_clock_source_create(ctx, ctx->dc_bios,
1529 CLOCK_SOURCE_COMBO_PHY_PLL3,
1530 &clk_src_regs[3], false);
1531 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
1532 dcn21_clock_source_create(ctx, ctx->dc_bios,
1533 CLOCK_SOURCE_COMBO_PHY_PLL4,
1534 &clk_src_regs[4], false);
1535
1536 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1537
1538 /* todo: not reuse phy_pll registers */
1539 pool->base.dp_clock_source =
1540 dcn21_clock_source_create(ctx, ctx->dc_bios,
1541 CLOCK_SOURCE_ID_DP_DTO,
1542 &clk_src_regs[0], true);
1543
1544 for (i = 0; i < pool->base.clk_src_count; i++) {
1545 if (pool->base.clock_sources[i] == NULL) {
1546 dm_error("DC: failed to create clock sources!\n");
1547 BREAK_TO_DEBUGGER();
1548 goto create_fail;
1549 }
1550 }
1551
1552 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1553 if (pool->base.dccg == NULL) {
1554 dm_error("DC: failed to create dccg!\n");
1555 BREAK_TO_DEBUGGER();
1556 goto create_fail;
1557 }
1558
1559 if (!dc->config.disable_dmcu) {
1560 pool->base.dmcu = dcn21_dmcu_create(ctx,
1561 &dmcu_regs,
1562 &dmcu_shift,
1563 &dmcu_mask);
1564 if (pool->base.dmcu == NULL) {
1565 dm_error("DC: failed to create dmcu!\n");
1566 BREAK_TO_DEBUGGER();
1567 goto create_fail;
1568 }
1569
1570 dc->debug.dmub_command_table = false;
1571 }
1572
1573 if (dc->config.disable_dmcu) {
1574 pool->base.psr = dmub_psr_create(ctx);
1575
1576 if (pool->base.psr == NULL) {
1577 dm_error("DC: failed to create psr obj!\n");
1578 BREAK_TO_DEBUGGER();
1579 goto create_fail;
1580 }
1581 }
1582
1583 if (dc->config.disable_dmcu)
1584 pool->base.abm = dmub_abm_create(ctx,
1585 &abm_regs,
1586 &abm_shift,
1587 &abm_mask);
1588 else
1589 pool->base.abm = dce_abm_create(ctx,
1590 &abm_regs,
1591 &abm_shift,
1592 &abm_mask);
1593
1594 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1595
1596 num_pipes = dcn2_1_ip.max_num_dpp;
1597
1598 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1599 if (pipe_fuses & 1 << i)
1600 num_pipes--;
1601 dcn2_1_ip.max_num_dpp = num_pipes;
1602 dcn2_1_ip.max_num_otg = num_pipes;
1603
1604 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1605
1606 init_data.ctx = dc->ctx;
1607 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1608 if (!pool->base.irqs)
1609 goto create_fail;
1610
1611 j = 0;
1612 /* mem input -> ipp -> dpp -> opp -> TG */
1613 for (i = 0; i < pool->base.pipe_count; i++) {
1614 /* if pipe is disabled, skip instance of HW pipe,
1615 * i.e, skip ASIC register instance
1616 */
1617 if ((pipe_fuses & (1 << i)) != 0)
1618 continue;
1619
1620 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1621 if (pool->base.hubps[j] == NULL) {
1622 BREAK_TO_DEBUGGER();
1623 dm_error(
1624 "DC: failed to create memory input!\n");
1625 goto create_fail;
1626 }
1627
1628 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1629 if (pool->base.ipps[j] == NULL) {
1630 BREAK_TO_DEBUGGER();
1631 dm_error(
1632 "DC: failed to create input pixel processor!\n");
1633 goto create_fail;
1634 }
1635
1636 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1637 if (pool->base.dpps[j] == NULL) {
1638 BREAK_TO_DEBUGGER();
1639 dm_error(
1640 "DC: failed to create dpps!\n");
1641 goto create_fail;
1642 }
1643
1644 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1645 if (pool->base.opps[j] == NULL) {
1646 BREAK_TO_DEBUGGER();
1647 dm_error(
1648 "DC: failed to create output pixel processor!\n");
1649 goto create_fail;
1650 }
1651
1652 pool->base.timing_generators[j] = dcn21_timing_generator_create(
1653 ctx, i);
1654 if (pool->base.timing_generators[j] == NULL) {
1655 BREAK_TO_DEBUGGER();
1656 dm_error("DC: failed to create tg!\n");
1657 goto create_fail;
1658 }
1659 j++;
1660 }
1661
1662 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1663 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1664 if (pool->base.engines[i] == NULL) {
1665 BREAK_TO_DEBUGGER();
1666 dm_error(
1667 "DC:failed to create aux engine!!\n");
1668 goto create_fail;
1669 }
1670 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1671 if (pool->base.hw_i2cs[i] == NULL) {
1672 BREAK_TO_DEBUGGER();
1673 dm_error(
1674 "DC:failed to create hw i2c!!\n");
1675 goto create_fail;
1676 }
1677 pool->base.sw_i2cs[i] = NULL;
1678 }
1679
1680 pool->base.timing_generator_count = j;
1681 pool->base.pipe_count = j;
1682 pool->base.mpcc_count = j;
1683
1684 pool->base.mpc = dcn21_mpc_create(ctx);
1685 if (pool->base.mpc == NULL) {
1686 BREAK_TO_DEBUGGER();
1687 dm_error("DC: failed to create mpc!\n");
1688 goto create_fail;
1689 }
1690
1691 pool->base.hubbub = dcn21_hubbub_create(ctx);
1692 if (pool->base.hubbub == NULL) {
1693 BREAK_TO_DEBUGGER();
1694 dm_error("DC: failed to create hubbub!\n");
1695 goto create_fail;
1696 }
1697
1698 /* DIO */
1699 pool->base.dio = dcn21_dio_create(ctx);
1700 if (pool->base.dio == NULL) {
1701 BREAK_TO_DEBUGGER();
1702 dm_error("DC: failed to create dio!\n");
1703 goto create_fail;
1704 }
1705
1706 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1707 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1708 if (pool->base.dscs[i] == NULL) {
1709 BREAK_TO_DEBUGGER();
1710 dm_error("DC: failed to create display stream compressor %d!\n", i);
1711 goto create_fail;
1712 }
1713 }
1714
1715 if (!dcn20_dwbc_create(ctx, &pool->base)) {
1716 BREAK_TO_DEBUGGER();
1717 dm_error("DC: failed to create dwbc!\n");
1718 goto create_fail;
1719 }
1720 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1721 BREAK_TO_DEBUGGER();
1722 dm_error("DC: failed to create mcif_wb!\n");
1723 goto create_fail;
1724 }
1725
1726 if (!resource_construct(num_virtual_links, dc, &pool->base,
1727 &res_create_funcs))
1728 goto create_fail;
1729
1730 dcn21_hw_sequencer_construct(dc);
1731
1732 dc->caps.max_planes = pool->base.pipe_count;
1733
1734 for (i = 0; i < dc->caps.max_planes; ++i)
1735 dc->caps.planes[i] = plane_cap;
1736
1737 dc->caps.max_odm_combine_factor = 2;
1738
1739 dc->cap_funcs = cap_funcs;
1740
1741 return true;
1742
1743 create_fail:
1744
1745 dcn21_resource_destruct(pool);
1746
1747 return false;
1748 }
1749
dcn21_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1750 struct resource_pool *dcn21_create_resource_pool(
1751 const struct dc_init_data *init_data,
1752 struct dc *dc)
1753 {
1754 struct dcn21_resource_pool *pool =
1755 kzalloc_obj(struct dcn21_resource_pool);
1756
1757 if (!pool)
1758 return NULL;
1759
1760 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
1761 return &pool->base;
1762
1763 BREAK_TO_DEBUGGER();
1764 kfree(pool);
1765 return NULL;
1766 }
1767