1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright 2011 Freescale Semiconductor, Inc. 4// Copyright 2011 Linaro Ltd. 5 6#include <dt-bindings/clock/imx6qdl-clock.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 /* 14 * The decompressor and also some bootloaders rely on a 15 * pre-existing /chosen node to be available to insert the 16 * command line and merge other ATAGS info. 17 */ 18 chosen {}; 19 20 aliases { 21 ethernet0 = &fec; 22 can0 = &can1; 23 can1 = &can2; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 gpio4 = &gpio5; 29 gpio5 = &gpio6; 30 gpio6 = &gpio7; 31 i2c0 = &i2c1; 32 i2c1 = &i2c2; 33 i2c2 = &i2c3; 34 ipu0 = &ipu1; 35 mmc0 = &usdhc1; 36 mmc1 = &usdhc2; 37 mmc2 = &usdhc3; 38 mmc3 = &usdhc4; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 spi0 = &ecspi1; 45 spi1 = &ecspi2; 46 spi2 = &ecspi3; 47 spi3 = &ecspi4; 48 usb0 = &usbotg; 49 usb1 = &usbh1; 50 usb2 = &usbh2; 51 usb3 = &usbh3; 52 usbphy0 = &usbphy1; 53 usbphy1 = &usbphy2; 54 }; 55 56 clocks { 57 ckil: ckil { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <32768>; 61 }; 62 63 ckih1: ckih1 { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 67 }; 68 69 osc: osc { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <24000000>; 73 }; 74 75 anaclk1: anaclk1 { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <0>; 79 }; 80 81 anaclk2: anaclk2 { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 }; 86 }; 87 88 ldb: ldb { 89 #address-cells = <1>; 90 #size-cells = <0>; 91 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; 92 gpr = <&gpr>; 93 status = "disabled"; 94 95 lvds-channel@0 { 96 #address-cells = <1>; 97 #size-cells = <0>; 98 reg = <0>; 99 status = "disabled"; 100 101 port@0 { 102 reg = <0>; 103 104 lvds0_mux_0: endpoint { 105 remote-endpoint = <&ipu1_di0_lvds0>; 106 }; 107 }; 108 109 port@1 { 110 reg = <1>; 111 112 lvds0_mux_1: endpoint { 113 remote-endpoint = <&ipu1_di1_lvds0>; 114 }; 115 }; 116 }; 117 118 lvds-channel@1 { 119 #address-cells = <1>; 120 #size-cells = <0>; 121 reg = <1>; 122 status = "disabled"; 123 124 port@0 { 125 reg = <0>; 126 127 lvds1_mux_0: endpoint { 128 remote-endpoint = <&ipu1_di0_lvds1>; 129 }; 130 }; 131 132 port@1 { 133 reg = <1>; 134 135 lvds1_mux_1: endpoint { 136 remote-endpoint = <&ipu1_di1_lvds1>; 137 }; 138 }; 139 }; 140 }; 141 142 pmu: pmu { 143 compatible = "arm,cortex-a9-pmu"; 144 interrupt-parent = <&gpc>; 145 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 146 }; 147 148 usbphynop1: usbphynop1 { 149 compatible = "usb-nop-xceiv"; 150 #phy-cells = <0>; 151 }; 152 153 usbphynop2: usbphynop2 { 154 compatible = "usb-nop-xceiv"; 155 #phy-cells = <0>; 156 }; 157 158 soc: soc { 159 #address-cells = <1>; 160 #size-cells = <1>; 161 compatible = "simple-bus"; 162 interrupt-parent = <&gpc>; 163 ranges; 164 bootph-all; 165 166 dma_apbh: dma-controller@110000 { 167 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 168 reg = <0x00110000 0x2000>; 169 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 170 <0 13 IRQ_TYPE_LEVEL_HIGH>, 171 <0 13 IRQ_TYPE_LEVEL_HIGH>, 172 <0 13 IRQ_TYPE_LEVEL_HIGH>; 173 #dma-cells = <1>; 174 dma-channels = <4>; 175 clocks = <&clks IMX6QDL_CLK_APBH_DMA>; 176 }; 177 178 gpmi: nand-controller@112000 { 179 compatible = "fsl,imx6q-gpmi-nand"; 180 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 181 reg-names = "gpmi-nand", "bch"; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "bch"; 186 clocks = <&clks IMX6QDL_CLK_GPMI_IO>, 187 <&clks IMX6QDL_CLK_GPMI_APB>, 188 <&clks IMX6QDL_CLK_GPMI_BCH>, 189 <&clks IMX6QDL_CLK_GPMI_BCH_APB>, 190 <&clks IMX6QDL_CLK_PER1_BCH>; 191 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 192 "gpmi_bch_apb", "per1_bch"; 193 dmas = <&dma_apbh 0>; 194 dma-names = "rx-tx"; 195 status = "disabled"; 196 }; 197 198 hdmi: hdmi@120000 { 199 reg = <0x00120000 0x9000>; 200 interrupts = <0 115 0x04>; 201 gpr = <&gpr>; 202 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, 203 <&clks IMX6QDL_CLK_HDMI_ISFR>; 204 clock-names = "iahb", "isfr"; 205 status = "disabled"; 206 207 ports { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 211 port@0 { 212 reg = <0>; 213 214 hdmi_mux_0: endpoint { 215 remote-endpoint = <&ipu1_di0_hdmi>; 216 }; 217 }; 218 219 port@1 { 220 reg = <1>; 221 222 hdmi_mux_1: endpoint { 223 remote-endpoint = <&ipu1_di1_hdmi>; 224 }; 225 }; 226 }; 227 }; 228 229 gpu_3d: gpu@130000 { 230 compatible = "vivante,gc"; 231 reg = <0x00130000 0x4000>; 232 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, 234 <&clks IMX6QDL_CLK_GPU3D_CORE>, 235 <&clks IMX6QDL_CLK_GPU3D_SHADER>; 236 clock-names = "bus", "core", "shader"; 237 power-domains = <&pd_pu>; 238 #cooling-cells = <2>; 239 }; 240 241 gpu_2d: gpu@134000 { 242 compatible = "vivante,gc"; 243 reg = <0x00134000 0x4000>; 244 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, 246 <&clks IMX6QDL_CLK_GPU2D_CORE>; 247 clock-names = "bus", "core"; 248 power-domains = <&pd_pu>; 249 #cooling-cells = <2>; 250 }; 251 252 timer@a00600 { 253 compatible = "arm,cortex-a9-twd-timer"; 254 reg = <0x00a00600 0x20>; 255 interrupts = <1 13 0xf01>; 256 interrupt-parent = <&intc>; 257 clocks = <&clks IMX6QDL_CLK_TWD>; 258 }; 259 260 intc: interrupt-controller@a01000 { 261 compatible = "arm,cortex-a9-gic"; 262 #interrupt-cells = <3>; 263 interrupt-controller; 264 reg = <0x00a01000 0x1000>, 265 <0x00a00100 0x100>; 266 interrupt-parent = <&intc>; 267 }; 268 269 L2: cache-controller@a02000 { 270 compatible = "arm,pl310-cache"; 271 reg = <0x00a02000 0x1000>; 272 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 273 cache-unified; 274 cache-level = <2>; 275 arm,tag-latency = <4 2 3>; 276 arm,data-latency = <4 2 3>; 277 arm,shared-override; 278 }; 279 280 pcie: pcie@1ffc000 { 281 compatible = "fsl,imx6q-pcie"; 282 reg = <0x01ffc000 0x04000>, 283 <0x01f00000 0x80000>; 284 reg-names = "dbi", "config"; 285 #address-cells = <3>; 286 #size-cells = <2>; 287 device_type = "pci"; 288 bus-range = <0x00 0xff>; 289 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */ 290 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 291 num-lanes = <1>; 292 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-names = "msi"; 294 #interrupt-cells = <1>; 295 interrupt-map-mask = <0 0 0 0x7>; 296 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 297 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 298 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 299 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 301 <&clks IMX6QDL_CLK_LVDS1_GATE>, 302 <&clks IMX6QDL_CLK_PCIE_REF_125M>; 303 clock-names = "pcie", "pcie_bus", "pcie_phy"; 304 status = "disabled"; 305 }; 306 307 aips1: bus@2000000 { /* AIPS1 */ 308 compatible = "fsl,aips-bus", "simple-bus"; 309 #address-cells = <1>; 310 #size-cells = <1>; 311 reg = <0x02000000 0x100000>; 312 ranges; 313 bootph-pre-ram; 314 315 spba-bus@2000000 { 316 compatible = "fsl,spba-bus", "simple-bus"; 317 #address-cells = <1>; 318 #size-cells = <1>; 319 reg = <0x02000000 0x40000>; 320 ranges; 321 bootph-pre-ram; 322 323 spdif: spdif@2004000 { 324 compatible = "fsl,imx35-spdif"; 325 reg = <0x02004000 0x4000>; 326 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; 327 dmas = <&sdma 14 18 0>, 328 <&sdma 15 18 0>; 329 dma-names = "rx", "tx"; 330 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, 331 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, 332 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, 333 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, 334 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; 335 clock-names = "core", "rxtx0", 336 "rxtx1", "rxtx2", 337 "rxtx3", "rxtx4", 338 "rxtx5", "rxtx6", 339 "rxtx7", "spba"; 340 status = "disabled"; 341 }; 342 343 ecspi1: spi@2008000 { 344 #address-cells = <1>; 345 #size-cells = <0>; 346 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 347 reg = <0x02008000 0x4000>; 348 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&clks IMX6QDL_CLK_ECSPI1>, 350 <&clks IMX6QDL_CLK_ECSPI1>; 351 clock-names = "ipg", "per"; 352 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 353 dma-names = "rx", "tx"; 354 status = "disabled"; 355 }; 356 357 ecspi2: spi@200c000 { 358 #address-cells = <1>; 359 #size-cells = <0>; 360 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 361 reg = <0x0200c000 0x4000>; 362 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&clks IMX6QDL_CLK_ECSPI2>, 364 <&clks IMX6QDL_CLK_ECSPI2>; 365 clock-names = "ipg", "per"; 366 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 367 dma-names = "rx", "tx"; 368 status = "disabled"; 369 }; 370 371 ecspi3: spi@2010000 { 372 #address-cells = <1>; 373 #size-cells = <0>; 374 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 375 reg = <0x02010000 0x4000>; 376 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&clks IMX6QDL_CLK_ECSPI3>, 378 <&clks IMX6QDL_CLK_ECSPI3>; 379 clock-names = "ipg", "per"; 380 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 381 dma-names = "rx", "tx"; 382 status = "disabled"; 383 }; 384 385 ecspi4: spi@2014000 { 386 #address-cells = <1>; 387 #size-cells = <0>; 388 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 389 reg = <0x02014000 0x4000>; 390 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&clks IMX6QDL_CLK_ECSPI4>, 392 <&clks IMX6QDL_CLK_ECSPI4>; 393 clock-names = "ipg", "per"; 394 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 395 dma-names = "rx", "tx"; 396 status = "disabled"; 397 }; 398 399 uart1: serial@2020000 { 400 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 401 reg = <0x02020000 0x4000>; 402 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 404 <&clks IMX6QDL_CLK_UART_SERIAL>; 405 clock-names = "ipg", "per"; 406 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 407 dma-names = "rx", "tx"; 408 status = "disabled"; 409 }; 410 411 esai: esai@2024000 { 412 #sound-dai-cells = <0>; 413 compatible = "fsl,imx35-esai"; 414 reg = <0x02024000 0x4000>; 415 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, 417 <&clks IMX6QDL_CLK_ESAI_EXTAL>, 418 <&clks IMX6QDL_CLK_ESAI_IPG>, 419 <&clks IMX6QDL_CLK_SPBA>; 420 clock-names = "core", "extal", "fsys", "spba"; 421 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; 422 dma-names = "rx", "tx"; 423 status = "disabled"; 424 }; 425 426 ssi1: ssi@2028000 { 427 #sound-dai-cells = <0>; 428 compatible = "fsl,imx6q-ssi", 429 "fsl,imx51-ssi"; 430 reg = <0x02028000 0x4000>; 431 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, 433 <&clks IMX6QDL_CLK_SSI1>; 434 clock-names = "ipg", "baud"; 435 dmas = <&sdma 37 1 0>, 436 <&sdma 38 1 0>; 437 dma-names = "rx", "tx"; 438 fsl,fifo-depth = <15>; 439 status = "disabled"; 440 }; 441 442 ssi2: ssi@202c000 { 443 #sound-dai-cells = <0>; 444 compatible = "fsl,imx6q-ssi", 445 "fsl,imx51-ssi"; 446 reg = <0x0202c000 0x4000>; 447 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, 449 <&clks IMX6QDL_CLK_SSI2>; 450 clock-names = "ipg", "baud"; 451 dmas = <&sdma 41 1 0>, 452 <&sdma 42 1 0>; 453 dma-names = "rx", "tx"; 454 fsl,fifo-depth = <15>; 455 status = "disabled"; 456 }; 457 458 ssi3: ssi@2030000 { 459 #sound-dai-cells = <0>; 460 compatible = "fsl,imx6q-ssi", 461 "fsl,imx51-ssi"; 462 reg = <0x02030000 0x4000>; 463 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, 465 <&clks IMX6QDL_CLK_SSI3>; 466 clock-names = "ipg", "baud"; 467 dmas = <&sdma 45 1 0>, 468 <&sdma 46 1 0>; 469 dma-names = "rx", "tx"; 470 fsl,fifo-depth = <15>; 471 status = "disabled"; 472 }; 473 474 asrc: asrc@2034000 { 475 compatible = "fsl,imx53-asrc"; 476 reg = <0x02034000 0x4000>; 477 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, 479 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, 480 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 481 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 482 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 483 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, 484 <&clks IMX6QDL_CLK_SPBA>; 485 clock-names = "mem", "ipg", "asrck_0", 486 "asrck_1", "asrck_2", "asrck_3", "asrck_4", 487 "asrck_5", "asrck_6", "asrck_7", "asrck_8", 488 "asrck_9", "asrck_a", "asrck_b", "asrck_c", 489 "asrck_d", "asrck_e", "asrck_f", "spba"; 490 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, 491 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; 492 dma-names = "rxa", "rxb", "rxc", 493 "txa", "txb", "txc"; 494 fsl,asrc-rate = <48000>; 495 fsl,asrc-width = <16>; 496 status = "okay"; 497 }; 498 499 spba-bus@203c000 { 500 reg = <0x0203c000 0x4000>; 501 }; 502 }; 503 504 vpu: vpu@2040000 { 505 compatible = "cnm,coda960"; 506 reg = <0x02040000 0x3c000>; 507 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, 508 <0 3 IRQ_TYPE_LEVEL_HIGH>; 509 interrupt-names = "bit", "jpeg"; 510 clocks = <&clks IMX6QDL_CLK_VPU_AXI>, 511 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; 512 clock-names = "per", "ahb"; 513 power-domains = <&pd_pu>; 514 resets = <&src 1>; 515 iram = <&ocram>; 516 }; 517 518 aipstz@207c000 { /* AIPSTZ1 */ 519 reg = <0x0207c000 0x4000>; 520 }; 521 522 pwm1: pwm@2080000 { 523 #pwm-cells = <3>; 524 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 525 reg = <0x02080000 0x4000>; 526 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&clks IMX6QDL_CLK_IPG>, 528 <&clks IMX6QDL_CLK_PWM1>; 529 clock-names = "ipg", "per"; 530 status = "disabled"; 531 }; 532 533 pwm2: pwm@2084000 { 534 #pwm-cells = <3>; 535 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 536 reg = <0x02084000 0x4000>; 537 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&clks IMX6QDL_CLK_IPG>, 539 <&clks IMX6QDL_CLK_PWM2>; 540 clock-names = "ipg", "per"; 541 status = "disabled"; 542 }; 543 544 pwm3: pwm@2088000 { 545 #pwm-cells = <3>; 546 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 547 reg = <0x02088000 0x4000>; 548 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&clks IMX6QDL_CLK_IPG>, 550 <&clks IMX6QDL_CLK_PWM3>; 551 clock-names = "ipg", "per"; 552 status = "disabled"; 553 }; 554 555 pwm4: pwm@208c000 { 556 #pwm-cells = <3>; 557 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 558 reg = <0x0208c000 0x4000>; 559 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&clks IMX6QDL_CLK_IPG>, 561 <&clks IMX6QDL_CLK_PWM4>; 562 clock-names = "ipg", "per"; 563 status = "disabled"; 564 }; 565 566 can1: can@2090000 { 567 compatible = "fsl,imx6q-flexcan"; 568 reg = <0x02090000 0x4000>; 569 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, 571 <&clks IMX6QDL_CLK_CAN1_SERIAL>; 572 clock-names = "ipg", "per"; 573 fsl,stop-mode = <&gpr 0x34 28>; 574 status = "disabled"; 575 }; 576 577 can2: can@2094000 { 578 compatible = "fsl,imx6q-flexcan"; 579 reg = <0x02094000 0x4000>; 580 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, 582 <&clks IMX6QDL_CLK_CAN2_SERIAL>; 583 clock-names = "ipg", "per"; 584 fsl,stop-mode = <&gpr 0x34 29>; 585 status = "disabled"; 586 }; 587 588 gpt: timer@2098000 { 589 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; 590 reg = <0x02098000 0x4000>; 591 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&clks IMX6QDL_CLK_GPT_IPG>, 593 <&clks IMX6QDL_CLK_GPT_IPG_PER>, 594 <&clks IMX6QDL_CLK_GPT_3M>; 595 clock-names = "ipg", "per", "osc_per"; 596 }; 597 598 gpio1: gpio@209c000 { 599 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 600 reg = <0x0209c000 0x4000>; 601 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, 602 <0 67 IRQ_TYPE_LEVEL_HIGH>; 603 gpio-controller; 604 #gpio-cells = <2>; 605 interrupt-controller; 606 #interrupt-cells = <2>; 607 }; 608 609 gpio2: gpio@20a0000 { 610 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 611 reg = <0x020a0000 0x4000>; 612 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, 613 <0 69 IRQ_TYPE_LEVEL_HIGH>; 614 gpio-controller; 615 #gpio-cells = <2>; 616 interrupt-controller; 617 #interrupt-cells = <2>; 618 }; 619 620 gpio3: gpio@20a4000 { 621 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 622 reg = <0x020a4000 0x4000>; 623 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, 624 <0 71 IRQ_TYPE_LEVEL_HIGH>; 625 gpio-controller; 626 #gpio-cells = <2>; 627 interrupt-controller; 628 #interrupt-cells = <2>; 629 }; 630 631 gpio4: gpio@20a8000 { 632 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 633 reg = <0x020a8000 0x4000>; 634 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, 635 <0 73 IRQ_TYPE_LEVEL_HIGH>; 636 gpio-controller; 637 #gpio-cells = <2>; 638 interrupt-controller; 639 #interrupt-cells = <2>; 640 }; 641 642 gpio5: gpio@20ac000 { 643 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 644 reg = <0x020ac000 0x4000>; 645 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, 646 <0 75 IRQ_TYPE_LEVEL_HIGH>; 647 gpio-controller; 648 #gpio-cells = <2>; 649 interrupt-controller; 650 #interrupt-cells = <2>; 651 }; 652 653 gpio6: gpio@20b0000 { 654 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 655 reg = <0x020b0000 0x4000>; 656 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, 657 <0 77 IRQ_TYPE_LEVEL_HIGH>; 658 gpio-controller; 659 #gpio-cells = <2>; 660 interrupt-controller; 661 #interrupt-cells = <2>; 662 }; 663 664 gpio7: gpio@20b4000 { 665 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 666 reg = <0x020b4000 0x4000>; 667 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, 668 <0 79 IRQ_TYPE_LEVEL_HIGH>; 669 gpio-controller; 670 #gpio-cells = <2>; 671 interrupt-controller; 672 #interrupt-cells = <2>; 673 }; 674 675 kpp: keypad@20b8000 { 676 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; 677 reg = <0x020b8000 0x4000>; 678 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&clks IMX6QDL_CLK_IPG>; 680 status = "disabled"; 681 }; 682 683 wdog1: watchdog@20bc000 { 684 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 685 reg = <0x020bc000 0x4000>; 686 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&clks IMX6QDL_CLK_IPG>; 688 }; 689 690 wdog2: watchdog@20c0000 { 691 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 692 reg = <0x020c0000 0x4000>; 693 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&clks IMX6QDL_CLK_IPG>; 695 status = "disabled"; 696 }; 697 698 clks: clock-controller@20c4000 { 699 compatible = "fsl,imx6q-ccm"; 700 reg = <0x020c4000 0x4000>; 701 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, 702 <0 88 IRQ_TYPE_LEVEL_HIGH>; 703 #clock-cells = <1>; 704 }; 705 706 anatop: anatop@20c8000 { 707 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd"; 708 reg = <0x020c8000 0x1000>; 709 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, 710 <0 54 IRQ_TYPE_LEVEL_HIGH>, 711 <0 127 IRQ_TYPE_LEVEL_HIGH>; 712 713 reg_vdd1p1: regulator-1p1 { 714 compatible = "fsl,anatop-regulator"; 715 regulator-name = "vdd1p1"; 716 regulator-min-microvolt = <1000000>; 717 regulator-max-microvolt = <1200000>; 718 regulator-always-on; 719 anatop-reg-offset = <0x110>; 720 anatop-vol-bit-shift = <8>; 721 anatop-vol-bit-width = <5>; 722 anatop-min-bit-val = <4>; 723 anatop-min-voltage = <800000>; 724 anatop-max-voltage = <1375000>; 725 anatop-enable-bit = <0>; 726 }; 727 728 reg_vdd3p0: regulator-3p0 { 729 compatible = "fsl,anatop-regulator"; 730 regulator-name = "vdd3p0"; 731 regulator-min-microvolt = <2625000>; 732 regulator-max-microvolt = <3400000>; 733 regulator-always-on; 734 anatop-reg-offset = <0x120>; 735 anatop-vol-bit-shift = <8>; 736 anatop-vol-bit-width = <5>; 737 anatop-min-bit-val = <0>; 738 anatop-min-voltage = <2625000>; 739 anatop-max-voltage = <3400000>; 740 anatop-enable-bit = <0>; 741 }; 742 743 reg_vdd2p5: regulator-2p5 { 744 compatible = "fsl,anatop-regulator"; 745 regulator-name = "vdd2p5"; 746 regulator-min-microvolt = <2250000>; 747 regulator-max-microvolt = <2750000>; 748 regulator-always-on; 749 anatop-reg-offset = <0x130>; 750 anatop-vol-bit-shift = <8>; 751 anatop-vol-bit-width = <5>; 752 anatop-min-bit-val = <0>; 753 anatop-min-voltage = <2100000>; 754 anatop-max-voltage = <2875000>; 755 anatop-enable-bit = <0>; 756 }; 757 758 reg_arm: regulator-vddcore { 759 compatible = "fsl,anatop-regulator"; 760 regulator-name = "vddarm"; 761 regulator-min-microvolt = <725000>; 762 regulator-max-microvolt = <1450000>; 763 regulator-always-on; 764 anatop-reg-offset = <0x140>; 765 anatop-vol-bit-shift = <0>; 766 anatop-vol-bit-width = <5>; 767 anatop-delay-reg-offset = <0x170>; 768 anatop-delay-bit-shift = <24>; 769 anatop-delay-bit-width = <2>; 770 anatop-min-bit-val = <1>; 771 anatop-min-voltage = <725000>; 772 anatop-max-voltage = <1450000>; 773 }; 774 775 reg_pu: regulator-vddpu { 776 compatible = "fsl,anatop-regulator"; 777 regulator-name = "vddpu"; 778 regulator-min-microvolt = <725000>; 779 regulator-max-microvolt = <1450000>; 780 regulator-enable-ramp-delay = <380>; 781 anatop-reg-offset = <0x140>; 782 anatop-vol-bit-shift = <9>; 783 anatop-vol-bit-width = <5>; 784 anatop-delay-reg-offset = <0x170>; 785 anatop-delay-bit-shift = <26>; 786 anatop-delay-bit-width = <2>; 787 anatop-min-bit-val = <1>; 788 anatop-min-voltage = <725000>; 789 anatop-max-voltage = <1450000>; 790 }; 791 792 reg_soc: regulator-vddsoc { 793 compatible = "fsl,anatop-regulator"; 794 regulator-name = "vddsoc"; 795 regulator-min-microvolt = <725000>; 796 regulator-max-microvolt = <1450000>; 797 regulator-always-on; 798 anatop-reg-offset = <0x140>; 799 anatop-vol-bit-shift = <18>; 800 anatop-vol-bit-width = <5>; 801 anatop-delay-reg-offset = <0x170>; 802 anatop-delay-bit-shift = <28>; 803 anatop-delay-bit-width = <2>; 804 anatop-min-bit-val = <1>; 805 anatop-min-voltage = <725000>; 806 anatop-max-voltage = <1450000>; 807 }; 808 809 tempmon: tempmon { 810 compatible = "fsl,imx6q-tempmon"; 811 interrupt-parent = <&gpc>; 812 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 813 fsl,tempmon = <&anatop>; 814 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 815 nvmem-cell-names = "calib", "temp_grade"; 816 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 817 #thermal-sensor-cells = <0>; 818 }; 819 }; 820 821 usbphy1: usbphy@20c9000 { 822 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 823 reg = <0x020c9000 0x1000>; 824 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&clks IMX6QDL_CLK_USBPHY1>; 826 phy-3p0-supply = <®_vdd3p0>; 827 fsl,anatop = <&anatop>; 828 }; 829 830 usbphy2: usbphy@20ca000 { 831 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 832 reg = <0x020ca000 0x1000>; 833 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&clks IMX6QDL_CLK_USBPHY2>; 835 phy-3p0-supply = <®_vdd3p0>; 836 fsl,anatop = <&anatop>; 837 }; 838 839 snvs: snvs@20cc000 { 840 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 841 reg = <0x020cc000 0x4000>; 842 843 snvs_rtc: snvs-rtc-lp { 844 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 845 regmap = <&snvs>; 846 offset = <0x34>; 847 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 848 <0 20 IRQ_TYPE_LEVEL_HIGH>; 849 }; 850 851 snvs_poweroff: snvs-poweroff { 852 compatible = "syscon-poweroff"; 853 regmap = <&snvs>; 854 offset = <0x38>; 855 value = <0x60>; 856 mask = <0x60>; 857 status = "disabled"; 858 }; 859 860 snvs_pwrkey: snvs-powerkey { 861 compatible = "fsl,sec-v4.0-pwrkey"; 862 regmap = <&snvs>; 863 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 864 linux,keycode = <KEY_POWER>; 865 wakeup-source; 866 status = "disabled"; 867 }; 868 869 snvs_lpgpr: snvs-lpgpr { 870 compatible = "fsl,imx6q-snvs-lpgpr"; 871 }; 872 }; 873 874 epit1: epit@20d0000 { /* EPIT1 */ 875 reg = <0x020d0000 0x4000>; 876 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 877 }; 878 879 epit2: epit@20d4000 { /* EPIT2 */ 880 reg = <0x020d4000 0x4000>; 881 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 882 }; 883 884 src: reset-controller@20d8000 { 885 compatible = "fsl,imx6q-src", "fsl,imx51-src"; 886 reg = <0x020d8000 0x4000>; 887 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, 888 <0 96 IRQ_TYPE_LEVEL_HIGH>; 889 #reset-cells = <1>; 890 }; 891 892 gpc: gpc@20dc000 { 893 compatible = "fsl,imx6q-gpc"; 894 reg = <0x020dc000 0x4000>; 895 #address-cells = <0>; 896 interrupt-controller; 897 #interrupt-cells = <3>; 898 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-parent = <&intc>; 900 clocks = <&clks IMX6QDL_CLK_IPG>; 901 clock-names = "ipg"; 902 903 pgc { 904 #address-cells = <1>; 905 #size-cells = <0>; 906 907 power-domain@0 { 908 reg = <0>; 909 #power-domain-cells = <0>; 910 }; 911 pd_pu: power-domain@1 { 912 reg = <1>; 913 #power-domain-cells = <0>; 914 power-supply = <®_pu>; 915 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, 916 <&clks IMX6QDL_CLK_GPU3D_SHADER>, 917 <&clks IMX6QDL_CLK_GPU2D_CORE>, 918 <&clks IMX6QDL_CLK_GPU2D_AXI>, 919 <&clks IMX6QDL_CLK_OPENVG_AXI>, 920 <&clks IMX6QDL_CLK_VPU_AXI>; 921 }; 922 }; 923 }; 924 925 gpr: iomuxc-gpr@20e0000 { 926 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; 927 reg = <0x20e0000 0x38>; 928 929 mux: mux-controller { 930 compatible = "mmio-mux"; 931 #mux-control-cells = <1>; 932 }; 933 }; 934 935 iomuxc: pinctrl@20e0000 { 936 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; 937 reg = <0x20e0000 0x4000>; 938 bootph-pre-ram; 939 }; 940 941 dcic1: dcic@20e4000 { 942 reg = <0x020e4000 0x4000>; 943 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; 944 }; 945 946 dcic2: dcic@20e8000 { 947 reg = <0x020e8000 0x4000>; 948 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; 949 }; 950 951 sdma: dma-controller@20ec000 { 952 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 953 reg = <0x020ec000 0x4000>; 954 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&clks IMX6QDL_CLK_IPG>, 956 <&clks IMX6QDL_CLK_SDMA>; 957 clock-names = "ipg", "ahb"; 958 #dma-cells = <3>; 959 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 960 }; 961 }; 962 963 aips2: bus@2100000 { /* AIPS2 */ 964 compatible = "fsl,aips-bus", "simple-bus"; 965 #address-cells = <1>; 966 #size-cells = <1>; 967 reg = <0x02100000 0x100000>; 968 ranges; 969 bootph-pre-ram; 970 971 crypto: crypto@2100000 { 972 compatible = "fsl,sec-v4.0"; 973 #address-cells = <1>; 974 #size-cells = <1>; 975 reg = <0x2100000 0x10000>; 976 ranges = <0 0x2100000 0x10000>; 977 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, 978 <&clks IMX6QDL_CLK_CAAM_ACLK>, 979 <&clks IMX6QDL_CLK_CAAM_IPG>, 980 <&clks IMX6QDL_CLK_EIM_SLOW>; 981 clock-names = "mem", "aclk", "ipg", "emi_slow"; 982 983 sec_jr0: jr@1000 { 984 compatible = "fsl,sec-v4.0-job-ring"; 985 reg = <0x1000 0x1000>; 986 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 987 }; 988 989 sec_jr1: jr@2000 { 990 compatible = "fsl,sec-v4.0-job-ring"; 991 reg = <0x2000 0x1000>; 992 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 993 }; 994 }; 995 996 aipstz@217c000 { /* AIPSTZ2 */ 997 reg = <0x0217c000 0x4000>; 998 }; 999 1000 usbotg: usb@2184000 { 1001 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1002 reg = <0x02184000 0x200>; 1003 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1005 fsl,usbphy = <&usbphy1>; 1006 fsl,usbmisc = <&usbmisc 0>; 1007 ahb-burst-config = <0x0>; 1008 tx-burst-size-dword = <0x10>; 1009 rx-burst-size-dword = <0x10>; 1010 status = "disabled"; 1011 }; 1012 1013 usbh1: usb@2184200 { 1014 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1015 reg = <0x02184200 0x200>; 1016 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1018 fsl,usbphy = <&usbphy2>; 1019 fsl,usbmisc = <&usbmisc 1>; 1020 dr_mode = "host"; 1021 ahb-burst-config = <0x0>; 1022 tx-burst-size-dword = <0x10>; 1023 rx-burst-size-dword = <0x10>; 1024 status = "disabled"; 1025 }; 1026 1027 usbh2: usb@2184400 { 1028 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1029 reg = <0x02184400 0x200>; 1030 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1032 fsl,usbphy = <&usbphynop1>; 1033 phy_type = "hsic"; 1034 fsl,usbmisc = <&usbmisc 2>; 1035 dr_mode = "host"; 1036 ahb-burst-config = <0x0>; 1037 tx-burst-size-dword = <0x10>; 1038 rx-burst-size-dword = <0x10>; 1039 status = "disabled"; 1040 }; 1041 1042 usbh3: usb@2184600 { 1043 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1044 reg = <0x02184600 0x200>; 1045 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 1046 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1047 fsl,usbphy = <&usbphynop2>; 1048 phy_type = "hsic"; 1049 fsl,usbmisc = <&usbmisc 3>; 1050 dr_mode = "host"; 1051 ahb-burst-config = <0x0>; 1052 tx-burst-size-dword = <0x10>; 1053 rx-burst-size-dword = <0x10>; 1054 status = "disabled"; 1055 }; 1056 1057 usbmisc: usbmisc@2184800 { 1058 #index-cells = <1>; 1059 compatible = "fsl,imx6q-usbmisc"; 1060 reg = <0x02184800 0x200>; 1061 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1062 }; 1063 1064 fec: ethernet@2188000 { 1065 compatible = "fsl,imx6q-fec"; 1066 reg = <0x02188000 0x4000>; 1067 interrupt-names = "int0", "pps"; 1068 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, 1069 <0 119 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&clks IMX6QDL_CLK_ENET>, 1071 <&clks IMX6QDL_CLK_ENET>, 1072 <&clks IMX6QDL_CLK_ENET_REF>, 1073 <&clks IMX6QDL_CLK_ENET_REF_SEL>; 1074 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; 1075 fsl,stop-mode = <&gpr 0x34 27>; 1076 nvmem-cells = <&fec_mac_addr>; 1077 nvmem-cell-names = "mac-address"; 1078 status = "disabled"; 1079 }; 1080 1081 mlb@218c000 { 1082 reg = <0x0218c000 0x4000>; 1083 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, 1084 <0 117 IRQ_TYPE_LEVEL_HIGH>, 1085 <0 126 IRQ_TYPE_LEVEL_HIGH>; 1086 }; 1087 1088 usdhc1: mmc@2190000 { 1089 compatible = "fsl,imx6q-usdhc"; 1090 reg = <0x02190000 0x4000>; 1091 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&clks IMX6QDL_CLK_USDHC1>, 1093 <&clks IMX6QDL_CLK_USDHC1>, 1094 <&clks IMX6QDL_CLK_USDHC1>; 1095 clock-names = "ipg", "ahb", "per"; 1096 bus-width = <4>; 1097 status = "disabled"; 1098 }; 1099 1100 usdhc2: mmc@2194000 { 1101 compatible = "fsl,imx6q-usdhc"; 1102 reg = <0x02194000 0x4000>; 1103 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&clks IMX6QDL_CLK_USDHC2>, 1105 <&clks IMX6QDL_CLK_USDHC2>, 1106 <&clks IMX6QDL_CLK_USDHC2>; 1107 clock-names = "ipg", "ahb", "per"; 1108 bus-width = <4>; 1109 status = "disabled"; 1110 }; 1111 1112 usdhc3: mmc@2198000 { 1113 compatible = "fsl,imx6q-usdhc"; 1114 reg = <0x02198000 0x4000>; 1115 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&clks IMX6QDL_CLK_USDHC3>, 1117 <&clks IMX6QDL_CLK_USDHC3>, 1118 <&clks IMX6QDL_CLK_USDHC3>; 1119 clock-names = "ipg", "ahb", "per"; 1120 bus-width = <4>; 1121 status = "disabled"; 1122 }; 1123 1124 usdhc4: mmc@219c000 { 1125 compatible = "fsl,imx6q-usdhc"; 1126 reg = <0x0219c000 0x4000>; 1127 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&clks IMX6QDL_CLK_USDHC4>, 1129 <&clks IMX6QDL_CLK_USDHC4>, 1130 <&clks IMX6QDL_CLK_USDHC4>; 1131 clock-names = "ipg", "ahb", "per"; 1132 bus-width = <4>; 1133 status = "disabled"; 1134 }; 1135 1136 i2c1: i2c@21a0000 { 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1140 reg = <0x021a0000 0x4000>; 1141 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&clks IMX6QDL_CLK_I2C1>; 1143 status = "disabled"; 1144 }; 1145 1146 i2c2: i2c@21a4000 { 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1150 reg = <0x021a4000 0x4000>; 1151 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&clks IMX6QDL_CLK_I2C2>; 1153 status = "disabled"; 1154 }; 1155 1156 i2c3: i2c@21a8000 { 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1160 reg = <0x021a8000 0x4000>; 1161 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&clks IMX6QDL_CLK_I2C3>; 1163 status = "disabled"; 1164 }; 1165 1166 romcp@21ac000 { 1167 reg = <0x021ac000 0x4000>; 1168 }; 1169 1170 mmdc0: memory-controller@21b0000 { /* MMDC0 */ 1171 compatible = "fsl,imx6q-mmdc"; 1172 reg = <0x021b0000 0x4000>; 1173 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; 1174 }; 1175 1176 mmdc1: memory-controller@21b4000 { /* MMDC1 */ 1177 compatible = "fsl,imx6q-mmdc"; 1178 reg = <0x021b4000 0x4000>; 1179 status = "disabled"; 1180 }; 1181 1182 weim: memory-controller@21b8000 { 1183 #address-cells = <2>; 1184 #size-cells = <1>; 1185 compatible = "fsl,imx6q-weim"; 1186 reg = <0x021b8000 0x4000>; 1187 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; 1189 fsl,weim-cs-gpr = <&gpr>; 1190 status = "disabled"; 1191 }; 1192 1193 ocotp: efuse@21bc000 { 1194 compatible = "fsl,imx6q-ocotp", "syscon"; 1195 reg = <0x021bc000 0x4000>; 1196 clocks = <&clks IMX6QDL_CLK_IIM>; 1197 #address-cells = <1>; 1198 #size-cells = <1>; 1199 1200 cpu_speed_grade: speed-grade@10 { 1201 reg = <0x10 4>; 1202 }; 1203 1204 tempmon_calib: calib@38 { 1205 reg = <0x38 4>; 1206 }; 1207 1208 tempmon_temp_grade: temp-grade@20 { 1209 reg = <0x20 4>; 1210 }; 1211 1212 fec_mac_addr: mac-addr@88 { 1213 reg = <0x88 6>; 1214 }; 1215 }; 1216 1217 tzasc@21d0000 { /* TZASC1 */ 1218 reg = <0x021d0000 0x4000>; 1219 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 1220 }; 1221 1222 tzasc@21d4000 { /* TZASC2 */ 1223 reg = <0x021d4000 0x4000>; 1224 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 1225 }; 1226 1227 audmux: audmux@21d8000 { 1228 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; 1229 reg = <0x021d8000 0x4000>; 1230 status = "disabled"; 1231 }; 1232 1233 mipi_csi: mipi@21dc000 { 1234 compatible = "fsl,imx6-mipi-csi2"; 1235 reg = <0x021dc000 0x4000>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 interrupts = <0 100 0x04>, <0 101 0x04>; 1239 clocks = <&clks IMX6QDL_CLK_HSI_TX>, 1240 <&clks IMX6QDL_CLK_VIDEO_27M>, 1241 <&clks IMX6QDL_CLK_EIM_PODF>; 1242 clock-names = "dphy", "ref", "pix"; 1243 status = "disabled"; 1244 }; 1245 1246 mipi_dsi: mipi@21e0000 { 1247 reg = <0x021e0000 0x4000>; 1248 status = "disabled"; 1249 1250 ports { 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 1254 port@0 { 1255 reg = <0>; 1256 1257 mipi_mux_0: endpoint { 1258 remote-endpoint = <&ipu1_di0_mipi>; 1259 }; 1260 }; 1261 1262 port@1 { 1263 reg = <1>; 1264 1265 mipi_mux_1: endpoint { 1266 remote-endpoint = <&ipu1_di1_mipi>; 1267 }; 1268 }; 1269 }; 1270 }; 1271 1272 vdoa@21e4000 { 1273 compatible = "fsl,imx6q-vdoa"; 1274 reg = <0x021e4000 0x4000>; 1275 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 1276 clocks = <&clks IMX6QDL_CLK_VDOA>; 1277 }; 1278 1279 uart2: serial@21e8000 { 1280 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1281 reg = <0x021e8000 0x4000>; 1282 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1284 <&clks IMX6QDL_CLK_UART_SERIAL>; 1285 clock-names = "ipg", "per"; 1286 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1287 dma-names = "rx", "tx"; 1288 status = "disabled"; 1289 }; 1290 1291 uart3: serial@21ec000 { 1292 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1293 reg = <0x021ec000 0x4000>; 1294 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 1295 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1296 <&clks IMX6QDL_CLK_UART_SERIAL>; 1297 clock-names = "ipg", "per"; 1298 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1299 dma-names = "rx", "tx"; 1300 status = "disabled"; 1301 }; 1302 1303 uart4: serial@21f0000 { 1304 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1305 reg = <0x021f0000 0x4000>; 1306 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 1307 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1308 <&clks IMX6QDL_CLK_UART_SERIAL>; 1309 clock-names = "ipg", "per"; 1310 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1311 dma-names = "rx", "tx"; 1312 status = "disabled"; 1313 }; 1314 1315 uart5: serial@21f4000 { 1316 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1317 reg = <0x021f4000 0x4000>; 1318 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 1319 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1320 <&clks IMX6QDL_CLK_UART_SERIAL>; 1321 clock-names = "ipg", "per"; 1322 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1323 dma-names = "rx", "tx"; 1324 status = "disabled"; 1325 }; 1326 }; 1327 1328 ipu1: ipu@2400000 { 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 compatible = "fsl,imx6q-ipu"; 1332 reg = <0x02400000 0x400000>; 1333 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, 1334 <0 5 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&clks IMX6QDL_CLK_IPU1>, 1336 <&clks IMX6QDL_CLK_IPU1_DI0>, 1337 <&clks IMX6QDL_CLK_IPU1_DI1>; 1338 clock-names = "bus", "di0", "di1"; 1339 resets = <&src 2>; 1340 bootph-all; 1341 1342 ipu1_csi0: port@0 { 1343 reg = <0>; 1344 1345 ipu1_csi0_from_ipu1_csi0_mux: endpoint { 1346 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>; 1347 }; 1348 }; 1349 1350 ipu1_csi1: port@1 { 1351 reg = <1>; 1352 }; 1353 1354 ipu1_di0: port@2 { 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 reg = <2>; 1358 1359 ipu1_di0_disp0: endpoint@0 { 1360 reg = <0>; 1361 }; 1362 1363 ipu1_di0_hdmi: endpoint@1 { 1364 reg = <1>; 1365 remote-endpoint = <&hdmi_mux_0>; 1366 }; 1367 1368 ipu1_di0_mipi: endpoint@2 { 1369 reg = <2>; 1370 remote-endpoint = <&mipi_mux_0>; 1371 }; 1372 1373 ipu1_di0_lvds0: endpoint@3 { 1374 reg = <3>; 1375 remote-endpoint = <&lvds0_mux_0>; 1376 }; 1377 1378 ipu1_di0_lvds1: endpoint@4 { 1379 reg = <4>; 1380 remote-endpoint = <&lvds1_mux_0>; 1381 }; 1382 }; 1383 1384 ipu1_di1: port@3 { 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 reg = <3>; 1388 1389 ipu1_di1_disp1: endpoint@0 { 1390 reg = <0>; 1391 }; 1392 1393 ipu1_di1_hdmi: endpoint@1 { 1394 reg = <1>; 1395 remote-endpoint = <&hdmi_mux_1>; 1396 }; 1397 1398 ipu1_di1_mipi: endpoint@2 { 1399 reg = <2>; 1400 remote-endpoint = <&mipi_mux_1>; 1401 }; 1402 1403 ipu1_di1_lvds0: endpoint@3 { 1404 reg = <3>; 1405 remote-endpoint = <&lvds0_mux_1>; 1406 }; 1407 1408 ipu1_di1_lvds1: endpoint@4 { 1409 reg = <4>; 1410 remote-endpoint = <&lvds1_mux_1>; 1411 }; 1412 }; 1413 }; 1414 }; 1415}; 1416