| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq()
99 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, in dccg2_set_fifo_errdet_ovr_en()
108 void dccg2_otg_add_pixel(struct dccg *dccg, in dccg2_otg_add_pixel()
120 void dccg2_otg_drop_pixel(struct dccg *dccg, in dccg2_otg_drop_pixel()
132 void dccg2_init(struct dccg *dccg) in dccg2_init()
148 void dccg2_refclk_setup(struct dccg *dccg) in dccg2_refclk_setup()
157 bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg) in dccg2_is_s0i3_golden_init_wa_done()
164 void dccg2_allow_clock_gating(struct dccg *dccg, bool allow) in dccg2_allow_clock_gating()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.c | 34 #define TO_DCN_DCCG(dccg)\ argument
50 struct dccg *dccg) in dccg314_trigger_dio_fifo_resync() argument
60 struct dccg *dccg, in dccg314_get_pixel_rate_div() argument
102 struct dccg *dcc in dccg314_set_pixel_rate_div() argument
150 dccg314_set_dtbclk_p_src(struct dccg * dccg,enum streamclk_source src,uint32_t otg_inst) dccg314_set_dtbclk_p_src() argument
207 dccg314_set_dtbclk_dto(struct dccg * dccg,const struct dtbclk_dto_params * params) dccg314_set_dtbclk_dto() argument
251 dccg314_set_dpstreamclk(struct dccg * dccg,enum streamclk_source src,int otg_inst,int dp_hpo_inst) dccg314_set_dpstreamclk() argument
289 dccg314_init(struct dccg * dccg) dccg314_init() argument
316 dccg314_set_valid_pixel_rate(struct dccg * dccg,int ref_dtbclk_khz,int otg_inst,int pixclk_khz) dccg314_set_valid_pixel_rate() argument
331 dccg314_dpp_root_clock_control(struct dccg * dccg,unsigned int dpp_inst,bool clock_on) dccg314_dpp_root_clock_control() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto()
114 static void dccg21_init(struct dccg *dccg) in dccg21_init()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| H A D | dcn201_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
48 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; dcn20_update_clocks_update_dentist() local
532 dcn20_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg) dcn20_clk_mgr_construct() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 193 struct dccg { struct
214 void (*update_dpp_dto)(struct dccg *dccg, argument
195 funcsdccg global() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/ |
| H A D | dcn301_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/ |
| H A D | dcn30_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 182 struct dccg *dccg) in dcn201_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| H A D | clk_mgr.c | 148 dc_clk_mgr_create(struct dc_context * ctx,struct pp_smu_funcs * pp_smu,struct dccg * dccg) dc_clk_mgr_create() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1206 struct dccg *dccg = dc->res_pool->dccg; dce110_disable_stream() local
1916 struct dccg *dccg = dc->res_pool->dccg; clean_up_dsc_blocks() local
2996 struct clk_mgr *dccg = dc->clk_mgr; dce110_prepare_bandwidth() local
3010 struct clk_mgr *dccg = dc->clk_mgr; dce110_optimize_bandwidth() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 2275 struct dccg *dccg = params->dccg_set_dto_dscclk_params.dccg; hwss_dccg_set_dto_dscclk() local
2896 struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg; hwss_dccg_set_ref_dscclk() local
2966 struct dccg *dccg = params->dccg_update_dpp_dto_params.dccg; hwss_dccg_update_dpp_dto() local
3173 hwss_add_dccg_set_dto_dscclk(struct block_sequence_state * seq_state,struct dccg * dccg,int inst,int num_slices_h) hwss_add_dccg_set_dto_dscclk() argument
3693 hwss_add_dccg_set_ref_dscclk(struct block_sequence_state * seq_state,struct dccg * dccg,int dsc_inst,bool * is_ungated) hwss_add_dccg_set_ref_dscclk() argument
3817 hwss_add_dccg_update_dpp_dto(struct block_sequence_state * seq_state,struct dccg * dccg,int dpp_inst,int dppclk_khz) hwss_add_dccg_update_dpp_dto() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 848 struct dccg *dccg = dc->res_pool->dccg; dcn401_enable_stream() local
3413 struct dccg *dccg = dc->res_pool->dccg; dcn401_post_unlock_reset_opp_sequence() local
3523 struct dccg *dccg = dc->res_pool->dccg; dcn401_update_dchubp_dpp_sequence() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/ |
| H A D | dcn42_clk_mgr.c | 1037 dcn42_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn42 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg) dcn42_clk_mgr_construct() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 676 struct dccg *dccg = dc->res_pool->dccg; link_set_dsc_on_stream() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 3141 } dccg; global() member
|