1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2012 Altera <www.altera.com> 4 */ 5 6#include <dt-bindings/reset/altr,rst-mgr.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 12 aliases { 13 serial0 = &uart0; 14 serial1 = &uart1; 15 timer0 = &timer0; 16 timer1 = &timer1; 17 timer2 = &timer2; 18 timer3 = &timer3; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 enable-method = "altr,socfpga-smp"; 25 26 cpu0: cpu@0 { 27 compatible = "arm,cortex-a9"; 28 device_type = "cpu"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 }; 32 cpu1: cpu@1 { 33 compatible = "arm,cortex-a9"; 34 device_type = "cpu"; 35 reg = <1>; 36 next-level-cache = <&L2>; 37 }; 38 }; 39 40 pmu: pmu@ff111000 { 41 compatible = "arm,cortex-a9-pmu"; 42 interrupt-parent = <&intc>; 43 interrupts = <0 176 4>, <0 177 4>; 44 interrupt-affinity = <&cpu0>, <&cpu1>; 45 reg = <0xff111000 0x1000>, 46 <0xff113000 0x1000>; 47 }; 48 49 intc: interrupt-controller@fffed000 { 50 compatible = "arm,cortex-a9-gic"; 51 #interrupt-cells = <3>; 52 interrupt-controller; 53 reg = <0xfffed000 0x1000>, 54 <0xfffec100 0x100>; 55 }; 56 57 soc { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "simple-bus"; 61 device_type = "soc"; 62 interrupt-parent = <&intc>; 63 ranges; 64 65 amba { 66 compatible = "simple-bus"; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 pdma: pdma@ffe01000 { 72 compatible = "arm,pl330", "arm,primecell"; 73 reg = <0xffe01000 0x1000>; 74 interrupts = <0 104 4>, 75 <0 105 4>, 76 <0 106 4>, 77 <0 107 4>, 78 <0 108 4>, 79 <0 109 4>, 80 <0 110 4>, 81 <0 111 4>; 82 #dma-cells = <1>; 83 clocks = <&l4_main_clk>; 84 clock-names = "apb_pclk"; 85 resets = <&rst DMA_RESET>; 86 reset-names = "dma"; 87 }; 88 }; 89 90 base_fpga_region: fpga-region { 91 compatible = "fpga-region"; 92 fpga-mgr = <&fpgamgr0>; 93 94 #address-cells = <0x1>; 95 #size-cells = <0x1>; 96 ranges; 97 }; 98 99 can0: can@ffc00000 { 100 compatible = "bosch,d_can"; 101 reg = <0xffc00000 0x1000>; 102 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; 103 clocks = <&can0_clk>; 104 resets = <&rst CAN0_RESET>; 105 status = "disabled"; 106 }; 107 108 can1: can@ffc01000 { 109 compatible = "bosch,d_can"; 110 reg = <0xffc01000 0x1000>; 111 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; 112 clocks = <&can1_clk>; 113 resets = <&rst CAN1_RESET>; 114 status = "disabled"; 115 }; 116 117 clkmgr@ffd04000 { 118 compatible = "altr,clk-mgr"; 119 reg = <0xffd04000 0x1000>; 120 121 clocks { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 125 osc1: osc1 { 126 #clock-cells = <0>; 127 compatible = "fixed-clock"; 128 }; 129 130 osc2: osc2 { 131 #clock-cells = <0>; 132 compatible = "fixed-clock"; 133 }; 134 135 f2s_periph_ref_clk: f2s_periph_ref_clk { 136 #clock-cells = <0>; 137 compatible = "fixed-clock"; 138 }; 139 140 f2s_sdram_ref_clk: f2s_sdram_ref_clk { 141 #clock-cells = <0>; 142 compatible = "fixed-clock"; 143 }; 144 145 main_pll: main_pll@40 { 146 #address-cells = <1>; 147 #size-cells = <0>; 148 #clock-cells = <0>; 149 compatible = "altr,socfpga-pll-clock"; 150 clocks = <&osc1>; 151 reg = <0x40>; 152 153 mpuclk: mpuclk@48 { 154 #clock-cells = <0>; 155 compatible = "altr,socfpga-perip-clk"; 156 clocks = <&main_pll>; 157 div-reg = <0xe0 0 9>; 158 reg = <0x48>; 159 }; 160 161 mainclk: mainclk@4c { 162 #clock-cells = <0>; 163 compatible = "altr,socfpga-perip-clk"; 164 clocks = <&main_pll>; 165 div-reg = <0xe4 0 9>; 166 reg = <0x4C>; 167 }; 168 169 dbg_base_clk: dbg_base_clk@50 { 170 #clock-cells = <0>; 171 compatible = "altr,socfpga-perip-clk"; 172 clocks = <&main_pll>, <&osc1>; 173 div-reg = <0xe8 0 9>; 174 reg = <0x50>; 175 }; 176 177 main_qspi_clk: main_qspi_clk@54 { 178 #clock-cells = <0>; 179 compatible = "altr,socfpga-perip-clk"; 180 clocks = <&main_pll>; 181 reg = <0x54>; 182 }; 183 184 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 { 185 #clock-cells = <0>; 186 compatible = "altr,socfpga-perip-clk"; 187 clocks = <&main_pll>; 188 reg = <0x58>; 189 }; 190 191 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c { 192 #clock-cells = <0>; 193 compatible = "altr,socfpga-perip-clk"; 194 clocks = <&main_pll>; 195 reg = <0x5C>; 196 }; 197 }; 198 199 periph_pll: periph_pll@80 { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 #clock-cells = <0>; 203 compatible = "altr,socfpga-pll-clock"; 204 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; 205 reg = <0x80>; 206 207 emac0_clk: emac0_clk@88 { 208 #clock-cells = <0>; 209 compatible = "altr,socfpga-perip-clk"; 210 clocks = <&periph_pll>; 211 reg = <0x88>; 212 }; 213 214 emac1_clk: emac1_clk@8c { 215 #clock-cells = <0>; 216 compatible = "altr,socfpga-perip-clk"; 217 clocks = <&periph_pll>; 218 reg = <0x8C>; 219 }; 220 221 per_qspi_clk: per_qsi_clk@90 { 222 #clock-cells = <0>; 223 compatible = "altr,socfpga-perip-clk"; 224 clocks = <&periph_pll>; 225 reg = <0x90>; 226 }; 227 228 per_nand_mmc_clk: per_nand_mmc_clk@94 { 229 #clock-cells = <0>; 230 compatible = "altr,socfpga-perip-clk"; 231 clocks = <&periph_pll>; 232 reg = <0x94>; 233 }; 234 235 per_base_clk: per_base_clk@98 { 236 #clock-cells = <0>; 237 compatible = "altr,socfpga-perip-clk"; 238 clocks = <&periph_pll>; 239 reg = <0x98>; 240 }; 241 242 h2f_usr1_clk: h2f_usr1_clk@9c { 243 #clock-cells = <0>; 244 compatible = "altr,socfpga-perip-clk"; 245 clocks = <&periph_pll>; 246 reg = <0x9C>; 247 }; 248 }; 249 250 sdram_pll: sdram_pll@c0 { 251 #address-cells = <1>; 252 #size-cells = <0>; 253 #clock-cells = <0>; 254 compatible = "altr,socfpga-pll-clock"; 255 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; 256 reg = <0xC0>; 257 258 ddr_dqs_clk: ddr_dqs_clk@c8 { 259 #clock-cells = <0>; 260 compatible = "altr,socfpga-perip-clk"; 261 clocks = <&sdram_pll>; 262 reg = <0xC8>; 263 }; 264 265 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc { 266 #clock-cells = <0>; 267 compatible = "altr,socfpga-perip-clk"; 268 clocks = <&sdram_pll>; 269 reg = <0xCC>; 270 }; 271 272 ddr_dq_clk: ddr_dq_clk@d0 { 273 #clock-cells = <0>; 274 compatible = "altr,socfpga-perip-clk"; 275 clocks = <&sdram_pll>; 276 reg = <0xD0>; 277 }; 278 279 h2f_usr2_clk: h2f_usr2_clk@d4 { 280 #clock-cells = <0>; 281 compatible = "altr,socfpga-perip-clk"; 282 clocks = <&sdram_pll>; 283 reg = <0xD4>; 284 }; 285 }; 286 287 mpu_periph_clk: mpu_periph_clk { 288 #clock-cells = <0>; 289 compatible = "altr,socfpga-perip-clk"; 290 clocks = <&mpuclk>; 291 fixed-divider = <4>; 292 }; 293 294 mpu_l2_ram_clk: mpu_l2_ram_clk { 295 #clock-cells = <0>; 296 compatible = "altr,socfpga-perip-clk"; 297 clocks = <&mpuclk>; 298 fixed-divider = <2>; 299 }; 300 301 l4_main_clk: l4_main_clk { 302 #clock-cells = <0>; 303 compatible = "altr,socfpga-gate-clk"; 304 clocks = <&mainclk>; 305 clk-gate = <0x60 0>; 306 }; 307 308 l3_main_clk: l3_main_clk { 309 #clock-cells = <0>; 310 compatible = "altr,socfpga-perip-clk"; 311 clocks = <&mainclk>; 312 fixed-divider = <1>; 313 }; 314 315 l3_mp_clk: l3_mp_clk { 316 #clock-cells = <0>; 317 compatible = "altr,socfpga-gate-clk"; 318 clocks = <&mainclk>; 319 div-reg = <0x64 0 2>; 320 clk-gate = <0x60 1>; 321 }; 322 323 l3_sp_clk: l3_sp_clk { 324 #clock-cells = <0>; 325 compatible = "altr,socfpga-gate-clk"; 326 clocks = <&l3_mp_clk>; 327 div-reg = <0x64 2 2>; 328 }; 329 330 l4_mp_clk: l4_mp_clk { 331 #clock-cells = <0>; 332 compatible = "altr,socfpga-gate-clk"; 333 clocks = <&mainclk>, <&per_base_clk>; 334 div-reg = <0x64 4 3>; 335 clk-gate = <0x60 2>; 336 }; 337 338 l4_sp_clk: l4_sp_clk { 339 #clock-cells = <0>; 340 compatible = "altr,socfpga-gate-clk"; 341 clocks = <&mainclk>, <&per_base_clk>; 342 div-reg = <0x64 7 3>; 343 clk-gate = <0x60 3>; 344 }; 345 346 dbg_at_clk: dbg_at_clk { 347 #clock-cells = <0>; 348 compatible = "altr,socfpga-gate-clk"; 349 clocks = <&dbg_base_clk>; 350 div-reg = <0x68 0 2>; 351 clk-gate = <0x60 4>; 352 }; 353 354 dbg_clk: dbg_clk { 355 #clock-cells = <0>; 356 compatible = "altr,socfpga-gate-clk"; 357 clocks = <&dbg_at_clk>; 358 div-reg = <0x68 2 2>; 359 clk-gate = <0x60 5>; 360 }; 361 362 dbg_trace_clk: dbg_trace_clk { 363 #clock-cells = <0>; 364 compatible = "altr,socfpga-gate-clk"; 365 clocks = <&dbg_base_clk>; 366 div-reg = <0x6C 0 3>; 367 clk-gate = <0x60 6>; 368 }; 369 370 dbg_timer_clk: dbg_timer_clk { 371 #clock-cells = <0>; 372 compatible = "altr,socfpga-gate-clk"; 373 clocks = <&dbg_base_clk>; 374 clk-gate = <0x60 7>; 375 }; 376 377 cfg_clk: cfg_clk { 378 #clock-cells = <0>; 379 compatible = "altr,socfpga-gate-clk"; 380 clocks = <&cfg_h2f_usr0_clk>; 381 clk-gate = <0x60 8>; 382 }; 383 384 h2f_user0_clk: h2f_user0_clk { 385 #clock-cells = <0>; 386 compatible = "altr,socfpga-gate-clk"; 387 clocks = <&cfg_h2f_usr0_clk>; 388 clk-gate = <0x60 9>; 389 }; 390 391 emac_0_clk: emac_0_clk { 392 #clock-cells = <0>; 393 compatible = "altr,socfpga-gate-clk"; 394 clocks = <&emac0_clk>; 395 clk-gate = <0xa0 0>; 396 }; 397 398 emac_1_clk: emac_1_clk { 399 #clock-cells = <0>; 400 compatible = "altr,socfpga-gate-clk"; 401 clocks = <&emac1_clk>; 402 clk-gate = <0xa0 1>; 403 }; 404 405 usb_mp_clk: usb_mp_clk { 406 #clock-cells = <0>; 407 compatible = "altr,socfpga-gate-clk"; 408 clocks = <&per_base_clk>; 409 clk-gate = <0xa0 2>; 410 div-reg = <0xa4 0 3>; 411 }; 412 413 spi_m_clk: spi_m_clk { 414 #clock-cells = <0>; 415 compatible = "altr,socfpga-gate-clk"; 416 clocks = <&per_base_clk>; 417 clk-gate = <0xa0 3>; 418 div-reg = <0xa4 3 3>; 419 }; 420 421 can0_clk: can0_clk { 422 #clock-cells = <0>; 423 compatible = "altr,socfpga-gate-clk"; 424 clocks = <&per_base_clk>; 425 clk-gate = <0xa0 4>; 426 div-reg = <0xa4 6 3>; 427 }; 428 429 can1_clk: can1_clk { 430 #clock-cells = <0>; 431 compatible = "altr,socfpga-gate-clk"; 432 clocks = <&per_base_clk>; 433 clk-gate = <0xa0 5>; 434 div-reg = <0xa4 9 3>; 435 }; 436 437 gpio_db_clk: gpio_db_clk { 438 #clock-cells = <0>; 439 compatible = "altr,socfpga-gate-clk"; 440 clocks = <&per_base_clk>; 441 clk-gate = <0xa0 6>; 442 div-reg = <0xa8 0 24>; 443 }; 444 445 h2f_user1_clk: h2f_user1_clk { 446 #clock-cells = <0>; 447 compatible = "altr,socfpga-gate-clk"; 448 clocks = <&h2f_usr1_clk>; 449 clk-gate = <0xa0 7>; 450 }; 451 452 sdmmc_clk: sdmmc_clk { 453 #clock-cells = <0>; 454 compatible = "altr,socfpga-gate-clk"; 455 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 456 clk-gate = <0xa0 8>; 457 }; 458 459 sdmmc_clk_divided: sdmmc_clk_divided { 460 #clock-cells = <0>; 461 compatible = "altr,socfpga-gate-clk"; 462 clocks = <&sdmmc_clk>; 463 clk-gate = <0xa0 8>; 464 fixed-divider = <4>; 465 }; 466 467 nand_x_clk: nand_x_clk { 468 #clock-cells = <0>; 469 compatible = "altr,socfpga-gate-clk"; 470 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 471 clk-gate = <0xa0 9>; 472 }; 473 474 nand_ecc_clk: nand_ecc_clk { 475 #clock-cells = <0>; 476 compatible = "altr,socfpga-gate-clk"; 477 clocks = <&nand_x_clk>; 478 clk-gate = <0xa0 9>; 479 }; 480 481 nand_clk: nand_clk { 482 #clock-cells = <0>; 483 compatible = "altr,socfpga-gate-clk"; 484 clocks = <&nand_x_clk>; 485 clk-gate = <0xa0 10>; 486 fixed-divider = <4>; 487 }; 488 489 qspi_clk: qspi_clk { 490 #clock-cells = <0>; 491 compatible = "altr,socfpga-gate-clk"; 492 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; 493 clk-gate = <0xa0 11>; 494 }; 495 496 ddr_dqs_clk_gate: ddr_dqs_clk_gate { 497 #clock-cells = <0>; 498 compatible = "altr,socfpga-gate-clk"; 499 clocks = <&ddr_dqs_clk>; 500 clk-gate = <0xd8 0>; 501 }; 502 503 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { 504 #clock-cells = <0>; 505 compatible = "altr,socfpga-gate-clk"; 506 clocks = <&ddr_2x_dqs_clk>; 507 clk-gate = <0xd8 1>; 508 }; 509 510 ddr_dq_clk_gate: ddr_dq_clk_gate { 511 #clock-cells = <0>; 512 compatible = "altr,socfpga-gate-clk"; 513 clocks = <&ddr_dq_clk>; 514 clk-gate = <0xd8 2>; 515 }; 516 517 h2f_user2_clk: h2f_user2_clk { 518 #clock-cells = <0>; 519 compatible = "altr,socfpga-gate-clk"; 520 clocks = <&h2f_usr2_clk>; 521 clk-gate = <0xd8 3>; 522 }; 523 524 }; 525 }; 526 527 fpga_bridge0: fpga_bridge@ff400000 { 528 compatible = "altr,socfpga-lwhps2fpga-bridge"; 529 reg = <0xff400000 0x100000>; 530 resets = <&rst LWHPS2FPGA_RESET>; 531 clocks = <&l4_main_clk>; 532 status = "disabled"; 533 }; 534 535 fpga_bridge1: fpga_bridge@ff500000 { 536 compatible = "altr,socfpga-hps2fpga-bridge"; 537 reg = <0xff500000 0x10000>; 538 resets = <&rst HPS2FPGA_RESET>; 539 clocks = <&l4_main_clk>; 540 status = "disabled"; 541 }; 542 543 fpga_bridge2: fpga-bridge@ff600000 { 544 compatible = "altr,socfpga-fpga2hps-bridge"; 545 reg = <0xff600000 0x100000>; 546 resets = <&rst FPGA2HPS_RESET>; 547 clocks = <&l4_main_clk>; 548 status = "disabled"; 549 }; 550 551 fpga_bridge3: fpga-bridge@ffc25080 { 552 compatible = "altr,socfpga-fpga2sdram-bridge"; 553 reg = <0xffc25080 0x4>; 554 status = "disabled"; 555 }; 556 557 fpgamgr0: fpgamgr@ff706000 { 558 compatible = "altr,socfpga-fpga-mgr"; 559 reg = <0xff706000 0x1000 560 0xffb90000 0x4>; 561 interrupts = <0 175 4>; 562 }; 563 564 socfpga_axi_setup: stmmac-axi-config { 565 snps,wr_osr_lmt = <0xf>; 566 snps,rd_osr_lmt = <0xf>; 567 snps,blen = <0 0 0 0 16 0 0>; 568 }; 569 570 gmac0: ethernet@ff700000 { 571 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 572 altr,sysmgr-syscon = <&sysmgr 0x60 0>; 573 reg = <0xff700000 0x2000>; 574 interrupts = <0 115 4>; 575 interrupt-names = "macirq"; 576 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 577 clocks = <&emac_0_clk>; 578 clock-names = "stmmaceth"; 579 resets = <&rst EMAC0_RESET>; 580 reset-names = "stmmaceth"; 581 snps,multicast-filter-bins = <256>; 582 snps,perfect-filter-entries = <128>; 583 tx-fifo-depth = <4096>; 584 rx-fifo-depth = <4096>; 585 snps,axi-config = <&socfpga_axi_setup>; 586 status = "disabled"; 587 }; 588 589 gmac1: ethernet@ff702000 { 590 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 591 altr,sysmgr-syscon = <&sysmgr 0x60 2>; 592 reg = <0xff702000 0x2000>; 593 interrupts = <0 120 4>; 594 interrupt-names = "macirq"; 595 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 596 clocks = <&emac_1_clk>; 597 clock-names = "stmmaceth"; 598 resets = <&rst EMAC1_RESET>; 599 reset-names = "stmmaceth"; 600 snps,multicast-filter-bins = <256>; 601 snps,perfect-filter-entries = <128>; 602 tx-fifo-depth = <4096>; 603 rx-fifo-depth = <4096>; 604 snps,axi-config = <&socfpga_axi_setup>; 605 status = "disabled"; 606 }; 607 608 gpio0: gpio@ff708000 { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 compatible = "snps,dw-apb-gpio"; 612 reg = <0xff708000 0x1000>; 613 clocks = <&l4_mp_clk>; 614 resets = <&rst GPIO0_RESET>; 615 status = "disabled"; 616 617 porta: gpio-controller@0 { 618 compatible = "snps,dw-apb-gpio-port"; 619 gpio-controller; 620 #gpio-cells = <2>; 621 snps,nr-gpios = <29>; 622 reg = <0>; 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 interrupts = <0 164 4>; 626 }; 627 }; 628 629 gpio1: gpio@ff709000 { 630 #address-cells = <1>; 631 #size-cells = <0>; 632 compatible = "snps,dw-apb-gpio"; 633 reg = <0xff709000 0x1000>; 634 clocks = <&l4_mp_clk>; 635 resets = <&rst GPIO1_RESET>; 636 status = "disabled"; 637 638 portb: gpio-controller@0 { 639 compatible = "snps,dw-apb-gpio-port"; 640 gpio-controller; 641 #gpio-cells = <2>; 642 snps,nr-gpios = <29>; 643 reg = <0>; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 interrupts = <0 165 4>; 647 }; 648 }; 649 650 gpio2: gpio@ff70a000 { 651 #address-cells = <1>; 652 #size-cells = <0>; 653 compatible = "snps,dw-apb-gpio"; 654 reg = <0xff70a000 0x1000>; 655 clocks = <&l4_mp_clk>; 656 resets = <&rst GPIO2_RESET>; 657 status = "disabled"; 658 659 portc: gpio-controller@0 { 660 compatible = "snps,dw-apb-gpio-port"; 661 gpio-controller; 662 #gpio-cells = <2>; 663 snps,nr-gpios = <27>; 664 reg = <0>; 665 interrupt-controller; 666 #interrupt-cells = <2>; 667 interrupts = <0 166 4>; 668 }; 669 }; 670 671 i2c0: i2c@ffc04000 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 compatible = "snps,designware-i2c"; 675 reg = <0xffc04000 0x1000>; 676 resets = <&rst I2C0_RESET>; 677 clocks = <&l4_sp_clk>; 678 interrupts = <0 158 0x4>; 679 status = "disabled"; 680 }; 681 682 i2c1: i2c@ffc05000 { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 compatible = "snps,designware-i2c"; 686 reg = <0xffc05000 0x1000>; 687 resets = <&rst I2C1_RESET>; 688 clocks = <&l4_sp_clk>; 689 interrupts = <0 159 0x4>; 690 status = "disabled"; 691 }; 692 693 i2c2: i2c@ffc06000 { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 compatible = "snps,designware-i2c"; 697 reg = <0xffc06000 0x1000>; 698 resets = <&rst I2C2_RESET>; 699 clocks = <&l4_sp_clk>; 700 interrupts = <0 160 0x4>; 701 status = "disabled"; 702 }; 703 704 i2c3: i2c@ffc07000 { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 compatible = "snps,designware-i2c"; 708 reg = <0xffc07000 0x1000>; 709 resets = <&rst I2C3_RESET>; 710 clocks = <&l4_sp_clk>; 711 interrupts = <0 161 0x4>; 712 status = "disabled"; 713 }; 714 715 eccmgr: eccmgr { 716 compatible = "altr,socfpga-ecc-manager"; 717 #address-cells = <1>; 718 #size-cells = <1>; 719 ranges; 720 721 l2-ecc@ffd08140 { 722 compatible = "altr,socfpga-l2-ecc"; 723 reg = <0xffd08140 0x4>; 724 interrupts = <0 36 1>, <0 37 1>; 725 }; 726 727 ocram-ecc@ffd08144 { 728 compatible = "altr,socfpga-ocram-ecc"; 729 reg = <0xffd08144 0x4>; 730 iram = <&ocram>; 731 interrupts = <0 178 1>, <0 179 1>; 732 }; 733 }; 734 735 L2: cache-controller@fffef000 { 736 compatible = "arm,pl310-cache"; 737 reg = <0xfffef000 0x1000>; 738 interrupts = <0 38 0x04>; 739 cache-unified; 740 cache-level = <2>; 741 arm,tag-latency = <1 1 1>; 742 arm,data-latency = <2 1 1>; 743 prefetch-data = <1>; 744 prefetch-instr = <1>; 745 arm,shared-override; 746 arm,double-linefill = <1>; 747 arm,double-linefill-incr = <0>; 748 arm,double-linefill-wrap = <1>; 749 arm,prefetch-drop = <0>; 750 arm,prefetch-offset = <7>; 751 }; 752 753 l3regs@ff800000 { 754 compatible = "altr,l3regs", "syscon"; 755 reg = <0xff800000 0x1000>; 756 }; 757 758 mmc: mmc@ff704000 { 759 compatible = "altr,socfpga-dw-mshc"; 760 reg = <0xff704000 0x1000>; 761 interrupts = <0 139 4>; 762 fifo-depth = <0x400>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; 766 clock-names = "biu", "ciu"; 767 resets = <&rst SDMMC_RESET>; 768 altr,sysmgr-syscon = <&sysmgr 0x108 3>; 769 status = "disabled"; 770 }; 771 772 nand0: nand-controller@ff900000 { 773 #address-cells = <0x1>; 774 #size-cells = <0x0>; 775 compatible = "altr,socfpga-denali-nand"; 776 reg = <0xff900000 0x100000>, 777 <0xffb80000 0x10000>; 778 reg-names = "nand_data", "denali_reg"; 779 interrupts = <0x0 0x90 0x4>; 780 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; 781 clock-names = "nand", "nand_x", "ecc"; 782 resets = <&rst NAND_RESET>; 783 status = "disabled"; 784 }; 785 786 ocram: sram@ffff0000 { 787 compatible = "mmio-sram"; 788 reg = <0xffff0000 0x10000>; 789 #address-cells = <0x1>; 790 #size-cells = <0x1>; 791 ranges; 792 }; 793 794 qspi: spi@ff705000 { 795 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 reg = <0xff705000 0x1000>, 799 <0xffa00000 0x1000>; 800 interrupts = <0 151 4>; 801 cdns,fifo-depth = <128>; 802 cdns,fifo-width = <4>; 803 cdns,trigger-address = <0x00000000>; 804 clocks = <&qspi_clk>; 805 resets = <&rst QSPI_RESET>; 806 status = "disabled"; 807 }; 808 809 rst: rstmgr@ffd05000 { 810 #reset-cells = <1>; 811 compatible = "altr,rst-mgr"; 812 reg = <0xffd05000 0x1000>; 813 altr,modrst-offset = <0x10>; 814 }; 815 816 scu: snoop-control-unit@fffec000 { 817 compatible = "arm,cortex-a9-scu"; 818 reg = <0xfffec000 0x100>; 819 }; 820 821 sdr: sdr@ffc25000 { 822 compatible = "altr,sdr-ctl", "syscon"; 823 reg = <0xffc25000 0x1000>; 824 resets = <&rst SDR_RESET>; 825 }; 826 827 sdramedac { 828 compatible = "altr,sdram-edac"; 829 altr,sdr-syscon = <&sdr>; 830 interrupts = <0 39 4>; 831 }; 832 833 spi0: spi@fff00000 { 834 compatible = "snps,dw-apb-ssi"; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 reg = <0xfff00000 0x1000>; 838 interrupts = <0 154 4>; 839 num-cs = <4>; 840 clocks = <&spi_m_clk>; 841 resets = <&rst SPIM0_RESET>; 842 reset-names = "spi"; 843 status = "disabled"; 844 }; 845 846 spi1: spi@fff01000 { 847 compatible = "snps,dw-apb-ssi"; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 reg = <0xfff01000 0x1000>; 851 interrupts = <0 155 4>; 852 num-cs = <4>; 853 clocks = <&spi_m_clk>; 854 resets = <&rst SPIM1_RESET>; 855 reset-names = "spi"; 856 status = "disabled"; 857 }; 858 859 sysmgr: sysmgr@ffd08000 { 860 compatible = "altr,sys-mgr", "syscon"; 861 reg = <0xffd08000 0x4000>; 862 }; 863 864 /* Local timer */ 865 timer@fffec600 { 866 compatible = "arm,cortex-a9-twd-timer"; 867 reg = <0xfffec600 0x100>; 868 interrupts = <1 13 0xf01>; 869 clocks = <&mpu_periph_clk>; 870 }; 871 872 timer0: timer0@ffc08000 { 873 compatible = "snps,dw-apb-timer"; 874 interrupts = <0 167 4>; 875 reg = <0xffc08000 0x1000>; 876 clocks = <&l4_sp_clk>; 877 clock-names = "timer"; 878 resets = <&rst SPTIMER0_RESET>; 879 reset-names = "timer"; 880 }; 881 882 timer1: timer1@ffc09000 { 883 compatible = "snps,dw-apb-timer"; 884 interrupts = <0 168 4>; 885 reg = <0xffc09000 0x1000>; 886 clocks = <&l4_sp_clk>; 887 clock-names = "timer"; 888 resets = <&rst SPTIMER1_RESET>; 889 reset-names = "timer"; 890 }; 891 892 timer2: timer2@ffd00000 { 893 compatible = "snps,dw-apb-timer"; 894 interrupts = <0 169 4>; 895 reg = <0xffd00000 0x1000>; 896 clocks = <&osc1>; 897 clock-names = "timer"; 898 resets = <&rst OSC1TIMER0_RESET>; 899 reset-names = "timer"; 900 }; 901 902 timer3: timer3@ffd01000 { 903 compatible = "snps,dw-apb-timer"; 904 interrupts = <0 170 4>; 905 reg = <0xffd01000 0x1000>; 906 clocks = <&osc1>; 907 clock-names = "timer"; 908 resets = <&rst OSC1TIMER1_RESET>; 909 reset-names = "timer"; 910 }; 911 912 uart0: serial@ffc02000 { 913 compatible = "snps,dw-apb-uart"; 914 reg = <0xffc02000 0x1000>; 915 interrupts = <0 162 4>; 916 reg-shift = <2>; 917 reg-io-width = <4>; 918 clocks = <&l4_sp_clk>; 919 dmas = <&pdma 28>, 920 <&pdma 29>; 921 dma-names = "tx", "rx"; 922 resets = <&rst UART0_RESET>; 923 }; 924 925 uart1: serial@ffc03000 { 926 compatible = "snps,dw-apb-uart"; 927 reg = <0xffc03000 0x1000>; 928 interrupts = <0 163 4>; 929 reg-shift = <2>; 930 reg-io-width = <4>; 931 clocks = <&l4_sp_clk>; 932 dmas = <&pdma 30>, 933 <&pdma 31>; 934 dma-names = "tx", "rx"; 935 resets = <&rst UART1_RESET>; 936 }; 937 938 usbphy0: usbphy { 939 #phy-cells = <0>; 940 compatible = "usb-nop-xceiv"; 941 status = "okay"; 942 }; 943 944 usb0: usb@ffb00000 { 945 compatible = "snps,dwc2"; 946 reg = <0xffb00000 0xffff>; 947 interrupts = <0 125 4>; 948 clocks = <&usb_mp_clk>; 949 clock-names = "otg"; 950 resets = <&rst USB0_RESET>; 951 reset-names = "dwc2"; 952 phys = <&usbphy0>; 953 phy-names = "usb2-phy"; 954 status = "disabled"; 955 }; 956 957 usb1: usb@ffb40000 { 958 compatible = "snps,dwc2"; 959 reg = <0xffb40000 0xffff>; 960 interrupts = <0 128 4>; 961 clocks = <&usb_mp_clk>; 962 clock-names = "otg"; 963 resets = <&rst USB1_RESET>; 964 reset-names = "dwc2"; 965 phys = <&usbphy0>; 966 phy-names = "usb2-phy"; 967 status = "disabled"; 968 }; 969 970 watchdog0: watchdog@ffd02000 { 971 compatible = "snps,dw-wdt"; 972 reg = <0xffd02000 0x1000>; 973 interrupts = <0 171 4>; 974 clocks = <&osc1>; 975 resets = <&rst L4WD0_RESET>; 976 status = "disabled"; 977 }; 978 979 watchdog1: watchdog@ffd03000 { 980 compatible = "snps,dw-wdt"; 981 reg = <0xffd03000 0x1000>; 982 interrupts = <0 172 4>; 983 clocks = <&osc1>; 984 resets = <&rst L4WD1_RESET>; 985 status = "disabled"; 986 }; 987 }; 988}; 989