1 /*-
2 * Copyright (c) 2015-2016 The FreeBSD Foundation
3 * Copyright (c) 2023 Arm Ltd
4 *
5 * This software was developed by Andrew Turner under
6 * the sponsorship of the FreeBSD Foundation.
7 *
8 * This software was developed by Semihalf under
9 * the sponsorship of the FreeBSD Foundation.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33 #include "opt_acpi.h"
34 #include "opt_platform.h"
35 #include "opt_iommu.h"
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/bus.h>
40 #include <sys/cpuset.h>
41 #include <sys/domainset.h>
42 #include <sys/endian.h>
43 #include <sys/kernel.h>
44 #include <sys/lock.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/physmem.h>
49 #include <sys/proc.h>
50 #include <sys/taskqueue.h>
51 #include <sys/tree.h>
52 #include <sys/queue.h>
53 #include <sys/rman.h>
54 #include <sys/sbuf.h>
55 #include <sys/smp.h>
56 #include <sys/sysctl.h>
57 #include <sys/vmem.h>
58
59 #include <vm/vm.h>
60 #include <vm/pmap.h>
61 #include <vm/vm_page.h>
62
63 #include <machine/bus.h>
64 #include <machine/intr.h>
65
66 #include <arm/arm/gic_common.h>
67 #include <arm64/arm64/gic_v3_reg.h>
68 #include <arm64/arm64/gic_v3_var.h>
69
70 #ifdef FDT
71 #include <dev/ofw/openfirm.h>
72 #include <dev/ofw/ofw_bus.h>
73 #include <dev/ofw/ofw_bus_subr.h>
74 #endif
75 #include <dev/pci/pcireg.h>
76 #include <dev/pci/pcivar.h>
77
78 #ifdef IOMMU
79 #include <dev/iommu/iommu.h>
80 #include <dev/iommu/iommu_gas.h>
81 #endif
82
83 #include "pcib_if.h"
84 #include "pic_if.h"
85 #include "msi_if.h"
86
87 MALLOC_DEFINE(M_GICV3_ITS, "GICv3 ITS",
88 "ARM GICv3 Interrupt Translation Service");
89
90 #define LPI_NIRQS (64 * 1024)
91
92 /* The size and alignment of the command circular buffer */
93 #define ITS_CMDQ_SIZE (64 * 1024) /* Must be a multiple of 4K */
94 #define ITS_CMDQ_ALIGN (64 * 1024)
95
96 #define LPI_CONFTAB_SIZE LPI_NIRQS
97 #define LPI_CONFTAB_ALIGN (64 * 1024)
98 #define LPI_CONFTAB_MAX_ADDR ((1ul << 48) - 1) /* We need a 47 bit PA */
99
100 /* 1 bit per SPI, PPI, and SGI (8k), and 1 bit per LPI (LPI_CONFTAB_SIZE) */
101 #define LPI_PENDTAB_SIZE ((LPI_NIRQS + GIC_FIRST_LPI) / 8)
102 #define LPI_PENDTAB_ALIGN (64 * 1024)
103 #define LPI_PENDTAB_MAX_ADDR ((1ul << 48) - 1) /* We need a 47 bit PA */
104
105 #define LPI_INT_TRANS_TAB_ALIGN 256
106 #define LPI_INT_TRANS_TAB_MAX_ADDR ((1ul << 48) - 1)
107
108 /* ITS commands encoding */
109 #define ITS_CMD_MOVI (0x01)
110 #define ITS_CMD_SYNC (0x05)
111 #define ITS_CMD_MAPD (0x08)
112 #define ITS_CMD_MAPC (0x09)
113 #define ITS_CMD_MAPTI (0x0a)
114 #define ITS_CMD_MAPI (0x0b)
115 #define ITS_CMD_INV (0x0c)
116 #define ITS_CMD_INVALL (0x0d)
117 /* Command */
118 #define CMD_COMMAND_MASK (0xFFUL)
119 /* PCI device ID */
120 #define CMD_DEVID_SHIFT (32)
121 #define CMD_DEVID_MASK (0xFFFFFFFFUL << CMD_DEVID_SHIFT)
122 /* Size of IRQ ID bitfield */
123 #define CMD_SIZE_MASK (0xFFUL)
124 /* Virtual LPI ID */
125 #define CMD_ID_MASK (0xFFFFFFFFUL)
126 /* Physical LPI ID */
127 #define CMD_PID_SHIFT (32)
128 #define CMD_PID_MASK (0xFFFFFFFFUL << CMD_PID_SHIFT)
129 /* Collection */
130 #define CMD_COL_MASK (0xFFFFUL)
131 /* Target (CPU or Re-Distributor) */
132 #define CMD_TARGET_SHIFT (16)
133 #define CMD_TARGET_MASK (0xFFFFFFFFUL << CMD_TARGET_SHIFT)
134 /* Interrupt Translation Table address */
135 #define CMD_ITT_MASK (0xFFFFFFFFFF00UL)
136 /* Valid command bit */
137 #define CMD_VALID_SHIFT (63)
138 #define CMD_VALID_MASK (1UL << CMD_VALID_SHIFT)
139
140 #define ITS_TARGET_NONE 0xFBADBEEF
141
142 /* LPI chunk owned by ITS device */
143 struct lpi_chunk {
144 u_int lpi_base;
145 u_int lpi_free; /* First free LPI in set */
146 u_int lpi_num; /* Total number of LPIs in chunk */
147 u_int lpi_busy; /* Number of busy LPIs in chink */
148 };
149
150 /* ITS device */
151 struct its_dev {
152 TAILQ_ENTRY(its_dev) entry;
153 /* PCI device */
154 device_t pci_dev;
155 /* Device ID (i.e. PCI device ID) */
156 uint32_t devid;
157 /* List of assigned LPIs */
158 struct lpi_chunk lpis;
159 /* Virtual address of ITT */
160 void *itt;
161 };
162
163 /*
164 * ITS command descriptor.
165 * Idea for command description passing taken from Linux.
166 */
167 struct its_cmd_desc {
168 uint8_t cmd_type;
169
170 union {
171 struct {
172 struct its_dev *its_dev;
173 struct its_col *col;
174 uint32_t id;
175 } cmd_desc_movi;
176
177 struct {
178 struct its_col *col;
179 } cmd_desc_sync;
180
181 struct {
182 struct its_col *col;
183 uint8_t valid;
184 } cmd_desc_mapc;
185
186 struct {
187 struct its_dev *its_dev;
188 struct its_col *col;
189 uint32_t pid;
190 uint32_t id;
191 } cmd_desc_mapvi;
192
193 struct {
194 struct its_dev *its_dev;
195 struct its_col *col;
196 uint32_t pid;
197 } cmd_desc_mapi;
198
199 struct {
200 struct its_dev *its_dev;
201 uint8_t valid;
202 } cmd_desc_mapd;
203
204 struct {
205 struct its_dev *its_dev;
206 struct its_col *col;
207 uint32_t pid;
208 } cmd_desc_inv;
209
210 struct {
211 struct its_col *col;
212 } cmd_desc_invall;
213 };
214 };
215
216 /* ITS command. Each command is 32 bytes long */
217 struct its_cmd {
218 uint64_t cmd_dword[4]; /* ITS command double word */
219 };
220
221 /* An ITS private table */
222 struct its_ptable {
223 void *ptab_vaddr;
224 /* Size of the L1 and L2 tables */
225 size_t ptab_l1_size;
226 size_t ptab_l2_size;
227 /* Number of L1 and L2 entries */
228 int ptab_l1_nidents;
229 int ptab_l2_nidents;
230
231 int ptab_page_size;
232 int ptab_share;
233 bool ptab_indirect;
234 };
235
236 /* ITS collection description. */
237 struct its_col {
238 uint64_t col_target; /* Target Re-Distributor */
239 uint64_t col_id; /* Collection ID */
240 };
241
242 struct gicv3_its_irqsrc {
243 struct intr_irqsrc gi_isrc;
244 u_int gi_id;
245 u_int gi_lpi;
246 struct its_dev *gi_its_dev;
247 TAILQ_ENTRY(gicv3_its_irqsrc) gi_link;
248 };
249
250 struct gicv3_its_softc {
251 device_t dev;
252 struct intr_pic *sc_pic;
253 struct resource *sc_its_res;
254
255 cpuset_t sc_cpus;
256 struct domainset *sc_ds;
257 u_int gic_irq_cpu;
258 int sc_devbits;
259 int sc_dev_table_idx;
260
261 struct its_ptable sc_its_ptab[GITS_BASER_NUM];
262 struct its_col *sc_its_cols[MAXCPU]; /* Per-CPU collections */
263
264 /*
265 * TODO: We should get these from the parent as we only want a
266 * single copy of each across the interrupt controller.
267 */
268 uint8_t *sc_conf_base;
269 void *sc_pend_base[MAXCPU];
270
271 /* Command handling */
272 struct mtx sc_its_cmd_lock;
273 struct its_cmd *sc_its_cmd_base; /* Command circular buffer address */
274 size_t sc_its_cmd_next_idx;
275
276 vmem_t *sc_irq_alloc;
277 struct gicv3_its_irqsrc **sc_irqs;
278 u_int sc_irq_base;
279 u_int sc_irq_length;
280 u_int sc_irq_count;
281
282 struct mtx sc_its_dev_lock;
283 TAILQ_HEAD(its_dev_list, its_dev) sc_its_dev_list;
284 TAILQ_HEAD(free_irqs, gicv3_its_irqsrc) sc_free_irqs;
285
286 #define ITS_FLAGS_CMDQ_FLUSH 0x00000001
287 #define ITS_FLAGS_LPI_CONF_FLUSH 0x00000002
288 #define ITS_FLAGS_ERRATA_CAVIUM_22375 0x00000004
289 #define ITS_FLAGS_LPI_PREALLOC 0x00000008
290 #define ITS_FLAGS_FORCE_NOSHAREABLE 0x00000010
291 u_int sc_its_flags;
292 bool trace_enable;
293 vm_page_t ma; /* fake msi page */
294 vm_paddr_t malloc_max_addr; /* max address for contigmalloc */
295 };
296
297 typedef bool (its_quirk_detect_t)(device_t);
298 typedef void (its_quirk_func_t)(device_t);
299
300 static its_quirk_detect_t its_detect_cavium_22375;
301 static its_quirk_func_t its_quirk_cavium_22375;
302 #ifdef FDT
303 static its_quirk_detect_t its_detect_rk356x;
304 static its_quirk_func_t its_quirk_rk356x;
305 static its_quirk_detect_t its_detect_rk3588;
306 static its_quirk_func_t its_quirk_rk3588;
307 #endif
308
309 static const struct {
310 const char *desc;
311 its_quirk_detect_t *detect;
312 its_quirk_func_t *func;
313 } its_quirks[] = {
314 {
315 /* Cavium ThunderX Pass 1.x */
316 .desc = "Cavium ThunderX errata: 22375, 24313",
317 .detect = its_detect_cavium_22375,
318 .func = its_quirk_cavium_22375,
319 },
320 #ifdef FDT
321 {
322 /* Rockchip RK356X implementation bugs */
323 .desc = "RK356X ITS errata",
324 .detect = its_detect_rk356x,
325 .func = its_quirk_rk356x,
326 },
327 {
328 /* Rockchip RK3588 implementation bugs */
329 .desc = "RK3588 ITS errata",
330 .detect = its_detect_rk3588,
331 .func = its_quirk_rk3588,
332 },
333 #endif
334 };
335
336 #define gic_its_read_4(sc, reg) \
337 bus_read_4((sc)->sc_its_res, (reg))
338 #define gic_its_read_8(sc, reg) \
339 bus_read_8((sc)->sc_its_res, (reg))
340
341 #define gic_its_write_4(sc, reg, val) \
342 bus_write_4((sc)->sc_its_res, (reg), (val))
343 #define gic_its_write_8(sc, reg, val) \
344 bus_write_8((sc)->sc_its_res, (reg), (val))
345
346 static device_attach_t gicv3_its_attach;
347 static device_detach_t gicv3_its_detach;
348
349 static pic_disable_intr_t gicv3_its_disable_intr;
350 static pic_enable_intr_t gicv3_its_enable_intr;
351 static pic_map_intr_t gicv3_its_map_intr;
352 static pic_setup_intr_t gicv3_its_setup_intr;
353 static pic_post_filter_t gicv3_its_post_filter;
354 static pic_post_ithread_t gicv3_its_post_ithread;
355 static pic_pre_ithread_t gicv3_its_pre_ithread;
356 static pic_bind_intr_t gicv3_its_bind_intr;
357 #ifdef SMP
358 static pic_init_secondary_t gicv3_its_init_secondary;
359 #endif
360 static msi_alloc_msi_t gicv3_its_alloc_msi;
361 static msi_release_msi_t gicv3_its_release_msi;
362 static msi_alloc_msix_t gicv3_its_alloc_msix;
363 static msi_release_msix_t gicv3_its_release_msix;
364 static msi_map_msi_t gicv3_its_map_msi;
365 #ifdef IOMMU
366 static msi_iommu_init_t gicv3_iommu_init;
367 static msi_iommu_deinit_t gicv3_iommu_deinit;
368 #endif
369
370 static void its_cmd_movi(device_t, struct gicv3_its_irqsrc *);
371 static void its_cmd_mapc(device_t, struct its_col *, uint8_t);
372 static void its_cmd_mapti(device_t, struct gicv3_its_irqsrc *);
373 static void its_cmd_mapd(device_t, struct its_dev *, uint8_t);
374 static void its_cmd_inv(device_t, struct its_dev *, struct gicv3_its_irqsrc *);
375 static void its_cmd_invall(device_t, struct its_col *);
376
377 static device_method_t gicv3_its_methods[] = {
378 /* Device interface */
379 DEVMETHOD(device_detach, gicv3_its_detach),
380
381 /* Interrupt controller interface */
382 DEVMETHOD(pic_disable_intr, gicv3_its_disable_intr),
383 DEVMETHOD(pic_enable_intr, gicv3_its_enable_intr),
384 DEVMETHOD(pic_map_intr, gicv3_its_map_intr),
385 DEVMETHOD(pic_setup_intr, gicv3_its_setup_intr),
386 DEVMETHOD(pic_post_filter, gicv3_its_post_filter),
387 DEVMETHOD(pic_post_ithread, gicv3_its_post_ithread),
388 DEVMETHOD(pic_pre_ithread, gicv3_its_pre_ithread),
389 #ifdef SMP
390 DEVMETHOD(pic_bind_intr, gicv3_its_bind_intr),
391 DEVMETHOD(pic_init_secondary, gicv3_its_init_secondary),
392 #endif
393
394 /* MSI/MSI-X */
395 DEVMETHOD(msi_alloc_msi, gicv3_its_alloc_msi),
396 DEVMETHOD(msi_release_msi, gicv3_its_release_msi),
397 DEVMETHOD(msi_alloc_msix, gicv3_its_alloc_msix),
398 DEVMETHOD(msi_release_msix, gicv3_its_release_msix),
399 DEVMETHOD(msi_map_msi, gicv3_its_map_msi),
400 #ifdef IOMMU
401 DEVMETHOD(msi_iommu_init, gicv3_iommu_init),
402 DEVMETHOD(msi_iommu_deinit, gicv3_iommu_deinit),
403 #endif
404
405 /* End */
406 DEVMETHOD_END
407 };
408
409 static DEFINE_CLASS_0(gic, gicv3_its_driver, gicv3_its_methods,
410 sizeof(struct gicv3_its_softc));
411
412 /* Limit maximum address for memory mapped tables and buffers */
413 static vm_paddr_t
gicv3_its_limit_max_addr(struct gicv3_its_softc * sc,vm_paddr_t addr)414 gicv3_its_limit_max_addr(struct gicv3_its_softc *sc, vm_paddr_t addr)
415 {
416 return (sc->malloc_max_addr > addr ? addr: sc->malloc_max_addr);
417 }
418
419 static void
gicv3_its_cmdq_init(struct gicv3_its_softc * sc)420 gicv3_its_cmdq_init(struct gicv3_its_softc *sc)
421 {
422 vm_paddr_t cmd_paddr;
423 uint64_t reg, tmp;
424
425 /* Set up the command circular buffer */
426 sc->sc_its_cmd_base = contigmalloc_domainset(ITS_CMDQ_SIZE, M_GICV3_ITS,
427 sc->sc_ds, M_WAITOK | M_ZERO, 0,
428 gicv3_its_limit_max_addr(sc, (1ul << 48) - 1), ITS_CMDQ_ALIGN,
429 0);
430 sc->sc_its_cmd_next_idx = 0;
431
432 cmd_paddr = vtophys(sc->sc_its_cmd_base);
433
434 /* Set the base of the command buffer */
435 reg = GITS_CBASER_VALID |
436 (GITS_CBASER_CACHE_NIWAWB << GITS_CBASER_CACHE_SHIFT) |
437 cmd_paddr | (ITS_CMDQ_SIZE / 4096 - 1);
438 if (sc->sc_its_flags & ITS_FLAGS_FORCE_NOSHAREABLE)
439 reg |= GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT;
440 else
441 reg |= GITS_CBASER_SHARE_IS << GITS_CBASER_SHARE_SHIFT;
442 gic_its_write_8(sc, GITS_CBASER, reg);
443
444 /* Read back to check for fixed value fields */
445 tmp = gic_its_read_8(sc, GITS_CBASER);
446
447 if ((tmp & GITS_CBASER_SHARE_MASK) !=
448 (GITS_CBASER_SHARE_IS << GITS_CBASER_SHARE_SHIFT)) {
449 /* Check if the hardware reported non-shareable */
450 if ((tmp & GITS_CBASER_SHARE_MASK) ==
451 (GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT)) {
452 /* If so remove the cache attribute */
453 reg &= ~GITS_CBASER_CACHE_MASK;
454 reg &= ~GITS_CBASER_SHARE_MASK;
455 /* Set to Non-cacheable, Non-shareable */
456 reg |= GITS_CBASER_CACHE_NIN << GITS_CBASER_CACHE_SHIFT;
457 reg |= GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT;
458
459 gic_its_write_8(sc, GITS_CBASER, reg);
460 }
461
462 /* The command queue has to be flushed after each command */
463 sc->sc_its_flags |= ITS_FLAGS_CMDQ_FLUSH;
464 }
465
466 /* Get the next command from the start of the buffer */
467 gic_its_write_8(sc, GITS_CWRITER, 0x0);
468 }
469
470 static int
gicv3_its_table_page_size(struct gicv3_its_softc * sc,int table)471 gicv3_its_table_page_size(struct gicv3_its_softc *sc, int table)
472 {
473 uint64_t reg, tmp;
474 int page_size;
475
476 page_size = PAGE_SIZE_64K;
477 reg = gic_its_read_8(sc, GITS_BASER(table));
478
479 while (1) {
480 reg &= ~GITS_BASER_PSZ_MASK;
481 switch (page_size) {
482 case PAGE_SIZE_4K: /* 4KB */
483 reg |= GITS_BASER_PSZ_4K << GITS_BASER_PSZ_SHIFT;
484 break;
485 case PAGE_SIZE_16K: /* 16KB */
486 reg |= GITS_BASER_PSZ_16K << GITS_BASER_PSZ_SHIFT;
487 break;
488 case PAGE_SIZE_64K: /* 64KB */
489 reg |= GITS_BASER_PSZ_64K << GITS_BASER_PSZ_SHIFT;
490 break;
491 }
492
493 /* Write the new page size */
494 gic_its_write_8(sc, GITS_BASER(table), reg);
495
496 /* Read back to check */
497 tmp = gic_its_read_8(sc, GITS_BASER(table));
498
499 /* The page size is correct */
500 if ((tmp & GITS_BASER_PSZ_MASK) == (reg & GITS_BASER_PSZ_MASK))
501 return (page_size);
502
503 switch (page_size) {
504 default:
505 return (-1);
506 case PAGE_SIZE_16K:
507 page_size = PAGE_SIZE_4K;
508 break;
509 case PAGE_SIZE_64K:
510 page_size = PAGE_SIZE_16K;
511 break;
512 }
513 }
514 }
515
516 static bool
gicv3_its_table_supports_indirect(struct gicv3_its_softc * sc,int table)517 gicv3_its_table_supports_indirect(struct gicv3_its_softc *sc, int table)
518 {
519 uint64_t reg;
520
521 reg = gic_its_read_8(sc, GITS_BASER(table));
522
523 /* Try setting the indirect flag */
524 reg |= GITS_BASER_INDIRECT;
525 gic_its_write_8(sc, GITS_BASER(table), reg);
526
527 /* Read back to check */
528 reg = gic_its_read_8(sc, GITS_BASER(table));
529 return ((reg & GITS_BASER_INDIRECT) != 0);
530 }
531
532
533 static int
gicv3_its_table_init(device_t dev,struct gicv3_its_softc * sc)534 gicv3_its_table_init(device_t dev, struct gicv3_its_softc *sc)
535 {
536 void *table;
537 vm_paddr_t paddr;
538 uint64_t cache, reg, share, tmp, type;
539 size_t its_tbl_size, nitspages, npages;
540 size_t l1_esize, l2_esize, l1_nidents, l2_nidents;
541 int i, page_size;
542 int devbits;
543 bool indirect;
544
545 if ((sc->sc_its_flags & ITS_FLAGS_ERRATA_CAVIUM_22375) != 0) {
546 /*
547 * GITS_TYPER[17:13] of ThunderX reports that device IDs
548 * are to be 21 bits in length. The entry size of the ITS
549 * table can be read from GITS_BASERn[52:48] and on ThunderX
550 * is supposed to be 8 bytes in length (for device table).
551 * Finally the page size that is to be used by ITS to access
552 * this table will be set to 64KB.
553 *
554 * This gives 0x200000 entries of size 0x8 bytes covered by
555 * 256 pages each of which 64KB in size. The number of pages
556 * (minus 1) should then be written to GITS_BASERn[7:0]. In
557 * that case this value would be 0xFF but on ThunderX the
558 * maximum value that HW accepts is 0xFD.
559 *
560 * Set an arbitrary number of device ID bits to 20 in order
561 * to limit the number of entries in ITS device table to
562 * 0x100000 and the table size to 8MB.
563 */
564 devbits = 20;
565 cache = 0;
566 } else {
567 devbits = GITS_TYPER_DEVB(gic_its_read_8(sc, GITS_TYPER));
568 if (sc->sc_its_flags & ITS_FLAGS_FORCE_NOSHAREABLE)
569 cache = GITS_BASER_CACHE_NC;
570 else
571 cache = GITS_BASER_CACHE_RAWAWB;
572 }
573 sc->sc_devbits = devbits;
574
575 if (sc->sc_its_flags & ITS_FLAGS_FORCE_NOSHAREABLE)
576 share = GITS_BASER_SHARE_NS;
577 else
578 share = GITS_BASER_SHARE_IS;
579
580 for (i = 0; i < GITS_BASER_NUM; i++) {
581 reg = gic_its_read_8(sc, GITS_BASER(i));
582 /* The type of table */
583 type = GITS_BASER_TYPE(reg);
584 if (type == GITS_BASER_TYPE_UNIMPL)
585 continue;
586
587 /* The table entry size */
588 l1_esize = GITS_BASER_ESIZE(reg);
589
590 /* Find the tables page size */
591 page_size = gicv3_its_table_page_size(sc, i);
592 if (page_size == -1) {
593 device_printf(dev, "No valid page size for table %d\n",
594 i);
595 return (EINVAL);
596 }
597
598 indirect = false;
599 l2_nidents = 0;
600 l2_esize = 0;
601 switch(type) {
602 case GITS_BASER_TYPE_DEV:
603 if (sc->sc_dev_table_idx != -1)
604 device_printf(dev,
605 "Warning: Multiple device tables found\n");
606
607 sc->sc_dev_table_idx = i;
608 l1_nidents = (1 << devbits);
609 if ((l1_esize * l1_nidents) > (page_size * 2)) {
610 indirect =
611 gicv3_its_table_supports_indirect(sc, i);
612 if (indirect) {
613 /*
614 * Each l1 entry is 8 bytes and points
615 * to an l2 table of size page_size.
616 * Calculate how many entries this is
617 * and use this to find how many
618 * 8 byte l1 idents we need.
619 */
620 l2_esize = l1_esize;
621 l2_nidents = page_size / l2_esize;
622 l1_nidents = l1_nidents / l2_nidents;
623 l1_esize = GITS_INDIRECT_L1_ESIZE;
624 }
625 }
626 its_tbl_size = l1_esize * l1_nidents;
627 its_tbl_size = roundup2(its_tbl_size, page_size);
628 break;
629 case GITS_BASER_TYPE_PP: /* Undocumented? */
630 case GITS_BASER_TYPE_IC:
631 its_tbl_size = page_size;
632 break;
633 case GITS_BASER_TYPE_VP:
634 /*
635 * If GITS_TYPER.SVPET != 0, the pending table is
636 * shared amongst the redistibutors and ther other
637 * ITSes. Requiring sharing across the ITSes when none
638 * of the redistributors have GICR_VPROPBASER.Valid==1
639 * isn't specified in the architecture, but that's how
640 * the GIC-700 behaves. We don't handle vPE tables at
641 * all yet, so just skip this base register.
642 */
643 default:
644 if (bootverbose)
645 device_printf(dev, "Unhandled table type %lx\n",
646 type);
647 continue;
648 }
649 npages = howmany(its_tbl_size, PAGE_SIZE);
650
651 /* Allocate the table */
652 table = contigmalloc_domainset(npages * PAGE_SIZE,
653 M_GICV3_ITS, sc->sc_ds, M_WAITOK | M_ZERO, 0,
654 gicv3_its_limit_max_addr(sc, (1ul << 48) - 1),
655 PAGE_SIZE_64K, 0);
656
657 sc->sc_its_ptab[i].ptab_vaddr = table;
658 sc->sc_its_ptab[i].ptab_l1_size = its_tbl_size;
659 sc->sc_its_ptab[i].ptab_l1_nidents = l1_nidents;
660 sc->sc_its_ptab[i].ptab_l2_size = page_size;
661 sc->sc_its_ptab[i].ptab_l2_nidents = l2_nidents;
662
663 sc->sc_its_ptab[i].ptab_indirect = indirect;
664 sc->sc_its_ptab[i].ptab_page_size = page_size;
665
666 paddr = vtophys(table);
667
668 while (1) {
669 nitspages = howmany(its_tbl_size, page_size);
670
671 /* Clear the fields we will be setting */
672 reg &= ~(GITS_BASER_VALID | GITS_BASER_INDIRECT |
673 GITS_BASER_CACHE_MASK | GITS_BASER_TYPE_MASK |
674 GITS_BASER_PA_MASK |
675 GITS_BASER_SHARE_MASK | GITS_BASER_PSZ_MASK |
676 GITS_BASER_SIZE_MASK);
677 /* Set the new values */
678 reg |= GITS_BASER_VALID |
679 (indirect ? GITS_BASER_INDIRECT : 0) |
680 (cache << GITS_BASER_CACHE_SHIFT) |
681 (type << GITS_BASER_TYPE_SHIFT) |
682 paddr | (share << GITS_BASER_SHARE_SHIFT) |
683 (nitspages - 1);
684
685 switch (page_size) {
686 case PAGE_SIZE_4K: /* 4KB */
687 reg |=
688 GITS_BASER_PSZ_4K << GITS_BASER_PSZ_SHIFT;
689 break;
690 case PAGE_SIZE_16K: /* 16KB */
691 reg |=
692 GITS_BASER_PSZ_16K << GITS_BASER_PSZ_SHIFT;
693 break;
694 case PAGE_SIZE_64K: /* 64KB */
695 reg |=
696 GITS_BASER_PSZ_64K << GITS_BASER_PSZ_SHIFT;
697 break;
698 }
699
700 gic_its_write_8(sc, GITS_BASER(i), reg);
701
702 /* Read back to check */
703 tmp = gic_its_read_8(sc, GITS_BASER(i));
704
705 /* Do the shareability masks line up? */
706 if ((tmp & GITS_BASER_SHARE_MASK) !=
707 (reg & GITS_BASER_SHARE_MASK)) {
708 share = (tmp & GITS_BASER_SHARE_MASK) >>
709 GITS_BASER_SHARE_SHIFT;
710 continue;
711 }
712
713 if (tmp != reg) {
714 device_printf(dev, "GITS_BASER%d: "
715 "unable to be updated: %lx != %lx\n",
716 i, reg, tmp);
717 return (ENXIO);
718 }
719
720 sc->sc_its_ptab[i].ptab_share = share;
721 /* We should have made all needed changes */
722 break;
723 }
724 }
725
726 return (0);
727 }
728
729 static void
gicv3_its_conftable_init(struct gicv3_its_softc * sc)730 gicv3_its_conftable_init(struct gicv3_its_softc *sc)
731 {
732 /* note: we assume the ITS children are serialized by the parent */
733 static void *conf_table;
734 int extra_flags = 0;
735 device_t gicv3;
736 uint32_t ctlr;
737 vm_paddr_t conf_pa;
738
739 /*
740 * The PROPBASER is a singleton in our parent. We only set it up the
741 * first time through. conf_table is effectively global to all the units
742 * and we rely on subr_bus to serialize probe/attach.
743 */
744 if (conf_table != NULL) {
745 sc->sc_conf_base = conf_table;
746 return;
747 }
748
749 gicv3 = device_get_parent(sc->dev);
750 ctlr = gic_r_read_4(gicv3, GICR_CTLR);
751 if ((ctlr & GICR_CTLR_LPI_ENABLE) != 0) {
752 conf_pa = gic_r_read_8(gicv3, GICR_PROPBASER);
753 conf_pa &= GICR_PROPBASER_PA_MASK;
754 /*
755 * If there was a pre-existing PROPBASER, then we need to honor
756 * it because implementation defined behavior in gicv3 makes it
757 * impossible to quiesce to change it out. We will only see a
758 * pre-existing one when we've been kexec'd from a Linux kernel,
759 * or from a LinuxBoot environment.
760 *
761 * Linux provides us with a MEMRESERVE table that we put into
762 * the excluded physmem area. If PROPBASER isn't in this tabke,
763 * the system cannot run due to random memory corruption,
764 * so we panic for this case.
765 */
766 if (!physmem_excluded(conf_pa, LPI_CONFTAB_SIZE))
767 panic("gicv3 PROPBASER needs to reuse %#lx, but not reserved",
768 conf_pa);
769 conf_table = PHYS_TO_DMAP(conf_pa);
770 if (!pmap_klookup((vm_offset_t)conf_table, NULL))
771 panic("Cannot map prior LPI mapping into KVA");
772 extra_flags = ITS_FLAGS_LPI_PREALLOC | ITS_FLAGS_LPI_CONF_FLUSH;
773 if (bootverbose)
774 device_printf(sc->dev,
775 "LPI enabled, conf table using pa %#lx va %p\n",
776 conf_pa, conf_table);
777 } else {
778 /*
779 * Otherwise just allocate contiguous pages. We'll configure the
780 * PROPBASER register later in its_init_cpu_lpi().
781 */
782 conf_table = contigmalloc(LPI_CONFTAB_SIZE,
783 M_GICV3_ITS, M_WAITOK, 0,
784 gicv3_its_limit_max_addr(sc, LPI_CONFTAB_MAX_ADDR),
785 LPI_CONFTAB_ALIGN, 0);
786 }
787 sc->sc_conf_base = conf_table;
788 sc->sc_its_flags |= extra_flags;
789
790 /* Set the default configuration */
791 memset(sc->sc_conf_base, GIC_PRIORITY_MAX | LPI_CONF_GROUP1,
792 LPI_CONFTAB_SIZE);
793
794 /* Flush the table to memory */
795 cpu_dcache_wb_range(sc->sc_conf_base, LPI_CONFTAB_SIZE);
796 }
797
798 static void
gicv3_its_pendtables_init(struct gicv3_its_softc * sc)799 gicv3_its_pendtables_init(struct gicv3_its_softc *sc)
800 {
801
802 if ((sc->sc_its_flags & ITS_FLAGS_LPI_PREALLOC) == 0) {
803 for (int i = 0; i <= mp_maxid; i++) {
804 if (CPU_ISSET(i, &sc->sc_cpus) == 0)
805 continue;
806
807 sc->sc_pend_base[i] = contigmalloc(
808 LPI_PENDTAB_SIZE, M_GICV3_ITS, M_WAITOK | M_ZERO,
809 0,
810 gicv3_its_limit_max_addr(sc, LPI_PENDTAB_MAX_ADDR),
811 LPI_PENDTAB_ALIGN, 0);
812
813 /* Flush so the ITS can see the memory */
814 cpu_dcache_wb_range(sc->sc_pend_base[i],
815 LPI_PENDTAB_SIZE);
816 }
817 }
818 }
819
820 static void
its_init_cpu_lpi(device_t dev,struct gicv3_its_softc * sc)821 its_init_cpu_lpi(device_t dev, struct gicv3_its_softc *sc)
822 {
823 device_t gicv3;
824 uint64_t xbaser, tmp, size;
825 uint32_t ctlr;
826 u_int cpuid;
827
828 gicv3 = device_get_parent(dev);
829 cpuid = PCPU_GET(cpuid);
830
831 /*
832 * Set the redistributor base. If we're reusing what we found on boot
833 * since the gic was already running, then don't touch it here. We also
834 * don't need to disable / enable LPI if we're not changing PROPBASER,
835 * so only do that if we're not prealloced.
836 */
837 if ((sc->sc_its_flags & ITS_FLAGS_LPI_PREALLOC) == 0) {
838 /* Disable LPIs */
839 ctlr = gic_r_read_4(gicv3, GICR_CTLR);
840 ctlr &= ~GICR_CTLR_LPI_ENABLE;
841 gic_r_write_4(gicv3, GICR_CTLR, ctlr);
842
843 /* Make sure changes are observable my the GIC */
844 dsb(sy);
845
846 size = ilog2_long(LPI_CONFTAB_SIZE | GIC_FIRST_LPI) - 1;
847
848 xbaser = vtophys(sc->sc_conf_base) |
849 (GICR_PROPBASER_CACHE_NIWAWB << GICR_PROPBASER_CACHE_SHIFT) |
850 size;
851 if (gicv3_get_flags(sc->dev) & GIC_V3_FLAGS_FORCE_NOSHAREABLE)
852 xbaser |= GICR_PROPBASER_SHARE_NS << GICR_PROPBASER_SHARE_SHIFT;
853 else
854 xbaser |= GICR_PROPBASER_SHARE_IS << GICR_PROPBASER_SHARE_SHIFT;
855 gic_r_write_8(gicv3, GICR_PROPBASER, xbaser);
856
857 /* Check the cache attributes we set */
858 tmp = gic_r_read_8(gicv3, GICR_PROPBASER);
859
860 if ((tmp & GICR_PROPBASER_SHARE_MASK) !=
861 (xbaser & GICR_PROPBASER_SHARE_MASK)) {
862 if ((tmp & GICR_PROPBASER_SHARE_MASK) ==
863 (GICR_PROPBASER_SHARE_NS << GICR_PROPBASER_SHARE_SHIFT)) {
864 /* We need to mark as non-cacheable */
865 xbaser &= ~(GICR_PROPBASER_SHARE_MASK |
866 GICR_PROPBASER_CACHE_MASK);
867 /* Non-cacheable */
868 xbaser |= GICR_PROPBASER_CACHE_NIN <<
869 GICR_PROPBASER_CACHE_SHIFT;
870 /* Non-shareable */
871 xbaser |= GICR_PROPBASER_SHARE_NS <<
872 GICR_PROPBASER_SHARE_SHIFT;
873 gic_r_write_8(gicv3, GICR_PROPBASER, xbaser);
874 }
875 sc->sc_its_flags |= ITS_FLAGS_LPI_CONF_FLUSH;
876 }
877
878 /*
879 * Set the LPI pending table base
880 */
881 xbaser = vtophys(sc->sc_pend_base[cpuid]) |
882 (GICR_PENDBASER_CACHE_NIWAWB << GICR_PENDBASER_CACHE_SHIFT);
883 if (sc->sc_its_flags & ITS_FLAGS_FORCE_NOSHAREABLE)
884 xbaser |= GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT;
885 else
886 xbaser |= GITS_CBASER_SHARE_IS << GITS_CBASER_SHARE_SHIFT;
887
888 gic_r_write_8(gicv3, GICR_PENDBASER, xbaser);
889
890 tmp = gic_r_read_8(gicv3, GICR_PENDBASER);
891
892 if ((tmp & GICR_PENDBASER_SHARE_MASK) ==
893 (GICR_PENDBASER_SHARE_NS << GICR_PENDBASER_SHARE_SHIFT)) {
894 /* Clear the cahce and shareability bits */
895 xbaser &= ~(GICR_PENDBASER_CACHE_MASK |
896 GICR_PENDBASER_SHARE_MASK);
897 /* Mark as non-shareable */
898 xbaser |= GICR_PENDBASER_SHARE_NS << GICR_PENDBASER_SHARE_SHIFT;
899 /* And non-cacheable */
900 xbaser |= GICR_PENDBASER_CACHE_NIN <<
901 GICR_PENDBASER_CACHE_SHIFT;
902 }
903
904 /* Enable LPIs */
905 ctlr = gic_r_read_4(gicv3, GICR_CTLR);
906 ctlr |= GICR_CTLR_LPI_ENABLE;
907 gic_r_write_4(gicv3, GICR_CTLR, ctlr);
908
909 /* Make sure the GIC has seen everything */
910 dsb(sy);
911 } else {
912 KASSERT(sc->sc_pend_base[cpuid] == NULL,
913 ("PREALLOC too soon cpuid %d", cpuid));
914 tmp = gic_r_read_8(gicv3, GICR_PENDBASER);
915 tmp &= GICR_PENDBASER_PA_MASK;
916 if (!physmem_excluded(tmp, LPI_PENDTAB_SIZE))
917 panic("gicv3 PENDBASER on cpu %d needs to reuse 0x%#lx, but not reserved\n",
918 cpuid, tmp);
919 sc->sc_pend_base[cpuid] = PHYS_TO_DMAP(tmp);
920 }
921
922
923 if (bootverbose)
924 device_printf(gicv3, "using %sPENDBASE of %#lx on cpu %d\n",
925 (sc->sc_its_flags & ITS_FLAGS_LPI_PREALLOC) ? "pre-existing " : "",
926 vtophys(sc->sc_pend_base[cpuid]), cpuid);
927 }
928
929 static int
its_init_cpu(device_t dev,struct gicv3_its_softc * sc)930 its_init_cpu(device_t dev, struct gicv3_its_softc *sc)
931 {
932 device_t gicv3;
933 vm_paddr_t target;
934 u_int cpuid;
935 struct redist_pcpu *rpcpu;
936
937 gicv3 = device_get_parent(dev);
938 cpuid = PCPU_GET(cpuid);
939 if (!CPU_ISSET(cpuid, &sc->sc_cpus))
940 return (0);
941
942 /* Check if the ITS is enabled on this CPU */
943 if ((gic_r_read_8(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0)
944 return (ENXIO);
945
946 rpcpu = gicv3_get_redist(dev);
947
948 /* Do per-cpu LPI init once */
949 if (!rpcpu->lpi_enabled) {
950 its_init_cpu_lpi(dev, sc);
951 rpcpu->lpi_enabled = true;
952 }
953
954 if ((gic_its_read_8(sc, GITS_TYPER) & GITS_TYPER_PTA) != 0) {
955 /* This ITS wants the redistributor physical address */
956 target = vtophys((vm_offset_t)rman_get_virtual(rpcpu->res) +
957 rpcpu->offset);
958 } else {
959 /* This ITS wants the unique processor number */
960 target = GICR_TYPER_CPUNUM(gic_r_read_8(gicv3, GICR_TYPER)) <<
961 CMD_TARGET_SHIFT;
962 }
963
964 sc->sc_its_cols[cpuid]->col_target = target;
965 sc->sc_its_cols[cpuid]->col_id = cpuid;
966
967 its_cmd_mapc(dev, sc->sc_its_cols[cpuid], 1);
968 its_cmd_invall(dev, sc->sc_its_cols[cpuid]);
969
970 return (0);
971 }
972
973 static int
gicv3_its_sysctl_trace_enable(SYSCTL_HANDLER_ARGS)974 gicv3_its_sysctl_trace_enable(SYSCTL_HANDLER_ARGS)
975 {
976 struct gicv3_its_softc *sc;
977 int rv;
978
979 sc = arg1;
980
981 rv = sysctl_handle_bool(oidp, &sc->trace_enable, 0, req);
982 if (rv != 0 || req->newptr == NULL)
983 return (rv);
984 if (sc->trace_enable)
985 gic_its_write_8(sc, GITS_TRKCTLR, 3);
986 else
987 gic_its_write_8(sc, GITS_TRKCTLR, 0);
988
989 return (0);
990 }
991
992 static int
gicv3_its_sysctl_trace_regs(SYSCTL_HANDLER_ARGS)993 gicv3_its_sysctl_trace_regs(SYSCTL_HANDLER_ARGS)
994 {
995 struct gicv3_its_softc *sc;
996 struct sbuf *sb;
997 int err;
998
999 sc = arg1;
1000 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
1001 if (sb == NULL) {
1002 device_printf(sc->dev, "Could not allocate sbuf for output.\n");
1003 return (ENOMEM);
1004 }
1005 sbuf_cat(sb, "\n");
1006 sbuf_printf(sb, "GITS_TRKCTLR: 0x%08X\n",
1007 gic_its_read_4(sc, GITS_TRKCTLR));
1008 sbuf_printf(sb, "GITS_TRKR: 0x%08X\n",
1009 gic_its_read_4(sc, GITS_TRKR));
1010 sbuf_printf(sb, "GITS_TRKDIDR: 0x%08X\n",
1011 gic_its_read_4(sc, GITS_TRKDIDR));
1012 sbuf_printf(sb, "GITS_TRKPIDR: 0x%08X\n",
1013 gic_its_read_4(sc, GITS_TRKPIDR));
1014 sbuf_printf(sb, "GITS_TRKVIDR: 0x%08X\n",
1015 gic_its_read_4(sc, GITS_TRKVIDR));
1016 sbuf_printf(sb, "GITS_TRKTGTR: 0x%08X\n",
1017 gic_its_read_4(sc, GITS_TRKTGTR));
1018
1019 err = sbuf_finish(sb);
1020 if (err)
1021 device_printf(sc->dev, "Error finishing sbuf: %d\n", err);
1022 sbuf_delete(sb);
1023 return(err);
1024 }
1025
1026 static int
gicv3_its_init_sysctl(struct gicv3_its_softc * sc)1027 gicv3_its_init_sysctl(struct gicv3_its_softc *sc)
1028 {
1029 struct sysctl_oid *oid, *child;
1030 struct sysctl_ctx_list *ctx_list;
1031
1032 ctx_list = device_get_sysctl_ctx(sc->dev);
1033 child = device_get_sysctl_tree(sc->dev);
1034 oid = SYSCTL_ADD_NODE(ctx_list,
1035 SYSCTL_CHILDREN(child), OID_AUTO, "tracing",
1036 CTLFLAG_RD| CTLFLAG_MPSAFE, NULL, "Messages tracing");
1037 if (oid == NULL)
1038 return (ENXIO);
1039
1040 /* Add registers */
1041 SYSCTL_ADD_PROC(ctx_list,
1042 SYSCTL_CHILDREN(oid), OID_AUTO, "enable",
1043 CTLTYPE_U8 | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
1044 gicv3_its_sysctl_trace_enable, "CU", "Enable tracing");
1045 SYSCTL_ADD_PROC(ctx_list,
1046 SYSCTL_CHILDREN(oid), OID_AUTO, "capture",
1047 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
1048 gicv3_its_sysctl_trace_regs, "", "Captured tracing registers.");
1049
1050 return (0);
1051 }
1052
1053 static int
gicv3_its_attach(device_t dev)1054 gicv3_its_attach(device_t dev)
1055 {
1056 struct gicv3_its_softc *sc;
1057 int domain, err, i, rid;
1058 uint64_t phys;
1059 uint32_t ctlr, iidr;
1060
1061 sc = device_get_softc(dev);
1062
1063 sc->sc_dev_table_idx = -1;
1064 sc->sc_irq_length = gicv3_get_nirqs(dev);
1065 sc->sc_irq_base = GIC_FIRST_LPI;
1066 sc->sc_irq_base += device_get_unit(dev) * sc->sc_irq_length;
1067 sc->malloc_max_addr = ~0;
1068
1069 rid = 0;
1070 sc->sc_its_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1071 RF_ACTIVE);
1072 if (sc->sc_its_res == NULL) {
1073 device_printf(dev, "Could not allocate memory\n");
1074 return (ENXIO);
1075 }
1076
1077 phys = rounddown2(vtophys(rman_get_virtual(sc->sc_its_res)) +
1078 GITS_TRANSLATER, PAGE_SIZE);
1079 sc->ma = malloc(sizeof(struct vm_page), M_DEVBUF, M_WAITOK | M_ZERO);
1080 vm_page_initfake(sc->ma, phys, VM_MEMATTR_DEFAULT);
1081
1082 CPU_COPY(&all_cpus, &sc->sc_cpus);
1083 iidr = gic_its_read_4(sc, GITS_IIDR);
1084 for (i = 0; i < nitems(its_quirks); i++) {
1085 if (its_quirks[i].detect(dev)) {
1086 if (bootverbose) {
1087 device_printf(dev, "Applying %s\n",
1088 its_quirks[i].desc);
1089 }
1090 its_quirks[i].func(dev);
1091 break;
1092 }
1093 }
1094
1095 if (bus_get_domain(dev, &domain) == 0 && domain < MAXMEMDOM) {
1096 sc->sc_ds = DOMAINSET_PREF(domain);
1097 } else {
1098 sc->sc_ds = DOMAINSET_RR();
1099 }
1100
1101 /*
1102 * GIT_CTLR_EN is mandated to reset to 0 on a Warm reset, but we may be
1103 * coming in via, for instance, a kexec/kboot style setup where a
1104 * previous kernel has configured then relinquished control. Clear it
1105 * so that we can reconfigure GITS_BASER*.
1106 */
1107 ctlr = gic_its_read_4(sc, GITS_CTLR);
1108 if ((ctlr & GITS_CTLR_EN) != 0) {
1109 ctlr &= ~GITS_CTLR_EN;
1110 gic_its_write_4(sc, GITS_CTLR, ctlr);
1111 }
1112
1113 /* Allocate the private tables */
1114 err = gicv3_its_table_init(dev, sc);
1115 if (err != 0)
1116 return (err);
1117
1118 /* Protects access to the device list */
1119 mtx_init(&sc->sc_its_dev_lock, "ITS device lock", NULL, MTX_SPIN);
1120
1121 /* Protects access to the ITS command circular buffer. */
1122 mtx_init(&sc->sc_its_cmd_lock, "ITS cmd lock", NULL, MTX_SPIN);
1123
1124 /* Allocate the command circular buffer */
1125 gicv3_its_cmdq_init(sc);
1126
1127 /* Allocate the per-CPU collections */
1128 for (int cpu = 0; cpu <= mp_maxid; cpu++)
1129 if (CPU_ISSET(cpu, &sc->sc_cpus) != 0)
1130 sc->sc_its_cols[cpu] = malloc_domainset(
1131 sizeof(*sc->sc_its_cols[0]), M_GICV3_ITS,
1132 DOMAINSET_PREF(pcpu_find(cpu)->pc_domain),
1133 M_WAITOK | M_ZERO);
1134 else
1135 sc->sc_its_cols[cpu] = NULL;
1136
1137 /* Enable the ITS */
1138 gic_its_write_4(sc, GITS_CTLR, ctlr | GITS_CTLR_EN);
1139
1140 /* Create the LPI configuration table */
1141 gicv3_its_conftable_init(sc);
1142
1143 /* And the pending tebles */
1144 gicv3_its_pendtables_init(sc);
1145
1146 /* Enable LPIs on this CPU */
1147 its_init_cpu(dev, sc);
1148
1149 TAILQ_INIT(&sc->sc_its_dev_list);
1150 TAILQ_INIT(&sc->sc_free_irqs);
1151
1152 /*
1153 * Create the vmem object to allocate INTRNG IRQs from. We try to
1154 * use all IRQs not already used by the GICv3.
1155 * XXX: This assumes there are no other interrupt controllers in the
1156 * system.
1157 */
1158 sc->sc_irq_alloc = vmem_create(device_get_nameunit(dev), 0,
1159 gicv3_get_nirqs(dev), 1, 0, M_FIRSTFIT | M_WAITOK);
1160
1161 sc->sc_irqs = malloc(sizeof(*sc->sc_irqs) * sc->sc_irq_length,
1162 M_GICV3_ITS, M_WAITOK | M_ZERO);
1163
1164 /* For GIC-500 install tracking sysctls. */
1165 if ((iidr & (GITS_IIDR_PRODUCT_MASK | GITS_IIDR_IMPLEMENTOR_MASK)) ==
1166 GITS_IIDR_RAW(GITS_IIDR_IMPL_ARM, GITS_IIDR_PROD_GIC500, 0, 0))
1167 gicv3_its_init_sysctl(sc);
1168
1169 return (0);
1170 }
1171
1172 static int
gicv3_its_detach(device_t dev)1173 gicv3_its_detach(device_t dev)
1174 {
1175
1176 return (ENXIO);
1177 }
1178
1179 static bool
its_detect_cavium_22375(device_t dev)1180 its_detect_cavium_22375(device_t dev)
1181 {
1182 uint32_t iidr;
1183 struct gicv3_its_softc *sc;
1184
1185 sc = device_get_softc(dev);
1186 iidr = gic_its_read_4(sc, GITS_IIDR);
1187 if ((iidr & ~GITS_IIDR_REVISION_MASK) ==
1188 GITS_IIDR_RAW(GITS_IIDR_IMPL_CAVIUM, GITS_IIDR_PROD_THUNDER,
1189 GITS_IIDR_VAR_THUNDER_1, 0))
1190 return (true);
1191 return(false);
1192 }
1193
1194 static void
its_quirk_cavium_22375(device_t dev)1195 its_quirk_cavium_22375(device_t dev)
1196 {
1197 struct gicv3_its_softc *sc;
1198 int domain;
1199
1200 sc = device_get_softc(dev);
1201 sc->sc_its_flags |= ITS_FLAGS_ERRATA_CAVIUM_22375;
1202
1203 /*
1204 * We need to limit which CPUs we send these interrupts to on
1205 * the original dual socket ThunderX as it is unable to
1206 * forward them between the two sockets.
1207 */
1208 if (bus_get_domain(dev, &domain) == 0) {
1209 if (domain < MAXMEMDOM) {
1210 CPU_COPY(&cpuset_domain[domain], &sc->sc_cpus);
1211 } else {
1212 CPU_ZERO(&sc->sc_cpus);
1213 }
1214 }
1215 }
1216
1217 #ifdef FDT
1218 static bool
its_detect_rk356x(device_t dev)1219 its_detect_rk356x(device_t dev)
1220 {
1221
1222 if (ofw_bus_is_machine_compatible("rockchip,rk3566") ||
1223 ofw_bus_is_machine_compatible("rockchip,rk3568"))
1224 return (true);
1225 return(false);
1226 }
1227
1228 static void
its_quirk_rk356x(device_t dev)1229 its_quirk_rk356x(device_t dev)
1230 {
1231 struct gicv3_its_softc *sc;
1232
1233 sc = device_get_softc(dev);
1234 sc->malloc_max_addr = (1ul << 32) - 1;
1235 }
1236
1237 static bool
its_detect_rk3588(device_t dev)1238 its_detect_rk3588(device_t dev)
1239 {
1240
1241 if (ofw_bus_is_machine_compatible("rockchip,rk3588") ||
1242 ofw_bus_is_machine_compatible("rockchip,rk3588s"))
1243 return (true);
1244 return(false);
1245 }
1246
1247 static void
its_quirk_rk3588(device_t dev)1248 its_quirk_rk3588(device_t dev)
1249 {
1250 struct gicv3_its_softc *sc;
1251
1252 sc = device_get_softc(dev);
1253 sc->sc_its_flags |= ITS_FLAGS_FORCE_NOSHAREABLE;
1254 }
1255 #endif
1256
1257 static void
gicv3_its_disable_intr(device_t dev,struct intr_irqsrc * isrc)1258 gicv3_its_disable_intr(device_t dev, struct intr_irqsrc *isrc)
1259 {
1260 struct gicv3_its_softc *sc;
1261 struct gicv3_its_irqsrc *girq;
1262 uint8_t *conf;
1263
1264 sc = device_get_softc(dev);
1265 girq = (struct gicv3_its_irqsrc *)isrc;
1266 conf = sc->sc_conf_base;
1267
1268 conf[girq->gi_lpi] &= ~LPI_CONF_ENABLE;
1269
1270 if ((sc->sc_its_flags & ITS_FLAGS_LPI_CONF_FLUSH) != 0) {
1271 /* Clean D-cache under command. */
1272 cpu_dcache_wb_range(&conf[girq->gi_lpi], 1);
1273 } else {
1274 /* DSB inner shareable, store */
1275 dsb(ishst);
1276 }
1277
1278 its_cmd_inv(dev, girq->gi_its_dev, girq);
1279 }
1280
1281 static void
gicv3_its_enable_intr(device_t dev,struct intr_irqsrc * isrc)1282 gicv3_its_enable_intr(device_t dev, struct intr_irqsrc *isrc)
1283 {
1284 struct gicv3_its_softc *sc;
1285 struct gicv3_its_irqsrc *girq;
1286 uint8_t *conf;
1287
1288 sc = device_get_softc(dev);
1289 girq = (struct gicv3_its_irqsrc *)isrc;
1290 conf = sc->sc_conf_base;
1291
1292 conf[girq->gi_lpi] |= LPI_CONF_ENABLE;
1293
1294 if ((sc->sc_its_flags & ITS_FLAGS_LPI_CONF_FLUSH) != 0) {
1295 /* Clean D-cache under command. */
1296 cpu_dcache_wb_range(&conf[girq->gi_lpi], 1);
1297 } else {
1298 /* DSB inner shareable, store */
1299 dsb(ishst);
1300 }
1301
1302 its_cmd_inv(dev, girq->gi_its_dev, girq);
1303 }
1304
1305 static int
gicv3_its_intr(void * arg,uintptr_t irq)1306 gicv3_its_intr(void *arg, uintptr_t irq)
1307 {
1308 struct gicv3_its_softc *sc = arg;
1309 struct gicv3_its_irqsrc *girq;
1310 struct trapframe *tf;
1311
1312 irq -= sc->sc_irq_base;
1313 girq = sc->sc_irqs[irq];
1314 if (girq == NULL)
1315 panic("gicv3_its_intr: Invalid interrupt %ld",
1316 irq + sc->sc_irq_base);
1317
1318 tf = curthread->td_intr_frame;
1319 intr_isrc_dispatch(&girq->gi_isrc, tf);
1320 return (FILTER_HANDLED);
1321 }
1322
1323 static void
gicv3_its_pre_ithread(device_t dev,struct intr_irqsrc * isrc)1324 gicv3_its_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1325 {
1326 struct gicv3_its_irqsrc *girq;
1327
1328 girq = (struct gicv3_its_irqsrc *)isrc;
1329 gic_icc_write(EOIR1, girq->gi_lpi + GIC_FIRST_LPI);
1330 }
1331
1332 static void
gicv3_its_post_ithread(device_t dev,struct intr_irqsrc * isrc)1333 gicv3_its_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1334 {
1335
1336 }
1337
1338 static void
gicv3_its_post_filter(device_t dev,struct intr_irqsrc * isrc)1339 gicv3_its_post_filter(device_t dev, struct intr_irqsrc *isrc)
1340 {
1341 struct gicv3_its_irqsrc *girq;
1342
1343 girq = (struct gicv3_its_irqsrc *)isrc;
1344 gic_icc_write(EOIR1, girq->gi_lpi + GIC_FIRST_LPI);
1345 }
1346
1347 static int
gicv3_its_select_cpu(device_t dev,struct intr_irqsrc * isrc)1348 gicv3_its_select_cpu(device_t dev, struct intr_irqsrc *isrc)
1349 {
1350 struct gicv3_its_softc *sc;
1351
1352 sc = device_get_softc(dev);
1353 if (CPU_EMPTY(&isrc->isrc_cpu)) {
1354 sc->gic_irq_cpu = intr_irq_next_cpu(sc->gic_irq_cpu,
1355 &sc->sc_cpus);
1356 CPU_SETOF(sc->gic_irq_cpu, &isrc->isrc_cpu);
1357 }
1358
1359 return (0);
1360 }
1361
1362 static int
gicv3_its_bind_intr(device_t dev,struct intr_irqsrc * isrc)1363 gicv3_its_bind_intr(device_t dev, struct intr_irqsrc *isrc)
1364 {
1365 struct gicv3_its_irqsrc *girq;
1366
1367 gicv3_its_select_cpu(dev, isrc);
1368
1369 girq = (struct gicv3_its_irqsrc *)isrc;
1370 its_cmd_movi(dev, girq);
1371 return (0);
1372 }
1373
1374 static int
gicv3_its_map_intr(device_t dev,struct intr_map_data * data,struct intr_irqsrc ** isrcp)1375 gicv3_its_map_intr(device_t dev, struct intr_map_data *data,
1376 struct intr_irqsrc **isrcp)
1377 {
1378
1379 /*
1380 * This should never happen, we only call this function to map
1381 * interrupts found before the controller driver is ready.
1382 */
1383 panic("gicv3_its_map_intr: Unable to map a MSI interrupt");
1384 }
1385
1386 static int
gicv3_its_setup_intr(device_t dev,struct intr_irqsrc * isrc,struct resource * res,struct intr_map_data * data)1387 gicv3_its_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1388 struct resource *res, struct intr_map_data *data)
1389 {
1390
1391 /* Bind the interrupt to a CPU */
1392 gicv3_its_bind_intr(dev, isrc);
1393
1394 return (0);
1395 }
1396
1397 #ifdef SMP
1398 static void
gicv3_its_init_secondary(device_t dev,uint32_t rootnum)1399 gicv3_its_init_secondary(device_t dev, uint32_t rootnum)
1400 {
1401 struct gicv3_its_softc *sc;
1402
1403 sc = device_get_softc(dev);
1404
1405 /*
1406 * This is fatal as otherwise we may bind interrupts to this CPU.
1407 * We need a way to tell the interrupt framework to only bind to a
1408 * subset of given CPUs when it performs the shuffle.
1409 */
1410 if (its_init_cpu(dev, sc) != 0)
1411 panic("gicv3_its_init_secondary: No usable ITS on CPU%d",
1412 PCPU_GET(cpuid));
1413 }
1414 #endif
1415
1416 static uint32_t
its_get_devid(device_t pci_dev)1417 its_get_devid(device_t pci_dev)
1418 {
1419 uintptr_t id;
1420
1421 if (pci_get_id(pci_dev, PCI_ID_MSI, &id) != 0)
1422 panic("%s: %s: Unable to get the MSI DeviceID", __func__,
1423 device_get_nameunit(pci_dev));
1424
1425 return (id);
1426 }
1427
1428 static struct its_dev *
its_device_find(device_t dev,device_t child)1429 its_device_find(device_t dev, device_t child)
1430 {
1431 struct gicv3_its_softc *sc;
1432 struct its_dev *its_dev = NULL;
1433
1434 sc = device_get_softc(dev);
1435
1436 mtx_lock_spin(&sc->sc_its_dev_lock);
1437 TAILQ_FOREACH(its_dev, &sc->sc_its_dev_list, entry) {
1438 if (its_dev->pci_dev == child)
1439 break;
1440 }
1441 mtx_unlock_spin(&sc->sc_its_dev_lock);
1442
1443 return (its_dev);
1444 }
1445
1446 static bool
its_device_alloc(struct gicv3_its_softc * sc,int devid)1447 its_device_alloc(struct gicv3_its_softc *sc, int devid)
1448 {
1449 struct its_ptable *ptable;
1450 void *l2_table;
1451 uint64_t *table;
1452 uint32_t index;
1453 bool shareable;
1454
1455 /* No device table */
1456 if (sc->sc_dev_table_idx < 0) {
1457 if (devid >= (1 << sc->sc_devbits)) {
1458 if (bootverbose) {
1459 device_printf(sc->dev,
1460 "%s: Device out of range for hardware "
1461 "(%x >= %x)\n", __func__, devid,
1462 1 << sc->sc_devbits);
1463 }
1464 return (false);
1465 }
1466 return (true);
1467 }
1468
1469 ptable = &sc->sc_its_ptab[sc->sc_dev_table_idx];
1470 /* Check the devid is within the table limit */
1471 if (!ptable->ptab_indirect) {
1472 if (devid >= ptable->ptab_l1_nidents) {
1473 if (bootverbose) {
1474 device_printf(sc->dev,
1475 "%s: Device out of range for table "
1476 "(%x >= %x)\n", __func__, devid,
1477 ptable->ptab_l1_nidents);
1478 }
1479 return (false);
1480 }
1481
1482 return (true);
1483 }
1484
1485 /* Check the devid is within the allocated range */
1486 index = devid / ptable->ptab_l2_nidents;
1487 if (index >= ptable->ptab_l1_nidents) {
1488 if (bootverbose) {
1489 device_printf(sc->dev,
1490 "%s: Index out of range for table (%x >= %x)\n",
1491 __func__, index, ptable->ptab_l1_nidents);
1492 }
1493 return (false);
1494 }
1495
1496 table = (uint64_t *)ptable->ptab_vaddr;
1497 /* We have an second level table */
1498 if ((table[index] & GITS_BASER_VALID) != 0)
1499 return (true);
1500
1501 shareable = true;
1502 if ((ptable->ptab_share & GITS_BASER_SHARE_MASK) == GITS_BASER_SHARE_NS)
1503 shareable = false;
1504
1505 l2_table = contigmalloc_domainset(ptable->ptab_l2_size,
1506 M_GICV3_ITS, sc->sc_ds, M_WAITOK | M_ZERO, 0,
1507 gicv3_its_limit_max_addr(sc, (1ul << 48) - 1),
1508 ptable->ptab_page_size, 0);
1509
1510 if (!shareable)
1511 cpu_dcache_wb_range(l2_table, ptable->ptab_l2_size);
1512
1513 table[index] = vtophys(l2_table) | GITS_BASER_VALID;
1514 if (!shareable)
1515 cpu_dcache_wb_range(&table[index], sizeof(table[index]));
1516
1517 dsb(sy);
1518 return (true);
1519 }
1520
1521 static struct its_dev *
its_device_get(device_t dev,device_t child,u_int nvecs)1522 its_device_get(device_t dev, device_t child, u_int nvecs)
1523 {
1524 struct gicv3_its_softc *sc;
1525 struct its_dev *its_dev;
1526 vmem_addr_t irq_base;
1527 size_t esize, itt_size;
1528
1529 sc = device_get_softc(dev);
1530
1531 its_dev = its_device_find(dev, child);
1532 if (its_dev != NULL)
1533 return (its_dev);
1534
1535 its_dev = malloc(sizeof(*its_dev), M_GICV3_ITS, M_NOWAIT | M_ZERO);
1536 if (its_dev == NULL)
1537 return (NULL);
1538
1539 its_dev->pci_dev = child;
1540 its_dev->devid = its_get_devid(child);
1541
1542 its_dev->lpis.lpi_busy = 0;
1543 its_dev->lpis.lpi_num = nvecs;
1544 its_dev->lpis.lpi_free = nvecs;
1545
1546 if (!its_device_alloc(sc, its_dev->devid)) {
1547 free(its_dev, M_GICV3_ITS);
1548 return (NULL);
1549 }
1550
1551 if (vmem_alloc(sc->sc_irq_alloc, nvecs, M_FIRSTFIT | M_NOWAIT,
1552 &irq_base) != 0) {
1553 free(its_dev, M_GICV3_ITS);
1554 return (NULL);
1555 }
1556 its_dev->lpis.lpi_base = irq_base;
1557
1558 /* Get ITT entry size */
1559 esize = GITS_TYPER_ITTES(gic_its_read_8(sc, GITS_TYPER));
1560
1561 /*
1562 * Allocate ITT for this device.
1563 * PA has to be 256 B aligned. At least two entries for device.
1564 */
1565 itt_size = roundup2(MAX(nvecs, 2) * esize, 256);
1566 its_dev->itt = contigmalloc_domainset(itt_size,
1567 M_GICV3_ITS, sc->sc_ds, M_NOWAIT | M_ZERO, 0,
1568 gicv3_its_limit_max_addr(sc, LPI_INT_TRANS_TAB_MAX_ADDR),
1569 LPI_INT_TRANS_TAB_ALIGN, 0);
1570 if (its_dev->itt == NULL) {
1571 vmem_free(sc->sc_irq_alloc, its_dev->lpis.lpi_base, nvecs);
1572 free(its_dev, M_GICV3_ITS);
1573 return (NULL);
1574 }
1575
1576 /* Make sure device sees zeroed ITT. */
1577 if ((sc->sc_its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0)
1578 cpu_dcache_wb_range(its_dev->itt, itt_size);
1579
1580 mtx_lock_spin(&sc->sc_its_dev_lock);
1581 TAILQ_INSERT_TAIL(&sc->sc_its_dev_list, its_dev, entry);
1582 mtx_unlock_spin(&sc->sc_its_dev_lock);
1583
1584 /* Map device to its ITT */
1585 its_cmd_mapd(dev, its_dev, 1);
1586
1587 return (its_dev);
1588 }
1589
1590 static void
its_device_release(device_t dev,struct its_dev * its_dev)1591 its_device_release(device_t dev, struct its_dev *its_dev)
1592 {
1593 struct gicv3_its_softc *sc;
1594
1595 KASSERT(its_dev->lpis.lpi_busy == 0,
1596 ("its_device_release: Trying to release an inuse ITS device"));
1597
1598 /* Unmap device in ITS */
1599 its_cmd_mapd(dev, its_dev, 0);
1600
1601 sc = device_get_softc(dev);
1602
1603 /* Remove the device from the list of devices */
1604 mtx_lock_spin(&sc->sc_its_dev_lock);
1605 TAILQ_REMOVE(&sc->sc_its_dev_list, its_dev, entry);
1606 mtx_unlock_spin(&sc->sc_its_dev_lock);
1607
1608 /* Free ITT */
1609 KASSERT(its_dev->itt != NULL, ("Invalid ITT in valid ITS device"));
1610 free(its_dev->itt, M_GICV3_ITS);
1611
1612 /* Free the IRQ allocation */
1613 vmem_free(sc->sc_irq_alloc, its_dev->lpis.lpi_base,
1614 its_dev->lpis.lpi_num);
1615
1616 free(its_dev, M_GICV3_ITS);
1617 }
1618
1619 static struct gicv3_its_irqsrc *
gicv3_its_alloc_irqsrc(device_t dev,struct gicv3_its_softc * sc,u_int irq)1620 gicv3_its_alloc_irqsrc(device_t dev, struct gicv3_its_softc *sc, u_int irq)
1621 {
1622 struct gicv3_its_irqsrc *girq = NULL;
1623
1624 KASSERT(sc->sc_irqs[irq] == NULL,
1625 ("%s: Interrupt %u already allocated", __func__, irq));
1626 mtx_lock_spin(&sc->sc_its_dev_lock);
1627 if (!TAILQ_EMPTY(&sc->sc_free_irqs)) {
1628 girq = TAILQ_FIRST(&sc->sc_free_irqs);
1629 TAILQ_REMOVE(&sc->sc_free_irqs, girq, gi_link);
1630 }
1631 mtx_unlock_spin(&sc->sc_its_dev_lock);
1632 if (girq == NULL) {
1633 girq = malloc(sizeof(*girq), M_GICV3_ITS,
1634 M_NOWAIT | M_ZERO);
1635 if (girq == NULL)
1636 return (NULL);
1637 girq->gi_id = -1;
1638 if (intr_isrc_register(&girq->gi_isrc, dev, 0,
1639 "%s,%u", device_get_nameunit(dev), irq) != 0) {
1640 free(girq, M_GICV3_ITS);
1641 return (NULL);
1642 }
1643 }
1644 girq->gi_lpi = irq + sc->sc_irq_base - GIC_FIRST_LPI;
1645 sc->sc_irqs[irq] = girq;
1646
1647 return (girq);
1648 }
1649
1650 static void
gicv3_its_release_irqsrc(struct gicv3_its_softc * sc,struct gicv3_its_irqsrc * girq)1651 gicv3_its_release_irqsrc(struct gicv3_its_softc *sc,
1652 struct gicv3_its_irqsrc *girq)
1653 {
1654 u_int irq;
1655
1656 mtx_assert(&sc->sc_its_dev_lock, MA_OWNED);
1657
1658 irq = girq->gi_lpi + GIC_FIRST_LPI - sc->sc_irq_base;
1659 sc->sc_irqs[irq] = NULL;
1660
1661 girq->gi_id = -1;
1662 girq->gi_its_dev = NULL;
1663 TAILQ_INSERT_TAIL(&sc->sc_free_irqs, girq, gi_link);
1664 }
1665
1666 static int
gicv3_its_alloc_msi(device_t dev,device_t child,int count,int maxcount,device_t * pic,struct intr_irqsrc ** srcs)1667 gicv3_its_alloc_msi(device_t dev, device_t child, int count, int maxcount,
1668 device_t *pic, struct intr_irqsrc **srcs)
1669 {
1670 struct gicv3_its_softc *sc;
1671 struct gicv3_its_irqsrc *girq;
1672 struct its_dev *its_dev;
1673 u_int irq;
1674 int i;
1675
1676 its_dev = its_device_get(dev, child, count);
1677 if (its_dev == NULL)
1678 return (ENXIO);
1679
1680 KASSERT(its_dev->lpis.lpi_free >= count,
1681 ("gicv3_its_alloc_msi: No free LPIs"));
1682 sc = device_get_softc(dev);
1683 irq = its_dev->lpis.lpi_base + its_dev->lpis.lpi_num -
1684 its_dev->lpis.lpi_free;
1685
1686 /* Allocate the irqsrc for each MSI */
1687 for (i = 0; i < count; i++, irq++) {
1688 its_dev->lpis.lpi_free--;
1689 srcs[i] = (struct intr_irqsrc *)gicv3_its_alloc_irqsrc(dev,
1690 sc, irq);
1691 if (srcs[i] == NULL)
1692 break;
1693 }
1694
1695 /* The allocation failed, release them */
1696 if (i != count) {
1697 mtx_lock_spin(&sc->sc_its_dev_lock);
1698 for (i = 0; i < count; i++) {
1699 girq = (struct gicv3_its_irqsrc *)srcs[i];
1700 if (girq == NULL)
1701 break;
1702 gicv3_its_release_irqsrc(sc, girq);
1703 srcs[i] = NULL;
1704 }
1705 mtx_unlock_spin(&sc->sc_its_dev_lock);
1706 return (ENXIO);
1707 }
1708
1709 /* Finish the allocation now we have all MSI irqsrcs */
1710 for (i = 0; i < count; i++) {
1711 girq = (struct gicv3_its_irqsrc *)srcs[i];
1712 girq->gi_id = i;
1713 girq->gi_its_dev = its_dev;
1714
1715 /* Map the message to the given IRQ */
1716 gicv3_its_select_cpu(dev, (struct intr_irqsrc *)girq);
1717 its_cmd_mapti(dev, girq);
1718 }
1719 its_dev->lpis.lpi_busy += count;
1720 *pic = dev;
1721
1722 return (0);
1723 }
1724
1725 static int
gicv3_its_release_msi(device_t dev,device_t child,int count,struct intr_irqsrc ** isrc)1726 gicv3_its_release_msi(device_t dev, device_t child, int count,
1727 struct intr_irqsrc **isrc)
1728 {
1729 struct gicv3_its_softc *sc;
1730 struct gicv3_its_irqsrc *girq;
1731 struct its_dev *its_dev;
1732 int i;
1733
1734 its_dev = its_device_find(dev, child);
1735
1736 KASSERT(its_dev != NULL,
1737 ("gicv3_its_release_msi: Releasing a MSI interrupt with "
1738 "no ITS device"));
1739 KASSERT(its_dev->lpis.lpi_busy >= count,
1740 ("gicv3_its_release_msi: Releasing more interrupts than "
1741 "were allocated: releasing %d, allocated %d", count,
1742 its_dev->lpis.lpi_busy));
1743
1744 sc = device_get_softc(dev);
1745 mtx_lock_spin(&sc->sc_its_dev_lock);
1746 for (i = 0; i < count; i++) {
1747 girq = (struct gicv3_its_irqsrc *)isrc[i];
1748 gicv3_its_release_irqsrc(sc, girq);
1749 }
1750 mtx_unlock_spin(&sc->sc_its_dev_lock);
1751 its_dev->lpis.lpi_busy -= count;
1752
1753 if (its_dev->lpis.lpi_busy == 0)
1754 its_device_release(dev, its_dev);
1755
1756 return (0);
1757 }
1758
1759 static int
gicv3_its_alloc_msix(device_t dev,device_t child,device_t * pic,struct intr_irqsrc ** isrcp)1760 gicv3_its_alloc_msix(device_t dev, device_t child, device_t *pic,
1761 struct intr_irqsrc **isrcp)
1762 {
1763 struct gicv3_its_softc *sc;
1764 struct gicv3_its_irqsrc *girq;
1765 struct its_dev *its_dev;
1766 u_int nvecs, irq;
1767
1768 nvecs = pci_msix_count(child);
1769 its_dev = its_device_get(dev, child, nvecs);
1770 if (its_dev == NULL)
1771 return (ENXIO);
1772
1773 KASSERT(its_dev->lpis.lpi_free > 0,
1774 ("gicv3_its_alloc_msix: No free LPIs"));
1775 sc = device_get_softc(dev);
1776 irq = its_dev->lpis.lpi_base + its_dev->lpis.lpi_num -
1777 its_dev->lpis.lpi_free;
1778
1779 girq = gicv3_its_alloc_irqsrc(dev, sc, irq);
1780 if (girq == NULL)
1781 return (ENXIO);
1782 girq->gi_id = its_dev->lpis.lpi_busy;
1783 girq->gi_its_dev = its_dev;
1784
1785 its_dev->lpis.lpi_free--;
1786 its_dev->lpis.lpi_busy++;
1787
1788 /* Map the message to the given IRQ */
1789 gicv3_its_select_cpu(dev, (struct intr_irqsrc *)girq);
1790 its_cmd_mapti(dev, girq);
1791
1792 *pic = dev;
1793 *isrcp = (struct intr_irqsrc *)girq;
1794
1795 return (0);
1796 }
1797
1798 static int
gicv3_its_release_msix(device_t dev,device_t child,struct intr_irqsrc * isrc)1799 gicv3_its_release_msix(device_t dev, device_t child, struct intr_irqsrc *isrc)
1800 {
1801 struct gicv3_its_softc *sc;
1802 struct gicv3_its_irqsrc *girq;
1803 struct its_dev *its_dev;
1804
1805 its_dev = its_device_find(dev, child);
1806
1807 KASSERT(its_dev != NULL,
1808 ("gicv3_its_release_msix: Releasing a MSI-X interrupt with "
1809 "no ITS device"));
1810 KASSERT(its_dev->lpis.lpi_busy > 0,
1811 ("gicv3_its_release_msix: Releasing more interrupts than "
1812 "were allocated: allocated %d", its_dev->lpis.lpi_busy));
1813
1814 sc = device_get_softc(dev);
1815 girq = (struct gicv3_its_irqsrc *)isrc;
1816 mtx_lock_spin(&sc->sc_its_dev_lock);
1817 gicv3_its_release_irqsrc(sc, girq);
1818 mtx_unlock_spin(&sc->sc_its_dev_lock);
1819 its_dev->lpis.lpi_busy--;
1820
1821 if (its_dev->lpis.lpi_busy == 0)
1822 its_device_release(dev, its_dev);
1823
1824 return (0);
1825 }
1826
1827 static int
gicv3_its_map_msi(device_t dev,device_t child,struct intr_irqsrc * isrc,uint64_t * addr,uint32_t * data)1828 gicv3_its_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
1829 uint64_t *addr, uint32_t *data)
1830 {
1831 struct gicv3_its_softc *sc;
1832 struct gicv3_its_irqsrc *girq;
1833
1834 sc = device_get_softc(dev);
1835 girq = (struct gicv3_its_irqsrc *)isrc;
1836
1837 *addr = vtophys(rman_get_virtual(sc->sc_its_res)) + GITS_TRANSLATER;
1838 *data = girq->gi_id;
1839
1840 return (0);
1841 }
1842
1843 #ifdef IOMMU
1844 static int
gicv3_iommu_init(device_t dev,device_t child,struct iommu_domain ** domain)1845 gicv3_iommu_init(device_t dev, device_t child, struct iommu_domain **domain)
1846 {
1847 struct gicv3_its_softc *sc;
1848 struct iommu_ctx *ctx;
1849 int error;
1850
1851 sc = device_get_softc(dev);
1852 /*
1853 * Get the context. If no context is found then the device isn't
1854 * behind an IOMMU so no setup is needed.
1855 */
1856 ctx = iommu_get_dev_ctx(child);
1857 if (ctx == NULL) {
1858 *domain = NULL;
1859 return (0);
1860 }
1861 /* Map the page containing the GITS_TRANSLATER register. */
1862 error = iommu_map_msi(ctx, PAGE_SIZE, 0,
1863 IOMMU_MAP_ENTRY_WRITE, IOMMU_MF_CANWAIT, &sc->ma);
1864 *domain = iommu_get_ctx_domain(ctx);
1865
1866 return (error);
1867 }
1868
1869 static void
gicv3_iommu_deinit(device_t dev,device_t child)1870 gicv3_iommu_deinit(device_t dev, device_t child)
1871 {
1872 struct iommu_ctx *ctx;
1873
1874 ctx = iommu_get_dev_ctx(child);
1875 if (ctx == NULL)
1876 return;
1877
1878 iommu_unmap_msi(ctx);
1879 }
1880 #endif
1881
1882 /*
1883 * Commands handling.
1884 */
1885
1886 static __inline void
cmd_format_command(struct its_cmd * cmd,uint8_t cmd_type)1887 cmd_format_command(struct its_cmd *cmd, uint8_t cmd_type)
1888 {
1889 /* Command field: DW0 [7:0] */
1890 cmd->cmd_dword[0] &= htole64(~CMD_COMMAND_MASK);
1891 cmd->cmd_dword[0] |= htole64(cmd_type);
1892 }
1893
1894 static __inline void
cmd_format_devid(struct its_cmd * cmd,uint32_t devid)1895 cmd_format_devid(struct its_cmd *cmd, uint32_t devid)
1896 {
1897 /* Device ID field: DW0 [63:32] */
1898 cmd->cmd_dword[0] &= htole64(~CMD_DEVID_MASK);
1899 cmd->cmd_dword[0] |= htole64((uint64_t)devid << CMD_DEVID_SHIFT);
1900 }
1901
1902 static __inline void
cmd_format_size(struct its_cmd * cmd,uint16_t size)1903 cmd_format_size(struct its_cmd *cmd, uint16_t size)
1904 {
1905 /* Size field: DW1 [4:0] */
1906 cmd->cmd_dword[1] &= htole64(~CMD_SIZE_MASK);
1907 cmd->cmd_dword[1] |= htole64((size & CMD_SIZE_MASK));
1908 }
1909
1910 static __inline void
cmd_format_id(struct its_cmd * cmd,uint32_t id)1911 cmd_format_id(struct its_cmd *cmd, uint32_t id)
1912 {
1913 /* ID field: DW1 [31:0] */
1914 cmd->cmd_dword[1] &= htole64(~CMD_ID_MASK);
1915 cmd->cmd_dword[1] |= htole64(id);
1916 }
1917
1918 static __inline void
cmd_format_pid(struct its_cmd * cmd,uint32_t pid)1919 cmd_format_pid(struct its_cmd *cmd, uint32_t pid)
1920 {
1921 /* Physical ID field: DW1 [63:32] */
1922 cmd->cmd_dword[1] &= htole64(~CMD_PID_MASK);
1923 cmd->cmd_dword[1] |= htole64((uint64_t)pid << CMD_PID_SHIFT);
1924 }
1925
1926 static __inline void
cmd_format_col(struct its_cmd * cmd,uint16_t col_id)1927 cmd_format_col(struct its_cmd *cmd, uint16_t col_id)
1928 {
1929 /* Collection field: DW2 [16:0] */
1930 cmd->cmd_dword[2] &= htole64(~CMD_COL_MASK);
1931 cmd->cmd_dword[2] |= htole64(col_id);
1932 }
1933
1934 static __inline void
cmd_format_target(struct its_cmd * cmd,uint64_t target)1935 cmd_format_target(struct its_cmd *cmd, uint64_t target)
1936 {
1937 /* Target Address field: DW2 [47:16] */
1938 cmd->cmd_dword[2] &= htole64(~CMD_TARGET_MASK);
1939 cmd->cmd_dword[2] |= htole64(target & CMD_TARGET_MASK);
1940 }
1941
1942 static __inline void
cmd_format_itt(struct its_cmd * cmd,uint64_t itt)1943 cmd_format_itt(struct its_cmd *cmd, uint64_t itt)
1944 {
1945 /* ITT Address field: DW2 [47:8] */
1946 cmd->cmd_dword[2] &= htole64(~CMD_ITT_MASK);
1947 cmd->cmd_dword[2] |= htole64(itt & CMD_ITT_MASK);
1948 }
1949
1950 static __inline void
cmd_format_valid(struct its_cmd * cmd,uint8_t valid)1951 cmd_format_valid(struct its_cmd *cmd, uint8_t valid)
1952 {
1953 /* Valid field: DW2 [63] */
1954 cmd->cmd_dword[2] &= htole64(~CMD_VALID_MASK);
1955 cmd->cmd_dword[2] |= htole64((uint64_t)valid << CMD_VALID_SHIFT);
1956 }
1957
1958 static inline bool
its_cmd_queue_full(struct gicv3_its_softc * sc)1959 its_cmd_queue_full(struct gicv3_its_softc *sc)
1960 {
1961 size_t read_idx, next_write_idx;
1962
1963 /* Get the index of the next command */
1964 next_write_idx = (sc->sc_its_cmd_next_idx + 1) %
1965 (ITS_CMDQ_SIZE / sizeof(struct its_cmd));
1966 /* And the index of the current command being read */
1967 read_idx = gic_its_read_4(sc, GITS_CREADR) / sizeof(struct its_cmd);
1968
1969 /*
1970 * The queue is full when the write offset points
1971 * at the command before the current read offset.
1972 */
1973 return (next_write_idx == read_idx);
1974 }
1975
1976 static inline void
its_cmd_sync(struct gicv3_its_softc * sc,struct its_cmd * cmd)1977 its_cmd_sync(struct gicv3_its_softc *sc, struct its_cmd *cmd)
1978 {
1979
1980 if ((sc->sc_its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0) {
1981 /* Clean D-cache under command. */
1982 cpu_dcache_wb_range(cmd, sizeof(*cmd));
1983 } else {
1984 /* DSB inner shareable, store */
1985 dsb(ishst);
1986 }
1987
1988 }
1989
1990 static inline uint64_t
its_cmd_cwriter_offset(struct gicv3_its_softc * sc,struct its_cmd * cmd)1991 its_cmd_cwriter_offset(struct gicv3_its_softc *sc, struct its_cmd *cmd)
1992 {
1993 uint64_t off;
1994
1995 off = (cmd - sc->sc_its_cmd_base) * sizeof(*cmd);
1996
1997 return (off);
1998 }
1999
2000 static void
its_cmd_wait_completion(device_t dev,struct its_cmd * cmd_first,struct its_cmd * cmd_last)2001 its_cmd_wait_completion(device_t dev, struct its_cmd *cmd_first,
2002 struct its_cmd *cmd_last)
2003 {
2004 struct gicv3_its_softc *sc;
2005 uint64_t first, last, read;
2006 size_t us_left;
2007
2008 sc = device_get_softc(dev);
2009
2010 /*
2011 * XXX ARM64TODO: This is obviously a significant delay.
2012 * The reason for that is that currently the time frames for
2013 * the command to complete are not known.
2014 */
2015 us_left = 1000000;
2016
2017 first = its_cmd_cwriter_offset(sc, cmd_first);
2018 last = its_cmd_cwriter_offset(sc, cmd_last);
2019
2020 for (;;) {
2021 read = gic_its_read_8(sc, GITS_CREADR);
2022 if (first < last) {
2023 if (read < first || read >= last)
2024 break;
2025 } else if (read < first && read >= last)
2026 break;
2027
2028 if (us_left-- == 0) {
2029 /* This means timeout */
2030 device_printf(dev,
2031 "Timeout while waiting for CMD completion.\n");
2032 return;
2033 }
2034 DELAY(1);
2035 }
2036 }
2037
2038 static struct its_cmd *
its_cmd_alloc_locked(device_t dev)2039 its_cmd_alloc_locked(device_t dev)
2040 {
2041 struct gicv3_its_softc *sc;
2042 struct its_cmd *cmd;
2043 size_t us_left;
2044
2045 sc = device_get_softc(dev);
2046
2047 /*
2048 * XXX ARM64TODO: This is obviously a significant delay.
2049 * The reason for that is that currently the time frames for
2050 * the command to complete (and therefore free the descriptor)
2051 * are not known.
2052 */
2053 us_left = 1000000;
2054
2055 mtx_assert(&sc->sc_its_cmd_lock, MA_OWNED);
2056 while (its_cmd_queue_full(sc)) {
2057 if (us_left-- == 0) {
2058 /* Timeout while waiting for free command */
2059 device_printf(dev,
2060 "Timeout while waiting for free command\n");
2061 return (NULL);
2062 }
2063 DELAY(1);
2064 }
2065
2066 cmd = &sc->sc_its_cmd_base[sc->sc_its_cmd_next_idx];
2067 sc->sc_its_cmd_next_idx++;
2068 sc->sc_its_cmd_next_idx %= ITS_CMDQ_SIZE / sizeof(struct its_cmd);
2069
2070 return (cmd);
2071 }
2072
2073 static uint64_t
its_cmd_prepare(struct its_cmd * cmd,struct its_cmd_desc * desc)2074 its_cmd_prepare(struct its_cmd *cmd, struct its_cmd_desc *desc)
2075 {
2076 uint64_t target;
2077 uint8_t cmd_type;
2078 u_int size;
2079
2080 cmd_type = desc->cmd_type;
2081 target = ITS_TARGET_NONE;
2082
2083 switch (cmd_type) {
2084 case ITS_CMD_MOVI: /* Move interrupt ID to another collection */
2085 target = desc->cmd_desc_movi.col->col_target;
2086 cmd_format_command(cmd, ITS_CMD_MOVI);
2087 cmd_format_id(cmd, desc->cmd_desc_movi.id);
2088 cmd_format_col(cmd, desc->cmd_desc_movi.col->col_id);
2089 cmd_format_devid(cmd, desc->cmd_desc_movi.its_dev->devid);
2090 break;
2091 case ITS_CMD_SYNC: /* Wait for previous commands completion */
2092 target = desc->cmd_desc_sync.col->col_target;
2093 cmd_format_command(cmd, ITS_CMD_SYNC);
2094 cmd_format_target(cmd, target);
2095 break;
2096 case ITS_CMD_MAPD: /* Assign ITT to device */
2097 cmd_format_command(cmd, ITS_CMD_MAPD);
2098 cmd_format_itt(cmd, vtophys(desc->cmd_desc_mapd.its_dev->itt));
2099 /*
2100 * Size describes number of bits to encode interrupt IDs
2101 * supported by the device minus one.
2102 * When V (valid) bit is zero, this field should be written
2103 * as zero.
2104 */
2105 if (desc->cmd_desc_mapd.valid != 0) {
2106 size = fls(desc->cmd_desc_mapd.its_dev->lpis.lpi_num);
2107 size = MAX(1, size) - 1;
2108 } else
2109 size = 0;
2110
2111 cmd_format_size(cmd, size);
2112 cmd_format_devid(cmd, desc->cmd_desc_mapd.its_dev->devid);
2113 cmd_format_valid(cmd, desc->cmd_desc_mapd.valid);
2114 break;
2115 case ITS_CMD_MAPC: /* Map collection to Re-Distributor */
2116 target = desc->cmd_desc_mapc.col->col_target;
2117 cmd_format_command(cmd, ITS_CMD_MAPC);
2118 cmd_format_col(cmd, desc->cmd_desc_mapc.col->col_id);
2119 cmd_format_valid(cmd, desc->cmd_desc_mapc.valid);
2120 cmd_format_target(cmd, target);
2121 break;
2122 case ITS_CMD_MAPTI:
2123 target = desc->cmd_desc_mapvi.col->col_target;
2124 cmd_format_command(cmd, ITS_CMD_MAPTI);
2125 cmd_format_devid(cmd, desc->cmd_desc_mapvi.its_dev->devid);
2126 cmd_format_id(cmd, desc->cmd_desc_mapvi.id);
2127 cmd_format_pid(cmd, desc->cmd_desc_mapvi.pid);
2128 cmd_format_col(cmd, desc->cmd_desc_mapvi.col->col_id);
2129 break;
2130 case ITS_CMD_MAPI:
2131 target = desc->cmd_desc_mapi.col->col_target;
2132 cmd_format_command(cmd, ITS_CMD_MAPI);
2133 cmd_format_devid(cmd, desc->cmd_desc_mapi.its_dev->devid);
2134 cmd_format_id(cmd, desc->cmd_desc_mapi.pid);
2135 cmd_format_col(cmd, desc->cmd_desc_mapi.col->col_id);
2136 break;
2137 case ITS_CMD_INV:
2138 target = desc->cmd_desc_inv.col->col_target;
2139 cmd_format_command(cmd, ITS_CMD_INV);
2140 cmd_format_devid(cmd, desc->cmd_desc_inv.its_dev->devid);
2141 cmd_format_id(cmd, desc->cmd_desc_inv.pid);
2142 break;
2143 case ITS_CMD_INVALL:
2144 cmd_format_command(cmd, ITS_CMD_INVALL);
2145 cmd_format_col(cmd, desc->cmd_desc_invall.col->col_id);
2146 break;
2147 default:
2148 panic("its_cmd_prepare: Invalid command: %x", cmd_type);
2149 }
2150
2151 return (target);
2152 }
2153
2154 static int
its_cmd_send(device_t dev,struct its_cmd_desc * desc)2155 its_cmd_send(device_t dev, struct its_cmd_desc *desc)
2156 {
2157 struct gicv3_its_softc *sc;
2158 struct its_cmd *cmd, *cmd_sync, *cmd_write;
2159 struct its_col col_sync;
2160 struct its_cmd_desc desc_sync;
2161 uint64_t target, cwriter;
2162
2163 sc = device_get_softc(dev);
2164 mtx_lock_spin(&sc->sc_its_cmd_lock);
2165 cmd = its_cmd_alloc_locked(dev);
2166 if (cmd == NULL) {
2167 device_printf(dev, "could not allocate ITS command\n");
2168 mtx_unlock_spin(&sc->sc_its_cmd_lock);
2169 return (EBUSY);
2170 }
2171
2172 target = its_cmd_prepare(cmd, desc);
2173 its_cmd_sync(sc, cmd);
2174
2175 if (target != ITS_TARGET_NONE) {
2176 cmd_sync = its_cmd_alloc_locked(dev);
2177 if (cmd_sync != NULL) {
2178 desc_sync.cmd_type = ITS_CMD_SYNC;
2179 col_sync.col_target = target;
2180 desc_sync.cmd_desc_sync.col = &col_sync;
2181 its_cmd_prepare(cmd_sync, &desc_sync);
2182 its_cmd_sync(sc, cmd_sync);
2183 }
2184 }
2185
2186 /* Update GITS_CWRITER */
2187 cwriter = sc->sc_its_cmd_next_idx * sizeof(struct its_cmd);
2188 gic_its_write_8(sc, GITS_CWRITER, cwriter);
2189 cmd_write = &sc->sc_its_cmd_base[sc->sc_its_cmd_next_idx];
2190 mtx_unlock_spin(&sc->sc_its_cmd_lock);
2191
2192 its_cmd_wait_completion(dev, cmd, cmd_write);
2193
2194 return (0);
2195 }
2196
2197 /* Handlers to send commands */
2198 static void
its_cmd_movi(device_t dev,struct gicv3_its_irqsrc * girq)2199 its_cmd_movi(device_t dev, struct gicv3_its_irqsrc *girq)
2200 {
2201 struct gicv3_its_softc *sc;
2202 struct its_cmd_desc desc;
2203 struct its_col *col;
2204
2205 sc = device_get_softc(dev);
2206 col = sc->sc_its_cols[CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1];
2207
2208 desc.cmd_type = ITS_CMD_MOVI;
2209 desc.cmd_desc_movi.its_dev = girq->gi_its_dev;
2210 desc.cmd_desc_movi.col = col;
2211 desc.cmd_desc_movi.id = girq->gi_id;
2212
2213 its_cmd_send(dev, &desc);
2214 }
2215
2216 static void
its_cmd_mapc(device_t dev,struct its_col * col,uint8_t valid)2217 its_cmd_mapc(device_t dev, struct its_col *col, uint8_t valid)
2218 {
2219 struct its_cmd_desc desc;
2220
2221 desc.cmd_type = ITS_CMD_MAPC;
2222 desc.cmd_desc_mapc.col = col;
2223 /*
2224 * Valid bit set - map the collection.
2225 * Valid bit cleared - unmap the collection.
2226 */
2227 desc.cmd_desc_mapc.valid = valid;
2228
2229 its_cmd_send(dev, &desc);
2230 }
2231
2232 static void
its_cmd_mapti(device_t dev,struct gicv3_its_irqsrc * girq)2233 its_cmd_mapti(device_t dev, struct gicv3_its_irqsrc *girq)
2234 {
2235 struct gicv3_its_softc *sc;
2236 struct its_cmd_desc desc;
2237 struct its_col *col;
2238 u_int col_id;
2239
2240 sc = device_get_softc(dev);
2241
2242 col_id = CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1;
2243 col = sc->sc_its_cols[col_id];
2244
2245 desc.cmd_type = ITS_CMD_MAPTI;
2246 desc.cmd_desc_mapvi.its_dev = girq->gi_its_dev;
2247 desc.cmd_desc_mapvi.col = col;
2248 /* The EventID sent to the device */
2249 desc.cmd_desc_mapvi.id = girq->gi_id;
2250 /* The physical interrupt presented to softeware */
2251 desc.cmd_desc_mapvi.pid = girq->gi_lpi + GIC_FIRST_LPI;
2252
2253 its_cmd_send(dev, &desc);
2254 }
2255
2256 static void
its_cmd_mapd(device_t dev,struct its_dev * its_dev,uint8_t valid)2257 its_cmd_mapd(device_t dev, struct its_dev *its_dev, uint8_t valid)
2258 {
2259 struct its_cmd_desc desc;
2260
2261 desc.cmd_type = ITS_CMD_MAPD;
2262 desc.cmd_desc_mapd.its_dev = its_dev;
2263 desc.cmd_desc_mapd.valid = valid;
2264
2265 its_cmd_send(dev, &desc);
2266 }
2267
2268 static void
its_cmd_inv(device_t dev,struct its_dev * its_dev,struct gicv3_its_irqsrc * girq)2269 its_cmd_inv(device_t dev, struct its_dev *its_dev,
2270 struct gicv3_its_irqsrc *girq)
2271 {
2272 struct gicv3_its_softc *sc;
2273 struct its_cmd_desc desc;
2274 struct its_col *col;
2275
2276 sc = device_get_softc(dev);
2277 col = sc->sc_its_cols[CPU_FFS(&girq->gi_isrc.isrc_cpu) - 1];
2278
2279 desc.cmd_type = ITS_CMD_INV;
2280 /* The EventID sent to the device */
2281 desc.cmd_desc_inv.pid = girq->gi_id;
2282 desc.cmd_desc_inv.its_dev = its_dev;
2283 desc.cmd_desc_inv.col = col;
2284
2285 its_cmd_send(dev, &desc);
2286 }
2287
2288 static void
its_cmd_invall(device_t dev,struct its_col * col)2289 its_cmd_invall(device_t dev, struct its_col *col)
2290 {
2291 struct its_cmd_desc desc;
2292
2293 desc.cmd_type = ITS_CMD_INVALL;
2294 desc.cmd_desc_invall.col = col;
2295
2296 its_cmd_send(dev, &desc);
2297 }
2298
2299 #ifdef FDT
2300 static device_probe_t gicv3_its_fdt_probe;
2301 static device_attach_t gicv3_its_fdt_attach;
2302
2303 static device_method_t gicv3_its_fdt_methods[] = {
2304 /* Device interface */
2305 DEVMETHOD(device_probe, gicv3_its_fdt_probe),
2306 DEVMETHOD(device_attach, gicv3_its_fdt_attach),
2307
2308 /* End */
2309 DEVMETHOD_END
2310 };
2311
2312 #define its_baseclasses its_fdt_baseclasses
2313 DEFINE_CLASS_1(its, gicv3_its_fdt_driver, gicv3_its_fdt_methods,
2314 sizeof(struct gicv3_its_softc), gicv3_its_driver);
2315 #undef its_baseclasses
2316
2317 EARLY_DRIVER_MODULE(its_fdt, gic, gicv3_its_fdt_driver, 0, 0,
2318 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
2319
2320 static int
gicv3_its_fdt_probe(device_t dev)2321 gicv3_its_fdt_probe(device_t dev)
2322 {
2323
2324 if (!ofw_bus_status_okay(dev))
2325 return (ENXIO);
2326
2327 if (!ofw_bus_is_compatible(dev, "arm,gic-v3-its"))
2328 return (ENXIO);
2329
2330 if (!gic_get_support_lpis(dev))
2331 return (ENXIO);
2332
2333 device_set_desc(dev, "ARM GIC Interrupt Translation Service");
2334 return (BUS_PROBE_DEFAULT);
2335 }
2336
2337 static int
gicv3_its_fdt_attach(device_t dev)2338 gicv3_its_fdt_attach(device_t dev)
2339 {
2340 struct gicv3_its_softc *sc;
2341 phandle_t xref, node;
2342 int err;
2343
2344 sc = device_get_softc(dev);
2345 sc->dev = dev;
2346 node = ofw_bus_get_node(dev);
2347 err = gicv3_its_attach(dev);
2348 if (err != 0)
2349 return (err);
2350
2351 if (OF_hasprop(node, "dma-noncoherent"))
2352 sc->sc_its_flags |= ITS_FLAGS_FORCE_NOSHAREABLE;
2353 /* Register this device as a interrupt controller */
2354 xref = OF_xref_from_node(node);
2355 sc->sc_pic = intr_pic_register(dev, xref);
2356 err = intr_pic_add_handler(device_get_parent(dev), sc->sc_pic,
2357 gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length);
2358 if (err != 0) {
2359 device_printf(dev, "Failed to add PIC handler: %d\n", err);
2360 return (err);
2361 }
2362
2363 /* Register this device to handle MSI interrupts */
2364 err = intr_msi_register(dev, xref);
2365 if (err != 0) {
2366 device_printf(dev, "Failed to register for MSIs: %d\n", err);
2367 return (err);
2368 }
2369
2370 return (0);
2371 }
2372 #endif
2373
2374 #ifdef DEV_ACPI
2375 static device_probe_t gicv3_its_acpi_probe;
2376 static device_attach_t gicv3_its_acpi_attach;
2377
2378 static device_method_t gicv3_its_acpi_methods[] = {
2379 /* Device interface */
2380 DEVMETHOD(device_probe, gicv3_its_acpi_probe),
2381 DEVMETHOD(device_attach, gicv3_its_acpi_attach),
2382
2383 /* End */
2384 DEVMETHOD_END
2385 };
2386
2387 #define its_baseclasses its_acpi_baseclasses
2388 DEFINE_CLASS_1(its, gicv3_its_acpi_driver, gicv3_its_acpi_methods,
2389 sizeof(struct gicv3_its_softc), gicv3_its_driver);
2390 #undef its_baseclasses
2391
2392 EARLY_DRIVER_MODULE(its_acpi, gic, gicv3_its_acpi_driver, 0, 0,
2393 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
2394
2395 static int
gicv3_its_acpi_probe(device_t dev)2396 gicv3_its_acpi_probe(device_t dev)
2397 {
2398
2399 if (gic_get_bus(dev) != GIC_BUS_ACPI)
2400 return (EINVAL);
2401
2402 if (gic_get_hw_rev(dev) < 3)
2403 return (EINVAL);
2404
2405 if (!gic_get_support_lpis(dev))
2406 return (ENXIO);
2407
2408 device_set_desc(dev, "ARM GIC Interrupt Translation Service");
2409 return (BUS_PROBE_DEFAULT);
2410 }
2411
2412 static int
gicv3_its_acpi_attach(device_t dev)2413 gicv3_its_acpi_attach(device_t dev)
2414 {
2415 struct gicv3_its_softc *sc;
2416 struct gic_v3_devinfo *di;
2417 int err;
2418
2419 sc = device_get_softc(dev);
2420 sc->dev = dev;
2421 err = gicv3_its_attach(dev);
2422 if (err != 0)
2423 return (err);
2424
2425 di = device_get_ivars(dev);
2426 sc->sc_pic = intr_pic_register(dev, di->msi_xref);
2427 err = intr_pic_add_handler(device_get_parent(dev), sc->sc_pic,
2428 gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length);
2429 if (err != 0) {
2430 device_printf(dev, "Failed to add PIC handler: %d\n", err);
2431 return (err);
2432 }
2433
2434 /* Register this device to handle MSI interrupts */
2435 err = intr_msi_register(dev, di->msi_xref);
2436 if (err != 0) {
2437 device_printf(dev, "Failed to register for MSIs: %d\n", err);
2438 return (err);
2439 }
2440
2441 return (0);
2442 }
2443 #endif
2444