1 /*
2 * Copyright (c) 2018-2019 Cavium, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 /*
29 * File: qlnxr_os.c
30 */
31 #include <sys/cdefs.h>
32 #include "qlnxr_def.h"
33
34 SYSCTL_NODE(_dev, OID_AUTO, qnxr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
35 "Qlogic RDMA module");
36
37 uint32_t delayed_ack = 0;
38 SYSCTL_UINT(_dev_qnxr, OID_AUTO, delayed_ack, CTLFLAG_RW, &delayed_ack, 1,
39 "iWARP: Delayed Ack: 0 - Disabled 1 - Enabled. Default: Disabled");
40
41 uint32_t timestamp = 1;
42 SYSCTL_UINT(_dev_qnxr, OID_AUTO, timestamp, CTLFLAG_RW, ×tamp, 1,
43 "iWARP: Timestamp: 0 - Disabled 1 - Enabled. Default:Enabled");
44
45 uint32_t rcv_wnd_size = 0;
46 SYSCTL_UINT(_dev_qnxr, OID_AUTO, rcv_wnd_size, CTLFLAG_RW, &rcv_wnd_size, 1,
47 "iWARP: Receive Window Size in K. Default 1M");
48
49 uint32_t crc_needed = 1;
50 SYSCTL_UINT(_dev_qnxr, OID_AUTO, crc_needed, CTLFLAG_RW, &crc_needed, 1,
51 "iWARP: CRC needed 0 - Disabled 1 - Enabled. Default:Enabled");
52
53 uint32_t peer2peer = 1;
54 SYSCTL_UINT(_dev_qnxr, OID_AUTO, peer2peer, CTLFLAG_RW, &peer2peer, 1,
55 "iWARP: Support peer2peer ULPs 0 - Disabled 1 - Enabled. Default:Enabled");
56
57 uint32_t mpa_enhanced = 1;
58 SYSCTL_UINT(_dev_qnxr, OID_AUTO, mpa_enhanced, CTLFLAG_RW, &mpa_enhanced, 1,
59 "iWARP: MPA Enhanced mode. Default:1");
60
61 uint32_t rtr_type = 7;
62 SYSCTL_UINT(_dev_qnxr, OID_AUTO, rtr_type, CTLFLAG_RW, &rtr_type, 1,
63 "iWARP: RDMAP opcode to use for the RTR message: BITMAP 1: RDMA_SEND 2: RDMA_WRITE 4: RDMA_READ. Default: 7");
64
65 #define QNXR_WQ_MULTIPLIER_MIN (1)
66 #define QNXR_WQ_MULTIPLIER_MAX (7)
67 #define QNXR_WQ_MULTIPLIER_DFT (3)
68
69 uint32_t wq_multiplier= QNXR_WQ_MULTIPLIER_DFT;
70 SYSCTL_UINT(_dev_qnxr, OID_AUTO, wq_multiplier, CTLFLAG_RW, &wq_multiplier, 1,
71 " When creating a WQ the actual number of WQE created will"
72 " be multiplied by this number (default is 3).");
73 static ssize_t
show_rev(struct device * device,struct device_attribute * attr,char * buf)74 show_rev(struct device *device, struct device_attribute *attr,
75 char *buf)
76 {
77 struct qlnxr_dev *dev = dev_get_drvdata(device);
78
79 return sprintf(buf, "0x%x\n", dev->cdev->vendor_id);
80 }
81
82 static ssize_t
show_hca_type(struct device * device,struct device_attribute * attr,char * buf)83 show_hca_type(struct device *device,
84 struct device_attribute *attr, char *buf)
85 {
86 struct qlnxr_dev *dev = dev_get_drvdata(device);
87 return sprintf(buf, "QLogic0x%x\n", dev->cdev->device_id);
88 }
89
90 static ssize_t
show_fw_ver(struct device * device,struct device_attribute * attr,char * buf)91 show_fw_ver(struct device *device,
92 struct device_attribute *attr, char *buf)
93 {
94 struct qlnxr_dev *dev = dev_get_drvdata(device);
95 uint32_t fw_ver = (uint32_t) dev->attr.fw_ver;
96
97 return sprintf(buf, "%d.%d.%d\n",
98 (fw_ver >> 24) & 0xff, (fw_ver >> 16) & 0xff,
99 (fw_ver >> 8) & 0xff);
100 }
101 static ssize_t
show_board(struct device * device,struct device_attribute * attr,char * buf)102 show_board(struct device *device,
103 struct device_attribute *attr, char *buf)
104 {
105 struct qlnxr_dev *dev = dev_get_drvdata(device);
106 return sprintf(buf, "%x\n", dev->cdev->device_id);
107 }
108
109 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
110 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL);
111 static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
112 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
113
114 static struct device_attribute *qlnxr_class_attributes[] = {
115 &dev_attr_hw_rev,
116 &dev_attr_hca_type,
117 &dev_attr_fw_ver,
118 &dev_attr_board_id
119 };
120
121 static void
qlnxr_ib_dispatch_event(qlnxr_dev_t * dev,uint8_t port_num,enum ib_event_type type)122 qlnxr_ib_dispatch_event(qlnxr_dev_t *dev, uint8_t port_num,
123 enum ib_event_type type)
124 {
125 struct ib_event ibev;
126
127 QL_DPRINT12(dev->ha, "enter\n");
128
129 ibev.device = &dev->ibdev;
130 ibev.element.port_num = port_num;
131 ibev.event = type;
132
133 ib_dispatch_event(&ibev);
134
135 QL_DPRINT12(dev->ha, "exit\n");
136 }
137
138 static int
__qlnxr_iw_destroy_listen(struct iw_cm_id * cm_id)139 __qlnxr_iw_destroy_listen(struct iw_cm_id *cm_id)
140 {
141 qlnxr_iw_destroy_listen(cm_id);
142
143 return (0);
144 }
145
146 static int
qlnxr_register_device(qlnxr_dev_t * dev)147 qlnxr_register_device(qlnxr_dev_t *dev)
148 {
149 struct ib_device *ibdev;
150 struct iw_cm_verbs *iwcm;
151 int ret;
152
153 QL_DPRINT12(dev->ha, "enter\n");
154
155 ibdev = &dev->ibdev;
156
157 #define qlnxr_ib_ah qlnxr_ah
158 #define qlnxr_ib_cq qlnxr_cq
159 #define qlnxr_ib_pd qlnxr_pd
160 #define qlnxr_ib_qp qlnxr_qp
161 #define qlnxr_ib_srq qlnxr_srq
162 #define qlnxr_ib_ucontext qlnxr_ucontext
163 INIT_IB_DEVICE_OPS(&ibdev->ops, qlnxr, QLNXR);
164 strlcpy(ibdev->name, "qlnxr%d", IB_DEVICE_NAME_MAX);
165
166 memset(&ibdev->node_guid, 0, sizeof(ibdev->node_guid));
167 memcpy(&ibdev->node_guid, dev->ha->primary_mac, ETHER_ADDR_LEN);
168
169 memcpy(ibdev->node_desc, QLNXR_NODE_DESC, sizeof(QLNXR_NODE_DESC));
170
171 ibdev->owner = THIS_MODULE;
172 ibdev->uverbs_abi_ver = 7;
173 ibdev->local_dma_lkey = 0;
174
175 ibdev->uverbs_cmd_mask =
176 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
177 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
178 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
179 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
180 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
181 (1ull << IB_USER_VERBS_CMD_REG_MR) |
182 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
183 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
184 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
185 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
186 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
187 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
188 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
189 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
190 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
191 (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
192 (1ull << IB_USER_VERBS_CMD_POST_SEND) |
193 (1ull << IB_USER_VERBS_CMD_POST_RECV);
194
195 if (QLNX_IS_IWARP(dev)) {
196 ibdev->node_type = RDMA_NODE_RNIC;
197 ibdev->query_gid = qlnxr_iw_query_gid;
198 } else {
199 ibdev->node_type = RDMA_NODE_IB_CA;
200 ibdev->uverbs_cmd_mask |=
201 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
202 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
203 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
204 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
205 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
206 ibdev->create_srq = qlnxr_create_srq;
207 ibdev->destroy_srq = qlnxr_destroy_srq;
208 ibdev->modify_srq = qlnxr_modify_srq;
209 ibdev->query_srq = qlnxr_query_srq;
210 ibdev->post_srq_recv = qlnxr_post_srq_recv;
211 }
212
213 ibdev->phys_port_cnt = 1;
214 ibdev->num_comp_vectors = dev->num_cnq;
215
216 /* mandatory verbs. */
217 ibdev->query_device = qlnxr_query_device;
218 ibdev->query_port = qlnxr_query_port;
219 ibdev->modify_port = qlnxr_modify_port;
220
221 ibdev->alloc_ucontext = qlnxr_alloc_ucontext;
222 ibdev->dealloc_ucontext = qlnxr_dealloc_ucontext;
223 /* mandatory to support user space verbs consumer. */
224 ibdev->mmap = qlnxr_mmap;
225
226 ibdev->alloc_pd = qlnxr_alloc_pd;
227 ibdev->dealloc_pd = qlnxr_dealloc_pd;
228
229 ibdev->create_cq = qlnxr_create_cq;
230 ibdev->destroy_cq = qlnxr_destroy_cq;
231 ibdev->resize_cq = qlnxr_resize_cq;
232 ibdev->req_notify_cq = qlnxr_arm_cq;
233
234 ibdev->create_qp = qlnxr_create_qp;
235 ibdev->modify_qp = qlnxr_modify_qp;
236 ibdev->query_qp = qlnxr_query_qp;
237 ibdev->destroy_qp = qlnxr_destroy_qp;
238
239 ibdev->query_pkey = qlnxr_query_pkey;
240 ibdev->create_ah = qlnxr_create_ah;
241 ibdev->destroy_ah = qlnxr_destroy_ah;
242 ibdev->query_ah = qlnxr_query_ah;
243 ibdev->modify_ah = qlnxr_modify_ah;
244 ibdev->get_dma_mr = qlnxr_get_dma_mr;
245 ibdev->dereg_mr = qlnxr_dereg_mr;
246 ibdev->reg_user_mr = qlnxr_reg_user_mr;
247
248 ibdev->alloc_mr = qlnxr_alloc_mr;
249 ibdev->map_mr_sg = qlnxr_map_mr_sg;
250 ibdev->get_port_immutable = qlnxr_get_port_immutable;
251
252 ibdev->poll_cq = qlnxr_poll_cq;
253 ibdev->post_send = qlnxr_post_send;
254 ibdev->post_recv = qlnxr_post_recv;
255 ibdev->process_mad = qlnxr_process_mad;
256
257 ibdev->dma_device = &dev->pdev.dev;
258
259 ibdev->get_link_layer = qlnxr_link_layer;
260
261 if (QLNX_IS_IWARP(dev)) {
262 iwcm = kmalloc(sizeof(*iwcm), GFP_KERNEL);
263
264 device_printf(dev->ha->pci_dev, "device is IWARP\n");
265 if (iwcm == NULL)
266 return (-ENOMEM);
267
268 ibdev->iwcm = iwcm;
269
270 iwcm->connect = qlnxr_iw_connect;
271 iwcm->accept = qlnxr_iw_accept;
272 iwcm->reject = qlnxr_iw_reject;
273
274 iwcm->create_listen = qlnxr_iw_create_listen;
275 iwcm->destroy_listen = __qlnxr_iw_destroy_listen;
276
277 iwcm->add_ref = qlnxr_iw_qp_add_ref;
278 iwcm->rem_ref = qlnxr_iw_qp_rem_ref;
279 iwcm->get_qp = qlnxr_iw_get_qp;
280 }
281
282 ret = ib_register_device(ibdev, NULL);
283 if (ret) {
284 kfree(iwcm);
285 }
286
287 QL_DPRINT12(dev->ha, "exit\n");
288 return ret;
289 }
290
291 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
292
293 static void
qlnxr_intr(void * handle)294 qlnxr_intr(void *handle)
295 {
296 struct qlnxr_cnq *cnq = handle;
297 struct qlnxr_cq *cq;
298 struct regpair *cq_handle;
299 u16 hw_comp_cons, sw_comp_cons;
300 qlnx_host_t *ha;
301
302 ha = cnq->dev->ha;
303
304 QL_DPRINT12(ha, "enter cnq = %p\n", handle);
305
306 ecore_sb_ack(cnq->sb, IGU_INT_DISABLE, 0 /*do not update*/);
307
308 ecore_sb_update_sb_idx(cnq->sb);
309
310 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
311 sw_comp_cons = ecore_chain_get_cons_idx(&cnq->pbl);
312
313 rmb();
314
315 QL_DPRINT12(ha, "enter cnq = %p hw_comp_cons = 0x%x sw_comp_cons = 0x%x\n",
316 handle, hw_comp_cons, sw_comp_cons);
317
318 while (sw_comp_cons != hw_comp_cons) {
319 cq_handle = (struct regpair *)ecore_chain_consume(&cnq->pbl);
320 cq = (struct qlnxr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
321 cq_handle->lo);
322
323 if (cq == NULL) {
324 QL_DPRINT11(ha, "cq == NULL\n");
325 break;
326 }
327
328 if (cq->sig != QLNXR_CQ_MAGIC_NUMBER) {
329 QL_DPRINT11(ha,
330 "cq->sig = 0x%x QLNXR_CQ_MAGIC_NUMBER = 0x%x\n",
331 cq->sig, QLNXR_CQ_MAGIC_NUMBER);
332 break;
333 }
334 cq->arm_flags = 0;
335
336 if (!cq->destroyed && cq->ibcq.comp_handler) {
337 QL_DPRINT11(ha, "calling comp_handler = %p "
338 "ibcq = %p cq_context = 0x%x\n",
339 &cq->ibcq, cq->ibcq.cq_context);
340
341 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
342 }
343 cq->cnq_notif++;
344
345 sw_comp_cons = ecore_chain_get_cons_idx(&cnq->pbl);
346
347 cnq->n_comp++;
348 }
349
350 ecore_rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index, sw_comp_cons);
351
352 ecore_sb_ack(cnq->sb, IGU_INT_ENABLE, 1 /*update*/);
353
354 QL_DPRINT12(ha, "exit cnq = %p\n", handle);
355 return;
356 }
357
358 static void
qlnxr_release_irqs(struct qlnxr_dev * dev)359 qlnxr_release_irqs(struct qlnxr_dev *dev)
360 {
361 int i;
362 qlnx_host_t *ha;
363
364 ha = dev->ha;
365
366 QL_DPRINT12(ha, "enter\n");
367
368 for (i = 0; i < dev->num_cnq; i++) {
369 if (dev->cnq_array[i].irq_handle)
370 (void)bus_teardown_intr(dev->ha->pci_dev,
371 dev->cnq_array[i].irq,
372 dev->cnq_array[i].irq_handle);
373
374 if (dev->cnq_array[i].irq)
375 (void) bus_release_resource(dev->ha->pci_dev,
376 SYS_RES_IRQ,
377 dev->cnq_array[i].irq_rid,
378 dev->cnq_array[i].irq);
379 }
380 QL_DPRINT12(ha, "exit\n");
381 return;
382 }
383
384 static int
qlnxr_setup_irqs(struct qlnxr_dev * dev)385 qlnxr_setup_irqs(struct qlnxr_dev *dev)
386 {
387 int start_irq_rid;
388 int i;
389 qlnx_host_t *ha;
390
391 ha = dev->ha;
392
393 start_irq_rid = dev->sb_start + 2;
394
395 QL_DPRINT12(ha, "enter start_irq_rid = %d num_rss = %d\n",
396 start_irq_rid, dev->ha->num_rss);
397
398 for (i = 0; i < dev->num_cnq; i++) {
399 dev->cnq_array[i].irq_rid = start_irq_rid + i;
400
401 dev->cnq_array[i].irq = bus_alloc_resource_any(dev->ha->pci_dev,
402 SYS_RES_IRQ,
403 &dev->cnq_array[i].irq_rid,
404 (RF_ACTIVE | RF_SHAREABLE));
405
406 if (dev->cnq_array[i].irq == NULL) {
407 QL_DPRINT11(ha,
408 "bus_alloc_resource_any failed irq_rid = %d\n",
409 dev->cnq_array[i].irq_rid);
410
411 goto qlnxr_setup_irqs_err;
412 }
413
414 if (bus_setup_intr(dev->ha->pci_dev,
415 dev->cnq_array[i].irq,
416 (INTR_TYPE_NET | INTR_MPSAFE),
417 NULL, qlnxr_intr, &dev->cnq_array[i],
418 &dev->cnq_array[i].irq_handle)) {
419 QL_DPRINT11(ha, "bus_setup_intr failed\n");
420 goto qlnxr_setup_irqs_err;
421 }
422 QL_DPRINT12(ha, "irq_rid = %d irq = %p irq_handle = %p\n",
423 dev->cnq_array[i].irq_rid, dev->cnq_array[i].irq,
424 dev->cnq_array[i].irq_handle);
425 }
426
427 QL_DPRINT12(ha, "exit\n");
428 return (0);
429
430 qlnxr_setup_irqs_err:
431 qlnxr_release_irqs(dev);
432
433 QL_DPRINT12(ha, "exit -1\n");
434 return (-1);
435 }
436
437 static void
qlnxr_free_resources(struct qlnxr_dev * dev)438 qlnxr_free_resources(struct qlnxr_dev *dev)
439 {
440 int i;
441 qlnx_host_t *ha;
442
443 ha = dev->ha;
444
445 QL_DPRINT12(ha, "enter dev->num_cnq = %d\n", dev->num_cnq);
446
447 if (QLNX_IS_IWARP(dev)) {
448 if (dev->iwarp_wq != NULL)
449 destroy_workqueue(dev->iwarp_wq);
450 }
451
452 for (i = 0; i < dev->num_cnq; i++) {
453 qlnx_free_mem_sb(dev->ha, &dev->sb_array[i]);
454 ecore_chain_free(&dev->ha->cdev, &dev->cnq_array[i].pbl);
455 }
456
457 bzero(dev->cnq_array, (sizeof(struct qlnxr_cnq) * QLNXR_MAX_MSIX));
458 bzero(dev->sb_array, (sizeof(struct ecore_sb_info) * QLNXR_MAX_MSIX));
459 bzero(dev->sgid_tbl, (sizeof(union ib_gid) * QLNXR_MAX_SGID));
460
461 if (mtx_initialized(&dev->idr_lock))
462 mtx_destroy(&dev->idr_lock);
463
464 if (mtx_initialized(&dev->sgid_lock))
465 mtx_destroy(&dev->sgid_lock);
466
467 QL_DPRINT12(ha, "exit\n");
468 return;
469 }
470
471 static int
qlnxr_alloc_resources(struct qlnxr_dev * dev)472 qlnxr_alloc_resources(struct qlnxr_dev *dev)
473 {
474 uint16_t n_entries;
475 int i, rc;
476 qlnx_host_t *ha;
477
478 ha = dev->ha;
479
480 QL_DPRINT12(ha, "enter\n");
481
482 bzero(dev->sgid_tbl, (sizeof (union ib_gid) * QLNXR_MAX_SGID));
483
484 mtx_init(&dev->idr_lock, "idr_lock", NULL, MTX_DEF);
485 mtx_init(&dev->sgid_lock, "sgid_lock", NULL, MTX_DEF);
486
487 idr_init(&dev->qpidr);
488
489 bzero(dev->sb_array, (sizeof (struct ecore_sb_info) * QLNXR_MAX_MSIX));
490 bzero(dev->cnq_array, (sizeof (struct qlnxr_cnq) * QLNXR_MAX_MSIX));
491
492 dev->sb_start = ecore_rdma_get_sb_id(dev->rdma_ctx, 0);
493
494 QL_DPRINT12(ha, "dev->sb_start = 0x%x\n", dev->sb_start);
495
496 /* Allocate CNQ PBLs */
497
498 n_entries = min_t(u32, ECORE_RDMA_MAX_CNQ_SIZE, QLNXR_ROCE_MAX_CNQ_SIZE);
499
500 for (i = 0; i < dev->num_cnq; i++) {
501 rc = qlnx_alloc_mem_sb(dev->ha, &dev->sb_array[i],
502 dev->sb_start + i);
503 if (rc)
504 goto qlnxr_alloc_resources_exit;
505
506 rc = ecore_chain_alloc(&dev->ha->cdev,
507 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
508 ECORE_CHAIN_MODE_PBL,
509 ECORE_CHAIN_CNT_TYPE_U16,
510 n_entries,
511 sizeof(struct regpair *),
512 &dev->cnq_array[i].pbl,
513 NULL);
514
515 /* configure cnq, except name since ibdev.name is still NULL */
516 dev->cnq_array[i].dev = dev;
517 dev->cnq_array[i].sb = &dev->sb_array[i];
518 dev->cnq_array[i].hw_cons_ptr =
519 &(dev->sb_array[i].sb_virt->pi_array[ECORE_ROCE_PROTOCOL_INDEX]);
520 dev->cnq_array[i].index = i;
521 sprintf(dev->cnq_array[i].name, "qlnxr%d@pci:%d",
522 i, (dev->ha->pci_func));
523 }
524
525 QL_DPRINT12(ha, "exit\n");
526 return 0;
527
528 qlnxr_alloc_resources_exit:
529
530 qlnxr_free_resources(dev);
531
532 QL_DPRINT12(ha, "exit -ENOMEM\n");
533 return -ENOMEM;
534 }
535
536 void
qlnxr_affiliated_event(void * context,u8 e_code,void * fw_handle)537 qlnxr_affiliated_event(void *context, u8 e_code, void *fw_handle)
538 {
539 #define EVENT_TYPE_NOT_DEFINED 0
540 #define EVENT_TYPE_CQ 1
541 #define EVENT_TYPE_QP 2
542 #define EVENT_TYPE_GENERAL 3
543
544 struct qlnxr_dev *dev = (struct qlnxr_dev *)context;
545 struct regpair *async_handle = (struct regpair *)fw_handle;
546 u64 roceHandle64 = ((u64)async_handle->hi << 32) + async_handle->lo;
547 struct qlnxr_cq *cq = (struct qlnxr_cq *)(uintptr_t)roceHandle64;
548 struct qlnxr_qp *qp = (struct qlnxr_qp *)(uintptr_t)roceHandle64;
549 u8 event_type = EVENT_TYPE_NOT_DEFINED;
550 struct ib_event event;
551 qlnx_host_t *ha;
552
553 ha = dev->ha;
554
555 QL_DPRINT12(ha, "enter context = %p e_code = 0x%x fw_handle = %p\n",
556 context, e_code, fw_handle);
557
558 if (QLNX_IS_IWARP(dev)) {
559 switch (e_code) {
560 case ECORE_IWARP_EVENT_CQ_OVERFLOW:
561 event.event = IB_EVENT_CQ_ERR;
562 event_type = EVENT_TYPE_CQ;
563 break;
564
565 default:
566 QL_DPRINT12(ha,
567 "unsupported event %d on handle=%llx\n",
568 e_code, roceHandle64);
569 break;
570 }
571 } else {
572 switch (e_code) {
573 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
574 event.event = IB_EVENT_CQ_ERR;
575 event_type = EVENT_TYPE_CQ;
576 break;
577
578 case ROCE_ASYNC_EVENT_SQ_DRAINED:
579 event.event = IB_EVENT_SQ_DRAINED;
580 event_type = EVENT_TYPE_QP;
581 break;
582
583 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
584 event.event = IB_EVENT_QP_FATAL;
585 event_type = EVENT_TYPE_QP;
586 break;
587
588 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
589 event.event = IB_EVENT_QP_REQ_ERR;
590 event_type = EVENT_TYPE_QP;
591 break;
592
593 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
594 event.event = IB_EVENT_QP_ACCESS_ERR;
595 event_type = EVENT_TYPE_QP;
596 break;
597
598 /* NOTE the following are not implemented in FW
599 * ROCE_ASYNC_EVENT_CQ_ERR
600 * ROCE_ASYNC_EVENT_COMM_EST
601 */
602 /* TODO associate the following events -
603 * ROCE_ASYNC_EVENT_SRQ_LIMIT
604 * ROCE_ASYNC_EVENT_LAST_WQE_REACHED
605 * ROCE_ASYNC_EVENT_LOCAL_CATASTROPHIC_ERR (un-affiliated)
606 */
607 default:
608 QL_DPRINT12(ha,
609 "unsupported event 0x%x on fw_handle = %p\n",
610 e_code, fw_handle);
611 break;
612 }
613 }
614
615 switch (event_type) {
616 case EVENT_TYPE_CQ:
617 if (cq && cq->sig == QLNXR_CQ_MAGIC_NUMBER) {
618 struct ib_cq *ibcq = &cq->ibcq;
619
620 if (ibcq->event_handler) {
621 event.device = ibcq->device;
622 event.element.cq = ibcq;
623 ibcq->event_handler(&event, ibcq->cq_context);
624 }
625 } else {
626 QL_DPRINT11(ha,
627 "CQ event with invalid CQ pointer"
628 " Handle = %llx\n", roceHandle64);
629 }
630 QL_DPRINT12(ha,
631 "CQ event 0x%x on handle = %p\n", e_code, cq);
632 break;
633
634 case EVENT_TYPE_QP:
635 if (qp && qp->sig == QLNXR_QP_MAGIC_NUMBER) {
636 struct ib_qp *ibqp = &qp->ibqp;
637
638 if (ibqp->event_handler) {
639 event.device = ibqp->device;
640 event.element.qp = ibqp;
641 ibqp->event_handler(&event, ibqp->qp_context);
642 }
643 } else {
644 QL_DPRINT11(ha,
645 "QP event 0x%x with invalid QP pointer"
646 " qp handle = %p\n",
647 e_code, roceHandle64);
648 }
649 QL_DPRINT12(ha, "QP event 0x%x on qp handle = %p\n",
650 e_code, qp);
651 break;
652
653 case EVENT_TYPE_GENERAL:
654 break;
655
656 default:
657 break;
658 }
659
660 QL_DPRINT12(ha, "exit\n");
661
662 return;
663 }
664
665 void
qlnxr_unaffiliated_event(void * context,u8 e_code)666 qlnxr_unaffiliated_event(void *context, u8 e_code)
667 {
668 struct qlnxr_dev *dev = (struct qlnxr_dev *)context;
669 qlnx_host_t *ha;
670
671 ha = dev->ha;
672
673 QL_DPRINT12(ha, "enter/exit \n");
674 return;
675 }
676
677 static int
qlnxr_set_device_attr(struct qlnxr_dev * dev)678 qlnxr_set_device_attr(struct qlnxr_dev *dev)
679 {
680 struct ecore_rdma_device *ecore_attr;
681 struct qlnxr_device_attr *attr;
682 u32 page_size;
683
684 ecore_attr = ecore_rdma_query_device(dev->rdma_ctx);
685
686 page_size = ~dev->attr.page_size_caps + 1;
687 if(page_size > PAGE_SIZE) {
688 QL_DPRINT12(dev->ha, "Kernel page size : %ld is smaller than"
689 " minimum page size : %ld required by qlnxr\n",
690 PAGE_SIZE, page_size);
691 return -ENODEV;
692 }
693 attr = &dev->attr;
694 attr->vendor_id = ecore_attr->vendor_id;
695 attr->vendor_part_id = ecore_attr->vendor_part_id;
696
697 QL_DPRINT12(dev->ha, "in qlnxr_set_device_attr, vendor : %x device : %x\n",
698 attr->vendor_id, attr->vendor_part_id);
699
700 attr->hw_ver = ecore_attr->hw_ver;
701 attr->fw_ver = ecore_attr->fw_ver;
702 attr->node_guid = ecore_attr->node_guid;
703 attr->sys_image_guid = ecore_attr->sys_image_guid;
704 attr->max_cnq = ecore_attr->max_cnq;
705 attr->max_sge = ecore_attr->max_sge;
706 attr->max_inline = ecore_attr->max_inline;
707 attr->max_sqe = min_t(u32, ecore_attr->max_wqe, QLNXR_MAX_SQE);
708 attr->max_rqe = min_t(u32, ecore_attr->max_wqe, QLNXR_MAX_RQE);
709 attr->max_qp_resp_rd_atomic_resc = ecore_attr->max_qp_resp_rd_atomic_resc;
710 attr->max_qp_req_rd_atomic_resc = ecore_attr->max_qp_req_rd_atomic_resc;
711 attr->max_dev_resp_rd_atomic_resc =
712 ecore_attr->max_dev_resp_rd_atomic_resc;
713 attr->max_cq = ecore_attr->max_cq;
714 attr->max_qp = ecore_attr->max_qp;
715 attr->max_mr = ecore_attr->max_mr;
716 attr->max_mr_size = ecore_attr->max_mr_size;
717 attr->max_cqe = min_t(u64, ecore_attr->max_cqe, QLNXR_MAX_CQES);
718 attr->max_mw = ecore_attr->max_mw;
719 attr->max_fmr = ecore_attr->max_fmr;
720 attr->max_mr_mw_fmr_pbl = ecore_attr->max_mr_mw_fmr_pbl;
721 attr->max_mr_mw_fmr_size = ecore_attr->max_mr_mw_fmr_size;
722 attr->max_pd = ecore_attr->max_pd;
723 attr->max_ah = ecore_attr->max_ah;
724 attr->max_pkey = ecore_attr->max_pkey;
725 attr->max_srq = ecore_attr->max_srq;
726 attr->max_srq_wr = ecore_attr->max_srq_wr;
727 //attr->dev_caps = ecore_attr->dev_caps;
728 attr->page_size_caps = ecore_attr->page_size_caps;
729 attr->dev_ack_delay = ecore_attr->dev_ack_delay;
730 attr->reserved_lkey = ecore_attr->reserved_lkey;
731 attr->bad_pkey_counter = ecore_attr->bad_pkey_counter;
732 attr->max_stats_queues = ecore_attr->max_stats_queues;
733
734 return 0;
735 }
736
737 static int
qlnxr_init_hw(struct qlnxr_dev * dev)738 qlnxr_init_hw(struct qlnxr_dev *dev)
739 {
740 struct ecore_rdma_events events;
741 struct ecore_rdma_add_user_out_params out_params;
742 struct ecore_rdma_cnq_params *cur_pbl;
743 struct ecore_rdma_start_in_params *in_params;
744 dma_addr_t p_phys_table;
745 u32 page_cnt;
746 int rc = 0;
747 int i;
748 qlnx_host_t *ha;
749
750 ha = dev->ha;
751
752 QL_DPRINT12(ha, "enter\n");
753
754 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL);
755 if (!in_params) {
756 rc = -ENOMEM;
757 goto out;
758 }
759
760 bzero(&out_params, sizeof(struct ecore_rdma_add_user_out_params));
761 bzero(&events, sizeof(struct ecore_rdma_events));
762
763 in_params->desired_cnq = dev->num_cnq;
764
765 for (i = 0; i < dev->num_cnq; i++) {
766 cur_pbl = &in_params->cnq_pbl_list[i];
767
768 page_cnt = ecore_chain_get_page_cnt(&dev->cnq_array[i].pbl);
769 cur_pbl->num_pbl_pages = page_cnt;
770
771 p_phys_table = ecore_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
772 cur_pbl->pbl_ptr = (u64)p_phys_table;
773 }
774
775 events.affiliated_event = qlnxr_affiliated_event;
776 events.unaffiliated_event = qlnxr_unaffiliated_event;
777 events.context = dev;
778
779 in_params->events = &events;
780 in_params->roce.cq_mode = ECORE_RDMA_CQ_MODE_32_BITS;
781 in_params->max_mtu = dev->ha->max_frame_size;
782
783 if (QLNX_IS_IWARP(dev)) {
784 if (delayed_ack)
785 in_params->iwarp.flags |= ECORE_IWARP_DA_EN;
786
787 if (timestamp)
788 in_params->iwarp.flags |= ECORE_IWARP_TS_EN;
789
790 in_params->iwarp.rcv_wnd_size = rcv_wnd_size*1024;
791 in_params->iwarp.crc_needed = crc_needed;
792 in_params->iwarp.ooo_num_rx_bufs =
793 (MAX_RXMIT_CONNS * in_params->iwarp.rcv_wnd_size) /
794 in_params->max_mtu;
795
796 in_params->iwarp.mpa_peer2peer = peer2peer;
797 in_params->iwarp.mpa_rev =
798 mpa_enhanced ? ECORE_MPA_REV2 : ECORE_MPA_REV1;
799 in_params->iwarp.mpa_rtr = rtr_type;
800 }
801
802 memcpy(&in_params->mac_addr[0], dev->ha->primary_mac, ETH_ALEN);
803
804 rc = ecore_rdma_start(dev->rdma_ctx, in_params);
805 if (rc)
806 goto out;
807
808 rc = ecore_rdma_add_user(dev->rdma_ctx, &out_params);
809 if (rc)
810 goto out;
811
812 dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr;
813 dev->db_phys_addr = out_params.dpi_phys_addr;
814 dev->db_size = out_params.dpi_size;
815 dev->dpi = out_params.dpi;
816
817 qlnxr_set_device_attr(dev);
818
819 QL_DPRINT12(ha,
820 "cdev->doorbells = %p, db_phys_addr = %p db_size = 0x%x\n",
821 (void *)ha->cdev.doorbells,
822 (void *)ha->cdev.db_phys_addr, ha->cdev.db_size);
823
824 QL_DPRINT12(ha,
825 "db_addr = %p db_phys_addr = %p db_size = 0x%x dpi = 0x%x\n",
826 (void *)dev->db_addr, (void *)dev->db_phys_addr,
827 dev->db_size, dev->dpi);
828 out:
829 kfree(in_params);
830
831 QL_DPRINT12(ha, "exit\n");
832 return rc;
833 }
834
835 static void
qlnxr_build_sgid_mac(union ib_gid * sgid,unsigned char * mac_addr,bool is_vlan,u16 vlan_id)836 qlnxr_build_sgid_mac(union ib_gid *sgid, unsigned char *mac_addr,
837 bool is_vlan, u16 vlan_id)
838 {
839 sgid->global.subnet_prefix = OSAL_CPU_TO_BE64(0xfe80000000000000LL);
840 sgid->raw[8] = mac_addr[0] ^ 2;
841 sgid->raw[9] = mac_addr[1];
842 sgid->raw[10] = mac_addr[2];
843 if (is_vlan) {
844 sgid->raw[11] = vlan_id >> 8;
845 sgid->raw[12] = vlan_id & 0xff;
846 } else {
847 sgid->raw[11] = 0xff;
848 sgid->raw[12] = 0xfe;
849 }
850 sgid->raw[13] = mac_addr[3];
851 sgid->raw[14] = mac_addr[4];
852 sgid->raw[15] = mac_addr[5];
853 }
854 static bool
855 qlnxr_add_sgid(struct qlnxr_dev *dev, union ib_gid *new_sgid);
856
857 struct qlnx_cb_s {
858 struct qlnxr_dev *dev;
859 union ib_gid gid;
860 };
861
862 static u_int
qlnxr_add_ip_based_gid_cb(void * arg,struct ifaddr * ifa,u_int count)863 qlnxr_add_ip_based_gid_cb(void *arg, struct ifaddr *ifa, u_int count)
864 {
865 struct qlnx_cb_s *cba = arg;
866
867 QL_DPRINT12(cba->dev->ha, "IP address : %x\n", ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr);
868 ipv6_addr_set_v4mapped(
869 ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr,
870 (struct in6_addr *)&cba->gid);
871 QL_DPRINT12(cba->dev->ha, "gid generated : %llx\n", cba->gid);
872
873 qlnxr_add_sgid(cba->dev, &cba->gid);
874 return (1);
875 }
876
877 static void
qlnxr_add_ip_based_gid(struct qlnxr_dev * dev,if_t ifp)878 qlnxr_add_ip_based_gid(struct qlnxr_dev *dev, if_t ifp)
879 {
880 struct qlnx_cb_s cba;
881
882 if_foreach_addr_type(ifp, AF_INET, qlnxr_add_ip_based_gid_cb, &cba);
883 for (int i = 0; i < 16; i++) {
884 QL_DPRINT12(dev->ha, "gid generated : %x\n", cba.gid.raw[i]);
885 }
886 }
887
888 static bool
qlnxr_add_sgid(struct qlnxr_dev * dev,union ib_gid * new_sgid)889 qlnxr_add_sgid(struct qlnxr_dev *dev, union ib_gid *new_sgid)
890 {
891 union ib_gid zero_sgid = { { 0 } };
892 int i;
893 //unsigned long flags;
894 mtx_lock(&dev->sgid_lock);
895 for (i = 0; i < QLNXR_MAX_SGID; i++) {
896 if (!memcmp(&dev->sgid_tbl[i], &zero_sgid,
897 sizeof(union ib_gid))) {
898 /* found free entry */
899 memcpy(&dev->sgid_tbl[i], new_sgid,
900 sizeof(union ib_gid));
901 QL_DPRINT12(dev->ha, "copying sgid : %llx\n",
902 *new_sgid);
903 mtx_unlock(&dev->sgid_lock);
904 //TODO ib_dispatch event here?
905 return true;
906 } else if (!memcmp(&dev->sgid_tbl[i], new_sgid,
907 sizeof(union ib_gid))) {
908 /* entry already present, no addition required */
909 mtx_unlock(&dev->sgid_lock);
910 QL_DPRINT12(dev->ha, "sgid present : %llx\n",
911 *new_sgid);
912 return false;
913 }
914 }
915 if (i == QLNXR_MAX_SGID) {
916 QL_DPRINT12(dev->ha, "didn't find an empty entry in sgid_tbl\n");
917 }
918 mtx_unlock(&dev->sgid_lock);
919 return false;
920 }
921
qlnxr_del_sgid(struct qlnxr_dev * dev,union ib_gid * gid)922 static bool qlnxr_del_sgid(struct qlnxr_dev *dev, union ib_gid *gid)
923 {
924 int found = false;
925 int i;
926 //unsigned long flags;
927
928 QL_DPRINT12(dev->ha, "removing gid %llx %llx\n",
929 gid->global.interface_id,
930 gid->global.subnet_prefix);
931 mtx_lock(&dev->sgid_lock);
932 /* first is the default sgid which cannot be deleted */
933 for (i = 1; i < QLNXR_MAX_SGID; i++) {
934 if (!memcmp(&dev->sgid_tbl[i], gid, sizeof(union ib_gid))) {
935 /* found matching entry */
936 memset(&dev->sgid_tbl[i], 0, sizeof(union ib_gid));
937 found = true;
938 break;
939 }
940 }
941 mtx_unlock(&dev->sgid_lock);
942
943 return found;
944 }
945
946 static void
qlnxr_add_sgids(struct qlnxr_dev * dev)947 qlnxr_add_sgids(struct qlnxr_dev *dev)
948 {
949 qlnx_host_t *ha = dev->ha;
950 u16 vlan_id;
951 bool is_vlan;
952 union ib_gid vgid;
953
954 qlnxr_add_ip_based_gid(dev, ha->ifp);
955 /* MAC/VLAN base GIDs */
956 is_vlan = is_vlan_dev(ha->ifp);
957 vlan_id = (is_vlan) ? vlan_dev_vlan_id(ha->ifp) : 0;
958 qlnxr_build_sgid_mac(&vgid, ha->primary_mac, is_vlan, vlan_id);
959 qlnxr_add_sgid(dev, &vgid);
960 }
961
962 static int
qlnxr_add_default_sgid(struct qlnxr_dev * dev)963 qlnxr_add_default_sgid(struct qlnxr_dev *dev)
964 {
965 /* GID Index 0 - Invariant manufacturer-assigned EUI-64 */
966 union ib_gid *sgid = &dev->sgid_tbl[0];
967 struct ecore_rdma_device *qattr;
968 qlnx_host_t *ha;
969 ha = dev->ha;
970
971 qattr = ecore_rdma_query_device(dev->rdma_ctx);
972 if(sgid == NULL)
973 QL_DPRINT12(ha, "sgid = NULL?\n");
974
975 sgid->global.subnet_prefix = OSAL_CPU_TO_BE64(0xfe80000000000000LL);
976 QL_DPRINT12(ha, "node_guid = %llx", dev->attr.node_guid);
977 memcpy(&sgid->raw[8], &qattr->node_guid,
978 sizeof(qattr->node_guid));
979 //memcpy(&sgid->raw[8], &dev->attr.node_guid,
980 // sizeof(dev->attr.node_guid));
981 QL_DPRINT12(ha, "DEFAULT sgid=[%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x]\n",
982 sgid->raw[0], sgid->raw[1], sgid->raw[2], sgid->raw[3], sgid->raw[4], sgid->raw[5],
983 sgid->raw[6], sgid->raw[7], sgid->raw[8], sgid->raw[9], sgid->raw[10], sgid->raw[11],
984 sgid->raw[12], sgid->raw[13], sgid->raw[14], sgid->raw[15]);
985 return 0;
986 }
987
qlnxr_addr_event(struct qlnxr_dev * dev,unsigned long event,if_t ifp,union ib_gid * gid)988 static int qlnxr_addr_event (struct qlnxr_dev *dev,
989 unsigned long event,
990 if_t ifp,
991 union ib_gid *gid)
992 {
993 bool is_vlan = false;
994 union ib_gid vgid;
995 u16 vlan_id = 0xffff;
996
997 QL_DPRINT12(dev->ha, "Link event occured\n");
998 is_vlan = is_vlan_dev(dev->ha->ifp);
999 vlan_id = (is_vlan) ? vlan_dev_vlan_id(dev->ha->ifp) : 0;
1000
1001 switch (event) {
1002 case NETDEV_UP :
1003 qlnxr_add_sgid(dev, gid);
1004 if (is_vlan) {
1005 qlnxr_build_sgid_mac(&vgid, dev->ha->primary_mac, is_vlan, vlan_id);
1006 qlnxr_add_sgid(dev, &vgid);
1007 }
1008 break;
1009 case NETDEV_DOWN :
1010 qlnxr_del_sgid(dev, gid);
1011 if (is_vlan) {
1012 qlnxr_build_sgid_mac(&vgid, dev->ha->primary_mac, is_vlan, vlan_id);
1013 qlnxr_del_sgid(dev, &vgid);
1014 }
1015 break;
1016 default :
1017 break;
1018 }
1019 return 1;
1020 }
1021
qlnxr_inetaddr_event(struct notifier_block * notifier,unsigned long event,void * ptr)1022 static int qlnxr_inetaddr_event(struct notifier_block *notifier,
1023 unsigned long event, void *ptr)
1024 {
1025 struct ifaddr *ifa = ptr;
1026 union ib_gid gid;
1027 struct qlnxr_dev *dev = container_of(notifier, struct qlnxr_dev, nb_inet);
1028 qlnx_host_t *ha = dev->ha;
1029
1030 ipv6_addr_set_v4mapped(
1031 ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr,
1032 (struct in6_addr *)&gid);
1033 return qlnxr_addr_event(dev, event, ha->ifp, &gid);
1034 }
1035
1036 static int
qlnxr_register_inet(struct qlnxr_dev * dev)1037 qlnxr_register_inet(struct qlnxr_dev *dev)
1038 {
1039 int ret;
1040 dev->nb_inet.notifier_call = qlnxr_inetaddr_event;
1041 ret = register_inetaddr_notifier(&dev->nb_inet);
1042 if (ret) {
1043 QL_DPRINT12(dev->ha, "Failed to register inetaddr\n");
1044 return ret;
1045 }
1046 /* TODO : add for CONFIG_IPV6) */
1047 return 0;
1048 }
1049
1050 static int
qlnxr_build_sgid_tbl(struct qlnxr_dev * dev)1051 qlnxr_build_sgid_tbl(struct qlnxr_dev *dev)
1052 {
1053 qlnxr_add_default_sgid(dev);
1054 qlnxr_add_sgids(dev);
1055 return 0;
1056 }
1057
1058 static struct qlnx_rdma_if qlnxr_drv;
1059
1060 static void *
qlnxr_add(void * eth_dev)1061 qlnxr_add(void *eth_dev)
1062 {
1063 struct qlnxr_dev *dev;
1064 int ret;
1065 //device_t pci_dev;
1066 qlnx_host_t *ha;
1067
1068 ha = eth_dev;
1069
1070 QL_DPRINT12(ha, "enter [ha = %p]\n", ha);
1071
1072 dev = (struct qlnxr_dev *)ib_alloc_device(sizeof(struct qlnxr_dev));
1073
1074 if (dev == NULL)
1075 return (NULL);
1076
1077 dev->ha = eth_dev;
1078 dev->cdev = &ha->cdev;
1079 /* Added to extend Application support */
1080 linux_pci_attach_device(dev->ha->pci_dev, NULL, NULL, &dev->pdev);
1081
1082 dev->rdma_ctx = &ha->cdev.hwfns[0];
1083 dev->wq_multiplier = wq_multiplier;
1084 dev->num_cnq = QLNX_NUM_CNQ;
1085
1086 QL_DPRINT12(ha,
1087 "ha = %p dev = %p ha->cdev = %p\n",
1088 ha, dev, &ha->cdev);
1089 QL_DPRINT12(ha,
1090 "dev->cdev = %p dev->rdma_ctx = %p\n",
1091 dev->cdev, dev->rdma_ctx);
1092
1093 ret = qlnxr_alloc_resources(dev);
1094
1095 if (ret)
1096 goto qlnxr_add_err;
1097
1098 ret = qlnxr_setup_irqs(dev);
1099
1100 if (ret) {
1101 qlnxr_free_resources(dev);
1102 goto qlnxr_add_err;
1103 }
1104
1105 ret = qlnxr_init_hw(dev);
1106
1107 if (ret) {
1108 qlnxr_release_irqs(dev);
1109 qlnxr_free_resources(dev);
1110 goto qlnxr_add_err;
1111 }
1112
1113 qlnxr_register_device(dev);
1114 for (int i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i) {
1115 if (device_create_file(&dev->ibdev.dev, qlnxr_class_attributes[i]))
1116 goto sysfs_err;
1117 }
1118 qlnxr_build_sgid_tbl(dev);
1119 //ret = qlnxr_register_inet(dev);
1120 QL_DPRINT12(ha, "exit\n");
1121 if (!test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state)) {
1122 QL_DPRINT12(ha, "dispatching IB_PORT_ACITVE event\n");
1123 qlnxr_ib_dispatch_event(dev, QLNXR_PORT,
1124 IB_EVENT_PORT_ACTIVE);
1125 }
1126
1127 return (dev);
1128 sysfs_err:
1129 for (int i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i) {
1130 device_remove_file(&dev->ibdev.dev, qlnxr_class_attributes[i]);
1131 }
1132 ib_unregister_device(&dev->ibdev);
1133
1134 qlnxr_add_err:
1135 ib_dealloc_device(&dev->ibdev);
1136
1137 QL_DPRINT12(ha, "exit failed\n");
1138 return (NULL);
1139 }
1140
1141 static void
qlnxr_remove_sysfiles(struct qlnxr_dev * dev)1142 qlnxr_remove_sysfiles(struct qlnxr_dev *dev)
1143 {
1144 int i;
1145 for (i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i)
1146 device_remove_file(&dev->ibdev.dev, qlnxr_class_attributes[i]);
1147 }
1148
1149 static int
qlnxr_remove(void * eth_dev,void * qlnx_rdma_dev)1150 qlnxr_remove(void *eth_dev, void *qlnx_rdma_dev)
1151 {
1152 struct qlnxr_dev *dev;
1153 qlnx_host_t *ha;
1154
1155 dev = qlnx_rdma_dev;
1156 ha = eth_dev;
1157
1158 if ((ha == NULL) || (dev == NULL))
1159 return (0);
1160
1161 QL_DPRINT12(ha, "enter ha = %p qlnx_rdma_dev = %p pd_count = %d\n",
1162 ha, qlnx_rdma_dev, dev->pd_count);
1163
1164 qlnxr_ib_dispatch_event(dev, QLNXR_PORT,
1165 IB_EVENT_PORT_ERR);
1166
1167 if (QLNX_IS_IWARP(dev)) {
1168 if (dev->pd_count)
1169 return (EBUSY);
1170 }
1171
1172 ib_unregister_device(&dev->ibdev);
1173
1174 if (QLNX_IS_ROCE(dev)) {
1175 if (dev->pd_count)
1176 return (EBUSY);
1177 }
1178
1179 ecore_rdma_remove_user(dev->rdma_ctx, dev->dpi);
1180 ecore_rdma_stop(dev->rdma_ctx);
1181
1182 qlnxr_release_irqs(dev);
1183
1184 qlnxr_free_resources(dev);
1185
1186 qlnxr_remove_sysfiles(dev);
1187 ib_dealloc_device(&dev->ibdev);
1188
1189 linux_pci_detach_device(&dev->pdev);
1190
1191 QL_DPRINT12(ha, "exit ha = %p qlnx_rdma_dev = %p\n", ha, qlnx_rdma_dev);
1192 return (0);
1193 }
1194
1195 int
qlnx_rdma_ll2_set_mac_filter(void * rdma_ctx,uint8_t * old_mac_address,uint8_t * new_mac_address)1196 qlnx_rdma_ll2_set_mac_filter(void *rdma_ctx, uint8_t *old_mac_address,
1197 uint8_t *new_mac_address)
1198 {
1199 struct ecore_hwfn *p_hwfn = rdma_ctx;
1200 struct qlnx_host *ha;
1201 int ret = 0;
1202
1203 ha = (struct qlnx_host *)(p_hwfn->p_dev);
1204 QL_DPRINT2(ha, "enter rdma_ctx (%p)\n", rdma_ctx);
1205
1206 if (old_mac_address)
1207 ecore_llh_remove_mac_filter(p_hwfn->p_dev, 0, old_mac_address);
1208
1209 if (new_mac_address)
1210 ret = ecore_llh_add_mac_filter(p_hwfn->p_dev, 0, new_mac_address);
1211
1212 QL_DPRINT2(ha, "exit rdma_ctx (%p)\n", rdma_ctx);
1213 return (ret);
1214 }
1215
1216 static void
qlnxr_mac_address_change(struct qlnxr_dev * dev)1217 qlnxr_mac_address_change(struct qlnxr_dev *dev)
1218 {
1219 qlnx_host_t *ha;
1220
1221 ha = dev->ha;
1222
1223 QL_DPRINT12(ha, "enter/exit\n");
1224
1225 return;
1226 }
1227
1228 static void
qlnxr_notify(void * eth_dev,void * qlnx_rdma_dev,enum qlnx_rdma_event event)1229 qlnxr_notify(void *eth_dev, void *qlnx_rdma_dev, enum qlnx_rdma_event event)
1230 {
1231 struct qlnxr_dev *dev;
1232 qlnx_host_t *ha;
1233
1234 dev = qlnx_rdma_dev;
1235
1236 if (dev == NULL)
1237 return;
1238
1239 ha = dev->ha;
1240
1241 QL_DPRINT12(ha, "enter (%p, %d)\n", qlnx_rdma_dev, event);
1242
1243 switch (event) {
1244 case QLNX_ETHDEV_UP:
1245 if (!test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state))
1246 qlnxr_ib_dispatch_event(dev, QLNXR_PORT,
1247 IB_EVENT_PORT_ACTIVE);
1248 break;
1249
1250 case QLNX_ETHDEV_CHANGE_ADDR:
1251 qlnxr_mac_address_change(dev);
1252 break;
1253
1254 case QLNX_ETHDEV_DOWN:
1255 if (test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state))
1256 qlnxr_ib_dispatch_event(dev, QLNXR_PORT,
1257 IB_EVENT_PORT_ERR);
1258 break;
1259 }
1260
1261 QL_DPRINT12(ha, "exit (%p, %d)\n", qlnx_rdma_dev, event);
1262 return;
1263 }
1264
1265 static int
qlnxr_mod_load(void)1266 qlnxr_mod_load(void)
1267 {
1268 int ret;
1269
1270 qlnxr_drv.add = qlnxr_add;
1271 qlnxr_drv.remove = qlnxr_remove;
1272 qlnxr_drv.notify = qlnxr_notify;
1273
1274 ret = qlnx_rdma_register_if(&qlnxr_drv);
1275
1276 return (ret);
1277 }
1278
1279 static int
qlnxr_mod_unload(void)1280 qlnxr_mod_unload(void)
1281 {
1282 int ret;
1283
1284 ret = qlnx_rdma_deregister_if(&qlnxr_drv);
1285 return (ret);
1286 }
1287
1288 static int
qlnxr_event_handler(module_t mod,int event,void * arg)1289 qlnxr_event_handler(module_t mod, int event, void *arg)
1290 {
1291
1292 int ret = 0;
1293
1294 switch (event) {
1295 case MOD_LOAD:
1296 ret = qlnxr_mod_load();
1297 break;
1298
1299 case MOD_UNLOAD:
1300 ret = qlnxr_mod_unload();
1301 break;
1302
1303 default:
1304 break;
1305 }
1306
1307 return (ret);
1308 }
1309
1310 static moduledata_t qlnxr_mod_info = {
1311 .name = "qlnxr",
1312 .evhand = qlnxr_event_handler,
1313 };
1314
1315 MODULE_VERSION(qlnxr, 1);
1316 MODULE_DEPEND(qlnxr, if_qlnxe, 1, 1, 1);
1317 MODULE_DEPEND(qlnxr, ibcore, 1, 1, 1);
1318 MODULE_DEPEND(qlnxr, linuxkpi, 1, 1, 1);
1319
1320 DECLARE_MODULE(qlnxr, qlnxr_mod_info, SI_SUB_LAST, SI_ORDER_ANY);
1321