1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/imx8mm-power.h> 11#include <dt-bindings/reset/imx8mq-reset.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mm-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clocks = <&clk IMX8MM_CLK_ARM>; 66 enable-method = "psci"; 67 i-cache-size = <0x8000>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <256>; 70 d-cache-size = <0x8000>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&A53_L2>; 74 operating-points-v2 = <&a53_opp_table>; 75 nvmem-cells = <&cpu_speed_grade>; 76 nvmem-cell-names = "speed_grade"; 77 cpu-idle-states = <&cpu_pd_wait>; 78 #cooling-cells = <2>; 79 }; 80 81 A53_1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x1>; 85 clocks = <&clk IMX8MM_CLK_ARM>; 86 enable-method = "psci"; 87 i-cache-size = <0x8000>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <256>; 90 d-cache-size = <0x8000>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <128>; 93 next-level-cache = <&A53_L2>; 94 operating-points-v2 = <&a53_opp_table>; 95 cpu-idle-states = <&cpu_pd_wait>; 96 #cooling-cells = <2>; 97 }; 98 99 A53_2: cpu@2 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x2>; 103 clocks = <&clk IMX8MM_CLK_ARM>; 104 enable-method = "psci"; 105 i-cache-size = <0x8000>; 106 i-cache-line-size = <64>; 107 i-cache-sets = <256>; 108 d-cache-size = <0x8000>; 109 d-cache-line-size = <64>; 110 d-cache-sets = <128>; 111 next-level-cache = <&A53_L2>; 112 operating-points-v2 = <&a53_opp_table>; 113 cpu-idle-states = <&cpu_pd_wait>; 114 #cooling-cells = <2>; 115 }; 116 117 A53_3: cpu@3 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a53"; 120 reg = <0x3>; 121 clocks = <&clk IMX8MM_CLK_ARM>; 122 enable-method = "psci"; 123 i-cache-size = <0x8000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <256>; 126 d-cache-size = <0x8000>; 127 d-cache-line-size = <64>; 128 d-cache-sets = <128>; 129 next-level-cache = <&A53_L2>; 130 operating-points-v2 = <&a53_opp_table>; 131 cpu-idle-states = <&cpu_pd_wait>; 132 #cooling-cells = <2>; 133 }; 134 135 A53_L2: l2-cache0 { 136 compatible = "cache"; 137 cache-level = <2>; 138 cache-unified; 139 cache-size = <0x80000>; 140 cache-line-size = <64>; 141 cache-sets = <512>; 142 }; 143 }; 144 145 a53_opp_table: opp-table { 146 compatible = "operating-points-v2"; 147 opp-shared; 148 149 opp-1200000000 { 150 opp-hz = /bits/ 64 <1200000000>; 151 opp-microvolt = <850000>; 152 opp-supported-hw = <0xe>, <0x7>; 153 clock-latency-ns = <150000>; 154 opp-suspend; 155 }; 156 157 opp-1600000000 { 158 opp-hz = /bits/ 64 <1600000000>; 159 opp-microvolt = <950000>; 160 opp-supported-hw = <0xc>, <0x7>; 161 clock-latency-ns = <150000>; 162 opp-suspend; 163 }; 164 165 opp-1800000000 { 166 opp-hz = /bits/ 64 <1800000000>; 167 opp-microvolt = <1000000>; 168 opp-supported-hw = <0x8>, <0x3>; 169 clock-latency-ns = <150000>; 170 opp-suspend; 171 }; 172 }; 173 174 osc_32k: clock-osc-32k { 175 compatible = "fixed-clock"; 176 #clock-cells = <0>; 177 clock-frequency = <32768>; 178 clock-output-names = "osc_32k"; 179 }; 180 181 osc_24m: clock-osc-24m { 182 compatible = "fixed-clock"; 183 #clock-cells = <0>; 184 clock-frequency = <24000000>; 185 clock-output-names = "osc_24m"; 186 }; 187 188 clk_ext1: clock-ext1 { 189 compatible = "fixed-clock"; 190 #clock-cells = <0>; 191 clock-frequency = <133000000>; 192 clock-output-names = "clk_ext1"; 193 }; 194 195 clk_ext2: clock-ext2 { 196 compatible = "fixed-clock"; 197 #clock-cells = <0>; 198 clock-frequency = <133000000>; 199 clock-output-names = "clk_ext2"; 200 }; 201 202 clk_ext3: clock-ext3 { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <133000000>; 206 clock-output-names = "clk_ext3"; 207 }; 208 209 clk_ext4: clock-ext4 { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <133000000>; 213 clock-output-names = "clk_ext4"; 214 }; 215 216 psci { 217 compatible = "arm,psci-1.0"; 218 method = "smc"; 219 }; 220 221 pmu { 222 compatible = "arm,cortex-a53-pmu"; 223 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 224 }; 225 226 timer { 227 compatible = "arm,armv8-timer"; 228 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 229 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 230 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 231 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 232 clock-frequency = <8000000>; 233 arm,no-tick-in-suspend; 234 }; 235 236 thermal_zones: thermal-zones { 237 cpu-thermal { 238 polling-delay-passive = <250>; 239 polling-delay = <2000>; 240 thermal-sensors = <&tmu>; 241 trips { 242 cpu_alert0: trip0 { 243 temperature = <85000>; 244 hysteresis = <2000>; 245 type = "passive"; 246 }; 247 248 cpu_crit0: trip1 { 249 temperature = <95000>; 250 hysteresis = <2000>; 251 type = "critical"; 252 }; 253 }; 254 255 cooling-maps { 256 map0 { 257 trip = <&cpu_alert0>; 258 cooling-device = 259 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 260 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 261 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 262 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 263 }; 264 }; 265 }; 266 }; 267 268 usbphynop1: usbphynop1 { 269 #phy-cells = <0>; 270 compatible = "usb-nop-xceiv"; 271 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 272 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 273 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 274 clock-names = "main_clk"; 275 power-domains = <&pgc_otg1>; 276 }; 277 278 usbphynop2: usbphynop2 { 279 #phy-cells = <0>; 280 compatible = "usb-nop-xceiv"; 281 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 282 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 283 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 284 clock-names = "main_clk"; 285 power-domains = <&pgc_otg2>; 286 }; 287 288 soc: soc@0 { 289 compatible = "fsl,imx8mm-soc", "simple-bus"; 290 #address-cells = <1>; 291 #size-cells = <1>; 292 ranges = <0x0 0x0 0x0 0x3e000000>; 293 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 294 nvmem-cells = <&imx8mm_uid>; 295 nvmem-cell-names = "soc_unique_id"; 296 297 aips1: bus@30000000 { 298 compatible = "fsl,aips-bus", "simple-bus"; 299 reg = <0x30000000 0x400000>; 300 #address-cells = <1>; 301 #size-cells = <1>; 302 ranges = <0x30000000 0x30000000 0x400000>; 303 304 spba2: spba-bus@30000000 { 305 compatible = "fsl,spba-bus", "simple-bus"; 306 #address-cells = <1>; 307 #size-cells = <1>; 308 reg = <0x30000000 0x100000>; 309 ranges; 310 311 sai1: sai@30010000 { 312 #sound-dai-cells = <0>; 313 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 314 reg = <0x30010000 0x10000>; 315 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 317 <&clk IMX8MM_CLK_SAI1_ROOT>, 318 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 319 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 320 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 321 dma-names = "rx", "tx"; 322 status = "disabled"; 323 }; 324 325 sai2: sai@30020000 { 326 #sound-dai-cells = <0>; 327 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 328 reg = <0x30020000 0x10000>; 329 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, 331 <&clk IMX8MM_CLK_SAI2_ROOT>, 332 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 333 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 334 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 335 dma-names = "rx", "tx"; 336 status = "disabled"; 337 }; 338 339 sai3: sai@30030000 { 340 #sound-dai-cells = <0>; 341 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 342 reg = <0x30030000 0x10000>; 343 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, 345 <&clk IMX8MM_CLK_SAI3_ROOT>, 346 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 347 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 348 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 349 dma-names = "rx", "tx"; 350 status = "disabled"; 351 }; 352 353 sai5: sai@30050000 { 354 #sound-dai-cells = <0>; 355 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 356 reg = <0x30050000 0x10000>; 357 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, 359 <&clk IMX8MM_CLK_SAI5_ROOT>, 360 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 361 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 362 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 363 dma-names = "rx", "tx"; 364 status = "disabled"; 365 }; 366 367 sai6: sai@30060000 { 368 #sound-dai-cells = <0>; 369 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 370 reg = <0x30060000 0x10000>; 371 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&clk IMX8MM_CLK_SAI6_IPG>, 373 <&clk IMX8MM_CLK_SAI6_ROOT>, 374 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 375 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 376 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 377 dma-names = "rx", "tx"; 378 status = "disabled"; 379 }; 380 381 micfil: audio-controller@30080000 { 382 compatible = "fsl,imx8mm-micfil"; 383 reg = <0x30080000 0x10000>; 384 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&clk IMX8MM_CLK_PDM_IPG>, 389 <&clk IMX8MM_CLK_PDM_ROOT>, 390 <&clk IMX8MM_AUDIO_PLL1_OUT>, 391 <&clk IMX8MM_AUDIO_PLL2_OUT>, 392 <&clk IMX8MM_CLK_EXT3>; 393 clock-names = "ipg_clk", "ipg_clk_app", 394 "pll8k", "pll11k", "clkext3"; 395 dmas = <&sdma2 24 25 0x80000000>; 396 dma-names = "rx"; 397 #sound-dai-cells = <0>; 398 status = "disabled"; 399 }; 400 401 spdif1: spdif@30090000 { 402 compatible = "fsl,imx8mm-spdif"; 403 reg = <0x30090000 0x10000>; 404 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ 406 <&clk IMX8MM_CLK_24M>, /* rxtx0 */ 407 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ 408 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ 409 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ 410 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ 411 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ 412 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ 413 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ 414 <&clk IMX8MM_CLK_DUMMY>; /* spba */ 415 clock-names = "core", "rxtx0", 416 "rxtx1", "rxtx2", 417 "rxtx3", "rxtx4", 418 "rxtx5", "rxtx6", 419 "rxtx7", "spba"; 420 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 421 dma-names = "rx", "tx"; 422 status = "disabled"; 423 }; 424 }; 425 426 gpio1: gpio@30200000 { 427 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 428 reg = <0x30200000 0x10000>; 429 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; 432 gpio-controller; 433 #gpio-cells = <2>; 434 interrupt-controller; 435 #interrupt-cells = <2>; 436 gpio-ranges = <&iomuxc 0 10 30>; 437 }; 438 439 gpio2: gpio@30210000 { 440 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 441 reg = <0x30210000 0x10000>; 442 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; 445 gpio-controller; 446 #gpio-cells = <2>; 447 interrupt-controller; 448 #interrupt-cells = <2>; 449 gpio-ranges = <&iomuxc 0 40 21>; 450 }; 451 452 gpio3: gpio@30220000 { 453 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 454 reg = <0x30220000 0x10000>; 455 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; 458 gpio-controller; 459 #gpio-cells = <2>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 gpio-ranges = <&iomuxc 0 61 26>; 463 }; 464 465 gpio4: gpio@30230000 { 466 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 467 reg = <0x30230000 0x10000>; 468 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; 471 gpio-controller; 472 #gpio-cells = <2>; 473 interrupt-controller; 474 #interrupt-cells = <2>; 475 gpio-ranges = <&iomuxc 0 87 32>; 476 }; 477 478 gpio5: gpio@30240000 { 479 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 480 reg = <0x30240000 0x10000>; 481 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; 484 gpio-controller; 485 #gpio-cells = <2>; 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 gpio-ranges = <&iomuxc 0 119 30>; 489 }; 490 491 tmu: tmu@30260000 { 492 compatible = "fsl,imx8mm-tmu"; 493 reg = <0x30260000 0x10000>; 494 clocks = <&clk IMX8MM_CLK_TMU_ROOT>; 495 nvmem-cells = <&tmu_calib>; 496 nvmem-cell-names = "calib"; 497 #thermal-sensor-cells = <0>; 498 }; 499 500 wdog1: watchdog@30280000 { 501 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 502 reg = <0x30280000 0x10000>; 503 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 505 status = "disabled"; 506 }; 507 508 wdog2: watchdog@30290000 { 509 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 510 reg = <0x30290000 0x10000>; 511 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 513 status = "disabled"; 514 }; 515 516 wdog3: watchdog@302a0000 { 517 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 518 reg = <0x302a0000 0x10000>; 519 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 521 status = "disabled"; 522 }; 523 524 sdma2: dma-controller@302c0000 { 525 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 526 reg = <0x302c0000 0x10000>; 527 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 529 <&clk IMX8MM_CLK_SDMA2_ROOT>; 530 clock-names = "ipg", "ahb"; 531 #dma-cells = <3>; 532 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 533 }; 534 535 sdma3: dma-controller@302b0000 { 536 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 537 reg = <0x302b0000 0x10000>; 538 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 540 <&clk IMX8MM_CLK_SDMA3_ROOT>; 541 clock-names = "ipg", "ahb"; 542 #dma-cells = <3>; 543 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 544 }; 545 546 iomuxc: pinctrl@30330000 { 547 compatible = "fsl,imx8mm-iomuxc"; 548 reg = <0x30330000 0x10000>; 549 }; 550 551 gpr: syscon@30340000 { 552 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; 553 reg = <0x30340000 0x10000>; 554 }; 555 556 ocotp: efuse@30350000 { 557 compatible = "fsl,imx8mm-ocotp", "syscon"; 558 reg = <0x30350000 0x10000>; 559 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 560 /* For nvmem subnodes */ 561 #address-cells = <1>; 562 #size-cells = <1>; 563 564 /* 565 * The register address below maps to the MX8M 566 * Fusemap Description Table entries this way. 567 * Assuming 568 * reg = <ADDR SIZE>; 569 * then 570 * Fuse Address = (ADDR * 4) + 0x400 571 * Note that if SIZE is greater than 4, then 572 * each subsequent fuse is located at offset 573 * +0x10 in Fusemap Description Table (e.g. 574 * reg = <0x4 0x8> describes fuses 0x410 and 575 * 0x420). 576 */ 577 imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ 578 reg = <0x4 0x8>; 579 }; 580 581 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 582 reg = <0x10 4>; 583 }; 584 585 tmu_calib: calib@3c { /* 0x4f0 */ 586 reg = <0x3c 4>; 587 }; 588 589 fec_mac_address: mac-address@90 { /* 0x640 */ 590 reg = <0x90 6>; 591 }; 592 }; 593 594 anatop: clock-controller@30360000 { 595 compatible = "fsl,imx8mm-anatop"; 596 reg = <0x30360000 0x10000>; 597 #clock-cells = <1>; 598 }; 599 600 snvs: snvs@30370000 { 601 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 602 reg = <0x30370000 0x10000>; 603 604 snvs_rtc: snvs-rtc-lp { 605 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 606 regmap = <&snvs>; 607 offset = <0x34>; 608 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 611 clock-names = "snvs-rtc"; 612 }; 613 614 snvs_pwrkey: snvs-powerkey { 615 compatible = "fsl,sec-v4.0-pwrkey"; 616 regmap = <&snvs>; 617 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 619 clock-names = "snvs-pwrkey"; 620 linux,keycode = <KEY_POWER>; 621 wakeup-source; 622 status = "disabled"; 623 }; 624 625 snvs_lpgpr: snvs-lpgpr { 626 compatible = "fsl,imx8mm-snvs-lpgpr", 627 "fsl,imx7d-snvs-lpgpr"; 628 }; 629 }; 630 631 clk: clock-controller@30380000 { 632 compatible = "fsl,imx8mm-ccm"; 633 reg = <0x30380000 0x10000>; 634 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 636 #clock-cells = <1>; 637 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 638 <&clk_ext3>, <&clk_ext4>; 639 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 640 "clk_ext3", "clk_ext4"; 641 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, 642 <&clk IMX8MM_CLK_A53_CORE>, 643 <&clk IMX8MM_CLK_NOC>, 644 <&clk IMX8MM_CLK_AUDIO_AHB>, 645 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, 646 <&clk IMX8MM_SYS_PLL3>, 647 <&clk IMX8MM_AUDIO_PLL1>; 648 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 649 <&clk IMX8MM_ARM_PLL_OUT>, 650 <&clk IMX8MM_SYS_PLL3_OUT>, 651 <&clk IMX8MM_SYS_PLL1_800M>; 652 assigned-clock-rates = <0>, <0>, <0>, 653 <400000000>, 654 <400000000>, 655 <750000000>, 656 <393216000>; 657 }; 658 659 src: reset-controller@30390000 { 660 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; 661 reg = <0x30390000 0x10000>; 662 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 663 #reset-cells = <1>; 664 }; 665 666 gpc: gpc@303a0000 { 667 compatible = "fsl,imx8mm-gpc"; 668 reg = <0x303a0000 0x10000>; 669 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 670 interrupt-parent = <&gic>; 671 interrupt-controller; 672 #interrupt-cells = <3>; 673 674 pgc { 675 #address-cells = <1>; 676 #size-cells = <0>; 677 678 pgc_hsiomix: power-domain@0 { 679 #power-domain-cells = <0>; 680 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; 681 clocks = <&clk IMX8MM_CLK_USB_BUS>; 682 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 683 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 684 }; 685 686 pgc_pcie: power-domain@1 { 687 #power-domain-cells = <0>; 688 reg = <IMX8MM_POWER_DOMAIN_PCIE>; 689 power-domains = <&pgc_hsiomix>; 690 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; 691 }; 692 693 pgc_otg1: power-domain@2 { 694 #power-domain-cells = <0>; 695 reg = <IMX8MM_POWER_DOMAIN_OTG1>; 696 }; 697 698 pgc_otg2: power-domain@3 { 699 #power-domain-cells = <0>; 700 reg = <IMX8MM_POWER_DOMAIN_OTG2>; 701 }; 702 703 pgc_gpumix: power-domain@4 { 704 #power-domain-cells = <0>; 705 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; 706 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 707 <&clk IMX8MM_CLK_GPU_AHB>; 708 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>, 709 <&clk IMX8MM_CLK_GPU_AHB>; 710 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 711 <&clk IMX8MM_SYS_PLL1_800M>; 712 assigned-clock-rates = <800000000>, <400000000>; 713 }; 714 715 pgc_gpu: power-domain@5 { 716 #power-domain-cells = <0>; 717 reg = <IMX8MM_POWER_DOMAIN_GPU>; 718 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 719 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 720 <&clk IMX8MM_CLK_GPU2D_ROOT>, 721 <&clk IMX8MM_CLK_GPU3D_ROOT>; 722 resets = <&src IMX8MQ_RESET_GPU_RESET>; 723 power-domains = <&pgc_gpumix>; 724 }; 725 726 pgc_vpumix: power-domain@6 { 727 #power-domain-cells = <0>; 728 reg = <IMX8MM_POWER_DOMAIN_VPUMIX>; 729 clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; 730 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>; 731 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>; 732 }; 733 734 pgc_vpu_g1: power-domain@7 { 735 #power-domain-cells = <0>; 736 reg = <IMX8MM_POWER_DOMAIN_VPUG1>; 737 }; 738 739 pgc_vpu_g2: power-domain@8 { 740 #power-domain-cells = <0>; 741 reg = <IMX8MM_POWER_DOMAIN_VPUG2>; 742 }; 743 744 pgc_vpu_h1: power-domain@9 { 745 #power-domain-cells = <0>; 746 reg = <IMX8MM_POWER_DOMAIN_VPUH1>; 747 }; 748 749 pgc_dispmix: power-domain@10 { 750 #power-domain-cells = <0>; 751 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>; 752 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, 753 <&clk IMX8MM_CLK_DISP_AXI_ROOT>; 754 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>, 755 <&clk IMX8MM_CLK_DISP_APB>; 756 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, 757 <&clk IMX8MM_SYS_PLL1_800M>; 758 assigned-clock-rates = <500000000>, <200000000>; 759 }; 760 761 pgc_mipi: power-domain@11 { 762 #power-domain-cells = <0>; 763 reg = <IMX8MM_POWER_DOMAIN_MIPI>; 764 }; 765 }; 766 }; 767 }; 768 769 aips2: bus@30400000 { 770 compatible = "fsl,aips-bus", "simple-bus"; 771 reg = <0x30400000 0x400000>; 772 #address-cells = <1>; 773 #size-cells = <1>; 774 ranges = <0x30400000 0x30400000 0x400000>; 775 776 pwm1: pwm@30660000 { 777 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 778 reg = <0x30660000 0x10000>; 779 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 781 <&clk IMX8MM_CLK_PWM1_ROOT>; 782 clock-names = "ipg", "per"; 783 #pwm-cells = <3>; 784 status = "disabled"; 785 }; 786 787 pwm2: pwm@30670000 { 788 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 789 reg = <0x30670000 0x10000>; 790 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 792 <&clk IMX8MM_CLK_PWM2_ROOT>; 793 clock-names = "ipg", "per"; 794 #pwm-cells = <3>; 795 status = "disabled"; 796 }; 797 798 pwm3: pwm@30680000 { 799 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 800 reg = <0x30680000 0x10000>; 801 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 803 <&clk IMX8MM_CLK_PWM3_ROOT>; 804 clock-names = "ipg", "per"; 805 #pwm-cells = <3>; 806 status = "disabled"; 807 }; 808 809 pwm4: pwm@30690000 { 810 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 811 reg = <0x30690000 0x10000>; 812 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 814 <&clk IMX8MM_CLK_PWM4_ROOT>; 815 clock-names = "ipg", "per"; 816 #pwm-cells = <3>; 817 status = "disabled"; 818 }; 819 820 system_counter: timer@306a0000 { 821 compatible = "nxp,sysctr-timer"; 822 reg = <0x306a0000 0x20000>; 823 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&osc_24m>; 825 clock-names = "per"; 826 }; 827 }; 828 829 aips3: bus@30800000 { 830 compatible = "fsl,aips-bus", "simple-bus"; 831 reg = <0x30800000 0x400000>; 832 #address-cells = <1>; 833 #size-cells = <1>; 834 ranges = <0x30800000 0x30800000 0x400000>, 835 <0x8000000 0x8000000 0x10000000>; 836 837 spba1: spba-bus@30800000 { 838 compatible = "fsl,spba-bus", "simple-bus"; 839 #address-cells = <1>; 840 #size-cells = <1>; 841 reg = <0x30800000 0x100000>; 842 ranges; 843 844 ecspi1: spi@30820000 { 845 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 reg = <0x30820000 0x10000>; 849 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 851 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 852 clock-names = "ipg", "per"; 853 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 854 dma-names = "rx", "tx"; 855 status = "disabled"; 856 }; 857 858 ecspi2: spi@30830000 { 859 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 reg = <0x30830000 0x10000>; 863 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 865 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 866 clock-names = "ipg", "per"; 867 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 868 dma-names = "rx", "tx"; 869 status = "disabled"; 870 }; 871 872 ecspi3: spi@30840000 { 873 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 reg = <0x30840000 0x10000>; 877 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 879 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 880 clock-names = "ipg", "per"; 881 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 882 dma-names = "rx", "tx"; 883 status = "disabled"; 884 }; 885 886 uart1: serial@30860000 { 887 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 888 reg = <0x30860000 0x10000>; 889 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 891 <&clk IMX8MM_CLK_UART1_ROOT>; 892 clock-names = "ipg", "per"; 893 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 894 dma-names = "rx", "tx"; 895 status = "disabled"; 896 }; 897 898 uart3: serial@30880000 { 899 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 900 reg = <0x30880000 0x10000>; 901 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 903 <&clk IMX8MM_CLK_UART3_ROOT>; 904 clock-names = "ipg", "per"; 905 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 906 dma-names = "rx", "tx"; 907 status = "disabled"; 908 }; 909 910 uart2: serial@30890000 { 911 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 912 reg = <0x30890000 0x10000>; 913 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 915 <&clk IMX8MM_CLK_UART2_ROOT>; 916 clock-names = "ipg", "per"; 917 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 918 dma-names = "rx", "tx"; 919 status = "disabled"; 920 }; 921 }; 922 923 crypto: crypto@30900000 { 924 compatible = "fsl,sec-v4.0"; 925 #address-cells = <1>; 926 #size-cells = <1>; 927 reg = <0x30900000 0x40000>; 928 ranges = <0 0x30900000 0x40000>; 929 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&clk IMX8MM_CLK_AHB>, 931 <&clk IMX8MM_CLK_IPG_ROOT>; 932 clock-names = "aclk", "ipg"; 933 934 sec_jr0: jr@1000 { 935 compatible = "fsl,sec-v4.0-job-ring"; 936 reg = <0x1000 0x1000>; 937 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 938 status = "disabled"; 939 }; 940 941 sec_jr1: jr@2000 { 942 compatible = "fsl,sec-v4.0-job-ring"; 943 reg = <0x2000 0x1000>; 944 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 945 }; 946 947 sec_jr2: jr@3000 { 948 compatible = "fsl,sec-v4.0-job-ring"; 949 reg = <0x3000 0x1000>; 950 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 951 }; 952 }; 953 954 i2c1: i2c@30a20000 { 955 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 reg = <0x30a20000 0x10000>; 959 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 961 status = "disabled"; 962 }; 963 964 i2c2: i2c@30a30000 { 965 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 reg = <0x30a30000 0x10000>; 969 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 971 status = "disabled"; 972 }; 973 974 i2c3: i2c@30a40000 { 975 #address-cells = <1>; 976 #size-cells = <0>; 977 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 978 reg = <0x30a40000 0x10000>; 979 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 981 status = "disabled"; 982 }; 983 984 i2c4: i2c@30a50000 { 985 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 reg = <0x30a50000 0x10000>; 989 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 991 status = "disabled"; 992 }; 993 994 uart4: serial@30a60000 { 995 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 996 reg = <0x30a60000 0x10000>; 997 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 999 <&clk IMX8MM_CLK_UART4_ROOT>; 1000 clock-names = "ipg", "per"; 1001 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1002 dma-names = "rx", "tx"; 1003 status = "disabled"; 1004 }; 1005 1006 mu: mailbox@30aa0000 { 1007 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; 1008 reg = <0x30aa0000 0x10000>; 1009 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&clk IMX8MM_CLK_MU_ROOT>; 1011 #mbox-cells = <2>; 1012 }; 1013 1014 usdhc1: mmc@30b40000 { 1015 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1016 reg = <0x30b40000 0x10000>; 1017 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 1019 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 1020 <&clk IMX8MM_CLK_USDHC1_ROOT>; 1021 clock-names = "ipg", "ahb", "per"; 1022 fsl,tuning-start-tap = <20>; 1023 fsl,tuning-step = <2>; 1024 bus-width = <4>; 1025 status = "disabled"; 1026 }; 1027 1028 usdhc2: mmc@30b50000 { 1029 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1030 reg = <0x30b50000 0x10000>; 1031 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 1033 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 1034 <&clk IMX8MM_CLK_USDHC2_ROOT>; 1035 clock-names = "ipg", "ahb", "per"; 1036 fsl,tuning-start-tap = <20>; 1037 fsl,tuning-step = <2>; 1038 bus-width = <4>; 1039 status = "disabled"; 1040 }; 1041 1042 usdhc3: mmc@30b60000 { 1043 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1044 reg = <0x30b60000 0x10000>; 1045 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1046 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 1047 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 1048 <&clk IMX8MM_CLK_USDHC3_ROOT>; 1049 clock-names = "ipg", "ahb", "per"; 1050 fsl,tuning-start-tap = <20>; 1051 fsl,tuning-step = <2>; 1052 bus-width = <4>; 1053 status = "disabled"; 1054 }; 1055 1056 flexspi: spi@30bb0000 { 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 compatible = "nxp,imx8mm-fspi"; 1060 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1061 reg-names = "fspi_base", "fspi_mmap"; 1062 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, 1064 <&clk IMX8MM_CLK_QSPI_ROOT>; 1065 clock-names = "fspi_en", "fspi"; 1066 status = "disabled"; 1067 }; 1068 1069 sdma1: dma-controller@30bd0000 { 1070 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 1071 reg = <0x30bd0000 0x10000>; 1072 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 1074 <&clk IMX8MM_CLK_AHB>; 1075 clock-names = "ipg", "ahb"; 1076 #dma-cells = <3>; 1077 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1078 }; 1079 1080 fec1: ethernet@30be0000 { 1081 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1082 reg = <0x30be0000 0x10000>; 1083 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1087 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 1088 <&clk IMX8MM_CLK_ENET1_ROOT>, 1089 <&clk IMX8MM_CLK_ENET_TIMER>, 1090 <&clk IMX8MM_CLK_ENET_REF>, 1091 <&clk IMX8MM_CLK_ENET_PHY_REF>; 1092 clock-names = "ipg", "ahb", "ptp", 1093 "enet_clk_ref", "enet_out"; 1094 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 1095 <&clk IMX8MM_CLK_ENET_TIMER>, 1096 <&clk IMX8MM_CLK_ENET_REF>, 1097 <&clk IMX8MM_CLK_ENET_PHY_REF>; 1098 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 1099 <&clk IMX8MM_SYS_PLL2_100M>, 1100 <&clk IMX8MM_SYS_PLL2_125M>, 1101 <&clk IMX8MM_SYS_PLL2_50M>; 1102 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1103 fsl,num-tx-queues = <3>; 1104 fsl,num-rx-queues = <3>; 1105 nvmem-cells = <&fec_mac_address>; 1106 nvmem-cell-names = "mac-address"; 1107 fsl,stop-mode = <&gpr 0x10 3>; 1108 status = "disabled"; 1109 }; 1110 1111 }; 1112 1113 aips4: bus@32c00000 { 1114 compatible = "fsl,aips-bus", "simple-bus"; 1115 reg = <0x32c00000 0x400000>; 1116 #address-cells = <1>; 1117 #size-cells = <1>; 1118 ranges = <0x32c00000 0x32c00000 0x400000>; 1119 1120 lcdif: lcdif@32e00000 { 1121 compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif"; 1122 reg = <0x32e00000 0x10000>; 1123 clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, 1124 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1125 <&clk IMX8MM_CLK_DISP_AXI_ROOT>; 1126 clock-names = "pix", "axi", "disp_axi"; 1127 assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, 1128 <&clk IMX8MM_CLK_DISP_AXI>, 1129 <&clk IMX8MM_CLK_DISP_APB>; 1130 assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, 1131 <&clk IMX8MM_SYS_PLL2_1000M>, 1132 <&clk IMX8MM_SYS_PLL1_800M>; 1133 assigned-clock-rates = <24000000>, <500000000>, <200000000>; 1134 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1135 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; 1136 status = "disabled"; 1137 1138 port { 1139 lcdif_to_dsim: endpoint { 1140 remote-endpoint = <&dsim_from_lcdif>; 1141 }; 1142 }; 1143 }; 1144 1145 mipi_dsi: dsi@32e10000 { 1146 compatible = "fsl,imx8mm-mipi-dsim"; 1147 reg = <0x32e10000 0x400>; 1148 clocks = <&clk IMX8MM_CLK_DSI_CORE>, 1149 <&clk IMX8MM_CLK_DSI_PHY_REF>; 1150 clock-names = "bus_clk", "sclk_mipi"; 1151 assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, 1152 <&clk IMX8MM_CLK_DSI_PHY_REF>; 1153 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 1154 <&clk IMX8MM_CLK_24M>; 1155 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1156 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; 1157 status = "disabled"; 1158 1159 ports { 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 1163 port@0 { 1164 reg = <0>; 1165 1166 dsim_from_lcdif: endpoint { 1167 remote-endpoint = <&lcdif_to_dsim>; 1168 }; 1169 }; 1170 1171 port@1 { 1172 reg = <1>; 1173 1174 mipi_dsi_out: endpoint { 1175 }; 1176 }; 1177 }; 1178 }; 1179 1180 csi: csi@32e20000 { 1181 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; 1182 reg = <0x32e20000 0x1000>; 1183 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; 1185 clock-names = "mclk"; 1186 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>; 1187 status = "disabled"; 1188 1189 port { 1190 csi_in: endpoint { 1191 remote-endpoint = <&imx8mm_mipi_csi_out>; 1192 }; 1193 }; 1194 }; 1195 1196 disp_blk_ctrl: blk-ctrl@32e28000 { 1197 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; 1198 reg = <0x32e28000 0x100>; 1199 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 1200 <&pgc_dispmix>, <&pgc_mipi>, 1201 <&pgc_mipi>; 1202 power-domain-names = "bus", "csi-bridge", 1203 "lcdif", "mipi-dsi", 1204 "mipi-csi"; 1205 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, 1206 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1207 <&clk IMX8MM_CLK_CSI1_ROOT>, 1208 <&clk IMX8MM_CLK_DISP_AXI_ROOT>, 1209 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1210 <&clk IMX8MM_CLK_DISP_ROOT>, 1211 <&clk IMX8MM_CLK_DSI_CORE>, 1212 <&clk IMX8MM_CLK_DSI_PHY_REF>, 1213 <&clk IMX8MM_CLK_CSI1_CORE>, 1214 <&clk IMX8MM_CLK_CSI1_PHY_REF>; 1215 clock-names = "csi-bridge-axi","csi-bridge-apb", 1216 "csi-bridge-core", "lcdif-axi", 1217 "lcdif-apb", "lcdif-pix", 1218 "dsi-pclk", "dsi-ref", 1219 "csi-aclk", "csi-pclk"; 1220 #power-domain-cells = <1>; 1221 }; 1222 1223 mipi_csi: mipi-csi@32e30000 { 1224 compatible = "fsl,imx8mm-mipi-csi2"; 1225 reg = <0x32e30000 0x1000>; 1226 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1227 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>; 1228 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>; 1229 1230 clock-frequency = <333000000>; 1231 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1232 <&clk IMX8MM_CLK_CSI1_ROOT>, 1233 <&clk IMX8MM_CLK_CSI1_PHY_REF>, 1234 <&clk IMX8MM_CLK_DISP_AXI_ROOT>; 1235 clock-names = "pclk", "wrap", "phy", "axi"; 1236 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>; 1237 status = "disabled"; 1238 1239 ports { 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 1243 port@0 { 1244 reg = <0>; 1245 }; 1246 1247 port@1 { 1248 reg = <1>; 1249 1250 imx8mm_mipi_csi_out: endpoint { 1251 remote-endpoint = <&csi_in>; 1252 }; 1253 }; 1254 }; 1255 }; 1256 1257 usbotg1: usb@32e40000 { 1258 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1259 reg = <0x32e40000 0x200>; 1260 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1262 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1263 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1264 phys = <&usbphynop1>; 1265 fsl,usbmisc = <&usbmisc1 0>; 1266 power-domains = <&pgc_hsiomix>; 1267 status = "disabled"; 1268 }; 1269 1270 usbmisc1: usbmisc@32e40200 { 1271 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1272 "fsl,imx6q-usbmisc"; 1273 #index-cells = <1>; 1274 reg = <0x32e40200 0x200>; 1275 }; 1276 1277 usbotg2: usb@32e50000 { 1278 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1279 reg = <0x32e50000 0x200>; 1280 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1281 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1282 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1283 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1284 phys = <&usbphynop2>; 1285 fsl,usbmisc = <&usbmisc2 0>; 1286 power-domains = <&pgc_hsiomix>; 1287 status = "disabled"; 1288 }; 1289 1290 usbmisc2: usbmisc@32e50200 { 1291 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1292 "fsl,imx6q-usbmisc"; 1293 #index-cells = <1>; 1294 reg = <0x32e50200 0x200>; 1295 }; 1296 1297 pcie_phy: pcie-phy@32f00000 { 1298 compatible = "fsl,imx8mm-pcie-phy"; 1299 reg = <0x32f00000 0x10000>; 1300 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 1301 clock-names = "ref"; 1302 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 1303 assigned-clock-rates = <100000000>; 1304 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; 1305 resets = <&src IMX8MQ_RESET_PCIEPHY>; 1306 reset-names = "pciephy"; 1307 #phy-cells = <0>; 1308 status = "disabled"; 1309 }; 1310 }; 1311 1312 dma_apbh: dma-controller@33000000 { 1313 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1314 reg = <0x33000000 0x2000>; 1315 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1319 #dma-cells = <1>; 1320 dma-channels = <4>; 1321 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1322 }; 1323 1324 gpmi: nand-controller@33002000 { 1325 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1329 reg-names = "gpmi-nand", "bch"; 1330 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1331 interrupt-names = "bch"; 1332 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 1333 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1334 clock-names = "gpmi_io", "gpmi_bch_apb"; 1335 dmas = <&dma_apbh 0>; 1336 dma-names = "rx-tx"; 1337 status = "disabled"; 1338 }; 1339 1340 pcie0: pcie@33800000 { 1341 compatible = "fsl,imx8mm-pcie"; 1342 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1343 reg-names = "dbi", "config"; 1344 #address-cells = <3>; 1345 #size-cells = <2>; 1346 device_type = "pci"; 1347 bus-range = <0x00 0xff>; 1348 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1349 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1350 num-lanes = <1>; 1351 num-viewport = <4>; 1352 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1353 interrupt-names = "msi"; 1354 #interrupt-cells = <1>; 1355 interrupt-map-mask = <0 0 0 0x7>; 1356 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1357 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1358 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1359 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1360 fsl,max-link-speed = <2>; 1361 linux,pci-domain = <0>; 1362 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 1363 <&clk IMX8MM_CLK_PCIE1_PHY>, 1364 <&clk IMX8MM_CLK_PCIE1_AUX>; 1365 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1366 power-domains = <&pgc_pcie>; 1367 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1368 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1369 reset-names = "apps", "turnoff"; 1370 phys = <&pcie_phy>; 1371 phy-names = "pcie-phy"; 1372 status = "disabled"; 1373 }; 1374 1375 pcie0_ep: pcie-ep@33800000 { 1376 compatible = "fsl,imx8mm-pcie-ep"; 1377 reg = <0x33800000 0x100000>, 1378 <0x18000000 0x8000000>, 1379 <0x33900000 0x100000>, 1380 <0x33b00000 0x100000>; 1381 reg-names = "dbi", "addr_space", "dbi2", "atu"; 1382 num-lanes = <1>; 1383 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1384 interrupt-names = "dma"; 1385 fsl,max-link-speed = <2>; 1386 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, 1387 <&clk IMX8MM_CLK_PCIE1_PHY>, 1388 <&clk IMX8MM_CLK_PCIE1_AUX>; 1389 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1390 power-domains = <&pgc_pcie>; 1391 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1392 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1393 reset-names = "apps", "turnoff"; 1394 phys = <&pcie_phy>; 1395 phy-names = "pcie-phy"; 1396 num-ib-windows = <4>; 1397 num-ob-windows = <4>; 1398 status = "disabled"; 1399 }; 1400 1401 gpu_3d: gpu@38000000 { 1402 compatible = "vivante,gc"; 1403 reg = <0x38000000 0x8000>; 1404 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1405 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 1406 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 1407 <&clk IMX8MM_CLK_GPU3D_ROOT>, 1408 <&clk IMX8MM_CLK_GPU3D_ROOT>; 1409 clock-names = "reg", "bus", "core", "shader"; 1410 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, 1411 <&clk IMX8MM_GPU_PLL_OUT>; 1412 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 1413 assigned-clock-rates = <0>, <800000000>; 1414 power-domains = <&pgc_gpu>; 1415 }; 1416 1417 gpu_2d: gpu@38008000 { 1418 compatible = "vivante,gc"; 1419 reg = <0x38008000 0x8000>; 1420 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1421 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 1422 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 1423 <&clk IMX8MM_CLK_GPU2D_ROOT>; 1424 clock-names = "reg", "bus", "core"; 1425 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, 1426 <&clk IMX8MM_GPU_PLL_OUT>; 1427 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 1428 assigned-clock-rates = <0>, <800000000>; 1429 power-domains = <&pgc_gpu>; 1430 }; 1431 1432 vpu_g1: video-codec@38300000 { 1433 compatible = "nxp,imx8mm-vpu-g1"; 1434 reg = <0x38300000 0x10000>; 1435 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; 1437 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; 1438 }; 1439 1440 vpu_g2: video-codec@38310000 { 1441 compatible = "nxp,imx8mq-vpu-g2"; 1442 reg = <0x38310000 0x10000>; 1443 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1444 clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; 1445 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; 1446 }; 1447 1448 vpu_blk_ctrl: blk-ctrl@38330000 { 1449 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; 1450 reg = <0x38330000 0x100>; 1451 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 1452 <&pgc_vpu_g2>, <&pgc_vpu_h1>; 1453 power-domain-names = "bus", "g1", "g2", "h1"; 1454 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, 1455 <&clk IMX8MM_CLK_VPU_G2_ROOT>, 1456 <&clk IMX8MM_CLK_VPU_H1_ROOT>; 1457 clock-names = "g1", "g2", "h1"; 1458 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, 1459 <&clk IMX8MM_CLK_VPU_G2>; 1460 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, 1461 <&clk IMX8MM_VPU_PLL_OUT>; 1462 assigned-clock-rates = <600000000>, 1463 <600000000>; 1464 #power-domain-cells = <1>; 1465 }; 1466 1467 gic: interrupt-controller@38800000 { 1468 compatible = "arm,gic-v3"; 1469 reg = <0x38800000 0x10000>, /* GIC Dist */ 1470 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ 1471 #address-cells = <0>; 1472 #interrupt-cells = <3>; 1473 interrupt-controller; 1474 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1475 }; 1476 1477 ddrc: memory-controller@3d400000 { 1478 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 1479 reg = <0x3d400000 0x400000>; 1480 clock-names = "core", "pll", "alt", "apb"; 1481 clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 1482 <&clk IMX8MM_DRAM_PLL>, 1483 <&clk IMX8MM_CLK_DRAM_ALT>, 1484 <&clk IMX8MM_CLK_DRAM_APB>; 1485 }; 1486 1487 ddr-pmu@3d800000 { 1488 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1489 reg = <0x3d800000 0x400000>; 1490 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1491 }; 1492 }; 1493}; 1494