1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2020 Arm Ltd. 3// based on the H6 dtsi, which is: 4// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-h616-ccu.h> 8#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9#include <dt-bindings/clock/sun6i-rtc.h> 10#include <dt-bindings/reset/sun50i-h616-ccu.h> 11#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 clocks = <&ccu CLK_CPUX>; 29 #cooling-cells = <2>; 30 i-cache-size = <0x8000>; 31 i-cache-line-size = <64>; 32 i-cache-sets = <256>; 33 d-cache-size = <0x8000>; 34 d-cache-line-size = <64>; 35 d-cache-sets = <128>; 36 next-level-cache = <&l2_cache>; 37 }; 38 39 cpu1: cpu@1 { 40 compatible = "arm,cortex-a53"; 41 device_type = "cpu"; 42 reg = <1>; 43 enable-method = "psci"; 44 clocks = <&ccu CLK_CPUX>; 45 #cooling-cells = <2>; 46 i-cache-size = <0x8000>; 47 i-cache-line-size = <64>; 48 i-cache-sets = <256>; 49 d-cache-size = <0x8000>; 50 d-cache-line-size = <64>; 51 d-cache-sets = <128>; 52 next-level-cache = <&l2_cache>; 53 }; 54 55 cpu2: cpu@2 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 reg = <2>; 59 enable-method = "psci"; 60 clocks = <&ccu CLK_CPUX>; 61 #cooling-cells = <2>; 62 i-cache-size = <0x8000>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <256>; 65 d-cache-size = <0x8000>; 66 d-cache-line-size = <64>; 67 d-cache-sets = <128>; 68 next-level-cache = <&l2_cache>; 69 }; 70 71 cpu3: cpu@3 { 72 compatible = "arm,cortex-a53"; 73 device_type = "cpu"; 74 reg = <3>; 75 enable-method = "psci"; 76 clocks = <&ccu CLK_CPUX>; 77 #cooling-cells = <2>; 78 i-cache-size = <0x8000>; 79 i-cache-line-size = <64>; 80 i-cache-sets = <256>; 81 d-cache-size = <0x8000>; 82 d-cache-line-size = <64>; 83 d-cache-sets = <128>; 84 next-level-cache = <&l2_cache>; 85 }; 86 87 l2_cache: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 cache-size = <0x40000>; 92 cache-line-size = <64>; 93 cache-sets = <256>; 94 }; 95 }; 96 97 reserved-memory { 98 #address-cells = <2>; 99 #size-cells = <2>; 100 ranges; 101 102 /* 103 * 256 KiB reserved for Trusted Firmware-A (BL31). 104 * This is added by BL31 itself, but some bootloaders fail 105 * to propagate this into the DTB handed to kernels. 106 */ 107 secmon@40000000 { 108 reg = <0x0 0x40000000 0x0 0x40000>; 109 no-map; 110 }; 111 }; 112 113 osc24M: osc24M-clk { 114 #clock-cells = <0>; 115 compatible = "fixed-clock"; 116 clock-frequency = <24000000>; 117 clock-output-names = "osc24M"; 118 }; 119 120 pmu { 121 compatible = "arm,cortex-a53-pmu"; 122 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 126 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 127 }; 128 129 psci { 130 compatible = "arm,psci-0.2"; 131 method = "smc"; 132 }; 133 134 timer { 135 compatible = "arm,armv8-timer"; 136 arm,no-tick-in-suspend; 137 interrupts = <GIC_PPI 13 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 139 <GIC_PPI 14 140 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 141 <GIC_PPI 11 142 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 143 <GIC_PPI 10 144 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 145 }; 146 147 soc { 148 compatible = "simple-bus"; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges = <0x0 0x0 0x0 0x40000000>; 152 153 gpu: gpu@1800000 { 154 compatible = "allwinner,sun50i-h616-mali", 155 "arm,mali-bifrost"; 156 reg = <0x1800000 0x40000>; 157 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-names = "job", "mmu", "gpu"; 161 clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>; 162 clock-names = "core", "bus"; 163 power-domains = <&prcm_ppu 2>; 164 resets = <&ccu RST_BUS_GPU>; 165 status = "disabled"; 166 }; 167 168 crypto: crypto@1904000 { 169 compatible = "allwinner,sun50i-h616-crypto"; 170 reg = <0x01904000 0x800>; 171 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, 173 <&ccu CLK_MBUS_CE>, <&rtc CLK_IOSC>; 174 clock-names = "bus", "mod", "ram", "trng"; 175 resets = <&ccu RST_BUS_CE>; 176 }; 177 178 syscon: syscon@3000000 { 179 compatible = "allwinner,sun50i-h616-system-control"; 180 reg = <0x03000000 0x1000>; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 ranges; 184 185 sram_c: sram@28000 { 186 compatible = "mmio-sram"; 187 reg = <0x00028000 0x30000>; 188 #address-cells = <1>; 189 #size-cells = <1>; 190 ranges = <0 0x00028000 0x30000>; 191 }; 192 }; 193 194 ccu: clock@3001000 { 195 compatible = "allwinner,sun50i-h616-ccu"; 196 reg = <0x03001000 0x1000>; 197 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; 198 clock-names = "hosc", "losc", "iosc"; 199 #clock-cells = <1>; 200 #reset-cells = <1>; 201 }; 202 203 dma: dma-controller@3002000 { 204 compatible = "allwinner,sun50i-h616-dma", 205 "allwinner,sun50i-a100-dma"; 206 reg = <0x03002000 0x1000>; 207 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 209 clock-names = "bus", "mbus"; 210 dma-channels = <16>; 211 dma-requests = <49>; 212 resets = <&ccu RST_BUS_DMA>; 213 #dma-cells = <1>; 214 }; 215 216 sid: efuse@3006000 { 217 compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; 218 reg = <0x03006000 0x1000>; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 222 ths_calibration: thermal-sensor-calibration@14 { 223 reg = <0x14 0x8>; 224 }; 225 226 cpu_speed_grade: cpu-speed-grade@0 { 227 reg = <0x0 2>; 228 }; 229 }; 230 231 watchdog: watchdog@30090a0 { 232 compatible = "allwinner,sun50i-h616-wdt", 233 "allwinner,sun6i-a31-wdt"; 234 reg = <0x030090a0 0x20>; 235 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&osc24M>; 237 }; 238 239 pio: pinctrl@300b000 { 240 compatible = "allwinner,sun50i-h616-pinctrl"; 241 reg = <0x0300b000 0x400>; 242 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 251 clock-names = "apb", "hosc", "losc"; 252 gpio-controller; 253 #gpio-cells = <3>; 254 interrupt-controller; 255 #interrupt-cells = <3>; 256 257 ext_rgmii_pins: rgmii-pins { 258 pins = "PI0", "PI1", "PI2", "PI3", "PI4", 259 "PI5", "PI7", "PI8", "PI9", "PI10", 260 "PI11", "PI12", "PI13", "PI14", "PI15", 261 "PI16"; 262 function = "emac0"; 263 drive-strength = <40>; 264 }; 265 266 i2c0_pins: i2c0-pins { 267 pins = "PI5", "PI6"; 268 function = "i2c0"; 269 }; 270 271 i2c3_ph_pins: i2c3-ph-pins { 272 pins = "PH4", "PH5"; 273 function = "i2c3"; 274 }; 275 276 ir_rx_pin: ir-rx-pin { 277 pins = "PH10"; 278 function = "ir_rx"; 279 }; 280 281 mmc0_pins: mmc0-pins { 282 pins = "PF0", "PF1", "PF2", "PF3", 283 "PF4", "PF5"; 284 function = "mmc0"; 285 drive-strength = <30>; 286 bias-pull-up; 287 }; 288 289 /omit-if-no-ref/ 290 mmc1_pins: mmc1-pins { 291 pins = "PG0", "PG1", "PG2", "PG3", 292 "PG4", "PG5"; 293 function = "mmc1"; 294 drive-strength = <30>; 295 bias-pull-up; 296 }; 297 298 mmc2_pins: mmc2-pins { 299 pins = "PC0", "PC1", "PC5", "PC6", 300 "PC8", "PC9", "PC10", "PC11", 301 "PC13", "PC14", "PC15", "PC16"; 302 function = "mmc2"; 303 drive-strength = <30>; 304 bias-pull-up; 305 }; 306 307 /omit-if-no-ref/ 308 spi0_pins: spi0-pins { 309 pins = "PC0", "PC2", "PC4"; 310 function = "spi0"; 311 }; 312 313 /omit-if-no-ref/ 314 spi0_cs0_pin: spi0-cs0-pin { 315 pins = "PC3"; 316 function = "spi0"; 317 }; 318 319 /omit-if-no-ref/ 320 spi1_pins: spi1-pins { 321 pins = "PH6", "PH7", "PH8"; 322 function = "spi1"; 323 }; 324 325 /omit-if-no-ref/ 326 spi1_cs0_pin: spi1-cs0-pin { 327 pins = "PH5"; 328 function = "spi1"; 329 }; 330 331 spdif_tx_pin: spdif-tx-pin { 332 pins = "PH4"; 333 function = "spdif"; 334 }; 335 336 uart0_ph_pins: uart0-ph-pins { 337 pins = "PH0", "PH1"; 338 function = "uart0"; 339 }; 340 341 /omit-if-no-ref/ 342 uart1_pins: uart1-pins { 343 pins = "PG6", "PG7"; 344 function = "uart1"; 345 }; 346 347 /omit-if-no-ref/ 348 uart1_rts_cts_pins: uart1-rts-cts-pins { 349 pins = "PG8", "PG9"; 350 function = "uart1"; 351 }; 352 353 /omit-if-no-ref/ 354 x32clk_fanout_pin: x32clk-fanout-pin { 355 pins = "PG10"; 356 function = "clock"; 357 }; 358 }; 359 360 gic: interrupt-controller@3021000 { 361 compatible = "arm,gic-400"; 362 reg = <0x03021000 0x1000>, 363 <0x03022000 0x2000>, 364 <0x03024000 0x2000>, 365 <0x03026000 0x2000>; 366 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 367 interrupt-controller; 368 #interrupt-cells = <3>; 369 }; 370 371 iommu: iommu@30f0000 { 372 compatible = "allwinner,sun50i-h616-iommu"; 373 reg = <0x030f0000 0x10000>; 374 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&ccu CLK_BUS_IOMMU>; 376 resets = <&ccu RST_BUS_IOMMU>; 377 #iommu-cells = <1>; 378 }; 379 380 mmc0: mmc@4020000 { 381 compatible = "allwinner,sun50i-h616-mmc", 382 "allwinner,sun50i-a100-mmc"; 383 reg = <0x04020000 0x1000>; 384 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 385 clock-names = "ahb", "mmc"; 386 resets = <&ccu RST_BUS_MMC0>; 387 reset-names = "ahb"; 388 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&mmc0_pins>; 391 status = "disabled"; 392 max-frequency = <150000000>; 393 cap-sd-highspeed; 394 cap-mmc-highspeed; 395 mmc-ddr-3_3v; 396 cap-sdio-irq; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 }; 400 401 mmc1: mmc@4021000 { 402 compatible = "allwinner,sun50i-h616-mmc", 403 "allwinner,sun50i-a100-mmc"; 404 reg = <0x04021000 0x1000>; 405 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 406 clock-names = "ahb", "mmc"; 407 resets = <&ccu RST_BUS_MMC1>; 408 reset-names = "ahb"; 409 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&mmc1_pins>; 412 status = "disabled"; 413 max-frequency = <150000000>; 414 cap-sd-highspeed; 415 cap-mmc-highspeed; 416 mmc-ddr-3_3v; 417 cap-sdio-irq; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 }; 421 422 mmc2: mmc@4022000 { 423 compatible = "allwinner,sun50i-h616-emmc", 424 "allwinner,sun50i-a100-emmc"; 425 reg = <0x04022000 0x1000>; 426 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 427 clock-names = "ahb", "mmc"; 428 resets = <&ccu RST_BUS_MMC2>; 429 reset-names = "ahb"; 430 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&mmc2_pins>; 433 status = "disabled"; 434 max-frequency = <150000000>; 435 cap-sd-highspeed; 436 cap-mmc-highspeed; 437 mmc-ddr-3_3v; 438 cap-sdio-irq; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 }; 442 443 uart0: serial@5000000 { 444 compatible = "snps,dw-apb-uart"; 445 reg = <0x05000000 0x400>; 446 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 447 reg-shift = <2>; 448 reg-io-width = <4>; 449 clocks = <&ccu CLK_BUS_UART0>; 450 dmas = <&dma 14>, <&dma 14>; 451 dma-names = "tx", "rx"; 452 resets = <&ccu RST_BUS_UART0>; 453 status = "disabled"; 454 }; 455 456 uart1: serial@5000400 { 457 compatible = "snps,dw-apb-uart"; 458 reg = <0x05000400 0x400>; 459 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 460 reg-shift = <2>; 461 reg-io-width = <4>; 462 clocks = <&ccu CLK_BUS_UART1>; 463 dmas = <&dma 15>, <&dma 15>; 464 dma-names = "tx", "rx"; 465 resets = <&ccu RST_BUS_UART1>; 466 status = "disabled"; 467 }; 468 469 uart2: serial@5000800 { 470 compatible = "snps,dw-apb-uart"; 471 reg = <0x05000800 0x400>; 472 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 473 reg-shift = <2>; 474 reg-io-width = <4>; 475 clocks = <&ccu CLK_BUS_UART2>; 476 dmas = <&dma 16>, <&dma 16>; 477 dma-names = "tx", "rx"; 478 resets = <&ccu RST_BUS_UART2>; 479 status = "disabled"; 480 }; 481 482 uart3: serial@5000c00 { 483 compatible = "snps,dw-apb-uart"; 484 reg = <0x05000c00 0x400>; 485 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 486 reg-shift = <2>; 487 reg-io-width = <4>; 488 clocks = <&ccu CLK_BUS_UART3>; 489 dmas = <&dma 17>, <&dma 17>; 490 dma-names = "tx", "rx"; 491 resets = <&ccu RST_BUS_UART3>; 492 status = "disabled"; 493 }; 494 495 uart4: serial@5001000 { 496 compatible = "snps,dw-apb-uart"; 497 reg = <0x05001000 0x400>; 498 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 499 reg-shift = <2>; 500 reg-io-width = <4>; 501 clocks = <&ccu CLK_BUS_UART4>; 502 dmas = <&dma 18>, <&dma 18>; 503 dma-names = "tx", "rx"; 504 resets = <&ccu RST_BUS_UART4>; 505 status = "disabled"; 506 }; 507 508 uart5: serial@5001400 { 509 compatible = "snps,dw-apb-uart"; 510 reg = <0x05001400 0x400>; 511 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 512 reg-shift = <2>; 513 reg-io-width = <4>; 514 clocks = <&ccu CLK_BUS_UART5>; 515 dmas = <&dma 19>, <&dma 19>; 516 dma-names = "tx", "rx"; 517 resets = <&ccu RST_BUS_UART5>; 518 status = "disabled"; 519 }; 520 521 i2c0: i2c@5002000 { 522 compatible = "allwinner,sun50i-h616-i2c", 523 "allwinner,sun8i-v536-i2c", 524 "allwinner,sun6i-a31-i2c"; 525 reg = <0x05002000 0x400>; 526 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&ccu CLK_BUS_I2C0>; 528 dmas = <&dma 43>, <&dma 43>; 529 dma-names = "rx", "tx"; 530 resets = <&ccu RST_BUS_I2C0>; 531 pinctrl-names = "default"; 532 pinctrl-0 = <&i2c0_pins>; 533 status = "disabled"; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 }; 537 538 i2c1: i2c@5002400 { 539 compatible = "allwinner,sun50i-h616-i2c", 540 "allwinner,sun8i-v536-i2c", 541 "allwinner,sun6i-a31-i2c"; 542 reg = <0x05002400 0x400>; 543 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&ccu CLK_BUS_I2C1>; 545 dmas = <&dma 44>, <&dma 44>; 546 dma-names = "rx", "tx"; 547 resets = <&ccu RST_BUS_I2C1>; 548 status = "disabled"; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 }; 552 553 i2c2: i2c@5002800 { 554 compatible = "allwinner,sun50i-h616-i2c", 555 "allwinner,sun8i-v536-i2c", 556 "allwinner,sun6i-a31-i2c"; 557 reg = <0x05002800 0x400>; 558 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&ccu CLK_BUS_I2C2>; 560 dmas = <&dma 45>, <&dma 45>; 561 dma-names = "rx", "tx"; 562 resets = <&ccu RST_BUS_I2C2>; 563 status = "disabled"; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 }; 567 568 i2c3: i2c@5002c00 { 569 compatible = "allwinner,sun50i-h616-i2c", 570 "allwinner,sun8i-v536-i2c", 571 "allwinner,sun6i-a31-i2c"; 572 reg = <0x05002c00 0x400>; 573 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&ccu CLK_BUS_I2C3>; 575 dmas = <&dma 46>, <&dma 46>; 576 dma-names = "rx", "tx"; 577 resets = <&ccu RST_BUS_I2C3>; 578 status = "disabled"; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 }; 582 583 i2c4: i2c@5003000 { 584 compatible = "allwinner,sun50i-h616-i2c", 585 "allwinner,sun8i-v536-i2c", 586 "allwinner,sun6i-a31-i2c"; 587 reg = <0x05003000 0x400>; 588 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&ccu CLK_BUS_I2C4>; 590 dmas = <&dma 47>, <&dma 47>; 591 dma-names = "rx", "tx"; 592 resets = <&ccu RST_BUS_I2C4>; 593 status = "disabled"; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 }; 597 598 spi0: spi@5010000 { 599 compatible = "allwinner,sun50i-h616-spi", 600 "allwinner,sun8i-h3-spi"; 601 reg = <0x05010000 0x1000>; 602 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 604 clock-names = "ahb", "mod"; 605 dmas = <&dma 22>, <&dma 22>; 606 dma-names = "rx", "tx"; 607 resets = <&ccu RST_BUS_SPI0>; 608 status = "disabled"; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 }; 612 613 spi1: spi@5011000 { 614 compatible = "allwinner,sun50i-h616-spi", 615 "allwinner,sun8i-h3-spi"; 616 reg = <0x05011000 0x1000>; 617 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 619 clock-names = "ahb", "mod"; 620 dmas = <&dma 23>, <&dma 23>; 621 dma-names = "rx", "tx"; 622 resets = <&ccu RST_BUS_SPI1>; 623 status = "disabled"; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 }; 627 628 emac0: ethernet@5020000 { 629 compatible = "allwinner,sun50i-h616-emac0", 630 "allwinner,sun50i-a64-emac"; 631 reg = <0x05020000 0x10000>; 632 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 633 interrupt-names = "macirq"; 634 clocks = <&ccu CLK_BUS_EMAC0>; 635 clock-names = "stmmaceth"; 636 resets = <&ccu RST_BUS_EMAC0>; 637 reset-names = "stmmaceth"; 638 syscon = <&syscon>; 639 status = "disabled"; 640 641 mdio0: mdio { 642 compatible = "snps,dwmac-mdio"; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 }; 646 }; 647 648 gpadc: adc@5070000 { 649 compatible = "allwinner,sun50i-h616-gpadc", 650 "allwinner,sun20i-d1-gpadc"; 651 reg = <0x05070000 0x400>; 652 clocks = <&ccu CLK_BUS_GPADC>; 653 resets = <&ccu RST_BUS_GPADC>; 654 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 655 status = "disabled"; 656 #io-channel-cells = <1>; 657 }; 658 659 ths: thermal-sensor@5070400 { 660 compatible = "allwinner,sun50i-h616-ths"; 661 reg = <0x05070400 0x400>; 662 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&ccu CLK_BUS_THS>; 664 clock-names = "bus"; 665 resets = <&ccu RST_BUS_THS>; 666 nvmem-cells = <&ths_calibration>; 667 nvmem-cell-names = "calibration"; 668 allwinner,sram = <&syscon>; 669 #thermal-sensor-cells = <1>; 670 }; 671 672 lradc: lradc@5070800 { 673 compatible = "allwinner,sun50i-h616-lradc", 674 "allwinner,sun50i-r329-lradc"; 675 reg = <0x05070800 0x400>; 676 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&ccu CLK_BUS_KEYADC>; 678 resets = <&ccu RST_BUS_KEYADC>; 679 status = "disabled"; 680 }; 681 682 spdif: spdif@5093000 { 683 compatible = "allwinner,sun50i-h616-spdif"; 684 reg = <0x05093000 0x400>; 685 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 687 clock-names = "apb", "spdif"; 688 resets = <&ccu RST_BUS_SPDIF>; 689 dmas = <&dma 2>; 690 dma-names = "tx"; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&spdif_tx_pin>; 693 #sound-dai-cells = <0>; 694 status = "disabled"; 695 }; 696 697 codec: codec@5096000 { 698 #sound-dai-cells = <0>; 699 compatible = "allwinner,sun50i-h616-codec"; 700 reg = <0x05096000 0x31c>; 701 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&ccu CLK_BUS_AUDIO_CODEC>, 703 <&ccu CLK_AUDIO_CODEC_1X>; 704 clock-names = "apb", "codec"; 705 resets = <&ccu RST_BUS_AUDIO_CODEC>; 706 dmas = <&dma 6>; 707 dma-names = "tx"; 708 status = "disabled"; 709 }; 710 711 usbotg: usb@5100000 { 712 compatible = "allwinner,sun50i-h616-musb", 713 "allwinner,sun8i-h3-musb"; 714 reg = <0x05100000 0x0400>; 715 clocks = <&ccu CLK_BUS_OTG>; 716 resets = <&ccu RST_BUS_OTG>; 717 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 718 interrupt-names = "mc"; 719 phys = <&usbphy 0>; 720 phy-names = "usb"; 721 extcon = <&usbphy 0>; 722 status = "disabled"; 723 }; 724 725 usbphy: phy@5100400 { 726 compatible = "allwinner,sun50i-h616-usb-phy"; 727 reg = <0x05100400 0x24>, 728 <0x05101800 0x14>, 729 <0x05200800 0x14>, 730 <0x05310800 0x14>, 731 <0x05311800 0x14>; 732 reg-names = "phy_ctrl", 733 "pmu0", 734 "pmu1", 735 "pmu2", 736 "pmu3"; 737 clocks = <&ccu CLK_USB_PHY0>, 738 <&ccu CLK_USB_PHY1>, 739 <&ccu CLK_USB_PHY2>, 740 <&ccu CLK_USB_PHY3>, 741 <&ccu CLK_BUS_EHCI2>; 742 clock-names = "usb0_phy", 743 "usb1_phy", 744 "usb2_phy", 745 "usb3_phy", 746 "pmu2_clk"; 747 resets = <&ccu RST_USB_PHY0>, 748 <&ccu RST_USB_PHY1>, 749 <&ccu RST_USB_PHY2>, 750 <&ccu RST_USB_PHY3>; 751 reset-names = "usb0_reset", 752 "usb1_reset", 753 "usb2_reset", 754 "usb3_reset"; 755 status = "disabled"; 756 #phy-cells = <1>; 757 }; 758 759 ehci0: usb@5101000 { 760 compatible = "allwinner,sun50i-h616-ehci", 761 "generic-ehci"; 762 reg = <0x05101000 0x100>; 763 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&ccu CLK_BUS_OHCI0>, 765 <&ccu CLK_BUS_EHCI0>, 766 <&ccu CLK_USB_OHCI0>; 767 resets = <&ccu RST_BUS_OHCI0>, 768 <&ccu RST_BUS_EHCI0>; 769 phys = <&usbphy 0>; 770 phy-names = "usb"; 771 status = "disabled"; 772 }; 773 774 ohci0: usb@5101400 { 775 compatible = "allwinner,sun50i-h616-ohci", 776 "generic-ohci"; 777 reg = <0x05101400 0x100>; 778 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&ccu CLK_BUS_OHCI0>, 780 <&ccu CLK_USB_OHCI0>; 781 resets = <&ccu RST_BUS_OHCI0>; 782 phys = <&usbphy 0>; 783 phy-names = "usb"; 784 status = "disabled"; 785 }; 786 787 ehci1: usb@5200000 { 788 compatible = "allwinner,sun50i-h616-ehci", 789 "generic-ehci"; 790 reg = <0x05200000 0x100>; 791 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&ccu CLK_BUS_OHCI1>, 793 <&ccu CLK_BUS_EHCI1>, 794 <&ccu CLK_USB_OHCI1>; 795 resets = <&ccu RST_BUS_OHCI1>, 796 <&ccu RST_BUS_EHCI1>; 797 phys = <&usbphy 1>; 798 phy-names = "usb"; 799 status = "disabled"; 800 }; 801 802 ohci1: usb@5200400 { 803 compatible = "allwinner,sun50i-h616-ohci", 804 "generic-ohci"; 805 reg = <0x05200400 0x100>; 806 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&ccu CLK_BUS_OHCI1>, 808 <&ccu CLK_USB_OHCI1>; 809 resets = <&ccu RST_BUS_OHCI1>; 810 phys = <&usbphy 1>; 811 phy-names = "usb"; 812 status = "disabled"; 813 }; 814 815 ehci2: usb@5310000 { 816 compatible = "allwinner,sun50i-h616-ehci", 817 "generic-ehci"; 818 reg = <0x05310000 0x100>; 819 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&ccu CLK_BUS_OHCI2>, 821 <&ccu CLK_BUS_EHCI2>, 822 <&ccu CLK_USB_OHCI2>; 823 resets = <&ccu RST_BUS_OHCI2>, 824 <&ccu RST_BUS_EHCI2>; 825 phys = <&usbphy 2>; 826 phy-names = "usb"; 827 status = "disabled"; 828 }; 829 830 ohci2: usb@5310400 { 831 compatible = "allwinner,sun50i-h616-ohci", 832 "generic-ohci"; 833 reg = <0x05310400 0x100>; 834 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&ccu CLK_BUS_OHCI2>, 836 <&ccu CLK_USB_OHCI2>; 837 resets = <&ccu RST_BUS_OHCI2>; 838 phys = <&usbphy 2>; 839 phy-names = "usb"; 840 status = "disabled"; 841 }; 842 843 ehci3: usb@5311000 { 844 compatible = "allwinner,sun50i-h616-ehci", 845 "generic-ehci"; 846 reg = <0x05311000 0x100>; 847 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&ccu CLK_BUS_OHCI3>, 849 <&ccu CLK_BUS_EHCI3>, 850 <&ccu CLK_USB_OHCI3>; 851 resets = <&ccu RST_BUS_OHCI3>, 852 <&ccu RST_BUS_EHCI3>; 853 phys = <&usbphy 3>; 854 phy-names = "usb"; 855 status = "disabled"; 856 }; 857 858 ohci3: usb@5311400 { 859 compatible = "allwinner,sun50i-h616-ohci", 860 "generic-ohci"; 861 reg = <0x05311400 0x100>; 862 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&ccu CLK_BUS_OHCI3>, 864 <&ccu CLK_USB_OHCI3>; 865 resets = <&ccu RST_BUS_OHCI3>; 866 phys = <&usbphy 3>; 867 phy-names = "usb"; 868 status = "disabled"; 869 }; 870 871 rtc: rtc@7000000 { 872 compatible = "allwinner,sun50i-h616-rtc"; 873 reg = <0x07000000 0x400>; 874 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, 876 <&ccu CLK_PLL_SYSTEM_32K>; 877 clock-names = "bus", "hosc", 878 "pll-32k"; 879 #clock-cells = <1>; 880 }; 881 882 r_ccu: clock@7010000 { 883 compatible = "allwinner,sun50i-h616-r-ccu"; 884 reg = <0x07010000 0x210>; 885 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 886 <&ccu CLK_PLL_PERIPH0>; 887 clock-names = "hosc", "losc", "iosc", "pll-periph"; 888 #clock-cells = <1>; 889 #reset-cells = <1>; 890 }; 891 892 prcm_ppu: power-controller@7010250 { 893 compatible = "allwinner,sun50i-h616-prcm-ppu"; 894 reg = <0x07010250 0x10>; 895 #power-domain-cells = <1>; 896 }; 897 898 nmi_intc: interrupt-controller@7010320 { 899 compatible = "allwinner,sun50i-h616-nmi", 900 "allwinner,sun9i-a80-nmi"; 901 reg = <0x07010320 0xc>; 902 interrupt-controller; 903 #interrupt-cells = <2>; 904 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 905 }; 906 907 r_pio: pinctrl@7022000 { 908 compatible = "allwinner,sun50i-h616-r-pinctrl"; 909 reg = <0x07022000 0x400>; 910 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, 911 <&rtc CLK_OSC32K>; 912 clock-names = "apb", "hosc", "losc"; 913 gpio-controller; 914 #gpio-cells = <3>; 915 916 /omit-if-no-ref/ 917 r_i2c_pins: r-i2c-pins { 918 pins = "PL0", "PL1"; 919 function = "s_i2c"; 920 }; 921 922 r_rsb_pins: r-rsb-pins { 923 pins = "PL0", "PL1"; 924 function = "s_rsb"; 925 }; 926 }; 927 928 ir: ir@7040000 { 929 compatible = "allwinner,sun50i-h616-ir", 930 "allwinner,sun6i-a31-ir"; 931 reg = <0x07040000 0x400>; 932 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&r_ccu CLK_R_APB1_IR>, 934 <&r_ccu CLK_IR>; 935 clock-names = "apb", "ir"; 936 resets = <&r_ccu RST_R_APB1_IR>; 937 pinctrl-names = "default"; 938 pinctrl-0 = <&ir_rx_pin>; 939 status = "disabled"; 940 }; 941 942 r_i2c: i2c@7081400 { 943 compatible = "allwinner,sun50i-h616-i2c", 944 "allwinner,sun8i-v536-i2c", 945 "allwinner,sun6i-a31-i2c"; 946 reg = <0x07081400 0x400>; 947 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&r_ccu CLK_R_APB2_I2C>; 949 dmas = <&dma 48>, <&dma 48>; 950 dma-names = "rx", "tx"; 951 resets = <&r_ccu RST_R_APB2_I2C>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&r_i2c_pins>; 954 status = "disabled"; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 }; 958 959 r_rsb: rsb@7083000 { 960 compatible = "allwinner,sun50i-h616-rsb", 961 "allwinner,sun8i-a23-rsb"; 962 reg = <0x07083000 0x400>; 963 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&r_ccu CLK_R_APB2_RSB>; 965 clock-frequency = <3000000>; 966 resets = <&r_ccu RST_R_APB2_RSB>; 967 pinctrl-names = "default"; 968 pinctrl-0 = <&r_rsb_pins>; 969 status = "disabled"; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 }; 973 }; 974 975 thermal-zones { 976 cpu-thermal { 977 polling-delay-passive = <500>; 978 polling-delay = <1000>; 979 thermal-sensors = <&ths 2>; 980 sustainable-power = <1000>; 981 982 trips { 983 cpu_threshold: cpu-trip-0 { 984 temperature = <60000>; 985 type = "passive"; 986 hysteresis = <0>; 987 }; 988 cpu_target: cpu-trip-1 { 989 temperature = <70000>; 990 type = "passive"; 991 hysteresis = <0>; 992 }; 993 cpu_critical: cpu-trip-2 { 994 temperature = <110000>; 995 type = "critical"; 996 hysteresis = <0>; 997 }; 998 }; 999 }; 1000 1001 gpu-thermal { 1002 polling-delay-passive = <500>; 1003 polling-delay = <1000>; 1004 thermal-sensors = <&ths 0>; 1005 sustainable-power = <1100>; 1006 1007 trips { 1008 gpu_temp_critical: gpu-trip-0 { 1009 temperature = <110000>; 1010 type = "critical"; 1011 hysteresis = <0>; 1012 }; 1013 }; 1014 }; 1015 1016 ve-thermal { 1017 polling-delay-passive = <0>; 1018 polling-delay = <0>; 1019 thermal-sensors = <&ths 1>; 1020 1021 trips { 1022 ve_temp_critical: ve-trip-0 { 1023 temperature = <110000>; 1024 type = "critical"; 1025 hysteresis = <0>; 1026 }; 1027 }; 1028 }; 1029 1030 ddr-thermal { 1031 polling-delay-passive = <0>; 1032 polling-delay = <0>; 1033 thermal-sensors = <&ths 3>; 1034 1035 trips { 1036 ddr_temp_critical: ddr-trip-0 { 1037 temperature = <110000>; 1038 type = "critical"; 1039 hysteresis = <0>; 1040 }; 1041 }; 1042 }; 1043 }; 1044}; 1045