1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com> 4 * 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8 9/* 10 * Instantiate the first external CP115 11 */ 12 13#define CP11X_NAME cp1 14#define CP11X_BASE f4000000 15#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) 16#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 17#define CP11X_PCIE0_BASE f4600000 18#define CP11X_PCIE1_BASE f4620000 19#define CP11X_PCIE2_BASE f4640000 20 21#include "armada-cp115.dtsi" 22 23#undef CP11X_NAME 24#undef CP11X_BASE 25#undef CP11X_PCIEx_MEM_BASE 26#undef CP11X_PCIEx_MEM_SIZE 27#undef CP11X_PCIE0_BASE 28#undef CP11X_PCIE1_BASE 29#undef CP11X_PCIE2_BASE 30 31/* 32 * Instantiate the second external CP115 33 */ 34 35#define CP11X_NAME cp2 36#define CP11X_BASE f6000000 37#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000)) 38#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 39#define CP11X_PCIE0_BASE f6600000 40#define CP11X_PCIE1_BASE f6620000 41#define CP11X_PCIE2_BASE f6640000 42 43#include "armada-cp115.dtsi" 44 45#undef CP11X_NAME 46#undef CP11X_BASE 47#undef CP11X_PCIEx_MEM_BASE 48#undef CP11X_PCIEx_MEM_SIZE 49#undef CP11X_PCIE0_BASE 50#undef CP11X_PCIE1_BASE 51#undef CP11X_PCIE2_BASE 52 53/ { 54 model = "SolidRun CN9132 COM Express Type 7 Module"; 55 compatible = "solidrun,cn9132-sr-cex7", "marvell,cn9130"; 56 57 aliases { 58 ethernet0 = &cp0_eth1; 59 gpio3 = &cp1_gpio1; 60 gpio4 = &cp1_gpio2; 61 gpio5 = &cp2_gpio1; 62 gpio6 = &cp2_gpio2; 63 i2c0 = &cp0_i2c0; 64 i2c1 = &cp0_i2c1; 65 i2c2 = &com_clkgen_i2c; 66 i2c3 = &com_10g_led_i2c; 67 i2c4 = &com_10g_sfp_i2c0; 68 i2c5 = &com_smbus; 69 i2c6 = &com_fanctrl_i2c; 70 mmc0 = &ap_sdhci0; 71 rtc0 = &cp0_rtc; 72 }; 73 74 chosen { 75 stdout-path = "serial0:115200n8"; 76 }; 77 78 fan: pwm-fan { 79 compatible = "pwm-fan"; 80 cooling-levels = <0 51 102 153 204 255>; 81 #cooling-cells = <2>; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&cp0_fan_pwm_pins &cp0_fan_tacho_pins>; 84 pwms = <&cp0_gpio2 7 40000>; 85 interrupt-parent = <&cp0_gpio1>; 86 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 87 }; 88 89 v_1_8: regulator-1-8 { 90 compatible = "regulator-fixed"; 91 regulator-name = "1v8"; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 }; 95 96 ap_vhv: regulator-ap-vhv-1-8 { 97 compatible = "regulator-fixed"; 98 regulator-name = "ap-vhv-1v8"; 99 regulator-min-microvolt = <1800000>; 100 regulator-max-microvolt = <1800000>; 101 pinctrl-0 = <&cp0_reg_ap_vhv_pins>; 102 pinctrl-names = "default"; 103 gpios = <&cp0_gpio2 21 GPIO_ACTIVE_HIGH>; 104 enable-active-high; 105 }; 106 107 cp_vhv: regulator-cp-vhv-1-8 { 108 compatible = "regulator-fixed"; 109 regulator-name = "cp-vhv-1v8"; 110 regulator-min-microvolt = <1800000>; 111 regulator-max-microvolt = <1800000>; 112 pinctrl-0 = <&cp0_reg_cp_vhv_pins>; 113 pinctrl-names = "default"; 114 gpios = <&cp0_gpio2 17 GPIO_ACTIVE_HIGH>; 115 enable-active-high; 116 }; 117}; 118 119&ap_pinctrl { 120 ap_mmc0_pins: ap-mmc0-pins { 121 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", 122 "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12"; 123 marvell,function = "sdio"; 124 /* 125 * mpp12 is emmc reset, function should be sdio (hw_rst), 126 * but pinctrl-mvebu does not support this. 127 * 128 * From pinctrl-mvebu.h: 129 * "The name will be used to switch to this setting in DT description, e.g. 130 * marvell,function = "uart2". subname is only for debugging purposes." 131 */ 132 }; 133}; 134 135&ap_sdhci0 { 136 bus-width = <8>; 137 pinctrl-0 = <&ap_mmc0_pins>; 138 pinctrl-names = "default"; 139 vqmmc-supply = <&v_1_8>; 140 /* 141 * Not stable in HS modes - phy needs "more calibration", so disable 142 * UHS (by preventing voltage switch), SDR104, SDR50 and DDR50 modes. 143 */ 144 no-1-8-v; 145 no-sd; 146 no-sdio; 147 non-removable; 148 status = "okay"; 149}; 150 151&ap_thermal_ic { 152 polling-delay = <1000>; 153 154 trips { 155 ap_active: trip-active { 156 temperature = <40000>; 157 hysteresis = <4000>; 158 type = "active"; 159 }; 160 }; 161 162 cooling-maps { 163 map0 { 164 trip = <&ap_active>; 165 cooling-device = <&fan THERMAL_NO_LIMIT 4>; 166 }; 167 168 map1 { 169 trip = <&ap_crit>; 170 cooling-device = <&fan 4 5>; 171 }; 172 }; 173}; 174 175&cp0_ethernet { 176 status = "okay"; 177}; 178 179&cp0_eth1 { 180 pinctrl-names = "default"; 181 pinctrl-0 = <&cp0_eth1_pins>; 182 phy-mode = "rgmii-id"; 183 phy = <&cp0_eth_phy0>; 184 status = "okay"; 185}; 186 187&cp0_gpio1 { 188 status = "okay"; 189 190 /* 191 * Tacho signal used as interrupt source by pwm-fan driver. 192 * Hog IO as input to ensure mvebu-gpio irq driver`s 193 * irq_set_type can succeed. 194 */ 195 pwm-tacho-irq-hog { 196 gpio-hog; 197 gpios = <26 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; 198 input; 199 line-name = "fan-tacho"; 200 }; 201}; 202 203&cp0_gpio2 { 204 status = "okay"; 205}; 206 207&cp0_i2c0 { 208 pinctrl-names = "default"; 209 pinctrl-0 = <&cp0_i2c0_pins>; 210 clock-frequency = <100000>; 211 status = "okay"; 212 213 com_eeprom: eeprom@50 { 214 compatible = "atmel,24c02"; 215 reg = <0x50>; 216 pagesize = <8>; 217 }; 218 219 eeprom@53 { 220 compatible = "atmel,spd"; 221 reg = <0x53>; 222 }; 223}; 224 225&cp0_i2c1 { 226 pinctrl-names = "default"; 227 pinctrl-0 = <&cp0_i2c1_pins>; 228 clock-frequency = <100000>; 229 status = "okay"; 230 231 i2c-mux@77 { 232 compatible = "nxp,pca9547"; 233 reg = <0x77>; 234 i2c-mux-idle-disconnect; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 238 com_clkgen_i2c: i2c@0 { 239 #address-cells = <1>; 240 #size-cells = <0>; 241 reg = <0>; 242 243 /* clock-controller@6b */ 244 }; 245 246 com_10g_led_i2c: i2c@1 { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 reg = <1>; 250 251 /* Routed to B2B Connector as I2C_10G_LED_SCL/SDA */ 252 }; 253 254 com_10g_sfp_i2c0: i2c@2 { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 reg = <2>; 258 259 /* Routed to B2B Connector as I2C_SFP0_CP0_SCL/SDA */ 260 }; 261 262 com_smbus: i2c@3 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 reg = <3>; 266 267 /* Routed to B2B Connector as SBM_CLK/DAT */ 268 }; 269 270 com_fanctrl_i2c: i2c@4 { 271 #address-cells = <1>; 272 #size-cells = <0>; 273 reg = <4>; 274 275 /* fan-controller@2f (assembly option) */ 276 }; 277 }; 278}; 279 280&cp0_mdio { 281 pinctrl-names = "default"; 282 pinctrl-0 = <&cp0_mdio_pins>; 283 status = "okay"; 284 285 cp0_eth_phy0: ethernet-phy@0 { 286 reg = <0>; 287 }; 288}; 289 290&cp0_spi1 { 291 pinctrl-names = "default"; 292 pinctrl-0 = <&cp0_spi1_pins>; 293 status = "okay"; 294 295 flash@0 { 296 compatible = "jedec,spi-nor"; 297 reg = <0>; 298 /* read command supports max. 50MHz */ 299 spi-max-frequency = <50000000>; 300 }; 301}; 302 303&cp0_syscon0 { 304 cp0_pinctrl: pinctrl { 305 compatible = "marvell,cp115-standalone-pinctrl"; 306 307 com_10g_int0_pins: cp0-10g-int-pins { 308 marvell,pins = "mpp24"; 309 marvell,function = "gpio"; 310 }; 311 312 cp0_eth1_pins: cp0-eth1-pins { 313 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", 314 "mpp4", "mpp5", "mpp6", "mpp7", 315 "mpp8", "mpp9", "mpp10", "mpp11"; 316 /* docs call it "ge1", but cp110-pinctrl "ge0" */ 317 marvell,function = "ge0"; 318 }; 319 320 cp0_fan_pwm_pins: cp0-fan-pwm-pins { 321 marvell,pins = "mpp39"; 322 marvell,function = "gpio"; 323 }; 324 325 cp0_fan_tacho_pins: cp0-fan-tacho-pins { 326 marvell,pins = "mpp26"; 327 marvell,function = "gpio"; 328 }; 329 330 cp0_i2c0_pins: cp0-i2c0-pins { 331 marvell,pins = "mpp37", "mpp38"; 332 marvell,function = "i2c0"; 333 }; 334 335 cp0_i2c1_pins: cp0-i2c1-pins { 336 marvell,pins = "mpp35", "mpp36"; 337 marvell,function = "i2c1"; 338 }; 339 340 cp0_mdio_pins: cp0-mdio-pins { 341 marvell,pins = "mpp40", "mpp41"; 342 marvell,function = "ge"; 343 }; 344 345 cp0_mmc0_pins: cp0-mmc0-pins { 346 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59", 347 "mpp60", "mpp61"; 348 marvell,function = "sdio"; 349 }; 350 351 cp0_mmc0_cd_pins: cp0-mmc0-cd-pins { 352 marvell,pins = "mpp55"; 353 marvell,function = "sdio_cd"; 354 }; 355 356 cp0_pwrbtn_pins: cp0-pwrbtn-pins { 357 marvell,pins = "mpp31"; 358 marvell,function = "gpio"; 359 }; 360 361 cp0_reg_ap_vhv_pins: cp0-reg-ap-vhv-pins { 362 marvell,pins = "mpp53"; 363 marvell,function = "gpio"; 364 }; 365 366 cp0_reg_cp_vhv_pins: cp0-reg-cp-vhv-pins { 367 marvell,pins = "mpp49"; 368 marvell,function = "gpio"; 369 }; 370 371 cp0_spi1_pins: cp0-spi1-pins { 372 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; 373 marvell,function = "spi1"; 374 }; 375 376 cp0_spi1_cs1_pins: cp0-spi1-cs1-pins { 377 marvell,pins = "mpp12"; 378 marvell,function = "spi1"; 379 }; 380 381 cp0_uart2_pins: cp0-uart2-pins { 382 marvell,pins = "mpp50", "mpp51"; 383 marvell,function = "uart2"; 384 }; 385 }; 386}; 387 388&cp0_thermal_ic { 389 polling-delay = <1000>; 390 391 trips { 392 cp0_active: trip-active { 393 temperature = <40000>; 394 hysteresis = <4000>; 395 type = "active"; 396 }; 397 }; 398 399 cooling-maps { 400 map0 { 401 trip = <&cp0_active>; 402 cooling-device = <&fan THERMAL_NO_LIMIT 4>; 403 }; 404 405 map1 { 406 trip = <&cp0_crit>; 407 cooling-device = <&fan 4 5>; 408 }; 409 }; 410}; 411 412/* USB-2.0 Host */ 413&cp0_usb3_0 { 414 phys = <&cp0_utmi0>; 415 phy-names = "utmi"; 416 dr_mode = "host"; 417 status = "okay"; 418}; 419 420/* USB-2.0 Host */ 421&cp0_usb3_1 { 422 phys = <&cp0_utmi1>; 423 phy-names = "utmi"; 424 dr_mode = "host"; 425 status = "okay"; 426}; 427 428&cp0_utmi { 429 status = "okay"; 430}; 431 432&cp1_gpio1 { 433 status = "okay"; 434}; 435 436&cp1_gpio2 { 437 status = "okay"; 438}; 439 440&cp1_rtc { 441 status = "disabled"; 442}; 443 444&cp1_spi1 { 445 pinctrl-names = "default"; 446 pinctrl-0 = <&cp1_spi1_pins>; 447 status = "okay"; 448 449 tpm@0 { 450 reg = <0>; 451 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 452 spi-max-frequency = <10000000>; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&cp1_tpm_irq_pins>; 455 interrupt-parent = <&cp1_gpio1>; 456 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 457 }; 458}; 459 460&cp1_syscon0 { 461 cp1_pinctrl: pinctrl { 462 compatible = "marvell,cp115-standalone-pinctrl"; 463 464 com_10g_int1_pins: cp1-10g-int-pins { 465 marvell,pins = "mpp50"; 466 marvell,function = "gpio"; 467 }; 468 469 cp1_10g_phy_rst_01_pins: cp1-10g-phy-rst-01-pins { 470 marvell,pins = "mpp43"; 471 marvell,function = "gpio"; 472 }; 473 474 cp1_10g_phy_rst_23_pins: cp1-10g-phy-rst-23-pins { 475 marvell,pins = "mpp42"; 476 marvell,function = "gpio"; 477 }; 478 479 cp1_batlow_pins: cp1-batlow-pins { 480 marvell,pins = "mpp11"; 481 marvell,function = "gpio"; 482 }; 483 484 cp1_rsvd16_pins: cp1-rsvd16-pins { 485 marvell,pins = "mpp29"; 486 marvell,function = "gpio"; 487 }; 488 489 cp1_sata_act_pins: cp1-sata-act-pins { 490 marvell,pins = "mpp39"; 491 marvell,function = "gpio"; 492 }; 493 494 cp1_spi1_pins: cp1-spi1-pins { 495 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; 496 marvell,function = "spi1"; 497 }; 498 499 cp1_thrm_irq_pins: cp1-thrm-irq-pins { 500 marvell,pins = "mpp34"; 501 marvell,function = "gpio"; 502 }; 503 504 cp1_thrm_trip_pins: cp1-thrm-trip-pins { 505 marvell,pins = "mpp33"; 506 marvell,function = "gpio"; 507 }; 508 509 cp1_tpm_irq_pins: cp1-tpm-irq-pins { 510 marvell,pins = "mpp17"; 511 marvell,function = "gpio"; 512 }; 513 514 cp1_wake0_pins: cp1-wake0-pins { 515 marvell,pins = "mpp40"; 516 marvell,function = "gpio"; 517 }; 518 519 cp1_wake1_pins: cp1-wake1-pins { 520 marvell,pins = "mpp51"; 521 marvell,function = "gpio"; 522 }; 523 524 cp1_xmdio_pins: cp1-xmdio-pins { 525 marvell,pins = "mpp37", "mpp38"; 526 marvell,function = "xg"; 527 }; 528 }; 529}; 530 531&cp1_thermal_ic { 532 polling-delay = <1000>; 533 534 trips { 535 cp1_active: trip-active { 536 temperature = <40000>; 537 hysteresis = <4000>; 538 type = "active"; 539 }; 540 }; 541 542 cooling-maps { 543 map0 { 544 trip = <&cp1_active>; 545 cooling-device = <&fan THERMAL_NO_LIMIT 4>; 546 }; 547 548 map1 { 549 trip = <&cp1_crit>; 550 cooling-device = <&fan 4 5>; 551 }; 552 }; 553}; 554 555/* USB-2.0 Host */ 556&cp1_usb3_0 { 557 phys = <&cp1_utmi0>; 558 phy-names = "utmi"; 559 dr_mode = "host"; 560 status = "okay"; 561}; 562 563&cp1_utmi { 564 status = "okay"; 565}; 566 567&cp2_ethernet { 568 status = "okay"; 569}; 570 571&cp2_gpio1 { 572 status = "okay"; 573}; 574 575&cp2_gpio2 { 576 status = "okay"; 577}; 578 579&cp2_rtc { 580 status = "disabled"; 581}; 582 583&cp2_syscon0 { 584 cp2_pinctrl: pinctrl { 585 compatible = "marvell,cp115-standalone-pinctrl"; 586 587 com_10g_int2_pins: cp2-10g-int-pins { 588 marvell,pins = "mpp50"; 589 marvell,function = "gpio"; 590 }; 591 592 cp2_rsvd0_pins: cp2-rsvd0-pins { 593 marvell,pins = "mpp0"; 594 marvell,function = "gpio"; 595 }; 596 597 cp2_rsvd1_pins: cp2-rsvd1-pins { 598 marvell,pins = "mpp1"; 599 marvell,function = "gpio"; 600 }; 601 602 cp2_rsvd2_pins: cp2-rsvd2-pins { 603 marvell,pins = "mpp2"; 604 marvell,function = "gpio"; 605 }; 606 607 cp2_rsvd3_pins: cp2-rsvd3-pins { 608 marvell,pins = "mpp3"; 609 marvell,function = "gpio"; 610 }; 611 612 cp2_rsvd4_pins: cp2-rsvd4-pins { 613 marvell,pins = "mpp4"; 614 marvell,function = "gpio"; 615 }; 616 617 cp2_rsvd5_pins: cp2-rsvd5-pins { 618 marvell,pins = "mpp54"; 619 marvell,function = "gpio"; 620 }; 621 622 cp2_rsvd7_pins: cp2-rsvd7-pins { 623 marvell,pins = "mpp7"; 624 marvell,function = "gpio"; 625 }; 626 627 cp2_rsvd8_pins: cp2-rsvd8-pins { 628 marvell,pins = "mpp8"; 629 marvell,function = "gpio"; 630 }; 631 632 cp2_rsvd9_pins: cp2-rsvd9-pins { 633 marvell,pins = "mpp9"; 634 marvell,function = "gpio"; 635 }; 636 637 cp2_rsvd10_pins: cp2-rsvd10-pins { 638 marvell,pins = "mpp10"; 639 marvell,function = "gpio"; 640 }; 641 642 cp2_rsvd11_pins: cp2-rsvd11-pins { 643 marvell,pins = "mpp11"; 644 marvell,function = "gpio"; 645 }; 646 647 cp2_rsvd27_pins: cp2-rsvd27-pins { 648 marvell,pins = "mpp11"; 649 marvell,function = "gpio"; 650 }; 651 652 cp2_rsvd31_pins: cp2-rsvd31-pins { 653 marvell,pins = "mpp31"; 654 marvell,function = "gpio"; 655 }; 656 657 cp2_rsvd32_pins: cp2-rsvd32-pins { 658 marvell,pins = "mpp32"; 659 marvell,function = "gpio"; 660 }; 661 662 cp2_rsvd55_pins: cp2-rsvd55-pins { 663 marvell,pins = "mpp55"; 664 marvell,function = "gpio"; 665 }; 666 667 cp2_rsvd56_pins: cp2-rsvd56-pins { 668 marvell,pins = "mpp56"; 669 marvell,function = "gpio"; 670 }; 671 672 cp2_xmdio_pins: cp2-xmdio-pins { 673 marvell,pins = "mpp37", "mpp38"; 674 marvell,function = "xg"; 675 }; 676 }; 677}; 678 679&cp2_thermal_ic { 680 polling-delay = <1000>; 681 682 trips { 683 cp2_active: trip-active { 684 temperature = <40000>; 685 hysteresis = <4000>; 686 type = "active"; 687 }; 688 }; 689 690 cooling-maps { 691 map0 { 692 trip = <&cp2_active>; 693 cooling-device = <&fan THERMAL_NO_LIMIT 4>; 694 }; 695 696 map1 { 697 trip = <&cp2_crit>; 698 cooling-device = <&fan 4 5>; 699 }; 700 }; 701}; 702 703/* USB-2.0/3.0 Host */ 704&cp2_usb3_0 { 705 phys = <&cp2_utmi0>, <&cp2_comphy1 0>; 706 phy-names = "utmi", "comphy"; 707 dr_mode = "host"; 708 status = "okay"; 709}; 710 711&cp2_utmi { 712 status = "okay"; 713}; 714 715/* AP default console */ 716&uart0 { 717 pinctrl-0 = <&uart0_pins>; 718 pinctrl-names = "default"; 719 status = "okay"; 720}; 721