xref: /linux/drivers/crypto/intel/qat/qat_common/qat_uclo.c (revision 6ac142bf267ecf0aee5038abd00072ab583ce0de)
1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 
4 #define pr_fmt(fmt)	"QAT: " fmt
5 
6 #include <linux/align.h>
7 #include <linux/bitops.h>
8 #include <linux/slab.h>
9 #include <linux/ctype.h>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/pci_ids.h>
13 #include <linux/wordpart.h>
14 #include "adf_accel_devices.h"
15 #include "adf_anti_rb.h"
16 #include "adf_common_drv.h"
17 #include "icp_qat_uclo.h"
18 #include "icp_qat_hal.h"
19 #include "icp_qat_fw_loader_handle.h"
20 
21 #define UWORD_CPYBUF_SIZE 1024U
22 #define INVLD_UWORD 0xffffffffffull
23 #define PID_MINOR_REV 0xf
24 #define PID_MAJOR_REV (0xf << 4)
25 
26 static int qat_uclo_init_ae_data(struct icp_qat_uclo_objhandle *obj_handle,
27 				 unsigned int ae, unsigned int image_num)
28 {
29 	struct icp_qat_uclo_aedata *ae_data;
30 	struct icp_qat_uclo_encapme *encap_image;
31 	struct icp_qat_uclo_page *page = NULL;
32 	struct icp_qat_uclo_aeslice *ae_slice = NULL;
33 
34 	ae_data = &obj_handle->ae_data[ae];
35 	encap_image = &obj_handle->ae_uimage[image_num];
36 	ae_slice = &ae_data->ae_slices[ae_data->slice_num];
37 	ae_slice->encap_image = encap_image;
38 
39 	if (encap_image->img_ptr) {
40 		ae_slice->ctx_mask_assigned =
41 					encap_image->img_ptr->ctx_assigned;
42 		ae_data->eff_ustore_size = obj_handle->ustore_phy_size;
43 	} else {
44 		ae_slice->ctx_mask_assigned = 0;
45 	}
46 	ae_slice->region = kzalloc_obj(*ae_slice->region);
47 	if (!ae_slice->region)
48 		return -ENOMEM;
49 	ae_slice->page = kzalloc_obj(*ae_slice->page);
50 	if (!ae_slice->page)
51 		goto out_err;
52 	page = ae_slice->page;
53 	page->encap_page = encap_image->page;
54 	ae_slice->page->region = ae_slice->region;
55 	ae_data->slice_num++;
56 	return 0;
57 out_err:
58 	kfree(ae_slice->region);
59 	ae_slice->region = NULL;
60 	return -ENOMEM;
61 }
62 
63 static int qat_uclo_free_ae_data(struct icp_qat_uclo_aedata *ae_data)
64 {
65 	unsigned int i;
66 
67 	if (!ae_data) {
68 		pr_err("bad argument, ae_data is NULL\n");
69 		return -EINVAL;
70 	}
71 
72 	for (i = 0; i < ae_data->slice_num; i++) {
73 		kfree(ae_data->ae_slices[i].region);
74 		ae_data->ae_slices[i].region = NULL;
75 		kfree(ae_data->ae_slices[i].page);
76 		ae_data->ae_slices[i].page = NULL;
77 	}
78 	return 0;
79 }
80 
81 static char *qat_uclo_get_string(struct icp_qat_uof_strtable *str_table,
82 				 unsigned int str_offset)
83 {
84 	if (!str_table->table_len || str_offset > str_table->table_len)
85 		return NULL;
86 	return (char *)(((uintptr_t)(str_table->strings)) + str_offset);
87 }
88 
89 static int qat_uclo_check_uof_format(struct icp_qat_uof_filehdr *hdr)
90 {
91 	int maj = hdr->maj_ver & 0xff;
92 	int min = hdr->min_ver & 0xff;
93 
94 	if (hdr->file_id != ICP_QAT_UOF_FID) {
95 		pr_err("Invalid header 0x%x\n", hdr->file_id);
96 		return -EINVAL;
97 	}
98 	if (min != ICP_QAT_UOF_MINVER || maj != ICP_QAT_UOF_MAJVER) {
99 		pr_err("bad UOF version, major 0x%x, minor 0x%x\n", maj, min);
100 		return -EINVAL;
101 	}
102 	return 0;
103 }
104 
105 static int qat_uclo_check_suof_format(struct icp_qat_suof_filehdr *suof_hdr)
106 {
107 	int maj = suof_hdr->maj_ver & 0xff;
108 	int min = suof_hdr->min_ver & 0xff;
109 
110 	if (suof_hdr->file_id != ICP_QAT_SUOF_FID) {
111 		pr_err("invalid header 0x%x\n", suof_hdr->file_id);
112 		return -EINVAL;
113 	}
114 	if (suof_hdr->fw_type != 0) {
115 		pr_err("unsupported firmware type\n");
116 		return -EINVAL;
117 	}
118 	if (suof_hdr->num_chunks <= 0x1) {
119 		pr_err("SUOF chunk amount is incorrect\n");
120 		return -EINVAL;
121 	}
122 	if (maj != ICP_QAT_SUOF_MAJVER || min != ICP_QAT_SUOF_MINVER) {
123 		pr_err("bad SUOF version, major 0x%x, minor 0x%x\n", maj, min);
124 		return -EINVAL;
125 	}
126 	return 0;
127 }
128 
129 static void qat_uclo_wr_sram_by_words(struct icp_qat_fw_loader_handle *handle,
130 				      unsigned int addr, unsigned int *val,
131 				      unsigned int num_in_bytes)
132 {
133 	unsigned int outval;
134 	unsigned char *ptr = (unsigned char *)val;
135 
136 	while (num_in_bytes) {
137 		memcpy(&outval, ptr, 4);
138 		SRAM_WRITE(handle, addr, outval);
139 		num_in_bytes -= 4;
140 		ptr += 4;
141 		addr += 4;
142 	}
143 }
144 
145 static void qat_uclo_wr_umem_by_words(struct icp_qat_fw_loader_handle *handle,
146 				      unsigned char ae, unsigned int addr,
147 				      unsigned int *val,
148 				      unsigned int num_in_bytes)
149 {
150 	unsigned int outval;
151 	unsigned char *ptr = (unsigned char *)val;
152 
153 	addr >>= 0x2; /* convert to uword address */
154 
155 	while (num_in_bytes) {
156 		memcpy(&outval, ptr, 4);
157 		qat_hal_wr_umem(handle, ae, addr++, 1, &outval);
158 		num_in_bytes -= 4;
159 		ptr += 4;
160 	}
161 }
162 
163 static void qat_uclo_batch_wr_umem(struct icp_qat_fw_loader_handle *handle,
164 				   unsigned char ae,
165 				   struct icp_qat_uof_batch_init
166 				   *umem_init_header)
167 {
168 	struct icp_qat_uof_batch_init *umem_init;
169 
170 	if (!umem_init_header)
171 		return;
172 	umem_init = umem_init_header->next;
173 	while (umem_init) {
174 		unsigned int addr, *value, size;
175 
176 		ae = umem_init->ae;
177 		addr = umem_init->addr;
178 		value = umem_init->value;
179 		size = umem_init->size;
180 		qat_uclo_wr_umem_by_words(handle, ae, addr, value, size);
181 		umem_init = umem_init->next;
182 	}
183 }
184 
185 static void
186 qat_uclo_cleanup_batch_init_list(struct icp_qat_fw_loader_handle *handle,
187 				 struct icp_qat_uof_batch_init **base)
188 {
189 	struct icp_qat_uof_batch_init *umem_init;
190 
191 	umem_init = *base;
192 	while (umem_init) {
193 		struct icp_qat_uof_batch_init *pre;
194 
195 		pre = umem_init;
196 		umem_init = umem_init->next;
197 		kfree(pre);
198 	}
199 	*base = NULL;
200 }
201 
202 static int qat_uclo_parse_num(char *str, unsigned int *num)
203 {
204 	unsigned long long ae;
205 	char *end;
206 
207 	ae = simple_strtoull(str, &end, 10);
208 	if (ae > UINT_MAX || str == end || (end - str) > 19)
209 		return -EINVAL;
210 	*num = (unsigned int)ae;
211 	return 0;
212 }
213 
214 static int qat_uclo_fetch_initmem_ae(struct icp_qat_fw_loader_handle *handle,
215 				     struct icp_qat_uof_initmem *init_mem,
216 				     unsigned int size_range, unsigned int *ae)
217 {
218 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
219 	char *str;
220 
221 	if ((init_mem->addr + init_mem->num_in_bytes) > (size_range << 0x2)) {
222 		pr_err("initmem is out of range");
223 		return -EINVAL;
224 	}
225 	if (init_mem->scope != ICP_QAT_UOF_LOCAL_SCOPE) {
226 		pr_err("Memory scope for init_mem error\n");
227 		return -EINVAL;
228 	}
229 	str = qat_uclo_get_string(&obj_handle->str_table, init_mem->sym_name);
230 	if (!str) {
231 		pr_err("AE name assigned in UOF init table is NULL\n");
232 		return -EINVAL;
233 	}
234 	if (qat_uclo_parse_num(str, ae)) {
235 		pr_err("Parse num for AE number failed\n");
236 		return -EINVAL;
237 	}
238 	if (*ae >= ICP_QAT_UCLO_MAX_AE) {
239 		pr_err("ae %d out of range\n", *ae);
240 		return -EINVAL;
241 	}
242 	return 0;
243 }
244 
245 static int qat_uclo_create_batch_init_list(struct icp_qat_fw_loader_handle
246 					   *handle, struct icp_qat_uof_initmem
247 					   *init_mem, unsigned int ae,
248 					   struct icp_qat_uof_batch_init
249 					   **init_tab_base)
250 {
251 	struct icp_qat_uof_batch_init *init_header, *tail;
252 	struct icp_qat_uof_batch_init *mem_init, *tail_old;
253 	struct icp_qat_uof_memvar_attr *mem_val_attr;
254 	unsigned int i, flag = 0;
255 
256 	mem_val_attr =
257 		(struct icp_qat_uof_memvar_attr *)((uintptr_t)init_mem +
258 		sizeof(struct icp_qat_uof_initmem));
259 
260 	init_header = *init_tab_base;
261 	if (!init_header) {
262 		init_header = kzalloc_obj(*init_header);
263 		if (!init_header)
264 			return -ENOMEM;
265 		init_header->size = 1;
266 		*init_tab_base = init_header;
267 		flag = 1;
268 	}
269 	tail_old = init_header;
270 	while (tail_old->next)
271 		tail_old = tail_old->next;
272 	tail = tail_old;
273 	for (i = 0; i < init_mem->val_attr_num; i++) {
274 		mem_init = kzalloc_obj(*mem_init);
275 		if (!mem_init)
276 			goto out_err;
277 		mem_init->ae = ae;
278 		mem_init->addr = init_mem->addr + mem_val_attr->offset_in_byte;
279 		mem_init->value = &mem_val_attr->value;
280 		mem_init->size = 4;
281 		mem_init->next = NULL;
282 		tail->next = mem_init;
283 		tail = mem_init;
284 		init_header->size += qat_hal_get_ins_num();
285 		mem_val_attr++;
286 	}
287 	return 0;
288 out_err:
289 	/* Do not free the list head unless we allocated it. */
290 	tail_old = tail_old->next;
291 	if (flag) {
292 		kfree(*init_tab_base);
293 		*init_tab_base = NULL;
294 	}
295 
296 	while (tail_old) {
297 		mem_init = tail_old->next;
298 		kfree(tail_old);
299 		tail_old = mem_init;
300 	}
301 	return -ENOMEM;
302 }
303 
304 static int qat_uclo_init_lmem_seg(struct icp_qat_fw_loader_handle *handle,
305 				  struct icp_qat_uof_initmem *init_mem)
306 {
307 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
308 	unsigned int ae;
309 
310 	if (qat_uclo_fetch_initmem_ae(handle, init_mem,
311 				      handle->chip_info->lm_size, &ae))
312 		return -EINVAL;
313 	if (qat_uclo_create_batch_init_list(handle, init_mem, ae,
314 					    &obj_handle->lm_init_tab[ae]))
315 		return -EINVAL;
316 	return 0;
317 }
318 
319 static int qat_uclo_init_umem_seg(struct icp_qat_fw_loader_handle *handle,
320 				  struct icp_qat_uof_initmem *init_mem)
321 {
322 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
323 	unsigned int ae, ustore_size, uaddr, i;
324 	struct icp_qat_uclo_aedata *aed;
325 
326 	ustore_size = obj_handle->ustore_phy_size;
327 	if (qat_uclo_fetch_initmem_ae(handle, init_mem, ustore_size, &ae))
328 		return -EINVAL;
329 	if (qat_uclo_create_batch_init_list(handle, init_mem, ae,
330 					    &obj_handle->umem_init_tab[ae]))
331 		return -EINVAL;
332 	/* set the highest ustore address referenced */
333 	uaddr = (init_mem->addr + init_mem->num_in_bytes) >> 0x2;
334 	aed = &obj_handle->ae_data[ae];
335 	for (i = 0; i < aed->slice_num; i++) {
336 		if (aed->ae_slices[i].encap_image->uwords_num < uaddr)
337 			aed->ae_slices[i].encap_image->uwords_num = uaddr;
338 	}
339 	return 0;
340 }
341 
342 static int qat_uclo_init_ae_memory(struct icp_qat_fw_loader_handle *handle,
343 				   struct icp_qat_uof_initmem *init_mem)
344 {
345 	switch (init_mem->region) {
346 	case ICP_QAT_UOF_LMEM_REGION:
347 		if (qat_uclo_init_lmem_seg(handle, init_mem))
348 			return -EINVAL;
349 		break;
350 	case ICP_QAT_UOF_UMEM_REGION:
351 		if (qat_uclo_init_umem_seg(handle, init_mem))
352 			return -EINVAL;
353 		break;
354 	default:
355 		pr_err("initmem region error. region type=0x%x\n", init_mem->region);
356 		return -EINVAL;
357 	}
358 	return 0;
359 }
360 
361 static int qat_uclo_init_ustore(struct icp_qat_fw_loader_handle *handle,
362 				struct icp_qat_uclo_encapme *image)
363 {
364 	unsigned int i;
365 	struct icp_qat_uclo_encap_page *page;
366 	struct icp_qat_uof_image *uof_image;
367 	unsigned char ae;
368 	unsigned int ustore_size;
369 	unsigned int patt_pos;
370 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
371 	unsigned long ae_mask = handle->hal_handle->ae_mask;
372 	unsigned long cfg_ae_mask = handle->cfg_ae_mask;
373 	u64 *fill_data;
374 
375 	uof_image = image->img_ptr;
376 	fill_data = kcalloc(ICP_QAT_UCLO_MAX_USTORE, sizeof(u64),
377 			    GFP_KERNEL);
378 	if (!fill_data)
379 		return -ENOMEM;
380 	for (i = 0; i < ICP_QAT_UCLO_MAX_USTORE; i++)
381 		memcpy(&fill_data[i], &uof_image->fill_pattern,
382 		       sizeof(u64));
383 	page = image->page;
384 
385 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
386 		unsigned long ae_assigned = uof_image->ae_assigned;
387 
388 		if (!test_bit(ae, &ae_assigned))
389 			continue;
390 
391 		if (!test_bit(ae, &cfg_ae_mask))
392 			continue;
393 
394 		ustore_size = obj_handle->ae_data[ae].eff_ustore_size;
395 		patt_pos = page->beg_addr_p + page->micro_words_num;
396 
397 		qat_hal_wr_uwords(handle, (unsigned char)ae, 0,
398 				  page->beg_addr_p, &fill_data[0]);
399 		qat_hal_wr_uwords(handle, (unsigned char)ae, patt_pos,
400 				  ustore_size - patt_pos + 1,
401 				  &fill_data[page->beg_addr_p]);
402 	}
403 	kfree(fill_data);
404 	return 0;
405 }
406 
407 static int qat_uclo_init_memory(struct icp_qat_fw_loader_handle *handle)
408 {
409 	int i, ae;
410 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
411 	struct icp_qat_uof_initmem *initmem = obj_handle->init_mem_tab.init_mem;
412 	unsigned long ae_mask = handle->hal_handle->ae_mask;
413 
414 	for (i = 0; i < obj_handle->init_mem_tab.entry_num; i++) {
415 		if (initmem->num_in_bytes) {
416 			if (qat_uclo_init_ae_memory(handle, initmem))
417 				return -EINVAL;
418 		}
419 		initmem = (struct icp_qat_uof_initmem *)((uintptr_t)(
420 			(uintptr_t)initmem +
421 			sizeof(struct icp_qat_uof_initmem)) +
422 			(sizeof(struct icp_qat_uof_memvar_attr) *
423 			initmem->val_attr_num));
424 	}
425 
426 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
427 		if (qat_hal_batch_wr_lm(handle, ae,
428 					obj_handle->lm_init_tab[ae])) {
429 			pr_err("fail to batch init lmem for AE %d\n", ae);
430 			return -EINVAL;
431 		}
432 		qat_uclo_cleanup_batch_init_list(handle,
433 						 &obj_handle->lm_init_tab[ae]);
434 		qat_uclo_batch_wr_umem(handle, ae,
435 				       obj_handle->umem_init_tab[ae]);
436 		qat_uclo_cleanup_batch_init_list(handle,
437 						 &obj_handle->
438 						 umem_init_tab[ae]);
439 	}
440 	return 0;
441 }
442 
443 static void *qat_uclo_find_chunk(struct icp_qat_uof_objhdr *obj_hdr,
444 				 char *chunk_id, void *cur)
445 {
446 	int i;
447 	struct icp_qat_uof_chunkhdr *chunk_hdr =
448 	    (struct icp_qat_uof_chunkhdr *)
449 	    ((uintptr_t)obj_hdr + sizeof(struct icp_qat_uof_objhdr));
450 
451 	for (i = 0; i < obj_hdr->num_chunks; i++) {
452 		if ((cur < (void *)&chunk_hdr[i]) &&
453 		    !strncmp(chunk_hdr[i].chunk_id, chunk_id,
454 			     ICP_QAT_UOF_OBJID_LEN)) {
455 			return &chunk_hdr[i];
456 		}
457 	}
458 	return NULL;
459 }
460 
461 static unsigned int qat_uclo_calc_checksum(unsigned int reg, int ch)
462 {
463 	int i;
464 	unsigned int topbit = 1 << 0xF;
465 	unsigned int inbyte = (unsigned int)((reg >> 0x18) ^ ch);
466 
467 	reg ^= inbyte << 0x8;
468 	for (i = 0; i < 0x8; i++) {
469 		if (reg & topbit)
470 			reg = (reg << 1) ^ 0x1021;
471 		else
472 			reg <<= 1;
473 	}
474 	return reg & 0xFFFF;
475 }
476 
477 static unsigned int qat_uclo_calc_str_checksum(char *ptr, int num)
478 {
479 	unsigned int chksum = 0;
480 
481 	if (ptr)
482 		while (num--)
483 			chksum = qat_uclo_calc_checksum(chksum, *ptr++);
484 	return chksum;
485 }
486 
487 static struct icp_qat_uclo_objhdr *
488 qat_uclo_map_chunk(char *buf, struct icp_qat_uof_filehdr *file_hdr,
489 		   char *chunk_id)
490 {
491 	struct icp_qat_uof_filechunkhdr *file_chunk;
492 	struct icp_qat_uclo_objhdr *obj_hdr;
493 	char *chunk;
494 	int i;
495 
496 	file_chunk = (struct icp_qat_uof_filechunkhdr *)
497 		(buf + sizeof(struct icp_qat_uof_filehdr));
498 	for (i = 0; i < file_hdr->num_chunks; i++) {
499 		if (!strncmp(file_chunk->chunk_id, chunk_id,
500 			     ICP_QAT_UOF_OBJID_LEN)) {
501 			chunk = buf + file_chunk->offset;
502 			if (file_chunk->checksum != qat_uclo_calc_str_checksum(
503 				chunk, file_chunk->size))
504 				break;
505 			obj_hdr = kzalloc_obj(*obj_hdr);
506 			if (!obj_hdr)
507 				break;
508 			obj_hdr->file_buff = chunk;
509 			obj_hdr->checksum = file_chunk->checksum;
510 			obj_hdr->size = file_chunk->size;
511 			return obj_hdr;
512 		}
513 		file_chunk++;
514 	}
515 	return NULL;
516 }
517 
518 static int
519 qat_uclo_check_image_compat(struct icp_qat_uof_encap_obj *encap_uof_obj,
520 			    struct icp_qat_uof_image *image)
521 {
522 	struct icp_qat_uof_objtable *uc_var_tab, *imp_var_tab, *imp_expr_tab;
523 	struct icp_qat_uof_objtable *neigh_reg_tab;
524 	struct icp_qat_uof_code_page *code_page;
525 
526 	code_page = (struct icp_qat_uof_code_page *)
527 			((char *)image + sizeof(struct icp_qat_uof_image));
528 	uc_var_tab = (struct icp_qat_uof_objtable *)(encap_uof_obj->beg_uof +
529 		     code_page->uc_var_tab_offset);
530 	imp_var_tab = (struct icp_qat_uof_objtable *)(encap_uof_obj->beg_uof +
531 		      code_page->imp_var_tab_offset);
532 	imp_expr_tab = (struct icp_qat_uof_objtable *)
533 		       (encap_uof_obj->beg_uof +
534 		       code_page->imp_expr_tab_offset);
535 	if (uc_var_tab->entry_num || imp_var_tab->entry_num ||
536 	    imp_expr_tab->entry_num) {
537 		pr_err("UOF can't contain imported variable to be parsed\n");
538 		return -EINVAL;
539 	}
540 	neigh_reg_tab = (struct icp_qat_uof_objtable *)
541 			(encap_uof_obj->beg_uof +
542 			code_page->neigh_reg_tab_offset);
543 	if (neigh_reg_tab->entry_num) {
544 		pr_err("UOF can't contain neighbor register table\n");
545 		return -EINVAL;
546 	}
547 	if (image->numpages > 1) {
548 		pr_err("UOF can't contain multiple pages\n");
549 		return -EINVAL;
550 	}
551 	if (ICP_QAT_SHARED_USTORE_MODE(image->ae_mode)) {
552 		pr_err("UOF can't use shared control store feature\n");
553 		return -EFAULT;
554 	}
555 	if (RELOADABLE_CTX_SHARED_MODE(image->ae_mode)) {
556 		pr_err("UOF can't use reloadable feature\n");
557 		return -EFAULT;
558 	}
559 	return 0;
560 }
561 
562 static void qat_uclo_map_image_page(struct icp_qat_uof_encap_obj
563 				     *encap_uof_obj,
564 				     struct icp_qat_uof_image *img,
565 				     struct icp_qat_uclo_encap_page *page)
566 {
567 	struct icp_qat_uof_code_page *code_page;
568 	struct icp_qat_uof_code_area *code_area;
569 	struct icp_qat_uof_objtable *uword_block_tab;
570 	struct icp_qat_uof_uword_block *uwblock;
571 	int i;
572 
573 	code_page = (struct icp_qat_uof_code_page *)
574 			((char *)img + sizeof(struct icp_qat_uof_image));
575 	page->def_page = code_page->def_page;
576 	page->page_region = code_page->page_region;
577 	page->beg_addr_v = code_page->beg_addr_v;
578 	page->beg_addr_p = code_page->beg_addr_p;
579 	code_area = (struct icp_qat_uof_code_area *)(encap_uof_obj->beg_uof +
580 						code_page->code_area_offset);
581 	page->micro_words_num = code_area->micro_words_num;
582 	uword_block_tab = (struct icp_qat_uof_objtable *)
583 			  (encap_uof_obj->beg_uof +
584 			  code_area->uword_block_tab);
585 	page->uwblock_num = uword_block_tab->entry_num;
586 	uwblock = (struct icp_qat_uof_uword_block *)((char *)uword_block_tab +
587 			sizeof(struct icp_qat_uof_objtable));
588 	page->uwblock = (struct icp_qat_uclo_encap_uwblock *)uwblock;
589 	for (i = 0; i < uword_block_tab->entry_num; i++)
590 		page->uwblock[i].micro_words =
591 		(uintptr_t)encap_uof_obj->beg_uof + uwblock[i].uword_offset;
592 }
593 
594 static int qat_uclo_map_uimage(struct icp_qat_uclo_objhandle *obj_handle,
595 			       struct icp_qat_uclo_encapme *ae_uimage,
596 			       int max_image)
597 {
598 	int i, j;
599 	struct icp_qat_uof_chunkhdr *chunk_hdr = NULL;
600 	struct icp_qat_uof_image *image;
601 	struct icp_qat_uof_objtable *ae_regtab;
602 	struct icp_qat_uof_objtable *init_reg_sym_tab;
603 	struct icp_qat_uof_objtable *sbreak_tab;
604 	struct icp_qat_uof_encap_obj *encap_uof_obj =
605 					&obj_handle->encap_uof_obj;
606 
607 	for (j = 0; j < max_image; j++) {
608 		chunk_hdr = qat_uclo_find_chunk(encap_uof_obj->obj_hdr,
609 						ICP_QAT_UOF_IMAG, chunk_hdr);
610 		if (!chunk_hdr)
611 			break;
612 		image = (struct icp_qat_uof_image *)(encap_uof_obj->beg_uof +
613 						     chunk_hdr->offset);
614 		ae_regtab = (struct icp_qat_uof_objtable *)
615 			   (image->reg_tab_offset +
616 			   obj_handle->obj_hdr->file_buff);
617 		ae_uimage[j].ae_reg_num = ae_regtab->entry_num;
618 		ae_uimage[j].ae_reg = (struct icp_qat_uof_ae_reg *)
619 			(((char *)ae_regtab) +
620 			sizeof(struct icp_qat_uof_objtable));
621 		init_reg_sym_tab = (struct icp_qat_uof_objtable *)
622 				   (image->init_reg_sym_tab +
623 				   obj_handle->obj_hdr->file_buff);
624 		ae_uimage[j].init_regsym_num = init_reg_sym_tab->entry_num;
625 		ae_uimage[j].init_regsym = (struct icp_qat_uof_init_regsym *)
626 			(((char *)init_reg_sym_tab) +
627 			sizeof(struct icp_qat_uof_objtable));
628 		sbreak_tab = (struct icp_qat_uof_objtable *)
629 			(image->sbreak_tab + obj_handle->obj_hdr->file_buff);
630 		ae_uimage[j].sbreak_num = sbreak_tab->entry_num;
631 		ae_uimage[j].sbreak = (struct icp_qat_uof_sbreak *)
632 				      (((char *)sbreak_tab) +
633 				      sizeof(struct icp_qat_uof_objtable));
634 		ae_uimage[j].img_ptr = image;
635 		if (qat_uclo_check_image_compat(encap_uof_obj, image))
636 			goto out_err;
637 		ae_uimage[j].page =
638 			kzalloc_obj(struct icp_qat_uclo_encap_page);
639 		if (!ae_uimage[j].page)
640 			goto out_err;
641 		qat_uclo_map_image_page(encap_uof_obj, image,
642 					ae_uimage[j].page);
643 	}
644 	return j;
645 out_err:
646 	for (i = 0; i < j; i++)
647 		kfree(ae_uimage[i].page);
648 	return 0;
649 }
650 
651 static int qat_uclo_map_ae(struct icp_qat_fw_loader_handle *handle, int max_ae)
652 {
653 	int i, ae;
654 	int mflag = 0;
655 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
656 	unsigned long ae_mask = handle->hal_handle->ae_mask;
657 	unsigned long cfg_ae_mask = handle->cfg_ae_mask;
658 
659 	for_each_set_bit(ae, &ae_mask, max_ae) {
660 		if (!test_bit(ae, &cfg_ae_mask))
661 			continue;
662 
663 		for (i = 0; i < obj_handle->uimage_num; i++) {
664 			unsigned long ae_assigned = obj_handle->ae_uimage[i].img_ptr->ae_assigned;
665 
666 			if (!test_bit(ae, &ae_assigned))
667 				continue;
668 			mflag = 1;
669 			if (qat_uclo_init_ae_data(obj_handle, ae, i))
670 				return -EINVAL;
671 		}
672 	}
673 	if (!mflag) {
674 		pr_err("uimage uses AE not set\n");
675 		return -EINVAL;
676 	}
677 	return 0;
678 }
679 
680 static struct icp_qat_uof_strtable *
681 qat_uclo_map_str_table(struct icp_qat_uclo_objhdr *obj_hdr,
682 		       char *tab_name, struct icp_qat_uof_strtable *str_table)
683 {
684 	struct icp_qat_uof_chunkhdr *chunk_hdr;
685 
686 	chunk_hdr = qat_uclo_find_chunk((struct icp_qat_uof_objhdr *)
687 					obj_hdr->file_buff, tab_name, NULL);
688 	if (chunk_hdr) {
689 		int hdr_size;
690 
691 		memcpy(&str_table->table_len, obj_hdr->file_buff +
692 		       chunk_hdr->offset, sizeof(str_table->table_len));
693 		hdr_size = (char *)&str_table->strings - (char *)str_table;
694 		str_table->strings = (uintptr_t)obj_hdr->file_buff +
695 					chunk_hdr->offset + hdr_size;
696 		return str_table;
697 	}
698 	return NULL;
699 }
700 
701 static void
702 qat_uclo_map_initmem_table(struct icp_qat_uof_encap_obj *encap_uof_obj,
703 			   struct icp_qat_uclo_init_mem_table *init_mem_tab)
704 {
705 	struct icp_qat_uof_chunkhdr *chunk_hdr;
706 
707 	chunk_hdr = qat_uclo_find_chunk(encap_uof_obj->obj_hdr,
708 					ICP_QAT_UOF_IMEM, NULL);
709 	if (chunk_hdr) {
710 		memmove(&init_mem_tab->entry_num, encap_uof_obj->beg_uof +
711 			chunk_hdr->offset, sizeof(unsigned int));
712 		init_mem_tab->init_mem = (struct icp_qat_uof_initmem *)
713 		(encap_uof_obj->beg_uof + chunk_hdr->offset +
714 		sizeof(unsigned int));
715 	}
716 }
717 
718 static unsigned int
719 qat_uclo_get_dev_type(struct icp_qat_fw_loader_handle *handle)
720 {
721 	switch (handle->pci_dev->device) {
722 	case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
723 		return ICP_QAT_AC_895XCC_DEV_TYPE;
724 	case PCI_DEVICE_ID_INTEL_QAT_C62X:
725 		return ICP_QAT_AC_C62X_DEV_TYPE;
726 	case PCI_DEVICE_ID_INTEL_QAT_C3XXX:
727 		return ICP_QAT_AC_C3XXX_DEV_TYPE;
728 	case PCI_DEVICE_ID_INTEL_QAT_4XXX:
729 	case PCI_DEVICE_ID_INTEL_QAT_401XX:
730 	case PCI_DEVICE_ID_INTEL_QAT_402XX:
731 	case PCI_DEVICE_ID_INTEL_QAT_420XX:
732 		return ICP_QAT_AC_4XXX_A_DEV_TYPE;
733 	case PCI_DEVICE_ID_INTEL_QAT_6XXX:
734 		return ICP_QAT_AC_6XXX_DEV_TYPE;
735 	default:
736 		pr_err("unsupported device 0x%x\n", handle->pci_dev->device);
737 		return 0;
738 	}
739 }
740 
741 static int qat_uclo_check_uof_compat(struct icp_qat_uclo_objhandle *obj_handle)
742 {
743 	unsigned int maj_ver, prod_type = obj_handle->prod_type;
744 
745 	if (!(prod_type & obj_handle->encap_uof_obj.obj_hdr->ac_dev_type)) {
746 		pr_err("UOF type 0x%x doesn't match with platform 0x%x\n",
747 		       obj_handle->encap_uof_obj.obj_hdr->ac_dev_type,
748 		       prod_type);
749 		return -EINVAL;
750 	}
751 	maj_ver = obj_handle->prod_rev & 0xff;
752 	if (obj_handle->encap_uof_obj.obj_hdr->max_cpu_ver < maj_ver ||
753 	    obj_handle->encap_uof_obj.obj_hdr->min_cpu_ver > maj_ver) {
754 		pr_err("UOF majVer 0x%x out of range\n", maj_ver);
755 		return -EINVAL;
756 	}
757 	return 0;
758 }
759 
760 static int qat_uclo_init_reg(struct icp_qat_fw_loader_handle *handle,
761 			     unsigned char ae, unsigned char ctx_mask,
762 			     enum icp_qat_uof_regtype reg_type,
763 			     unsigned short reg_addr, unsigned int value)
764 {
765 	switch (reg_type) {
766 	case ICP_GPA_ABS:
767 	case ICP_GPB_ABS:
768 		ctx_mask = 0;
769 		fallthrough;
770 	case ICP_GPA_REL:
771 	case ICP_GPB_REL:
772 		return qat_hal_init_gpr(handle, ae, ctx_mask, reg_type,
773 					reg_addr, value);
774 	case ICP_SR_ABS:
775 	case ICP_DR_ABS:
776 	case ICP_SR_RD_ABS:
777 	case ICP_DR_RD_ABS:
778 		ctx_mask = 0;
779 		fallthrough;
780 	case ICP_SR_REL:
781 	case ICP_DR_REL:
782 	case ICP_SR_RD_REL:
783 	case ICP_DR_RD_REL:
784 		return qat_hal_init_rd_xfer(handle, ae, ctx_mask, reg_type,
785 					    reg_addr, value);
786 	case ICP_SR_WR_ABS:
787 	case ICP_DR_WR_ABS:
788 		ctx_mask = 0;
789 		fallthrough;
790 	case ICP_SR_WR_REL:
791 	case ICP_DR_WR_REL:
792 		return qat_hal_init_wr_xfer(handle, ae, ctx_mask, reg_type,
793 					    reg_addr, value);
794 	case ICP_NEIGH_REL:
795 		return qat_hal_init_nn(handle, ae, ctx_mask, reg_addr, value);
796 	default:
797 		pr_err("UOF uses not supported reg type 0x%x\n", reg_type);
798 		return -EFAULT;
799 	}
800 	return 0;
801 }
802 
803 static int qat_uclo_init_reg_sym(struct icp_qat_fw_loader_handle *handle,
804 				 unsigned int ae,
805 				 struct icp_qat_uclo_encapme *encap_ae)
806 {
807 	unsigned int i;
808 	unsigned char ctx_mask;
809 	struct icp_qat_uof_init_regsym *init_regsym;
810 
811 	if (ICP_QAT_CTX_MODE(encap_ae->img_ptr->ae_mode) ==
812 	    ICP_QAT_UCLO_MAX_CTX)
813 		ctx_mask = 0xff;
814 	else
815 		ctx_mask = 0x55;
816 
817 	for (i = 0; i < encap_ae->init_regsym_num; i++) {
818 		unsigned int exp_res;
819 
820 		init_regsym = &encap_ae->init_regsym[i];
821 		exp_res = init_regsym->value;
822 		switch (init_regsym->init_type) {
823 		case ICP_QAT_UOF_INIT_REG:
824 			qat_uclo_init_reg(handle, ae, ctx_mask,
825 					  (enum icp_qat_uof_regtype)
826 					  init_regsym->reg_type,
827 					  (unsigned short)init_regsym->reg_addr,
828 					  exp_res);
829 			break;
830 		case ICP_QAT_UOF_INIT_REG_CTX:
831 			/* check if ctx is appropriate for the ctxMode */
832 			if (!((1 << init_regsym->ctx) & ctx_mask)) {
833 				pr_err("invalid ctx num = 0x%x\n", init_regsym->ctx);
834 				return -EINVAL;
835 			}
836 			qat_uclo_init_reg(handle, ae,
837 					  (unsigned char)
838 					  (1 << init_regsym->ctx),
839 					  (enum icp_qat_uof_regtype)
840 					  init_regsym->reg_type,
841 					  (unsigned short)init_regsym->reg_addr,
842 					  exp_res);
843 			break;
844 		case ICP_QAT_UOF_INIT_EXPR:
845 			pr_err("INIT_EXPR feature not supported\n");
846 			return -EINVAL;
847 		case ICP_QAT_UOF_INIT_EXPR_ENDIAN_SWAP:
848 			pr_err("INIT_EXPR_ENDIAN_SWAP feature not supported\n");
849 			return -EINVAL;
850 		default:
851 			break;
852 		}
853 	}
854 	return 0;
855 }
856 
857 static int qat_uclo_init_globals(struct icp_qat_fw_loader_handle *handle)
858 {
859 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
860 	unsigned long ae_mask = handle->hal_handle->ae_mask;
861 	struct icp_qat_uclo_aedata *aed;
862 	unsigned int s, ae;
863 
864 	if (obj_handle->global_inited)
865 		return 0;
866 	if (obj_handle->init_mem_tab.entry_num) {
867 		if (qat_uclo_init_memory(handle)) {
868 			pr_err("initialize memory failed\n");
869 			return -EINVAL;
870 		}
871 	}
872 
873 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
874 		aed = &obj_handle->ae_data[ae];
875 		for (s = 0; s < aed->slice_num; s++) {
876 			if (!aed->ae_slices[s].encap_image)
877 				continue;
878 			if (qat_uclo_init_reg_sym(handle, ae, aed->ae_slices[s].encap_image))
879 				return -EINVAL;
880 		}
881 	}
882 	obj_handle->global_inited = 1;
883 	return 0;
884 }
885 
886 static int qat_hal_set_modes(struct icp_qat_fw_loader_handle *handle,
887 			     struct icp_qat_uclo_objhandle *obj_handle,
888 			     unsigned char ae,
889 			     struct icp_qat_uof_image *uof_image)
890 {
891 	unsigned char mode;
892 	int ret;
893 
894 	mode = ICP_QAT_CTX_MODE(uof_image->ae_mode);
895 	ret = qat_hal_set_ae_ctx_mode(handle, ae, mode);
896 	if (ret) {
897 		pr_err("qat_hal_set_ae_ctx_mode error\n");
898 		return ret;
899 	}
900 	if (handle->chip_info->nn) {
901 		mode = ICP_QAT_NN_MODE(uof_image->ae_mode);
902 		ret = qat_hal_set_ae_nn_mode(handle, ae, mode);
903 		if (ret) {
904 			pr_err("qat_hal_set_ae_nn_mode error\n");
905 			return ret;
906 		}
907 	}
908 	mode = ICP_QAT_LOC_MEM0_MODE(uof_image->ae_mode);
909 	ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM0, mode);
910 	if (ret) {
911 		pr_err("qat_hal_set_ae_lm_mode LMEM0 error\n");
912 		return ret;
913 	}
914 	mode = ICP_QAT_LOC_MEM1_MODE(uof_image->ae_mode);
915 	ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM1, mode);
916 	if (ret) {
917 		pr_err("qat_hal_set_ae_lm_mode LMEM1 error\n");
918 		return ret;
919 	}
920 	if (handle->chip_info->lm2lm3) {
921 		mode = ICP_QAT_LOC_MEM2_MODE(uof_image->ae_mode);
922 		ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM2, mode);
923 		if (ret) {
924 			pr_err("qat_hal_set_ae_lm_mode LMEM2 error\n");
925 			return ret;
926 		}
927 		mode = ICP_QAT_LOC_MEM3_MODE(uof_image->ae_mode);
928 		ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM3, mode);
929 		if (ret) {
930 			pr_err("qat_hal_set_ae_lm_mode LMEM3 error\n");
931 			return ret;
932 		}
933 		mode = ICP_QAT_LOC_TINDEX_MODE(uof_image->ae_mode);
934 		qat_hal_set_ae_tindex_mode(handle, ae, mode);
935 	}
936 	return 0;
937 }
938 
939 static int qat_uclo_set_ae_mode(struct icp_qat_fw_loader_handle *handle)
940 {
941 	struct icp_qat_uof_image *uof_image;
942 	struct icp_qat_uclo_aedata *ae_data;
943 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
944 	unsigned long ae_mask = handle->hal_handle->ae_mask;
945 	unsigned long cfg_ae_mask = handle->cfg_ae_mask;
946 	unsigned char ae, s;
947 	int error;
948 
949 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
950 		if (!test_bit(ae, &cfg_ae_mask))
951 			continue;
952 
953 		ae_data = &obj_handle->ae_data[ae];
954 		for (s = 0; s < min_t(unsigned int, ae_data->slice_num,
955 				      ICP_QAT_UCLO_MAX_CTX); s++) {
956 			if (!obj_handle->ae_data[ae].ae_slices[s].encap_image)
957 				continue;
958 			uof_image = ae_data->ae_slices[s].encap_image->img_ptr;
959 			error = qat_hal_set_modes(handle, obj_handle, ae,
960 						  uof_image);
961 			if (error)
962 				return error;
963 		}
964 	}
965 	return 0;
966 }
967 
968 static void qat_uclo_init_uword_num(struct icp_qat_fw_loader_handle *handle)
969 {
970 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
971 	struct icp_qat_uclo_encapme *image;
972 	int a;
973 
974 	for (a = 0; a < obj_handle->uimage_num; a++) {
975 		image = &obj_handle->ae_uimage[a];
976 		image->uwords_num = image->page->beg_addr_p +
977 					image->page->micro_words_num;
978 	}
979 }
980 
981 static int qat_uclo_parse_uof_obj(struct icp_qat_fw_loader_handle *handle)
982 {
983 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
984 	unsigned int ae;
985 
986 	obj_handle->encap_uof_obj.beg_uof = obj_handle->obj_hdr->file_buff;
987 	obj_handle->encap_uof_obj.obj_hdr = (struct icp_qat_uof_objhdr *)
988 					     obj_handle->obj_hdr->file_buff;
989 	obj_handle->uword_in_bytes = 6;
990 	obj_handle->prod_type = qat_uclo_get_dev_type(handle);
991 	obj_handle->prod_rev = PID_MAJOR_REV |
992 			(PID_MINOR_REV & handle->hal_handle->revision_id);
993 	if (qat_uclo_check_uof_compat(obj_handle)) {
994 		pr_err("UOF incompatible\n");
995 		return -EINVAL;
996 	}
997 	obj_handle->uword_buf = kcalloc(UWORD_CPYBUF_SIZE, sizeof(u64),
998 					GFP_KERNEL);
999 	if (!obj_handle->uword_buf)
1000 		return -ENOMEM;
1001 	obj_handle->ustore_phy_size = ICP_QAT_UCLO_MAX_USTORE;
1002 	if (!obj_handle->obj_hdr->file_buff ||
1003 	    !qat_uclo_map_str_table(obj_handle->obj_hdr, ICP_QAT_UOF_STRT,
1004 				    &obj_handle->str_table)) {
1005 		pr_err("UOF doesn't have effective images\n");
1006 		goto out_err;
1007 	}
1008 	obj_handle->uimage_num =
1009 		qat_uclo_map_uimage(obj_handle, obj_handle->ae_uimage,
1010 				    ICP_QAT_UCLO_MAX_AE * ICP_QAT_UCLO_MAX_CTX);
1011 	if (!obj_handle->uimage_num)
1012 		goto out_err;
1013 	if (qat_uclo_map_ae(handle, handle->hal_handle->ae_max_num)) {
1014 		pr_err("Bad object\n");
1015 		goto out_check_uof_aemask_err;
1016 	}
1017 	qat_uclo_init_uword_num(handle);
1018 	qat_uclo_map_initmem_table(&obj_handle->encap_uof_obj,
1019 				   &obj_handle->init_mem_tab);
1020 	if (qat_uclo_set_ae_mode(handle))
1021 		goto out_check_uof_aemask_err;
1022 	return 0;
1023 out_check_uof_aemask_err:
1024 	for (ae = 0; ae < obj_handle->uimage_num; ae++)
1025 		kfree(obj_handle->ae_uimage[ae].page);
1026 out_err:
1027 	kfree(obj_handle->uword_buf);
1028 	return -EFAULT;
1029 }
1030 
1031 static unsigned int qat_uclo_simg_hdr2sign_len(struct icp_qat_fw_loader_handle *handle)
1032 {
1033 	if (handle->chip_info->dual_sign)
1034 		return ICP_QAT_DUALSIGN_OPAQUE_DATA_LEN;
1035 
1036 	return ICP_QAT_AE_IMG_OFFSET(handle);
1037 }
1038 
1039 static unsigned int qat_uclo_simg_hdr2cont_len(struct icp_qat_fw_loader_handle *handle)
1040 {
1041 	if (handle->chip_info->dual_sign)
1042 		return ICP_QAT_DUALSIGN_OPAQUE_DATA_LEN + ICP_QAT_DUALSIGN_MISC_INFO_LEN;
1043 
1044 	return ICP_QAT_AE_IMG_OFFSET(handle);
1045 }
1046 
1047 static unsigned int qat_uclo_simg_fw_type(struct icp_qat_fw_loader_handle *handle, void *img_ptr)
1048 {
1049 	struct icp_qat_css_hdr *hdr = img_ptr;
1050 	char *fw_hdr = img_ptr;
1051 	unsigned int offset;
1052 
1053 	if (handle->chip_info->dual_sign) {
1054 		offset = qat_uclo_simg_hdr2sign_len(handle) + ICP_QAT_DUALSIGN_FW_TYPE_LEN;
1055 		return *(fw_hdr + offset);
1056 	}
1057 
1058 	return hdr->fw_type;
1059 }
1060 
1061 static int qat_uclo_map_suof_file_hdr(struct icp_qat_fw_loader_handle *handle,
1062 				      struct icp_qat_suof_filehdr *suof_ptr,
1063 				      int suof_size)
1064 {
1065 	unsigned int check_sum = 0;
1066 	unsigned int min_ver_offset = 0;
1067 	struct icp_qat_suof_handle *suof_handle = handle->sobj_handle;
1068 
1069 	suof_handle->file_id = ICP_QAT_SUOF_FID;
1070 	suof_handle->suof_buf = (char *)suof_ptr;
1071 	suof_handle->suof_size = suof_size;
1072 	min_ver_offset = suof_size - offsetof(struct icp_qat_suof_filehdr,
1073 					      min_ver);
1074 	check_sum = qat_uclo_calc_str_checksum((char *)&suof_ptr->min_ver,
1075 					       min_ver_offset);
1076 	if (check_sum != suof_ptr->check_sum) {
1077 		pr_err("incorrect SUOF checksum\n");
1078 		return -EINVAL;
1079 	}
1080 	suof_handle->check_sum = suof_ptr->check_sum;
1081 	suof_handle->min_ver = suof_ptr->min_ver;
1082 	suof_handle->maj_ver = suof_ptr->maj_ver;
1083 	suof_handle->fw_type = suof_ptr->fw_type;
1084 	return 0;
1085 }
1086 
1087 static void qat_uclo_map_simg(struct icp_qat_fw_loader_handle *handle,
1088 			      struct icp_qat_suof_img_hdr *suof_img_hdr,
1089 			      struct icp_qat_suof_chunk_hdr *suof_chunk_hdr)
1090 {
1091 	struct icp_qat_suof_handle *suof_handle = handle->sobj_handle;
1092 	unsigned int offset = qat_uclo_simg_hdr2cont_len(handle);
1093 	struct icp_qat_suof_objhdr *suof_objhdr;
1094 	struct icp_qat_simg_ae_mode *ae_mode;
1095 
1096 	suof_img_hdr->simg_buf  = (suof_handle->suof_buf +
1097 				   suof_chunk_hdr->offset +
1098 				   sizeof(*suof_objhdr));
1099 	suof_img_hdr->simg_len = ((struct icp_qat_suof_objhdr *)(uintptr_t)
1100 				  (suof_handle->suof_buf +
1101 				   suof_chunk_hdr->offset))->img_length;
1102 
1103 	suof_img_hdr->css_header = suof_img_hdr->simg_buf;
1104 	suof_img_hdr->css_simg = suof_img_hdr->css_header + offset;
1105 
1106 	ae_mode = (struct icp_qat_simg_ae_mode *)(suof_img_hdr->css_simg);
1107 	suof_img_hdr->ae_mask = ae_mode->ae_mask;
1108 	suof_img_hdr->simg_name = (unsigned long)&ae_mode->simg_name;
1109 	suof_img_hdr->appmeta_data = (unsigned long)&ae_mode->appmeta_data;
1110 	suof_img_hdr->fw_type = ae_mode->fw_type;
1111 }
1112 
1113 static void
1114 qat_uclo_map_suof_symobjs(struct icp_qat_suof_handle *suof_handle,
1115 			  struct icp_qat_suof_chunk_hdr *suof_chunk_hdr)
1116 {
1117 	char **sym_str = (char **)&suof_handle->sym_str;
1118 	unsigned int *sym_size = &suof_handle->sym_size;
1119 	struct icp_qat_suof_strtable *str_table_obj;
1120 
1121 	*sym_size = *(unsigned int *)(uintptr_t)
1122 		   (suof_chunk_hdr->offset + suof_handle->suof_buf);
1123 	*sym_str = (char *)(uintptr_t)
1124 		   (suof_handle->suof_buf + suof_chunk_hdr->offset +
1125 		   sizeof(str_table_obj->tab_length));
1126 }
1127 
1128 static int qat_uclo_check_simg_compat(struct icp_qat_fw_loader_handle *handle,
1129 				      struct icp_qat_suof_img_hdr *img_hdr)
1130 {
1131 	struct icp_qat_simg_ae_mode *img_ae_mode = NULL;
1132 	unsigned int prod_rev, maj_ver, prod_type;
1133 
1134 	prod_type = qat_uclo_get_dev_type(handle);
1135 	img_ae_mode = (struct icp_qat_simg_ae_mode *)img_hdr->css_simg;
1136 	prod_rev = PID_MAJOR_REV |
1137 			 (PID_MINOR_REV & handle->hal_handle->revision_id);
1138 	if (img_ae_mode->dev_type != prod_type) {
1139 		pr_err("incompatible product type %x\n", img_ae_mode->dev_type);
1140 		return -EINVAL;
1141 	}
1142 	maj_ver = prod_rev & 0xff;
1143 	if (maj_ver > img_ae_mode->devmax_ver ||
1144 	    maj_ver < img_ae_mode->devmin_ver) {
1145 		pr_err("incompatible device majver 0x%x\n", maj_ver);
1146 		return -EINVAL;
1147 	}
1148 	return 0;
1149 }
1150 
1151 static void qat_uclo_del_suof(struct icp_qat_fw_loader_handle *handle)
1152 {
1153 	struct icp_qat_suof_handle *sobj_handle = handle->sobj_handle;
1154 
1155 	kfree(sobj_handle->img_table.simg_hdr);
1156 	sobj_handle->img_table.simg_hdr = NULL;
1157 	kfree(handle->sobj_handle);
1158 	handle->sobj_handle = NULL;
1159 }
1160 
1161 static void qat_uclo_tail_img(struct icp_qat_suof_img_hdr *suof_img_hdr,
1162 			      unsigned int img_id, unsigned int num_simgs)
1163 {
1164 	struct icp_qat_suof_img_hdr img_header;
1165 
1166 	if (img_id != num_simgs - 1) {
1167 		memcpy(&img_header, &suof_img_hdr[num_simgs - 1],
1168 		       sizeof(*suof_img_hdr));
1169 		memcpy(&suof_img_hdr[num_simgs - 1], &suof_img_hdr[img_id],
1170 		       sizeof(*suof_img_hdr));
1171 		memcpy(&suof_img_hdr[img_id], &img_header,
1172 		       sizeof(*suof_img_hdr));
1173 	}
1174 }
1175 
1176 static int qat_uclo_map_suof(struct icp_qat_fw_loader_handle *handle,
1177 			     struct icp_qat_suof_filehdr *suof_ptr,
1178 			     int suof_size)
1179 {
1180 	struct icp_qat_suof_handle *suof_handle = handle->sobj_handle;
1181 	struct icp_qat_suof_chunk_hdr *suof_chunk_hdr = NULL;
1182 	struct icp_qat_suof_img_hdr *suof_img_hdr = NULL;
1183 	int ret = 0, ae0_img = ICP_QAT_UCLO_MAX_AE;
1184 	unsigned int i = 0;
1185 	struct icp_qat_suof_img_hdr img_header;
1186 
1187 	if (!suof_ptr || suof_size == 0) {
1188 		pr_err("input parameter SUOF pointer/size is NULL\n");
1189 		return -EINVAL;
1190 	}
1191 	if (qat_uclo_check_suof_format(suof_ptr))
1192 		return -EINVAL;
1193 	ret = qat_uclo_map_suof_file_hdr(handle, suof_ptr, suof_size);
1194 	if (ret)
1195 		return ret;
1196 	suof_chunk_hdr = (struct icp_qat_suof_chunk_hdr *)
1197 			 ((uintptr_t)suof_ptr + sizeof(*suof_ptr));
1198 
1199 	qat_uclo_map_suof_symobjs(suof_handle, suof_chunk_hdr);
1200 	suof_handle->img_table.num_simgs = suof_ptr->num_chunks - 1;
1201 
1202 	if (suof_handle->img_table.num_simgs != 0) {
1203 		suof_img_hdr = kzalloc_objs(img_header,
1204 					    suof_handle->img_table.num_simgs);
1205 		if (!suof_img_hdr)
1206 			return -ENOMEM;
1207 		suof_handle->img_table.simg_hdr = suof_img_hdr;
1208 
1209 		for (i = 0; i < suof_handle->img_table.num_simgs; i++) {
1210 			qat_uclo_map_simg(handle, &suof_img_hdr[i],
1211 					  &suof_chunk_hdr[1 + i]);
1212 			ret = qat_uclo_check_simg_compat(handle,
1213 							 &suof_img_hdr[i]);
1214 			if (ret)
1215 				return ret;
1216 			suof_img_hdr[i].ae_mask &= handle->cfg_ae_mask;
1217 			if ((suof_img_hdr[i].ae_mask & 0x1) != 0)
1218 				ae0_img = i;
1219 		}
1220 
1221 		if (!handle->chip_info->tgroup_share_ustore) {
1222 			qat_uclo_tail_img(suof_img_hdr, ae0_img,
1223 					  suof_handle->img_table.num_simgs);
1224 		}
1225 	}
1226 	return 0;
1227 }
1228 
1229 #define ADD_ADDR(high, low)  ((((u64)high) << 32) + low)
1230 
1231 static int qat_uclo_auth_fw(struct icp_qat_fw_loader_handle *handle,
1232 			    struct icp_qat_fw_auth_desc *desc)
1233 {
1234 	unsigned int retries = FW_AUTH_MAX_RETRY;
1235 	u32 fcu_ctl_csr, fcu_sts_csr;
1236 	u32 fcu_dram_hi_csr, fcu_dram_lo_csr;
1237 	u64 bus_addr;
1238 	u32 fcu_sts;
1239 
1240 	bus_addr = ADD_ADDR(desc->css_hdr_high, desc->css_hdr_low)
1241 			   - sizeof(struct icp_qat_auth_chunk);
1242 
1243 	fcu_ctl_csr = handle->chip_info->fcu_ctl_csr;
1244 	fcu_sts_csr = handle->chip_info->fcu_sts_csr;
1245 	fcu_dram_hi_csr = handle->chip_info->fcu_dram_addr_hi;
1246 	fcu_dram_lo_csr = handle->chip_info->fcu_dram_addr_lo;
1247 
1248 	SET_CAP_CSR(handle, fcu_dram_hi_csr, bus_addr >> BITS_PER_TYPE(u32));
1249 	SET_CAP_CSR(handle, fcu_dram_lo_csr, bus_addr);
1250 	SET_CAP_CSR(handle, fcu_ctl_csr, FCU_CTRL_CMD_AUTH);
1251 
1252 	do {
1253 		int arb_ret;
1254 
1255 		msleep(FW_AUTH_WAIT_PERIOD);
1256 		fcu_sts = GET_CAP_CSR(handle, fcu_sts_csr);
1257 
1258 		arb_ret = adf_anti_rb_check(handle->pci_dev);
1259 		if (arb_ret == -EAGAIN) {
1260 			if ((fcu_sts & FCU_AUTH_STS_MASK) == FCU_STS_VERI_FAIL) {
1261 				SET_CAP_CSR(handle, fcu_ctl_csr, FCU_CTRL_CMD_AUTH);
1262 				continue;
1263 			}
1264 		} else if (arb_ret) {
1265 			goto auth_fail;
1266 		}
1267 
1268 		if ((fcu_sts & FCU_AUTH_STS_MASK) == FCU_STS_VERI_FAIL)
1269 			goto auth_fail;
1270 
1271 		if (((fcu_sts >> FCU_STS_AUTHFWLD_POS) & 0x1))
1272 			if ((fcu_sts & FCU_AUTH_STS_MASK) == FCU_STS_VERI_DONE)
1273 				return 0;
1274 	} while (--retries);
1275 
1276 auth_fail:
1277 	pr_err("authentication error (FCU_STATUS = 0x%x)\n", fcu_sts & FCU_AUTH_STS_MASK);
1278 
1279 	return -EINVAL;
1280 }
1281 
1282 static bool qat_uclo_is_broadcast(struct icp_qat_fw_loader_handle *handle,
1283 				  int imgid)
1284 {
1285 	struct icp_qat_suof_handle *sobj_handle;
1286 
1287 	if (!handle->chip_info->tgroup_share_ustore)
1288 		return false;
1289 
1290 	sobj_handle = (struct icp_qat_suof_handle *)handle->sobj_handle;
1291 	if (handle->hal_handle->admin_ae_mask &
1292 	    sobj_handle->img_table.simg_hdr[imgid].ae_mask)
1293 		return false;
1294 
1295 	return true;
1296 }
1297 
1298 static int qat_uclo_broadcast_load_fw(struct icp_qat_fw_loader_handle *handle,
1299 				      struct icp_qat_fw_auth_desc *desc)
1300 {
1301 	unsigned long ae_mask = handle->hal_handle->ae_mask;
1302 	unsigned long desc_ae_mask = desc->ae_mask;
1303 	u32 fcu_sts, ae_broadcast_mask = 0;
1304 	u32 fcu_loaded_csr, ae_loaded;
1305 	u32 fcu_sts_csr, fcu_ctl_csr;
1306 	unsigned int ae, retry = 0;
1307 
1308 	if (handle->chip_info->tgroup_share_ustore) {
1309 		fcu_ctl_csr = handle->chip_info->fcu_ctl_csr;
1310 		fcu_sts_csr = handle->chip_info->fcu_sts_csr;
1311 		fcu_loaded_csr = handle->chip_info->fcu_loaded_ae_csr;
1312 	} else {
1313 		pr_err("Chip 0x%x doesn't support broadcast load\n", handle->pci_dev->device);
1314 		return -EINVAL;
1315 	}
1316 
1317 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
1318 		if (qat_hal_check_ae_active(handle, (unsigned char)ae)) {
1319 			pr_err("Broadcast load failed. AE is not enabled or active.\n");
1320 			return -EINVAL;
1321 		}
1322 
1323 		if (test_bit(ae, &desc_ae_mask))
1324 			ae_broadcast_mask |= 1 << ae;
1325 	}
1326 
1327 	if (ae_broadcast_mask) {
1328 		SET_CAP_CSR(handle, FCU_ME_BROADCAST_MASK_TYPE,
1329 			    ae_broadcast_mask);
1330 
1331 		SET_CAP_CSR(handle, fcu_ctl_csr, FCU_CTRL_CMD_LOAD);
1332 
1333 		do {
1334 			msleep(FW_AUTH_WAIT_PERIOD);
1335 			fcu_sts = GET_CAP_CSR(handle, fcu_sts_csr);
1336 			fcu_sts &= FCU_AUTH_STS_MASK;
1337 
1338 			if (fcu_sts == FCU_STS_LOAD_FAIL) {
1339 				pr_err("Broadcast load failed: 0x%x)\n", fcu_sts);
1340 				return -EINVAL;
1341 			} else if (fcu_sts == FCU_STS_LOAD_DONE) {
1342 				ae_loaded = GET_CAP_CSR(handle, fcu_loaded_csr);
1343 				ae_loaded >>= handle->chip_info->fcu_loaded_ae_pos;
1344 
1345 				if ((ae_loaded & ae_broadcast_mask) == ae_broadcast_mask)
1346 					break;
1347 			}
1348 		} while (retry++ < FW_AUTH_MAX_RETRY);
1349 
1350 		if (retry > FW_AUTH_MAX_RETRY) {
1351 			pr_err("broadcast load failed timeout %d\n", retry);
1352 			return -EINVAL;
1353 		}
1354 	}
1355 	return 0;
1356 }
1357 
1358 static int qat_uclo_simg_alloc(struct icp_qat_fw_loader_handle *handle,
1359 			       struct icp_firml_dram_desc *dram_desc,
1360 			       unsigned int size)
1361 {
1362 	void *vptr;
1363 	dma_addr_t ptr;
1364 
1365 	vptr = dma_alloc_coherent(&handle->pci_dev->dev,
1366 				  size, &ptr, GFP_KERNEL);
1367 	if (!vptr)
1368 		return -ENOMEM;
1369 	dram_desc->dram_base_addr_v = vptr;
1370 	dram_desc->dram_bus_addr = ptr;
1371 	dram_desc->dram_size = size;
1372 	return 0;
1373 }
1374 
1375 static void qat_uclo_simg_free(struct icp_qat_fw_loader_handle *handle,
1376 			       struct icp_firml_dram_desc *dram_desc)
1377 {
1378 	if (handle && dram_desc && dram_desc->dram_base_addr_v) {
1379 		dma_free_coherent(&handle->pci_dev->dev,
1380 				  (size_t)(dram_desc->dram_size),
1381 				  dram_desc->dram_base_addr_v,
1382 				  dram_desc->dram_bus_addr);
1383 	}
1384 
1385 	if (dram_desc)
1386 		memset(dram_desc, 0, sizeof(*dram_desc));
1387 }
1388 
1389 static void qat_uclo_ummap_auth_fw(struct icp_qat_fw_loader_handle *handle,
1390 				   struct icp_qat_fw_auth_desc **desc)
1391 {
1392 	struct icp_firml_dram_desc dram_desc;
1393 
1394 	if (*desc) {
1395 		dram_desc.dram_base_addr_v = *desc;
1396 		dram_desc.dram_bus_addr = ((struct icp_qat_auth_chunk *)
1397 					   (*desc))->chunk_bus_addr;
1398 		dram_desc.dram_size = ((struct icp_qat_auth_chunk *)
1399 				       (*desc))->chunk_size;
1400 		qat_uclo_simg_free(handle, &dram_desc);
1401 	}
1402 }
1403 
1404 static int qat_uclo_check_image(struct icp_qat_fw_loader_handle *handle,
1405 				void *image, unsigned int size,
1406 				unsigned int fw_type)
1407 {
1408 	char *fw_type_name = fw_type ? "MMP" : "AE";
1409 	unsigned int css_dword_size = sizeof(u32);
1410 	unsigned int header_len, simg_type;
1411 	struct icp_qat_css_hdr *css_hdr;
1412 
1413 	if (handle->chip_info->fw_auth) {
1414 		header_len = qat_uclo_simg_hdr2sign_len(handle);
1415 		simg_type = qat_uclo_simg_fw_type(handle, image);
1416 		css_hdr = image;
1417 
1418 		if (handle->chip_info->dual_sign) {
1419 			if (css_hdr->module_type != ICP_QAT_DUALSIGN_MODULE_TYPE)
1420 				goto err;
1421 			if (css_hdr->header_len != ICP_QAT_DUALSIGN_HDR_LEN)
1422 				goto err;
1423 			if (css_hdr->header_ver != ICP_QAT_DUALSIGN_HDR_VER)
1424 				goto err;
1425 		} else {
1426 			if (css_hdr->header_len * css_dword_size != header_len)
1427 				goto err;
1428 			if (css_hdr->size * css_dword_size != size)
1429 				goto err;
1430 			if (size <= header_len)
1431 				goto err;
1432 		}
1433 
1434 		if (fw_type != simg_type)
1435 			goto err;
1436 
1437 		size -= header_len;
1438 	}
1439 
1440 	if (fw_type == CSS_AE_FIRMWARE) {
1441 		if (size < sizeof(struct icp_qat_simg_ae_mode *) +
1442 		    ICP_QAT_SIMG_AE_INIT_SEQ_LEN)
1443 			goto err;
1444 		if (size > ICP_QAT_CSS_RSA4K_MAX_IMAGE_LEN)
1445 			goto err;
1446 	} else if (fw_type == CSS_MMP_FIRMWARE) {
1447 		if (size > ICP_QAT_CSS_RSA3K_MAX_IMAGE_LEN)
1448 			goto err;
1449 	} else {
1450 		pr_err("Unsupported firmware type\n");
1451 		return -EINVAL;
1452 	}
1453 	return 0;
1454 
1455 err:
1456 	pr_err("Invalid %s firmware image\n", fw_type_name);
1457 	return -EINVAL;
1458 }
1459 
1460 static int qat_uclo_build_auth_desc_RSA(struct icp_qat_fw_loader_handle *handle,
1461 					char *image, unsigned int size,
1462 					struct icp_firml_dram_desc *dram_desc,
1463 					unsigned int fw_type, struct icp_qat_fw_auth_desc **desc)
1464 {
1465 	struct icp_qat_css_hdr *css_hdr = (struct icp_qat_css_hdr *)image;
1466 	struct icp_qat_simg_ae_mode *simg_ae_mode;
1467 	struct icp_qat_fw_auth_desc *auth_desc;
1468 	char *virt_addr, *virt_base;
1469 	u64 bus_addr;
1470 
1471 	virt_base = dram_desc->dram_base_addr_v;
1472 	virt_base += sizeof(struct icp_qat_auth_chunk);
1473 	bus_addr  = dram_desc->dram_bus_addr + sizeof(struct icp_qat_auth_chunk);
1474 	auth_desc = dram_desc->dram_base_addr_v;
1475 	auth_desc->css_hdr_high = upper_32_bits(bus_addr);
1476 	auth_desc->css_hdr_low = lower_32_bits(bus_addr);
1477 	virt_addr = virt_base;
1478 
1479 	memcpy(virt_addr, image, sizeof(*css_hdr));
1480 	/* pub key */
1481 	bus_addr = ADD_ADDR(auth_desc->css_hdr_high, auth_desc->css_hdr_low) +
1482 			   sizeof(*css_hdr);
1483 	virt_addr = virt_addr + sizeof(*css_hdr);
1484 
1485 	auth_desc->fwsk_pub_high = upper_32_bits(bus_addr);
1486 	auth_desc->fwsk_pub_low = lower_32_bits(bus_addr);
1487 
1488 	memcpy(virt_addr, image + sizeof(*css_hdr), ICP_QAT_CSS_FWSK_MODULUS_LEN(handle));
1489 	/* padding */
1490 	memset((void *)(uintptr_t)(virt_addr + ICP_QAT_CSS_FWSK_MODULUS_LEN(handle)),
1491 	       0, ICP_QAT_CSS_FWSK_PAD_LEN(handle));
1492 
1493 	/* exponent */
1494 	memcpy(virt_addr + ICP_QAT_CSS_FWSK_MODULUS_LEN(handle) +
1495 	       ICP_QAT_CSS_FWSK_PAD_LEN(handle), image + sizeof(*css_hdr) +
1496 	       ICP_QAT_CSS_FWSK_MODULUS_LEN(handle), sizeof(unsigned int));
1497 
1498 	/* signature */
1499 	bus_addr = ADD_ADDR(auth_desc->fwsk_pub_high,
1500 			    auth_desc->fwsk_pub_low) +
1501 		   ICP_QAT_CSS_FWSK_PUB_LEN(handle);
1502 	virt_addr = virt_addr + ICP_QAT_CSS_FWSK_PUB_LEN(handle);
1503 	auth_desc->signature_high = upper_32_bits(bus_addr);
1504 	auth_desc->signature_low = lower_32_bits(bus_addr);
1505 
1506 	memcpy(virt_addr, image + sizeof(*css_hdr) + ICP_QAT_CSS_FWSK_MODULUS_LEN(handle) +
1507 	       ICP_QAT_CSS_FWSK_EXPONENT_LEN(handle), ICP_QAT_CSS_SIGNATURE_LEN(handle));
1508 
1509 	bus_addr = ADD_ADDR(auth_desc->signature_high,
1510 			    auth_desc->signature_low) +
1511 		   ICP_QAT_CSS_SIGNATURE_LEN(handle);
1512 	virt_addr += ICP_QAT_CSS_SIGNATURE_LEN(handle);
1513 
1514 	auth_desc->img_high = upper_32_bits(bus_addr);
1515 	auth_desc->img_low = lower_32_bits(bus_addr);
1516 	auth_desc->img_len = size - qat_uclo_simg_hdr2sign_len(handle);
1517 	if (bus_addr + auth_desc->img_len >
1518 	    dram_desc->dram_bus_addr + ICP_QAT_CSS_RSA4K_MAX_IMAGE_LEN) {
1519 		pr_err("insufficient memory size for authentication data\n");
1520 		qat_uclo_simg_free(handle, dram_desc);
1521 		return -ENOMEM;
1522 	}
1523 
1524 	memcpy(virt_addr, image + qat_uclo_simg_hdr2sign_len(handle), auth_desc->img_len);
1525 	virt_addr = virt_base;
1526 	/* AE firmware */
1527 	if (fw_type == CSS_AE_FIRMWARE) {
1528 		auth_desc->img_ae_mode_data_high = auth_desc->img_high;
1529 		auth_desc->img_ae_mode_data_low = auth_desc->img_low;
1530 		bus_addr = ADD_ADDR(auth_desc->img_ae_mode_data_high,
1531 				    auth_desc->img_ae_mode_data_low) +
1532 			   sizeof(struct icp_qat_simg_ae_mode);
1533 
1534 		auth_desc->img_ae_init_data_high = upper_32_bits(bus_addr);
1535 		auth_desc->img_ae_init_data_low = lower_32_bits(bus_addr);
1536 		bus_addr += ICP_QAT_SIMG_AE_INIT_SEQ_LEN;
1537 		auth_desc->img_ae_insts_high = upper_32_bits(bus_addr);
1538 		auth_desc->img_ae_insts_low = lower_32_bits(bus_addr);
1539 		virt_addr += sizeof(struct icp_qat_css_hdr);
1540 		virt_addr += ICP_QAT_CSS_FWSK_PUB_LEN(handle);
1541 		virt_addr += ICP_QAT_CSS_SIGNATURE_LEN(handle);
1542 		simg_ae_mode = (struct icp_qat_simg_ae_mode *)(uintptr_t)virt_addr;
1543 		auth_desc->ae_mask = simg_ae_mode->ae_mask & handle->cfg_ae_mask;
1544 	} else {
1545 		auth_desc->img_ae_insts_high = auth_desc->img_high;
1546 		auth_desc->img_ae_insts_low = auth_desc->img_low;
1547 	}
1548 	*desc = auth_desc;
1549 	return 0;
1550 }
1551 
1552 static int qat_uclo_build_auth_desc_dualsign(struct icp_qat_fw_loader_handle *handle,
1553 					     char *image, unsigned int size,
1554 					     struct icp_firml_dram_desc *dram_desc,
1555 					     unsigned int fw_type,
1556 					     struct icp_qat_fw_auth_desc **desc)
1557 {
1558 	struct icp_qat_simg_ae_mode *simg_ae_mode;
1559 	struct icp_qat_fw_auth_desc *auth_desc;
1560 	unsigned int chunk_offset, img_offset;
1561 	u64 bus_addr, addr;
1562 	char *virt_addr;
1563 
1564 	virt_addr = dram_desc->dram_base_addr_v;
1565 	virt_addr += sizeof(struct icp_qat_auth_chunk);
1566 	bus_addr  = dram_desc->dram_bus_addr + sizeof(struct icp_qat_auth_chunk);
1567 
1568 	auth_desc = dram_desc->dram_base_addr_v;
1569 	auth_desc->img_len = size - qat_uclo_simg_hdr2sign_len(handle);
1570 	auth_desc->css_hdr_high = upper_32_bits(bus_addr);
1571 	auth_desc->css_hdr_low = lower_32_bits(bus_addr);
1572 	memcpy(virt_addr, image, ICP_QAT_DUALSIGN_OPAQUE_HDR_LEN);
1573 
1574 	img_offset = ICP_QAT_DUALSIGN_OPAQUE_HDR_LEN;
1575 	chunk_offset = ICP_QAT_DUALSIGN_OPAQUE_HDR_ALIGN_LEN;
1576 
1577 	/* RSA pub key */
1578 	addr = bus_addr + chunk_offset;
1579 	auth_desc->fwsk_pub_high = upper_32_bits(addr);
1580 	auth_desc->fwsk_pub_low = lower_32_bits(addr);
1581 	memcpy(virt_addr + chunk_offset, image + img_offset, ICP_QAT_CSS_FWSK_MODULUS_LEN(handle));
1582 
1583 	img_offset += ICP_QAT_CSS_FWSK_MODULUS_LEN(handle);
1584 	chunk_offset += ICP_QAT_CSS_FWSK_MODULUS_LEN(handle);
1585 	/* RSA padding */
1586 	memset(virt_addr + chunk_offset, 0, ICP_QAT_CSS_FWSK_PAD_LEN(handle));
1587 
1588 	chunk_offset += ICP_QAT_CSS_FWSK_PAD_LEN(handle);
1589 	/* RSA exponent */
1590 	memcpy(virt_addr + chunk_offset, image + img_offset, ICP_QAT_CSS_FWSK_EXPONENT_LEN(handle));
1591 
1592 	img_offset += ICP_QAT_CSS_FWSK_EXPONENT_LEN(handle);
1593 	chunk_offset += ICP_QAT_CSS_FWSK_EXPONENT_LEN(handle);
1594 	/* RSA signature */
1595 	addr = bus_addr + chunk_offset;
1596 	auth_desc->signature_high = upper_32_bits(addr);
1597 	auth_desc->signature_low = lower_32_bits(addr);
1598 	memcpy(virt_addr + chunk_offset, image + img_offset, ICP_QAT_CSS_SIGNATURE_LEN(handle));
1599 
1600 	img_offset += ICP_QAT_CSS_SIGNATURE_LEN(handle);
1601 	chunk_offset += ICP_QAT_CSS_SIGNATURE_LEN(handle);
1602 	/* XMSS pubkey */
1603 	addr = bus_addr + chunk_offset;
1604 	auth_desc->xmss_pubkey_high = upper_32_bits(addr);
1605 	auth_desc->xmss_pubkey_low = lower_32_bits(addr);
1606 	memcpy(virt_addr + chunk_offset, image + img_offset, ICP_QAT_DUALSIGN_XMSS_PUBKEY_LEN);
1607 
1608 	img_offset += ICP_QAT_DUALSIGN_XMSS_PUBKEY_LEN;
1609 	chunk_offset += ICP_QAT_DUALSIGN_XMSS_PUBKEY_LEN;
1610 	/* XMSS signature */
1611 	addr = bus_addr + chunk_offset;
1612 	auth_desc->xmss_sig_high = upper_32_bits(addr);
1613 	auth_desc->xmss_sig_low = lower_32_bits(addr);
1614 	memcpy(virt_addr + chunk_offset, image + img_offset, ICP_QAT_DUALSIGN_XMSS_SIG_LEN);
1615 
1616 	img_offset += ICP_QAT_DUALSIGN_XMSS_SIG_LEN;
1617 	chunk_offset += ICP_QAT_DUALSIGN_XMSS_SIG_ALIGN_LEN;
1618 
1619 	if (dram_desc->dram_size < (chunk_offset + auth_desc->img_len)) {
1620 		pr_err("auth chunk memory size is not enough to store data\n");
1621 		return -ENOMEM;
1622 	}
1623 
1624 	/* Signed data */
1625 	addr = bus_addr + chunk_offset;
1626 	auth_desc->img_high = upper_32_bits(addr);
1627 	auth_desc->img_low = lower_32_bits(addr);
1628 	memcpy(virt_addr + chunk_offset, image + img_offset, auth_desc->img_len);
1629 
1630 	chunk_offset += ICP_QAT_DUALSIGN_MISC_INFO_LEN;
1631 	/* AE firmware */
1632 	if (fw_type == CSS_AE_FIRMWARE) {
1633 		/* AE mode data */
1634 		addr = bus_addr + chunk_offset;
1635 		auth_desc->img_ae_mode_data_high = upper_32_bits(addr);
1636 		auth_desc->img_ae_mode_data_low = lower_32_bits(addr);
1637 		simg_ae_mode =
1638 			(struct icp_qat_simg_ae_mode *)(virt_addr + chunk_offset);
1639 		auth_desc->ae_mask = simg_ae_mode->ae_mask & handle->cfg_ae_mask;
1640 
1641 		chunk_offset += sizeof(struct icp_qat_simg_ae_mode);
1642 		/* AE init seq */
1643 		addr = bus_addr + chunk_offset;
1644 		auth_desc->img_ae_init_data_high = upper_32_bits(addr);
1645 		auth_desc->img_ae_init_data_low = lower_32_bits(addr);
1646 
1647 		chunk_offset += ICP_QAT_SIMG_AE_INIT_SEQ_LEN;
1648 		/* AE instructions */
1649 		addr = bus_addr + chunk_offset;
1650 		auth_desc->img_ae_insts_high = upper_32_bits(addr);
1651 		auth_desc->img_ae_insts_low = lower_32_bits(addr);
1652 	} else {
1653 		addr = bus_addr + chunk_offset;
1654 		auth_desc->img_ae_insts_high = upper_32_bits(addr);
1655 		auth_desc->img_ae_insts_low = lower_32_bits(addr);
1656 	}
1657 	*desc = auth_desc;
1658 	return 0;
1659 }
1660 
1661 static int qat_uclo_map_auth_fw(struct icp_qat_fw_loader_handle *handle,
1662 				char *image, unsigned int size,
1663 				struct icp_qat_fw_auth_desc **desc)
1664 {
1665 	struct icp_qat_auth_chunk *auth_chunk;
1666 	struct icp_firml_dram_desc img_desc;
1667 	unsigned int simg_fw_type;
1668 	int ret;
1669 
1670 	ret = qat_uclo_simg_alloc(handle, &img_desc, ICP_QAT_CSS_RSA4K_MAX_IMAGE_LEN);
1671 	if (ret)
1672 		return ret;
1673 
1674 	simg_fw_type = qat_uclo_simg_fw_type(handle, image);
1675 	auth_chunk = img_desc.dram_base_addr_v;
1676 	auth_chunk->chunk_size = img_desc.dram_size;
1677 	auth_chunk->chunk_bus_addr = img_desc.dram_bus_addr;
1678 
1679 	if (handle->chip_info->dual_sign)
1680 		return qat_uclo_build_auth_desc_dualsign(handle, image, size, &img_desc,
1681 							 simg_fw_type, desc);
1682 
1683 	return qat_uclo_build_auth_desc_RSA(handle, image, size, &img_desc,
1684 					    simg_fw_type, desc);
1685 }
1686 
1687 static int qat_uclo_load_fw(struct icp_qat_fw_loader_handle *handle,
1688 			    struct icp_qat_fw_auth_desc *desc)
1689 {
1690 	unsigned long ae_mask = handle->hal_handle->ae_mask;
1691 	u32 fcu_sts_csr, fcu_ctl_csr;
1692 	u32 loaded_aes, loaded_csr;
1693 	unsigned int i;
1694 	u32 fcu_sts;
1695 
1696 	fcu_ctl_csr = handle->chip_info->fcu_ctl_csr;
1697 	fcu_sts_csr = handle->chip_info->fcu_sts_csr;
1698 	loaded_csr = handle->chip_info->fcu_loaded_ae_csr;
1699 
1700 	for_each_set_bit(i, &ae_mask, handle->hal_handle->ae_max_num) {
1701 		int retry = 0;
1702 
1703 		if (!((desc->ae_mask >> i) & 0x1))
1704 			continue;
1705 		if (qat_hal_check_ae_active(handle, i)) {
1706 			pr_err("AE %d is active\n", i);
1707 			return -EINVAL;
1708 		}
1709 		SET_CAP_CSR(handle, fcu_ctl_csr,
1710 			    (FCU_CTRL_CMD_LOAD |
1711 			    (1 << FCU_CTRL_BROADCAST_POS) |
1712 			    (i << FCU_CTRL_AE_POS)));
1713 
1714 		do {
1715 			msleep(FW_AUTH_WAIT_PERIOD);
1716 			fcu_sts = GET_CAP_CSR(handle, fcu_sts_csr);
1717 			if ((fcu_sts & FCU_AUTH_STS_MASK) ==
1718 			    FCU_STS_LOAD_DONE) {
1719 				loaded_aes = GET_CAP_CSR(handle, loaded_csr);
1720 				loaded_aes >>= handle->chip_info->fcu_loaded_ae_pos;
1721 				if (loaded_aes & (1 << i))
1722 					break;
1723 			}
1724 		} while (retry++ < FW_AUTH_MAX_RETRY);
1725 		if (retry > FW_AUTH_MAX_RETRY) {
1726 			pr_err("firmware load failed timeout %x\n", retry);
1727 			return -EINVAL;
1728 		}
1729 	}
1730 	return 0;
1731 }
1732 
1733 static int qat_uclo_map_suof_obj(struct icp_qat_fw_loader_handle *handle,
1734 				 void *addr_ptr, int mem_size)
1735 {
1736 	struct icp_qat_suof_handle *suof_handle;
1737 
1738 	suof_handle = kzalloc_obj(*suof_handle);
1739 	if (!suof_handle)
1740 		return -ENOMEM;
1741 	handle->sobj_handle = suof_handle;
1742 	if (qat_uclo_map_suof(handle, addr_ptr, mem_size)) {
1743 		qat_uclo_del_suof(handle);
1744 		pr_err("map SUOF failed\n");
1745 		return -EINVAL;
1746 	}
1747 	return 0;
1748 }
1749 
1750 int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle,
1751 		       void *addr_ptr, int mem_size)
1752 {
1753 	struct icp_qat_fw_auth_desc *desc = NULL;
1754 	int status = 0;
1755 	int ret;
1756 
1757 	ret = qat_uclo_check_image(handle, addr_ptr, mem_size, CSS_MMP_FIRMWARE);
1758 	if (ret)
1759 		return ret;
1760 
1761 	if (handle->chip_info->fw_auth) {
1762 		status = qat_uclo_map_auth_fw(handle, addr_ptr, mem_size, &desc);
1763 		if (!status)
1764 			status = qat_uclo_auth_fw(handle, desc);
1765 		qat_uclo_ummap_auth_fw(handle, &desc);
1766 	} else {
1767 		if (handle->chip_info->mmp_sram_size < mem_size) {
1768 			pr_err("MMP size is too large: 0x%x\n", mem_size);
1769 			return -EFBIG;
1770 		}
1771 		qat_uclo_wr_sram_by_words(handle, 0, addr_ptr, mem_size);
1772 	}
1773 	return status;
1774 }
1775 
1776 static int qat_uclo_map_uof_obj(struct icp_qat_fw_loader_handle *handle,
1777 				void *addr_ptr, int mem_size)
1778 {
1779 	struct icp_qat_uof_filehdr *filehdr;
1780 	struct icp_qat_uclo_objhandle *objhdl;
1781 
1782 	objhdl = kzalloc_obj(*objhdl);
1783 	if (!objhdl)
1784 		return -ENOMEM;
1785 	objhdl->obj_buf = kmemdup(addr_ptr, mem_size, GFP_KERNEL);
1786 	if (!objhdl->obj_buf)
1787 		goto out_objbuf_err;
1788 	filehdr = (struct icp_qat_uof_filehdr *)objhdl->obj_buf;
1789 	if (qat_uclo_check_uof_format(filehdr))
1790 		goto out_objhdr_err;
1791 	objhdl->obj_hdr = qat_uclo_map_chunk((char *)objhdl->obj_buf, filehdr,
1792 					     ICP_QAT_UOF_OBJS);
1793 	if (!objhdl->obj_hdr) {
1794 		pr_err("object file chunk is null\n");
1795 		goto out_objhdr_err;
1796 	}
1797 	handle->obj_handle = objhdl;
1798 	if (qat_uclo_parse_uof_obj(handle))
1799 		goto out_overlay_obj_err;
1800 	return 0;
1801 
1802 out_overlay_obj_err:
1803 	handle->obj_handle = NULL;
1804 	kfree(objhdl->obj_hdr);
1805 out_objhdr_err:
1806 	kfree(objhdl->obj_buf);
1807 out_objbuf_err:
1808 	kfree(objhdl);
1809 	return -ENOMEM;
1810 }
1811 
1812 static int qat_uclo_map_mof_file_hdr(struct icp_qat_fw_loader_handle *handle,
1813 				     struct icp_qat_mof_file_hdr *mof_ptr,
1814 				     u32 mof_size)
1815 {
1816 	struct icp_qat_mof_handle *mobj_handle = handle->mobj_handle;
1817 	unsigned int min_ver_offset;
1818 	unsigned int checksum;
1819 
1820 	mobj_handle->file_id = ICP_QAT_MOF_FID;
1821 	mobj_handle->mof_buf = (char *)mof_ptr;
1822 	mobj_handle->mof_size = mof_size;
1823 
1824 	min_ver_offset = mof_size - offsetof(struct icp_qat_mof_file_hdr,
1825 					     min_ver);
1826 	checksum = qat_uclo_calc_str_checksum(&mof_ptr->min_ver,
1827 					      min_ver_offset);
1828 	if (checksum != mof_ptr->checksum) {
1829 		pr_err("incorrect MOF checksum\n");
1830 		return -EINVAL;
1831 	}
1832 
1833 	mobj_handle->checksum = mof_ptr->checksum;
1834 	mobj_handle->min_ver = mof_ptr->min_ver;
1835 	mobj_handle->maj_ver = mof_ptr->maj_ver;
1836 	return 0;
1837 }
1838 
1839 static void qat_uclo_del_mof(struct icp_qat_fw_loader_handle *handle)
1840 {
1841 	struct icp_qat_mof_handle *mobj_handle = handle->mobj_handle;
1842 
1843 	kfree(mobj_handle->obj_table.obj_hdr);
1844 	mobj_handle->obj_table.obj_hdr = NULL;
1845 	kfree(handle->mobj_handle);
1846 	handle->mobj_handle = NULL;
1847 }
1848 
1849 static int qat_uclo_seek_obj_inside_mof(struct icp_qat_mof_handle *mobj_handle,
1850 					const char *obj_name, char **obj_ptr,
1851 					unsigned int *obj_size)
1852 {
1853 	struct icp_qat_mof_objhdr *obj_hdr = mobj_handle->obj_table.obj_hdr;
1854 	unsigned int i;
1855 
1856 	for (i = 0; i < mobj_handle->obj_table.num_objs; i++) {
1857 		if (!strncmp(obj_hdr[i].obj_name, obj_name,
1858 			     ICP_QAT_SUOF_OBJ_NAME_LEN)) {
1859 			*obj_ptr  = obj_hdr[i].obj_buf;
1860 			*obj_size = obj_hdr[i].obj_size;
1861 			return 0;
1862 		}
1863 	}
1864 
1865 	pr_err("object %s is not found inside MOF\n", obj_name);
1866 	return -EINVAL;
1867 }
1868 
1869 static int qat_uclo_map_obj_from_mof(struct icp_qat_mof_handle *mobj_handle,
1870 				     struct icp_qat_mof_objhdr *mobj_hdr,
1871 				     struct icp_qat_mof_obj_chunkhdr *obj_chunkhdr)
1872 {
1873 	u8 *obj;
1874 
1875 	if (!strncmp(obj_chunkhdr->chunk_id, ICP_QAT_UOF_IMAG,
1876 		     ICP_QAT_MOF_OBJ_CHUNKID_LEN)) {
1877 		obj = mobj_handle->uobjs_hdr + obj_chunkhdr->offset;
1878 	} else if (!strncmp(obj_chunkhdr->chunk_id, ICP_QAT_SUOF_IMAG,
1879 			    ICP_QAT_MOF_OBJ_CHUNKID_LEN)) {
1880 		obj = mobj_handle->sobjs_hdr + obj_chunkhdr->offset;
1881 	} else {
1882 		pr_err("unsupported chunk id\n");
1883 		return -EINVAL;
1884 	}
1885 	mobj_hdr->obj_buf = obj;
1886 	mobj_hdr->obj_size = (unsigned int)obj_chunkhdr->size;
1887 	mobj_hdr->obj_name = obj_chunkhdr->name + mobj_handle->sym_str;
1888 	return 0;
1889 }
1890 
1891 static int qat_uclo_map_objs_from_mof(struct icp_qat_mof_handle *mobj_handle)
1892 {
1893 	struct icp_qat_mof_obj_chunkhdr *uobj_chunkhdr;
1894 	struct icp_qat_mof_obj_chunkhdr *sobj_chunkhdr;
1895 	struct icp_qat_mof_obj_hdr *uobj_hdr;
1896 	struct icp_qat_mof_obj_hdr *sobj_hdr;
1897 	struct icp_qat_mof_objhdr *mobj_hdr;
1898 	unsigned int uobj_chunk_num = 0;
1899 	unsigned int sobj_chunk_num = 0;
1900 	unsigned int *valid_chunk;
1901 	int ret, i;
1902 
1903 	uobj_hdr = (struct icp_qat_mof_obj_hdr *)mobj_handle->uobjs_hdr;
1904 	sobj_hdr = (struct icp_qat_mof_obj_hdr *)mobj_handle->sobjs_hdr;
1905 	if (uobj_hdr)
1906 		uobj_chunk_num = uobj_hdr->num_chunks;
1907 	if (sobj_hdr)
1908 		sobj_chunk_num = sobj_hdr->num_chunks;
1909 
1910 	mobj_hdr = kzalloc_objs(*mobj_hdr,
1911 				size_add(uobj_chunk_num, sobj_chunk_num));
1912 	if (!mobj_hdr)
1913 		return -ENOMEM;
1914 
1915 	mobj_handle->obj_table.obj_hdr = mobj_hdr;
1916 	valid_chunk = &mobj_handle->obj_table.num_objs;
1917 	uobj_chunkhdr = (struct icp_qat_mof_obj_chunkhdr *)
1918 			 ((uintptr_t)uobj_hdr + sizeof(*uobj_hdr));
1919 	sobj_chunkhdr = (struct icp_qat_mof_obj_chunkhdr *)
1920 			((uintptr_t)sobj_hdr + sizeof(*sobj_hdr));
1921 
1922 	/* map uof objects */
1923 	for (i = 0; i < uobj_chunk_num; i++) {
1924 		ret = qat_uclo_map_obj_from_mof(mobj_handle,
1925 						&mobj_hdr[*valid_chunk],
1926 						&uobj_chunkhdr[i]);
1927 		if (ret)
1928 			return ret;
1929 		(*valid_chunk)++;
1930 	}
1931 
1932 	/* map suof objects */
1933 	for (i = 0; i < sobj_chunk_num; i++) {
1934 		ret = qat_uclo_map_obj_from_mof(mobj_handle,
1935 						&mobj_hdr[*valid_chunk],
1936 						&sobj_chunkhdr[i]);
1937 		if (ret)
1938 			return ret;
1939 		(*valid_chunk)++;
1940 	}
1941 
1942 	if ((uobj_chunk_num + sobj_chunk_num) != *valid_chunk) {
1943 		pr_err("inconsistent UOF/SUOF chunk amount\n");
1944 		return -EINVAL;
1945 	}
1946 	return 0;
1947 }
1948 
1949 static void qat_uclo_map_mof_symobjs(struct icp_qat_mof_handle *mobj_handle,
1950 				     struct icp_qat_mof_chunkhdr *mof_chunkhdr)
1951 {
1952 	char **sym_str = (char **)&mobj_handle->sym_str;
1953 	unsigned int *sym_size = &mobj_handle->sym_size;
1954 	struct icp_qat_mof_str_table *str_table_obj;
1955 
1956 	*sym_size = *(unsigned int *)(uintptr_t)
1957 		    (mof_chunkhdr->offset + mobj_handle->mof_buf);
1958 	*sym_str = (char *)(uintptr_t)
1959 		   (mobj_handle->mof_buf + mof_chunkhdr->offset +
1960 		    sizeof(str_table_obj->tab_len));
1961 }
1962 
1963 static void qat_uclo_map_mof_chunk(struct icp_qat_mof_handle *mobj_handle,
1964 				   struct icp_qat_mof_chunkhdr *mof_chunkhdr)
1965 {
1966 	char *chunk_id = mof_chunkhdr->chunk_id;
1967 
1968 	if (!strncmp(chunk_id, ICP_QAT_MOF_SYM_OBJS, ICP_QAT_MOF_OBJ_ID_LEN))
1969 		qat_uclo_map_mof_symobjs(mobj_handle, mof_chunkhdr);
1970 	else if (!strncmp(chunk_id, ICP_QAT_UOF_OBJS, ICP_QAT_MOF_OBJ_ID_LEN))
1971 		mobj_handle->uobjs_hdr = mobj_handle->mof_buf +
1972 					 mof_chunkhdr->offset;
1973 	else if (!strncmp(chunk_id, ICP_QAT_SUOF_OBJS, ICP_QAT_MOF_OBJ_ID_LEN))
1974 		mobj_handle->sobjs_hdr = mobj_handle->mof_buf +
1975 					 mof_chunkhdr->offset;
1976 }
1977 
1978 static int qat_uclo_check_mof_format(struct icp_qat_mof_file_hdr *mof_hdr)
1979 {
1980 	int maj = mof_hdr->maj_ver & 0xff;
1981 	int min = mof_hdr->min_ver & 0xff;
1982 
1983 	if (mof_hdr->file_id != ICP_QAT_MOF_FID) {
1984 		pr_err("invalid header 0x%x\n", mof_hdr->file_id);
1985 		return -EINVAL;
1986 	}
1987 
1988 	if (mof_hdr->num_chunks <= 0x1) {
1989 		pr_err("MOF chunk amount is incorrect\n");
1990 		return -EINVAL;
1991 	}
1992 	if (maj != ICP_QAT_MOF_MAJVER || min != ICP_QAT_MOF_MINVER) {
1993 		pr_err("bad MOF version, major 0x%x, minor 0x%x\n", maj, min);
1994 		return -EINVAL;
1995 	}
1996 	return 0;
1997 }
1998 
1999 static int qat_uclo_map_mof_obj(struct icp_qat_fw_loader_handle *handle,
2000 				struct icp_qat_mof_file_hdr *mof_ptr,
2001 				u32 mof_size, const char *obj_name,
2002 				char **obj_ptr, unsigned int *obj_size)
2003 {
2004 	struct icp_qat_mof_chunkhdr *mof_chunkhdr;
2005 	unsigned int file_id = mof_ptr->file_id;
2006 	struct icp_qat_mof_handle *mobj_handle;
2007 	unsigned short chunks_num;
2008 	unsigned int i;
2009 	int ret;
2010 
2011 	if (file_id == ICP_QAT_UOF_FID || file_id == ICP_QAT_SUOF_FID) {
2012 		if (obj_ptr)
2013 			*obj_ptr = (char *)mof_ptr;
2014 		if (obj_size)
2015 			*obj_size = mof_size;
2016 		return 0;
2017 	}
2018 	if (qat_uclo_check_mof_format(mof_ptr))
2019 		return -EINVAL;
2020 
2021 	mobj_handle = kzalloc_obj(*mobj_handle);
2022 	if (!mobj_handle)
2023 		return -ENOMEM;
2024 
2025 	handle->mobj_handle = mobj_handle;
2026 	ret = qat_uclo_map_mof_file_hdr(handle, mof_ptr, mof_size);
2027 	if (ret)
2028 		return ret;
2029 
2030 	mof_chunkhdr = (void *)mof_ptr + sizeof(*mof_ptr);
2031 	chunks_num = mof_ptr->num_chunks;
2032 
2033 	/* Parse MOF file chunks */
2034 	for (i = 0; i < chunks_num; i++)
2035 		qat_uclo_map_mof_chunk(mobj_handle, &mof_chunkhdr[i]);
2036 
2037 	/* All sym_objs uobjs and sobjs should be available */
2038 	if (!mobj_handle->sym_str ||
2039 	    (!mobj_handle->uobjs_hdr && !mobj_handle->sobjs_hdr))
2040 		return -EINVAL;
2041 
2042 	ret = qat_uclo_map_objs_from_mof(mobj_handle);
2043 	if (ret)
2044 		return ret;
2045 
2046 	/* Seek specified uof object in MOF */
2047 	return qat_uclo_seek_obj_inside_mof(mobj_handle, obj_name,
2048 					    obj_ptr, obj_size);
2049 }
2050 
2051 int qat_uclo_map_obj(struct icp_qat_fw_loader_handle *handle,
2052 		     void *addr_ptr, u32 mem_size, const char *obj_name)
2053 {
2054 	char *obj_addr;
2055 	u32 obj_size;
2056 	int ret;
2057 
2058 	BUILD_BUG_ON(ICP_QAT_UCLO_MAX_AE >=
2059 		     (sizeof(handle->hal_handle->ae_mask) * 8));
2060 
2061 	if (!handle || !addr_ptr || mem_size < 24)
2062 		return -EINVAL;
2063 
2064 	if (obj_name) {
2065 		ret = qat_uclo_map_mof_obj(handle, addr_ptr, mem_size, obj_name,
2066 					   &obj_addr, &obj_size);
2067 		if (ret)
2068 			return ret;
2069 	} else {
2070 		obj_addr = addr_ptr;
2071 		obj_size = mem_size;
2072 	}
2073 
2074 	return (handle->chip_info->fw_auth) ?
2075 			qat_uclo_map_suof_obj(handle, obj_addr, obj_size) :
2076 			qat_uclo_map_uof_obj(handle, obj_addr, obj_size);
2077 }
2078 
2079 void qat_uclo_del_obj(struct icp_qat_fw_loader_handle *handle)
2080 {
2081 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
2082 	unsigned int a;
2083 
2084 	if (handle->mobj_handle)
2085 		qat_uclo_del_mof(handle);
2086 	if (handle->sobj_handle)
2087 		qat_uclo_del_suof(handle);
2088 	if (!obj_handle)
2089 		return;
2090 
2091 	kfree(obj_handle->uword_buf);
2092 	for (a = 0; a < obj_handle->uimage_num; a++)
2093 		kfree(obj_handle->ae_uimage[a].page);
2094 
2095 	for (a = 0; a < handle->hal_handle->ae_max_num; a++)
2096 		qat_uclo_free_ae_data(&obj_handle->ae_data[a]);
2097 
2098 	kfree(obj_handle->obj_hdr);
2099 	kfree(obj_handle->obj_buf);
2100 	kfree(obj_handle);
2101 	handle->obj_handle = NULL;
2102 }
2103 
2104 static void qat_uclo_fill_uwords(struct icp_qat_uclo_objhandle *obj_handle,
2105 				 struct icp_qat_uclo_encap_page *encap_page,
2106 				 u64 *uword, unsigned int addr_p,
2107 				 unsigned int raddr, u64 fill)
2108 {
2109 	unsigned int i, addr;
2110 	u64 uwrd = 0;
2111 
2112 	if (!encap_page) {
2113 		*uword = fill;
2114 		return;
2115 	}
2116 	addr = (encap_page->page_region) ? raddr : addr_p;
2117 	for (i = 0; i < encap_page->uwblock_num; i++) {
2118 		if (addr >= encap_page->uwblock[i].start_addr &&
2119 		    addr <= encap_page->uwblock[i].start_addr +
2120 		    encap_page->uwblock[i].words_num - 1) {
2121 			addr -= encap_page->uwblock[i].start_addr;
2122 			addr *= obj_handle->uword_in_bytes;
2123 			memcpy(&uwrd, (void *)(((uintptr_t)
2124 			       encap_page->uwblock[i].micro_words) + addr),
2125 			       obj_handle->uword_in_bytes);
2126 			uwrd = uwrd & GENMASK_ULL(43, 0);
2127 		}
2128 	}
2129 	*uword = uwrd;
2130 	if (*uword == INVLD_UWORD)
2131 		*uword = fill;
2132 }
2133 
2134 static void qat_uclo_wr_uimage_raw_page(struct icp_qat_fw_loader_handle *handle,
2135 					struct icp_qat_uclo_encap_page
2136 					*encap_page, unsigned int ae)
2137 {
2138 	unsigned int uw_physical_addr, uw_relative_addr, i, words_num, cpylen;
2139 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
2140 	u64 fill_pat;
2141 
2142 	/* load the page starting at appropriate ustore address */
2143 	/* get fill-pattern from an image -- they are all the same */
2144 	memcpy(&fill_pat, obj_handle->ae_uimage[0].img_ptr->fill_pattern,
2145 	       sizeof(u64));
2146 	uw_physical_addr = encap_page->beg_addr_p;
2147 	uw_relative_addr = 0;
2148 	words_num = encap_page->micro_words_num;
2149 	while (words_num) {
2150 		cpylen = min(words_num, UWORD_CPYBUF_SIZE);
2151 
2152 		/* load the buffer */
2153 		for (i = 0; i < cpylen; i++)
2154 			qat_uclo_fill_uwords(obj_handle, encap_page,
2155 					     &obj_handle->uword_buf[i],
2156 					     uw_physical_addr + i,
2157 					     uw_relative_addr + i, fill_pat);
2158 
2159 		/* copy the buffer to ustore */
2160 		qat_hal_wr_uwords(handle, (unsigned char)ae,
2161 				  uw_physical_addr, cpylen,
2162 				  obj_handle->uword_buf);
2163 
2164 		uw_physical_addr += cpylen;
2165 		uw_relative_addr += cpylen;
2166 		words_num -= cpylen;
2167 	}
2168 }
2169 
2170 static void qat_uclo_wr_uimage_page(struct icp_qat_fw_loader_handle *handle,
2171 				    struct icp_qat_uof_image *image)
2172 {
2173 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
2174 	unsigned long ae_mask = handle->hal_handle->ae_mask;
2175 	unsigned long cfg_ae_mask = handle->cfg_ae_mask;
2176 	unsigned long ae_assigned = image->ae_assigned;
2177 	struct icp_qat_uclo_aedata *aed;
2178 	unsigned int ctx_mask, s;
2179 	struct icp_qat_uclo_page *page;
2180 	unsigned char ae;
2181 	int ctx;
2182 
2183 	if (ICP_QAT_CTX_MODE(image->ae_mode) == ICP_QAT_UCLO_MAX_CTX)
2184 		ctx_mask = 0xff;
2185 	else
2186 		ctx_mask = 0x55;
2187 	/* load the default page and set assigned CTX PC
2188 	 * to the entrypoint address */
2189 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
2190 		if (!test_bit(ae, &cfg_ae_mask))
2191 			continue;
2192 
2193 		if (!test_bit(ae, &ae_assigned))
2194 			continue;
2195 
2196 		aed = &obj_handle->ae_data[ae];
2197 		/* find the slice to which this image is assigned */
2198 		for (s = 0; s < aed->slice_num; s++) {
2199 			if (image->ctx_assigned &
2200 			    aed->ae_slices[s].ctx_mask_assigned)
2201 				break;
2202 		}
2203 		if (s >= aed->slice_num)
2204 			continue;
2205 		page = aed->ae_slices[s].page;
2206 		if (!page->encap_page->def_page)
2207 			continue;
2208 		qat_uclo_wr_uimage_raw_page(handle, page->encap_page, ae);
2209 
2210 		page = aed->ae_slices[s].page;
2211 		for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++)
2212 			aed->ae_slices[s].cur_page[ctx] =
2213 					(ctx_mask & (1 << ctx)) ? page : NULL;
2214 		qat_hal_set_live_ctx(handle, (unsigned char)ae,
2215 				     image->ctx_assigned);
2216 		qat_hal_set_pc(handle, (unsigned char)ae, image->ctx_assigned,
2217 			       image->entry_address);
2218 	}
2219 }
2220 
2221 static int qat_uclo_wr_suof_img(struct icp_qat_fw_loader_handle *handle)
2222 {
2223 	unsigned int i;
2224 	struct icp_qat_fw_auth_desc *desc = NULL;
2225 	struct icp_qat_suof_handle *sobj_handle = handle->sobj_handle;
2226 	struct icp_qat_suof_img_hdr *simg_hdr = sobj_handle->img_table.simg_hdr;
2227 	int ret;
2228 
2229 	for (i = 0; i < sobj_handle->img_table.num_simgs; i++) {
2230 		ret = qat_uclo_check_image(handle, simg_hdr[i].simg_buf,
2231 					   simg_hdr[i].simg_len,
2232 					   CSS_AE_FIRMWARE);
2233 		if (ret)
2234 			return ret;
2235 
2236 		if (qat_uclo_map_auth_fw(handle,
2237 					 (char *)simg_hdr[i].simg_buf,
2238 					 (unsigned int)
2239 					 simg_hdr[i].simg_len,
2240 					 &desc))
2241 			goto wr_err;
2242 		if (qat_uclo_auth_fw(handle, desc))
2243 			goto wr_err;
2244 		if (qat_uclo_is_broadcast(handle, i)) {
2245 			if (qat_uclo_broadcast_load_fw(handle, desc))
2246 				goto wr_err;
2247 		} else {
2248 			if (qat_uclo_load_fw(handle, desc))
2249 				goto wr_err;
2250 		}
2251 		qat_uclo_ummap_auth_fw(handle, &desc);
2252 	}
2253 	return 0;
2254 wr_err:
2255 	qat_uclo_ummap_auth_fw(handle, &desc);
2256 	return -EINVAL;
2257 }
2258 
2259 static int qat_uclo_wr_uof_img(struct icp_qat_fw_loader_handle *handle)
2260 {
2261 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
2262 	unsigned int i;
2263 
2264 	if (qat_uclo_init_globals(handle))
2265 		return -EINVAL;
2266 	for (i = 0; i < obj_handle->uimage_num; i++) {
2267 		if (!obj_handle->ae_uimage[i].img_ptr)
2268 			return -EINVAL;
2269 		if (qat_uclo_init_ustore(handle, &obj_handle->ae_uimage[i]))
2270 			return -EINVAL;
2271 		qat_uclo_wr_uimage_page(handle,
2272 					obj_handle->ae_uimage[i].img_ptr);
2273 	}
2274 	return 0;
2275 }
2276 
2277 int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle)
2278 {
2279 	return (handle->chip_info->fw_auth) ? qat_uclo_wr_suof_img(handle) :
2280 				   qat_uclo_wr_uof_img(handle);
2281 }
2282 
2283 int qat_uclo_set_cfg_ae_mask(struct icp_qat_fw_loader_handle *handle,
2284 			     unsigned int cfg_ae_mask)
2285 {
2286 	if (!cfg_ae_mask)
2287 		return -EINVAL;
2288 
2289 	handle->cfg_ae_mask = cfg_ae_mask;
2290 	return 0;
2291 }
2292