1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #ifndef WITHOUT_CAPSICUM
31 #include <sys/capsicum.h>
32 #endif
33 #include <sys/types.h>
34 #include <sys/mman.h>
35 #include <sys/pciio.h>
36 #include <sys/ioctl.h>
37 #include <sys/stat.h>
38
39 #include <dev/io/iodev.h>
40 #include <dev/pci/pcireg.h>
41 #include <dev/vmm/vmm_mem.h>
42
43 #include <vm/vm.h>
44
45 #include <machine/iodev.h>
46 #include <machine/vm.h>
47
48 #ifndef WITHOUT_CAPSICUM
49 #include <capsicum_helpers.h>
50 #endif
51 #include <ctype.h>
52 #include <stdio.h>
53 #include <stdlib.h>
54 #include <string.h>
55 #include <err.h>
56 #include <errno.h>
57 #include <fcntl.h>
58 #include <sysexits.h>
59 #include <unistd.h>
60
61 #include <machine/vmm.h>
62
63 #include "debug.h"
64 #include "mem.h"
65 #include "pci_passthru.h"
66
67 #ifndef _PATH_DEVPCI
68 #define _PATH_DEVPCI "/dev/pci"
69 #endif
70
71 #define LEGACY_SUPPORT 1
72
73 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)
74 #define MSIX_CAPLEN 12
75
76 #define PASSTHRU_MMIO_MAX 3
77
78 static int pcifd = -1;
79
80 SET_DECLARE(passthru_dev_set, struct passthru_dev);
81
82 struct passthru_softc {
83 struct pci_devinst *psc_pi;
84 /* ROM is handled like a BAR */
85 struct pcibar psc_bar[PCI_BARMAX_WITH_ROM + 1];
86 struct {
87 int capoff;
88 int msgctrl;
89 int emulated;
90 } psc_msi;
91 struct {
92 int capoff;
93 } psc_msix;
94 struct pcisel psc_sel;
95
96 struct passthru_mmio_mapping psc_mmio_map[PASSTHRU_MMIO_MAX];
97 cfgread_handler psc_pcir_rhandler[PCI_REGMAX + 1];
98 cfgwrite_handler psc_pcir_whandler[PCI_REGMAX + 1];
99 };
100
101 static int
msi_caplen(int msgctrl)102 msi_caplen(int msgctrl)
103 {
104 int len;
105
106 len = 10; /* minimum length of msi capability */
107
108 if (msgctrl & PCIM_MSICTRL_64BIT)
109 len += 4;
110
111 #if 0
112 /*
113 * Ignore the 'mask' and 'pending' bits in the MSI capability.
114 * We'll let the guest manipulate them directly.
115 */
116 if (msgctrl & PCIM_MSICTRL_VECTOR)
117 len += 10;
118 #endif
119
120 return (len);
121 }
122
123 static int
pcifd_open(void)124 pcifd_open(void)
125 {
126 int fd;
127
128 fd = open(_PATH_DEVPCI, O_RDWR, 0);
129 if (fd < 0) {
130 warn("failed to open %s", _PATH_DEVPCI);
131 return (-1);
132 }
133 return (fd);
134 }
135
136 static int
pcifd_init(void)137 pcifd_init(void)
138 {
139 pcifd = pcifd_open();
140 if (pcifd < 0)
141 return (1);
142
143 #ifndef WITHOUT_CAPSICUM
144 cap_rights_t pcifd_rights;
145 cap_rights_init(&pcifd_rights, CAP_IOCTL, CAP_READ, CAP_WRITE);
146 if (caph_rights_limit(pcifd, &pcifd_rights) == -1)
147 errx(EX_OSERR, "Unable to apply rights for sandbox");
148
149 const cap_ioctl_t pcifd_ioctls[] = { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR,
150 PCIOCBARIO, PCIOCBARMMAP, PCIOCGETCONF };
151 if (caph_ioctls_limit(pcifd, pcifd_ioctls, nitems(pcifd_ioctls)) == -1)
152 errx(EX_OSERR, "Unable to apply rights for sandbox");
153 #endif
154
155 return (0);
156 }
157
158 static uint32_t
host_read_config(int fd,const struct pcisel * sel,long reg,int width)159 host_read_config(int fd, const struct pcisel *sel, long reg, int width)
160 {
161 struct pci_io pi;
162
163 bzero(&pi, sizeof(pi));
164 pi.pi_sel = *sel;
165 pi.pi_reg = reg;
166 pi.pi_width = width;
167
168 if (ioctl(fd, PCIOCREAD, &pi) < 0)
169 return (0); /* XXX */
170 else
171 return (pi.pi_data);
172 }
173
174 static uint32_t
passthru_read_config(const struct pcisel * sel,long reg,int width)175 passthru_read_config(const struct pcisel *sel, long reg, int width)
176 {
177 return (host_read_config(pcifd, sel, reg, width));
178 }
179
180 uint32_t
pci_host_read_config(const struct pcisel * sel,long reg,int width)181 pci_host_read_config(const struct pcisel *sel, long reg, int width)
182 {
183 uint32_t ret;
184 int fd;
185
186 fd = pcifd_open();
187 if (fd < 0)
188 return (0);
189 ret = host_read_config(fd, sel, reg, width);
190 (void)close(fd);
191 return (ret);
192 }
193
194 static void
host_write_config(int fd,const struct pcisel * sel,long reg,int width,uint32_t data)195 host_write_config(int fd, const struct pcisel *sel, long reg, int width,
196 uint32_t data)
197 {
198 struct pci_io pi;
199
200 bzero(&pi, sizeof(pi));
201 pi.pi_sel = *sel;
202 pi.pi_reg = reg;
203 pi.pi_width = width;
204 pi.pi_data = data;
205
206 (void)ioctl(fd, PCIOCWRITE, &pi); /* XXX */
207 }
208
209 static void
passthru_write_config(const struct pcisel * sel,long reg,int width,uint32_t data)210 passthru_write_config(const struct pcisel *sel, long reg, int width,
211 uint32_t data)
212 {
213 host_write_config(pcifd, sel, reg, width, data);
214 }
215
216 void
pci_host_write_config(const struct pcisel * sel,long reg,int width,uint32_t data)217 pci_host_write_config(const struct pcisel *sel, long reg, int width,
218 uint32_t data)
219 {
220 int fd;
221
222 fd = pcifd_open();
223 if (fd < 0)
224 return;
225 host_write_config(fd, sel, reg, width, data);
226 (void)close(fd);
227 }
228
229 #ifdef LEGACY_SUPPORT
230 static int
passthru_add_msicap(struct pci_devinst * pi,int msgnum,int nextptr)231 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
232 {
233 int capoff;
234 struct msicap msicap;
235 u_char *capdata;
236
237 pci_populate_msicap(&msicap, msgnum, nextptr);
238
239 /*
240 * XXX
241 * Copy the msi capability structure in the last 16 bytes of the
242 * config space. This is wrong because it could shadow something
243 * useful to the device.
244 */
245 capoff = 256 - roundup(sizeof(msicap), 4);
246 capdata = (u_char *)&msicap;
247 for (size_t i = 0; i < sizeof(msicap); i++)
248 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
249
250 return (capoff);
251 }
252 #endif /* LEGACY_SUPPORT */
253
254 static int
cfginitmsi(struct passthru_softc * sc)255 cfginitmsi(struct passthru_softc *sc)
256 {
257 int i, ptr, capptr, cap, sts, caplen, table_size;
258 uint32_t u32;
259 struct pcisel sel;
260 struct pci_devinst *pi;
261 struct msixcap msixcap;
262 char *msixcap_ptr;
263
264 pi = sc->psc_pi;
265 sel = sc->psc_sel;
266
267 /*
268 * Parse the capabilities and cache the location of the MSI
269 * and MSI-X capabilities.
270 */
271 sts = passthru_read_config(&sel, PCIR_STATUS, 2);
272 if (sts & PCIM_STATUS_CAPPRESENT) {
273 ptr = passthru_read_config(&sel, PCIR_CAP_PTR, 1);
274 while (ptr != 0 && ptr != 0xff) {
275 cap = passthru_read_config(&sel, ptr + PCICAP_ID, 1);
276 if (cap == PCIY_MSI) {
277 /*
278 * Copy the MSI capability into the config
279 * space of the emulated pci device
280 */
281 sc->psc_msi.capoff = ptr;
282 sc->psc_msi.msgctrl =
283 passthru_read_config(&sel, ptr + 2, 2);
284 sc->psc_msi.emulated = 0;
285 caplen = msi_caplen(sc->psc_msi.msgctrl);
286 capptr = ptr;
287 while (caplen > 0) {
288 u32 = passthru_read_config(&sel, capptr,
289 4);
290 pci_set_cfgdata32(pi, capptr, u32);
291 caplen -= 4;
292 capptr += 4;
293 }
294 } else if (cap == PCIY_MSIX) {
295 /*
296 * Copy the MSI-X capability
297 */
298 sc->psc_msix.capoff = ptr;
299 caplen = 12;
300 msixcap_ptr = (char *)&msixcap;
301 capptr = ptr;
302 while (caplen > 0) {
303 u32 = passthru_read_config(&sel, capptr,
304 4);
305 memcpy(msixcap_ptr, &u32, 4);
306 pci_set_cfgdata32(pi, capptr, u32);
307 caplen -= 4;
308 capptr += 4;
309 msixcap_ptr += 4;
310 }
311 }
312 ptr = passthru_read_config(&sel, ptr + PCICAP_NEXTPTR,
313 1);
314 }
315 }
316
317 if (sc->psc_msix.capoff != 0) {
318 pi->pi_msix.pba_bar =
319 msixcap.pba_info & PCIM_MSIX_BIR_MASK;
320 pi->pi_msix.pba_offset =
321 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK;
322 pi->pi_msix.table_bar =
323 msixcap.table_info & PCIM_MSIX_BIR_MASK;
324 pi->pi_msix.table_offset =
325 msixcap.table_info & ~PCIM_MSIX_BIR_MASK;
326 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
327 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
328
329 /* Allocate the emulated MSI-X table array */
330 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
331 pi->pi_msix.table = calloc(1, table_size);
332
333 /* Mask all table entries */
334 for (i = 0; i < pi->pi_msix.table_count; i++) {
335 pi->pi_msix.table[i].vector_control |=
336 PCIM_MSIX_VCTRL_MASK;
337 }
338 }
339
340 #ifdef LEGACY_SUPPORT
341 /*
342 * If the passthrough device does not support MSI then craft a
343 * MSI capability for it. We link the new MSI capability at the
344 * head of the list of capabilities.
345 */
346 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) {
347 int origptr, msiptr;
348 origptr = passthru_read_config(&sel, PCIR_CAP_PTR, 1);
349 msiptr = passthru_add_msicap(pi, 1, origptr);
350 sc->psc_msi.capoff = msiptr;
351 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
352 sc->psc_msi.emulated = 1;
353 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
354 }
355 #endif
356
357 /* Make sure one of the capabilities is present */
358 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
359 return (-1);
360 else
361 return (0);
362 }
363
364 static uint64_t
msix_table_read(struct passthru_softc * sc,uint64_t offset,int size)365 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
366 {
367 struct pci_devinst *pi;
368 struct msix_table_entry *entry;
369 uint8_t *src8;
370 uint16_t *src16;
371 uint32_t *src32;
372 uint64_t *src64;
373 uint64_t data;
374 size_t entry_offset;
375 uint32_t table_offset;
376 int index, table_count;
377
378 pi = sc->psc_pi;
379
380 table_offset = pi->pi_msix.table_offset;
381 table_count = pi->pi_msix.table_count;
382 if (offset < table_offset ||
383 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) {
384 switch (size) {
385 case 1:
386 src8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
387 data = *src8;
388 break;
389 case 2:
390 src16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
391 data = *src16;
392 break;
393 case 4:
394 src32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
395 data = *src32;
396 break;
397 case 8:
398 src64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
399 data = *src64;
400 break;
401 default:
402 return (-1);
403 }
404 return (data);
405 }
406
407 offset -= table_offset;
408 index = offset / MSIX_TABLE_ENTRY_SIZE;
409 assert(index < table_count);
410
411 entry = &pi->pi_msix.table[index];
412 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
413
414 switch (size) {
415 case 1:
416 src8 = (uint8_t *)((uint8_t *)entry + entry_offset);
417 data = *src8;
418 break;
419 case 2:
420 src16 = (uint16_t *)((uint8_t *)entry + entry_offset);
421 data = *src16;
422 break;
423 case 4:
424 src32 = (uint32_t *)((uint8_t *)entry + entry_offset);
425 data = *src32;
426 break;
427 case 8:
428 src64 = (uint64_t *)((uint8_t *)entry + entry_offset);
429 data = *src64;
430 break;
431 default:
432 return (-1);
433 }
434
435 return (data);
436 }
437
438 static void
msix_table_write(struct passthru_softc * sc,uint64_t offset,int size,uint64_t data)439 msix_table_write(struct passthru_softc *sc, uint64_t offset, int size,
440 uint64_t data)
441 {
442 struct pci_devinst *pi;
443 struct msix_table_entry *entry;
444 uint8_t *dest8;
445 uint16_t *dest16;
446 uint32_t *dest32;
447 uint64_t *dest64;
448 size_t entry_offset;
449 uint32_t table_offset, vector_control;
450 int index, table_count;
451
452 pi = sc->psc_pi;
453
454 table_offset = pi->pi_msix.table_offset;
455 table_count = pi->pi_msix.table_count;
456 if (offset < table_offset ||
457 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) {
458 switch (size) {
459 case 1:
460 dest8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
461 *dest8 = data;
462 break;
463 case 2:
464 dest16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
465 *dest16 = data;
466 break;
467 case 4:
468 dest32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
469 *dest32 = data;
470 break;
471 case 8:
472 dest64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
473 *dest64 = data;
474 break;
475 }
476 return;
477 }
478
479 offset -= table_offset;
480 index = offset / MSIX_TABLE_ENTRY_SIZE;
481 assert(index < table_count);
482
483 entry = &pi->pi_msix.table[index];
484 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
485
486 /* Only 4 byte naturally-aligned writes are supported */
487 assert(size == 4);
488 assert(entry_offset % 4 == 0);
489
490 vector_control = entry->vector_control;
491 dest32 = (uint32_t *)((uint8_t *)entry + entry_offset);
492 *dest32 = data;
493 /* If MSI-X hasn't been enabled, do nothing */
494 if (pi->pi_msix.enabled) {
495 /* If the entry is masked, don't set it up */
496 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
497 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
498 (void)vm_setup_pptdev_msix(sc->psc_pi->pi_vmctx,
499 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
500 sc->psc_sel.pc_func, index, entry->addr,
501 entry->msg_data, entry->vector_control);
502 }
503 }
504 }
505
506 static int
init_msix_table(struct passthru_softc * sc)507 init_msix_table(struct passthru_softc *sc)
508 {
509 struct pci_devinst *pi = sc->psc_pi;
510 struct pci_bar_mmap pbm;
511 int b, s, f;
512 uint32_t table_size, table_offset;
513
514 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
515
516 b = sc->psc_sel.pc_bus;
517 s = sc->psc_sel.pc_dev;
518 f = sc->psc_sel.pc_func;
519
520 /*
521 * Map the region of the BAR containing the MSI-X table. This is
522 * necessary for two reasons:
523 * 1. The PBA may reside in the first or last page containing the MSI-X
524 * table.
525 * 2. While PCI devices are not supposed to use the page(s) containing
526 * the MSI-X table for other purposes, some do in practice.
527 */
528 memset(&pbm, 0, sizeof(pbm));
529 pbm.pbm_sel = sc->psc_sel;
530 pbm.pbm_flags = PCIIO_BAR_MMAP_RW;
531 pbm.pbm_reg = PCIR_BAR(pi->pi_msix.table_bar);
532 pbm.pbm_memattr = VM_MEMATTR_DEVICE;
533
534 if (ioctl(pcifd, PCIOCBARMMAP, &pbm) != 0) {
535 warn("Failed to map MSI-X table BAR on %d/%d/%d", b, s, f);
536 return (-1);
537 }
538 assert(pbm.pbm_bar_off == 0);
539 pi->pi_msix.mapped_addr = (uint8_t *)(uintptr_t)pbm.pbm_map_base;
540 pi->pi_msix.mapped_size = pbm.pbm_map_length;
541
542 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
543
544 table_size = pi->pi_msix.table_offset - table_offset;
545 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
546 table_size = roundup2(table_size, 4096);
547
548 /*
549 * Unmap any pages not containing the table, we do not need to emulate
550 * accesses to them. Avoid releasing address space to help ensure that
551 * a buggy out-of-bounds access causes a crash.
552 */
553 if (table_offset != 0)
554 if (mprotect(pi->pi_msix.mapped_addr, table_offset,
555 PROT_NONE) != 0)
556 warn("Failed to unmap MSI-X table BAR region");
557 if (table_offset + table_size != pi->pi_msix.mapped_size)
558 if (mprotect(
559 pi->pi_msix.mapped_addr + table_offset + table_size,
560 pi->pi_msix.mapped_size - (table_offset + table_size),
561 PROT_NONE) != 0)
562 warn("Failed to unmap MSI-X table BAR region");
563
564 return (0);
565 }
566
567 static int
cfginitbar(struct passthru_softc * sc)568 cfginitbar(struct passthru_softc *sc)
569 {
570 int i, error;
571 struct pci_devinst *pi;
572 struct pci_bar_io bar;
573 enum pcibar_type bartype;
574 uint64_t base, size;
575
576 pi = sc->psc_pi;
577
578 /*
579 * Initialize BAR registers
580 */
581 for (i = 0; i <= PCI_BARMAX; i++) {
582 uint8_t lobits;
583
584 bzero(&bar, sizeof(bar));
585 bar.pbi_sel = sc->psc_sel;
586 bar.pbi_reg = PCIR_BAR(i);
587
588 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0)
589 continue;
590
591 if (PCI_BAR_IO(bar.pbi_base)) {
592 bartype = PCIBAR_IO;
593 base = bar.pbi_base & PCIM_BAR_IO_BASE;
594 } else {
595 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
596 case PCIM_BAR_MEM_64:
597 bartype = PCIBAR_MEM64;
598 break;
599 default:
600 bartype = PCIBAR_MEM32;
601 break;
602 }
603 base = bar.pbi_base & PCIM_BAR_MEM_BASE;
604 }
605 size = bar.pbi_length;
606
607 if (bartype != PCIBAR_IO) {
608 if (((base | size) & PAGE_MASK) != 0) {
609 warnx("passthru device %d/%d/%d BAR %d: "
610 "base %#lx or size %#lx not page aligned\n",
611 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
612 sc->psc_sel.pc_func, i, base, size);
613 return (-1);
614 }
615 }
616
617 /* Cache information about the "real" BAR */
618 sc->psc_bar[i].type = bartype;
619 sc->psc_bar[i].size = size;
620 sc->psc_bar[i].addr = base;
621 sc->psc_bar[i].lobits = 0;
622
623 /* Allocate the BAR in the guest I/O or MMIO space */
624 error = pci_emul_alloc_bar(pi, i, bartype, size);
625 if (error)
626 return (-1);
627
628 /* Use same lobits as physical bar */
629 lobits = (uint8_t)passthru_read_config(&sc->psc_sel,
630 PCIR_BAR(i), 0x01);
631 if (bartype == PCIBAR_MEM32 || bartype == PCIBAR_MEM64) {
632 lobits &= ~PCIM_BAR_MEM_BASE;
633 } else {
634 lobits &= ~PCIM_BAR_IO_BASE;
635 }
636 sc->psc_bar[i].lobits = lobits;
637 pi->pi_bar[i].lobits = lobits;
638
639 /*
640 * 64-bit BAR takes up two slots so skip the next one.
641 */
642 if (bartype == PCIBAR_MEM64) {
643 i++;
644 assert(i <= PCI_BARMAX);
645 sc->psc_bar[i].type = PCIBAR_MEMHI64;
646 }
647 }
648 return (0);
649 }
650
651 static int
cfginit(struct pci_devinst * pi,int bus,int slot,int func)652 cfginit(struct pci_devinst *pi, int bus, int slot, int func)
653 {
654 int error;
655 struct passthru_softc *sc;
656 uint16_t cmd;
657 uint8_t intline, intpin;
658
659 error = 1;
660 sc = pi->pi_arg;
661
662 bzero(&sc->psc_sel, sizeof(struct pcisel));
663 sc->psc_sel.pc_bus = bus;
664 sc->psc_sel.pc_dev = slot;
665 sc->psc_sel.pc_func = func;
666
667 /*
668 * Copy physical PCI header to virtual config space. COMMAND,
669 * INTLINE, and INTPIN shouldn't be aligned with their
670 * physical value and they are already set by pci_emul_init().
671 */
672 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
673 intline = pci_get_cfgdata8(pi, PCIR_INTLINE);
674 intpin = pci_get_cfgdata8(pi, PCIR_INTPIN);
675 for (int i = 0; i <= PCIR_MAXLAT; i += 4) {
676 pci_set_cfgdata32(pi, i,
677 passthru_read_config(&sc->psc_sel, i, 4));
678 }
679 pci_set_cfgdata16(pi, PCIR_COMMAND, cmd);
680 pci_set_cfgdata8(pi, PCIR_INTLINE, intline);
681 pci_set_cfgdata8(pi, PCIR_INTPIN, intpin);
682
683 if (cfginitmsi(sc) != 0) {
684 warnx("failed to initialize MSI for PCI %d/%d/%d",
685 bus, slot, func);
686 goto done;
687 }
688
689 if (cfginitbar(sc) != 0) {
690 warnx("failed to initialize BARs for PCI %d/%d/%d",
691 bus, slot, func);
692 goto done;
693 }
694
695 if (pci_msix_table_bar(pi) >= 0) {
696 error = init_msix_table(sc);
697 if (error != 0) {
698 warnx(
699 "failed to initialize MSI-X table for PCI %d/%d/%d: %d",
700 bus, slot, func, error);
701 goto done;
702 }
703 }
704
705 error = 0; /* success */
706 done:
707 return (error);
708 }
709
710 struct passthru_mmio_mapping *
passthru_get_mmio(struct passthru_softc * sc,int num)711 passthru_get_mmio(struct passthru_softc *sc, int num)
712 {
713 assert(sc != NULL);
714 assert(num < PASSTHRU_MMIO_MAX);
715
716 return (&sc->psc_mmio_map[num]);
717 }
718
719 struct pcisel *
passthru_get_sel(struct passthru_softc * sc)720 passthru_get_sel(struct passthru_softc *sc)
721 {
722 assert(sc != NULL);
723
724 return (&sc->psc_sel);
725 }
726
727 int
set_pcir_handler(struct passthru_softc * sc,int reg,int len,cfgread_handler rhandler,cfgwrite_handler whandler)728 set_pcir_handler(struct passthru_softc *sc, int reg, int len,
729 cfgread_handler rhandler, cfgwrite_handler whandler)
730 {
731 if (reg > PCI_REGMAX || reg + len > PCI_REGMAX + 1)
732 return (-1);
733
734 for (int i = reg; i < reg + len; ++i) {
735 assert(sc->psc_pcir_rhandler[i] == NULL || rhandler == NULL);
736 assert(sc->psc_pcir_whandler[i] == NULL || whandler == NULL);
737 sc->psc_pcir_rhandler[i] = rhandler;
738 sc->psc_pcir_whandler[i] = whandler;
739 }
740
741 return (0);
742 }
743
744 static int
passthru_legacy_config(nvlist_t * nvl,const char * opts)745 passthru_legacy_config(nvlist_t *nvl, const char *opts)
746 {
747 const char *cp;
748 char *tofree;
749 char value[16];
750 int bus, slot, func;
751
752 if (opts == NULL)
753 return (0);
754
755 cp = strchr(opts, ',');
756
757 if (strncmp(opts, "ppt", strlen("ppt")) == 0) {
758 tofree = strndup(opts, cp - opts);
759 set_config_value_node(nvl, "pptdev", tofree);
760 free(tofree);
761 } else if (sscanf(opts, "pci0:%d:%d:%d", &bus, &slot, &func) == 3 ||
762 sscanf(opts, "pci%d:%d:%d", &bus, &slot, &func) == 3 ||
763 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) == 3) {
764 snprintf(value, sizeof(value), "%d", bus);
765 set_config_value_node(nvl, "bus", value);
766 snprintf(value, sizeof(value), "%d", slot);
767 set_config_value_node(nvl, "slot", value);
768 snprintf(value, sizeof(value), "%d", func);
769 set_config_value_node(nvl, "func", value);
770 } else {
771 EPRINTLN("passthru: invalid options \"%s\"", opts);
772 return (-1);
773 }
774
775 if (cp == NULL) {
776 return (0);
777 }
778
779 return (pci_parse_legacy_config(nvl, cp + 1));
780 }
781
782 static int
passthru_init_rom(struct passthru_softc * const sc,const char * const romfile)783 passthru_init_rom(struct passthru_softc *const sc, const char *const romfile)
784 {
785 if (romfile == NULL) {
786 return (0);
787 }
788
789 const int fd = open(romfile, O_RDONLY);
790 if (fd < 0) {
791 warnx("%s: can't open romfile \"%s\"", __func__, romfile);
792 return (-1);
793 }
794
795 struct stat sbuf;
796 if (fstat(fd, &sbuf) < 0) {
797 warnx("%s: can't fstat romfile \"%s\"", __func__, romfile);
798 close(fd);
799 return (-1);
800 }
801 const uint64_t rom_size = sbuf.st_size;
802
803 void *const rom_data = mmap(NULL, rom_size, PROT_READ, MAP_SHARED, fd,
804 0);
805 if (rom_data == MAP_FAILED) {
806 warnx("%s: unable to mmap romfile \"%s\" (%d)", __func__,
807 romfile, errno);
808 close(fd);
809 return (-1);
810 }
811
812 void *rom_addr;
813 int error = pci_emul_alloc_rom(sc->psc_pi, rom_size, &rom_addr);
814 if (error) {
815 warnx("%s: failed to alloc rom segment", __func__);
816 munmap(rom_data, rom_size);
817 close(fd);
818 return (error);
819 }
820 memcpy(rom_addr, rom_data, rom_size);
821
822 sc->psc_bar[PCI_ROM_IDX].type = PCIBAR_ROM;
823 sc->psc_bar[PCI_ROM_IDX].addr = (uint64_t)rom_addr;
824 sc->psc_bar[PCI_ROM_IDX].size = rom_size;
825
826 munmap(rom_data, rom_size);
827 close(fd);
828
829 return (0);
830 }
831
832 static bool
passthru_lookup_pptdev(const char * name,int * bus,int * slot,int * func)833 passthru_lookup_pptdev(const char *name, int *bus, int *slot, int *func)
834 {
835 struct pci_conf_io pc;
836 struct pci_conf conf[1];
837 struct pci_match_conf patterns[1];
838 char *cp;
839
840 bzero(&pc, sizeof(struct pci_conf_io));
841 pc.match_buf_len = sizeof(conf);
842 pc.matches = conf;
843
844 bzero(&patterns, sizeof(patterns));
845
846 /*
847 * The pattern structure requires the unit to be split out from
848 * the driver name. Walk backwards from the end of the name to
849 * find the start of the unit.
850 */
851 cp = strchr(name, '\0');
852 assert(cp != NULL);
853 while (cp != name && isdigit(cp[-1]))
854 cp--;
855 if (cp == name || !isdigit(*cp)) {
856 EPRINTLN("Invalid passthru device name %s", name);
857 return (false);
858 }
859 if ((size_t)(cp - name) + 1 > sizeof(patterns[0].pd_name)) {
860 EPRINTLN("Passthru device name %s is too long", name);
861 return (false);
862 }
863 memcpy(patterns[0].pd_name, name, cp - name);
864 patterns[0].pd_unit = strtol(cp, &cp, 10);
865 if (*cp != '\0') {
866 EPRINTLN("Invalid passthru device name %s", name);
867 return (false);
868 }
869 patterns[0].flags = PCI_GETCONF_MATCH_NAME | PCI_GETCONF_MATCH_UNIT;
870 pc.num_patterns = 1;
871 pc.pat_buf_len = sizeof(patterns);
872 pc.patterns = patterns;
873
874 if (ioctl(pcifd, PCIOCGETCONF, &pc) == -1) {
875 EPRINTLN("ioctl(PCIOCGETCONF): %s", strerror(errno));
876 return (false);
877 }
878 if (pc.status != PCI_GETCONF_LAST_DEVICE &&
879 pc.status != PCI_GETCONF_MORE_DEVS) {
880 EPRINTLN("error returned from PCIOCGETCONF ioctl");
881 return (false);
882 }
883 if (pc.num_matches == 0) {
884 EPRINTLN("Passthru device %s not found", name);
885 return (false);
886 }
887
888 if (conf[0].pc_sel.pc_domain != 0) {
889 EPRINTLN("Passthru device %s on unsupported domain", name);
890 return (false);
891 }
892 *bus = conf[0].pc_sel.pc_bus;
893 *slot = conf[0].pc_sel.pc_dev;
894 *func = conf[0].pc_sel.pc_func;
895 return (true);
896 }
897
898 static int
passthru_init(struct pci_devinst * pi,nvlist_t * nvl)899 passthru_init(struct pci_devinst *pi, nvlist_t *nvl)
900 {
901 int bus, slot, func, error, memflags;
902 struct passthru_softc *sc;
903 struct passthru_dev **devpp;
904 struct passthru_dev *devp, *dev = NULL;
905 const char *value;
906
907 sc = NULL;
908 error = 1;
909
910 memflags = vm_get_memflags(pi->pi_vmctx);
911 if (!(memflags & VM_MEM_F_WIRED)) {
912 warnx("passthru requires guest memory to be wired");
913 return (error);
914 }
915
916 if (pcifd < 0 && pcifd_init()) {
917 return (error);
918 }
919
920 #define GET_INT_CONFIG(var, name) do { \
921 value = get_config_value_node(nvl, name); \
922 if (value == NULL) { \
923 EPRINTLN("passthru: missing required %s setting", name); \
924 return (error); \
925 } \
926 var = atoi(value); \
927 } while (0)
928
929 value = get_config_value_node(nvl, "pptdev");
930 if (value != NULL) {
931 if (!passthru_lookup_pptdev(value, &bus, &slot, &func))
932 return (error);
933 } else {
934 GET_INT_CONFIG(bus, "bus");
935 GET_INT_CONFIG(slot, "slot");
936 GET_INT_CONFIG(func, "func");
937 }
938
939 if (vm_assign_pptdev(pi->pi_vmctx, bus, slot, func) != 0) {
940 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver",
941 bus, slot, func);
942 goto done;
943 }
944
945 sc = calloc(1, sizeof(struct passthru_softc));
946
947 pi->pi_arg = sc;
948 sc->psc_pi = pi;
949
950 /* initialize config space */
951 if ((error = cfginit(pi, bus, slot, func)) != 0)
952 goto done;
953
954 /* initialize ROM */
955 if ((error = passthru_init_rom(sc,
956 get_config_value_node(nvl, "rom"))) != 0)
957 goto done;
958
959 /* Emulate most PCI header register. */
960 if ((error = set_pcir_handler(sc, 0, PCIR_MAXLAT + 1,
961 passthru_cfgread_emulate, passthru_cfgwrite_emulate)) != 0)
962 goto done;
963
964 /* Allow access to the physical status register. */
965 if ((error = set_pcir_handler(sc, PCIR_COMMAND, 0x04, NULL, NULL)) != 0)
966 goto done;
967
968 SET_FOREACH(devpp, passthru_dev_set) {
969 devp = *devpp;
970 assert(devp->probe != NULL);
971 if (devp->probe(pi) == 0) {
972 dev = devp;
973 break;
974 }
975 }
976
977 if (dev != NULL) {
978 error = dev->init(pi, nvl);
979 if (error != 0)
980 goto done;
981 }
982
983 error = 0; /* success */
984 done:
985 if (error) {
986 if (dev != NULL)
987 dev->deinit(pi);
988 free(sc);
989 vm_unassign_pptdev(pi->pi_vmctx, bus, slot, func);
990 }
991 return (error);
992 }
993
994 static int
msicap_access(struct passthru_softc * sc,int coff)995 msicap_access(struct passthru_softc *sc, int coff)
996 {
997 int caplen;
998
999 if (sc->psc_msi.capoff == 0)
1000 return (0);
1001
1002 caplen = msi_caplen(sc->psc_msi.msgctrl);
1003
1004 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen)
1005 return (1);
1006 else
1007 return (0);
1008 }
1009
1010 static int
msixcap_access(struct passthru_softc * sc,int coff)1011 msixcap_access(struct passthru_softc *sc, int coff)
1012 {
1013 if (sc->psc_msix.capoff == 0)
1014 return (0);
1015
1016 return (coff >= sc->psc_msix.capoff &&
1017 coff < sc->psc_msix.capoff + MSIX_CAPLEN);
1018 }
1019
1020 static int
passthru_cfgread_default(struct passthru_softc * sc,struct pci_devinst * pi __unused,int coff,int bytes,uint32_t * rv)1021 passthru_cfgread_default(struct passthru_softc *sc,
1022 struct pci_devinst *pi __unused, int coff, int bytes, uint32_t *rv)
1023 {
1024 /*
1025 * MSI capability is emulated.
1026 */
1027 if (msicap_access(sc, coff) || msixcap_access(sc, coff))
1028 return (-1);
1029
1030 /*
1031 * Emulate the command register. If a single read reads both the
1032 * command and status registers, read the status register from the
1033 * device's config space.
1034 */
1035 if (coff == PCIR_COMMAND) {
1036 uint32_t st;
1037
1038 if (bytes <= 2)
1039 return (-1);
1040 st = passthru_read_config(&sc->psc_sel, PCIR_STATUS, 2);
1041 *rv = (st << 16) | pci_get_cfgdata16(pi, PCIR_COMMAND);
1042 return (0);
1043 }
1044
1045 /* Everything else just read from the device's config space */
1046 *rv = passthru_read_config(&sc->psc_sel, coff, bytes);
1047
1048 return (0);
1049 }
1050
1051 int
passthru_cfgread_emulate(struct passthru_softc * sc __unused,struct pci_devinst * pi __unused,int coff __unused,int bytes __unused,uint32_t * rv __unused)1052 passthru_cfgread_emulate(struct passthru_softc *sc __unused,
1053 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused,
1054 uint32_t *rv __unused)
1055 {
1056 return (-1);
1057 }
1058
1059 static int
passthru_cfgread(struct pci_devinst * pi,int coff,int bytes,uint32_t * rv)1060 passthru_cfgread(struct pci_devinst *pi, int coff, int bytes, uint32_t *rv)
1061 {
1062 struct passthru_softc *sc;
1063
1064 sc = pi->pi_arg;
1065
1066 if (sc->psc_pcir_rhandler[coff] != NULL)
1067 return (sc->psc_pcir_rhandler[coff](sc, pi, coff, bytes, rv));
1068
1069 return (passthru_cfgread_default(sc, pi, coff, bytes, rv));
1070 }
1071
1072 static int
passthru_cfgwrite_default(struct passthru_softc * sc,struct pci_devinst * pi,int coff,int bytes,uint32_t val)1073 passthru_cfgwrite_default(struct passthru_softc *sc, struct pci_devinst *pi,
1074 int coff, int bytes, uint32_t val)
1075 {
1076 int error, msix_table_entries, i;
1077 uint16_t cmd_old;
1078
1079 /*
1080 * MSI capability is emulated
1081 */
1082 if (msicap_access(sc, coff)) {
1083 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff,
1084 PCIY_MSI);
1085 error = vm_setup_pptdev_msi(pi->pi_vmctx, sc->psc_sel.pc_bus,
1086 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
1087 pi->pi_msi.addr, pi->pi_msi.msg_data,
1088 pi->pi_msi.maxmsgnum);
1089 if (error != 0)
1090 err(1, "vm_setup_pptdev_msi");
1091 return (0);
1092 }
1093
1094 if (msixcap_access(sc, coff)) {
1095 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msix.capoff,
1096 PCIY_MSIX);
1097 if (pi->pi_msix.enabled) {
1098 msix_table_entries = pi->pi_msix.table_count;
1099 for (i = 0; i < msix_table_entries; i++) {
1100 error = vm_setup_pptdev_msix(pi->pi_vmctx,
1101 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
1102 sc->psc_sel.pc_func, i,
1103 pi->pi_msix.table[i].addr,
1104 pi->pi_msix.table[i].msg_data,
1105 pi->pi_msix.table[i].vector_control);
1106
1107 if (error)
1108 err(1, "vm_setup_pptdev_msix");
1109 }
1110 } else {
1111 error = vm_disable_pptdev_msix(pi->pi_vmctx,
1112 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
1113 sc->psc_sel.pc_func);
1114 if (error)
1115 err(1, "vm_disable_pptdev_msix");
1116 }
1117 return (0);
1118 }
1119
1120 /*
1121 * The command register is emulated, but the status register
1122 * is passed through.
1123 */
1124 if (coff == PCIR_COMMAND) {
1125 if (bytes <= 2)
1126 return (-1);
1127
1128 /* Update the physical status register. */
1129 passthru_write_config(&sc->psc_sel, PCIR_STATUS, val >> 16, 2);
1130
1131 /* Update the virtual command register. */
1132 cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND);
1133 pci_set_cfgdata16(pi, PCIR_COMMAND, val & 0xffff);
1134 pci_emul_cmd_changed(pi, cmd_old);
1135 return (0);
1136 }
1137
1138 passthru_write_config(&sc->psc_sel, coff, bytes, val);
1139
1140 return (0);
1141 }
1142
1143 int
passthru_cfgwrite_emulate(struct passthru_softc * sc __unused,struct pci_devinst * pi __unused,int coff __unused,int bytes __unused,uint32_t val __unused)1144 passthru_cfgwrite_emulate(struct passthru_softc *sc __unused,
1145 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused,
1146 uint32_t val __unused)
1147 {
1148 return (-1);
1149 }
1150
1151 static int
passthru_cfgwrite(struct pci_devinst * pi,int coff,int bytes,uint32_t val)1152 passthru_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val)
1153 {
1154 struct passthru_softc *sc;
1155
1156 sc = pi->pi_arg;
1157
1158 if (sc->psc_pcir_whandler[coff] != NULL)
1159 return (sc->psc_pcir_whandler[coff](sc, pi, coff, bytes, val));
1160
1161 return (passthru_cfgwrite_default(sc, pi, coff, bytes, val));
1162 }
1163
1164 static void
passthru_write(struct pci_devinst * pi,int baridx,uint64_t offset,int size,uint64_t value)1165 passthru_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
1166 uint64_t value)
1167 {
1168 struct passthru_softc *sc;
1169 struct pci_bar_ioreq pio;
1170
1171 sc = pi->pi_arg;
1172
1173 if (baridx == pci_msix_table_bar(pi)) {
1174 msix_table_write(sc, offset, size, value);
1175 } else {
1176 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
1177 assert(size == 1 || size == 2 || size == 4);
1178 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
1179
1180 bzero(&pio, sizeof(pio));
1181 pio.pbi_sel = sc->psc_sel;
1182 pio.pbi_op = PCIBARIO_WRITE;
1183 pio.pbi_bar = baridx;
1184 pio.pbi_offset = (uint32_t)offset;
1185 pio.pbi_width = size;
1186 pio.pbi_value = (uint32_t)value;
1187
1188 (void)ioctl(pcifd, PCIOCBARIO, &pio);
1189 }
1190 }
1191
1192 static uint64_t
passthru_read(struct pci_devinst * pi,int baridx,uint64_t offset,int size)1193 passthru_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
1194 {
1195 struct passthru_softc *sc;
1196 struct pci_bar_ioreq pio;
1197 uint64_t val;
1198
1199 sc = pi->pi_arg;
1200
1201 if (baridx == pci_msix_table_bar(pi)) {
1202 val = msix_table_read(sc, offset, size);
1203 } else {
1204 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
1205 assert(size == 1 || size == 2 || size == 4);
1206 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
1207
1208 bzero(&pio, sizeof(pio));
1209 pio.pbi_sel = sc->psc_sel;
1210 pio.pbi_op = PCIBARIO_READ;
1211 pio.pbi_bar = baridx;
1212 pio.pbi_offset = (uint32_t)offset;
1213 pio.pbi_width = size;
1214
1215 (void)ioctl(pcifd, PCIOCBARIO, &pio);
1216
1217 val = pio.pbi_value;
1218 }
1219
1220 return (val);
1221 }
1222
1223 static void
passthru_msix_addr(struct pci_devinst * pi,int baridx,int enabled,uint64_t address)1224 passthru_msix_addr(struct pci_devinst *pi, int baridx, int enabled,
1225 uint64_t address)
1226 {
1227 struct passthru_softc *sc;
1228 size_t remaining;
1229 uint32_t table_size, table_offset;
1230
1231 sc = pi->pi_arg;
1232 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
1233 if (table_offset > 0) {
1234 if (!enabled) {
1235 if (vm_unmap_pptdev_mmio(pi->pi_vmctx,
1236 sc->psc_sel.pc_bus,
1237 sc->psc_sel.pc_dev,
1238 sc->psc_sel.pc_func, address,
1239 table_offset) != 0)
1240 warnx("pci_passthru: unmap_pptdev_mmio failed");
1241 } else {
1242 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1243 sc->psc_sel.pc_dev,
1244 sc->psc_sel.pc_func, address,
1245 table_offset,
1246 sc->psc_bar[baridx].addr) != 0)
1247 warnx("pci_passthru: map_pptdev_mmio failed");
1248 }
1249 }
1250 table_size = pi->pi_msix.table_offset - table_offset;
1251 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
1252 table_size = roundup2(table_size, 4096);
1253 remaining = pi->pi_bar[baridx].size - table_offset - table_size;
1254 if (remaining > 0) {
1255 address += table_offset + table_size;
1256 if (!enabled) {
1257 if (vm_unmap_pptdev_mmio(pi->pi_vmctx,
1258 sc->psc_sel.pc_bus,
1259 sc->psc_sel.pc_dev,
1260 sc->psc_sel.pc_func, address,
1261 remaining) != 0)
1262 warnx("pci_passthru: unmap_pptdev_mmio failed");
1263 } else {
1264 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1265 sc->psc_sel.pc_dev,
1266 sc->psc_sel.pc_func, address,
1267 remaining,
1268 sc->psc_bar[baridx].addr +
1269 table_offset + table_size) != 0)
1270 warnx("pci_passthru: map_pptdev_mmio failed");
1271 }
1272 }
1273 }
1274
1275 static void
passthru_mmio_addr(struct pci_devinst * pi,int baridx,int enabled,uint64_t address)1276 passthru_mmio_addr(struct pci_devinst *pi, int baridx, int enabled,
1277 uint64_t address)
1278 {
1279 struct passthru_softc *sc;
1280
1281 sc = pi->pi_arg;
1282 if (!enabled) {
1283 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1284 sc->psc_sel.pc_dev,
1285 sc->psc_sel.pc_func, address,
1286 sc->psc_bar[baridx].size) != 0)
1287 warnx("pci_passthru: unmap_pptdev_mmio failed");
1288 } else {
1289 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1290 sc->psc_sel.pc_dev,
1291 sc->psc_sel.pc_func, address,
1292 sc->psc_bar[baridx].size,
1293 sc->psc_bar[baridx].addr) != 0)
1294 warnx("pci_passthru: map_pptdev_mmio failed");
1295 }
1296 }
1297
1298 static void
passthru_addr_rom(struct pci_devinst * const pi,const int idx,const int enabled)1299 passthru_addr_rom(struct pci_devinst *const pi, const int idx,
1300 const int enabled)
1301 {
1302 const uint64_t addr = pi->pi_bar[idx].addr;
1303 const uint64_t size = pi->pi_bar[idx].size;
1304
1305 if (!enabled) {
1306 if (vm_munmap_memseg(pi->pi_vmctx, addr, size) != 0) {
1307 errx(4, "%s: munmap_memseg @ [%016lx - %016lx] failed",
1308 __func__, addr, addr + size);
1309 }
1310
1311 } else {
1312 if (vm_mmap_memseg(pi->pi_vmctx, addr, VM_PCIROM,
1313 pi->pi_romoffset, size, PROT_READ | PROT_EXEC) != 0) {
1314 errx(4, "%s: mmap_memseg @ [%016lx - %016lx] failed",
1315 __func__, addr, addr + size);
1316 }
1317 }
1318 }
1319
1320 static void
passthru_addr(struct pci_devinst * pi,int baridx,int enabled,uint64_t address)1321 passthru_addr(struct pci_devinst *pi, int baridx, int enabled, uint64_t address)
1322 {
1323 switch (pi->pi_bar[baridx].type) {
1324 case PCIBAR_IO:
1325 /* IO BARs are emulated */
1326 break;
1327 case PCIBAR_ROM:
1328 passthru_addr_rom(pi, baridx, enabled);
1329 break;
1330 case PCIBAR_MEM32:
1331 case PCIBAR_MEM64:
1332 if (baridx == pci_msix_table_bar(pi))
1333 passthru_msix_addr(pi, baridx, enabled, address);
1334 else
1335 passthru_mmio_addr(pi, baridx, enabled, address);
1336 break;
1337 default:
1338 errx(4, "%s: invalid BAR type %d", __func__,
1339 pi->pi_bar[baridx].type);
1340 }
1341 }
1342
1343 static const struct pci_devemu passthru = {
1344 .pe_emu = "passthru",
1345 .pe_init = passthru_init,
1346 .pe_legacy_config = passthru_legacy_config,
1347 .pe_cfgwrite = passthru_cfgwrite,
1348 .pe_cfgread = passthru_cfgread,
1349 .pe_barwrite = passthru_write,
1350 .pe_barread = passthru_read,
1351 .pe_baraddr = passthru_addr,
1352 };
1353 PCI_EMUL_SET(passthru);
1354