1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Sepherosa Ziehau <sepherosa@gmail.com>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in
17 * the documentation and/or other materials provided with the
18 * distribution.
19 * 3. Neither the name of The DragonFly Project nor the names of its
20 * contributors may be used to endorse or promote products derived
21 * from this software without specific, prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $
37 */
38
39 #include <sys/cdefs.h>
40 #include "opt_inet.h"
41 #include "opt_bwi.h"
42 #include "opt_wlan.h"
43
44 #include <sys/param.h>
45 #include <sys/endian.h>
46 #include <sys/kernel.h>
47 #include <sys/bus.h>
48 #include <sys/malloc.h>
49 #include <sys/proc.h>
50 #include <sys/rman.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/systm.h>
55 #include <sys/taskqueue.h>
56
57 #include <net/if.h>
58 #include <net/if_var.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_arp.h>
63 #include <net/ethernet.h>
64 #include <net/if_llc.h>
65
66 #include <net80211/ieee80211_var.h>
67 #include <net80211/ieee80211_radiotap.h>
68 #include <net80211/ieee80211_regdomain.h>
69 #include <net80211/ieee80211_phy.h>
70 #include <net80211/ieee80211_ratectl.h>
71
72 #include <net/bpf.h>
73
74 #ifdef INET
75 #include <netinet/in.h>
76 #include <netinet/if_ether.h>
77 #endif
78
79 #include <machine/bus.h>
80
81 #include <dev/pci/pcivar.h>
82 #include <dev/pci/pcireg.h>
83
84 #include <dev/bwi/bitops.h>
85 #include <dev/bwi/if_bwireg.h>
86 #include <dev/bwi/if_bwivar.h>
87 #include <dev/bwi/bwimac.h>
88 #include <dev/bwi/bwirf.h>
89
90 struct bwi_clock_freq {
91 u_int clkfreq_min;
92 u_int clkfreq_max;
93 };
94
95 struct bwi_myaddr_bssid {
96 uint8_t myaddr[IEEE80211_ADDR_LEN];
97 uint8_t bssid[IEEE80211_ADDR_LEN];
98 } __packed;
99
100 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *,
101 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
102 const uint8_t [IEEE80211_ADDR_LEN],
103 const uint8_t [IEEE80211_ADDR_LEN]);
104 static void bwi_vap_delete(struct ieee80211vap *);
105 static void bwi_init(struct bwi_softc *);
106 static void bwi_parent(struct ieee80211com *);
107 static int bwi_transmit(struct ieee80211com *, struct mbuf *);
108 static void bwi_start_locked(struct bwi_softc *);
109 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *,
110 const struct ieee80211_bpf_params *);
111 static void bwi_watchdog(void *);
112 static void bwi_scan_start(struct ieee80211com *);
113 static void bwi_getradiocaps(struct ieee80211com *, int, int *,
114 struct ieee80211_channel[]);
115 static void bwi_set_channel(struct ieee80211com *);
116 static void bwi_scan_end(struct ieee80211com *);
117 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int);
118 static void bwi_updateslot(struct ieee80211com *);
119
120 static void bwi_calibrate(void *);
121
122 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
123 static int bwi_calc_noise(struct bwi_softc *);
124 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype);
125 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
126 struct bwi_rxbuf_hdr *, const void *, int, int, int);
127
128 static void bwi_restart(void *, int);
129 static void bwi_init_statechg(struct bwi_softc *, int);
130 static void bwi_stop(struct bwi_softc *, int);
131 static void bwi_stop_locked(struct bwi_softc *, int);
132 static int bwi_newbuf(struct bwi_softc *, int, int);
133 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
134 struct ieee80211_node *);
135 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *,
136 struct ieee80211_node *,
137 const struct ieee80211_bpf_params *);
138
139 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
140 bus_addr_t, int, int);
141 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
142
143 static int bwi_init_tx_ring32(struct bwi_softc *, int);
144 static int bwi_init_rx_ring32(struct bwi_softc *);
145 static int bwi_init_txstats32(struct bwi_softc *);
146 static void bwi_free_tx_ring32(struct bwi_softc *, int);
147 static void bwi_free_rx_ring32(struct bwi_softc *);
148 static void bwi_free_txstats32(struct bwi_softc *);
149 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
150 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
151 int, bus_addr_t, int);
152 static int bwi_rxeof32(struct bwi_softc *);
153 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
154 static void bwi_txeof_status32(struct bwi_softc *);
155
156 static int bwi_init_tx_ring64(struct bwi_softc *, int);
157 static int bwi_init_rx_ring64(struct bwi_softc *);
158 static int bwi_init_txstats64(struct bwi_softc *);
159 static void bwi_free_tx_ring64(struct bwi_softc *, int);
160 static void bwi_free_rx_ring64(struct bwi_softc *);
161 static void bwi_free_txstats64(struct bwi_softc *);
162 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
163 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
164 int, bus_addr_t, int);
165 static int bwi_rxeof64(struct bwi_softc *);
166 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
167 static void bwi_txeof_status64(struct bwi_softc *);
168
169 static int bwi_rxeof(struct bwi_softc *, int);
170 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
171 static void bwi_txeof(struct bwi_softc *);
172 static void bwi_txeof_status(struct bwi_softc *, int);
173 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
174 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
175
176 static int bwi_dma_alloc(struct bwi_softc *);
177 static void bwi_dma_free(struct bwi_softc *);
178 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
179 struct bwi_ring_data *, bus_size_t,
180 uint32_t);
181 static int bwi_dma_mbuf_create(struct bwi_softc *);
182 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
183 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
184 static void bwi_dma_txstats_free(struct bwi_softc *);
185 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
186 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
187 bus_size_t, int);
188
189 static void bwi_power_on(struct bwi_softc *, int);
190 static int bwi_power_off(struct bwi_softc *, int);
191 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
192 static int bwi_set_clock_delay(struct bwi_softc *);
193 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
194 static int bwi_get_pwron_delay(struct bwi_softc *sc);
195 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
196 const uint8_t *);
197 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
198
199 static void bwi_get_card_flags(struct bwi_softc *);
200 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
201
202 static int bwi_bus_attach(struct bwi_softc *);
203 static int bwi_bbp_attach(struct bwi_softc *);
204 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
205 static void bwi_bbp_power_off(struct bwi_softc *);
206
207 static const char *bwi_regwin_name(const struct bwi_regwin *);
208 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
209 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
210 static int bwi_regwin_select(struct bwi_softc *, int);
211
212 static void bwi_led_attach(struct bwi_softc *);
213 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
214 static void bwi_led_event(struct bwi_softc *, int);
215 static void bwi_led_blink_start(struct bwi_softc *, int, int);
216 static void bwi_led_blink_next(void *);
217 static void bwi_led_blink_end(void *);
218
219 static const struct {
220 uint16_t did_min;
221 uint16_t did_max;
222 uint16_t bbp_id;
223 } bwi_bbpid_map[] = {
224 { 0x4301, 0x4301, 0x4301 },
225 { 0x4305, 0x4307, 0x4307 },
226 { 0x4402, 0x4403, 0x4402 },
227 { 0x4610, 0x4615, 0x4610 },
228 { 0x4710, 0x4715, 0x4710 },
229 { 0x4720, 0x4725, 0x4309 }
230 };
231
232 static const struct {
233 uint16_t bbp_id;
234 int nregwin;
235 } bwi_regwin_count[] = {
236 { 0x4301, 5 },
237 { 0x4306, 6 },
238 { 0x4307, 5 },
239 { 0x4310, 8 },
240 { 0x4401, 3 },
241 { 0x4402, 3 },
242 { 0x4610, 9 },
243 { 0x4704, 9 },
244 { 0x4710, 9 },
245 { 0x5365, 7 }
246 };
247
248 #define CLKSRC(src) \
249 [BWI_CLKSRC_ ## src] = { \
250 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
251 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
252 }
253
254 static const struct {
255 u_int freq_min;
256 u_int freq_max;
257 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
258 CLKSRC(LP_OSC),
259 CLKSRC(CS_OSC),
260 CLKSRC(PCI)
261 };
262
263 #undef CLKSRC
264
265 #define VENDOR_LED_ACT(vendor) \
266 { \
267 .vid = PCI_VENDOR_##vendor, \
268 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
269 }
270
271 static const struct {
272 #define PCI_VENDOR_COMPAQ 0x0e11
273 #define PCI_VENDOR_LINKSYS 0x1737
274 uint16_t vid;
275 uint8_t led_act[BWI_LED_MAX];
276 } bwi_vendor_led_act[] = {
277 VENDOR_LED_ACT(COMPAQ),
278 VENDOR_LED_ACT(LINKSYS)
279 #undef PCI_VENDOR_LINKSYS
280 #undef PCI_VENDOR_COMPAQ
281 };
282
283 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
284 { BWI_VENDOR_LED_ACT_DEFAULT };
285
286 #undef VENDOR_LED_ACT
287
288 static const struct {
289 int on_dur;
290 int off_dur;
291 } bwi_led_duration[109] = {
292 [0] = { 400, 100 },
293 [2] = { 150, 75 },
294 [4] = { 90, 45 },
295 [11] = { 66, 34 },
296 [12] = { 53, 26 },
297 [18] = { 42, 21 },
298 [22] = { 35, 17 },
299 [24] = { 32, 16 },
300 [36] = { 21, 10 },
301 [48] = { 16, 8 },
302 [72] = { 11, 5 },
303 [96] = { 9, 4 },
304 [108] = { 7, 3 }
305 };
306
307 #ifdef BWI_DEBUG
308 #ifdef BWI_DEBUG_VERBOSE
309 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
310 #else
311 static uint32_t bwi_debug;
312 #endif
313 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
314 #endif /* BWI_DEBUG */
315
316 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
317
318 uint16_t
bwi_read_sprom(struct bwi_softc * sc,uint16_t ofs)319 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
320 {
321 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
322 }
323
324 static __inline void
bwi_setup_desc32(struct bwi_softc * sc,struct bwi_desc32 * desc_array,int ndesc,int desc_idx,bus_addr_t paddr,int buf_len,int tx)325 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
326 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
327 int tx)
328 {
329 struct bwi_desc32 *desc = &desc_array[desc_idx];
330 uint32_t ctrl, addr, addr_hi, addr_lo;
331
332 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
333 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
334
335 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
336 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
337
338 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
339 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
340 if (desc_idx == ndesc - 1)
341 ctrl |= BWI_DESC32_C_EOR;
342 if (tx) {
343 /* XXX */
344 ctrl |= BWI_DESC32_C_FRAME_START |
345 BWI_DESC32_C_FRAME_END |
346 BWI_DESC32_C_INTR;
347 }
348
349 desc->addr = htole32(addr);
350 desc->ctrl = htole32(ctrl);
351 }
352
353 int
bwi_attach(struct bwi_softc * sc)354 bwi_attach(struct bwi_softc *sc)
355 {
356 struct ieee80211com *ic = &sc->sc_ic;
357 device_t dev = sc->sc_dev;
358 struct bwi_mac *mac;
359 struct bwi_phy *phy;
360 int i, error;
361
362 BWI_LOCK_INIT(sc);
363
364 /*
365 * Initialize taskq and various tasks
366 */
367 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO,
368 taskqueue_thread_enqueue, &sc->sc_tq);
369 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
370 device_get_nameunit(dev));
371 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc);
372 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0);
373 mbufq_init(&sc->sc_snd, ifqmaxlen);
374
375 /*
376 * Initialize sysctl variables
377 */
378 sc->sc_fw_version = BWI_FW_VERSION3;
379 sc->sc_led_idle = (2350 * hz) / 1000;
380 sc->sc_led_ticks = ticks - sc->sc_led_idle;
381 sc->sc_led_blink = 1;
382 sc->sc_txpwr_calib = 1;
383 #ifdef BWI_DEBUG
384 sc->sc_debug = bwi_debug;
385 #endif
386 bwi_power_on(sc, 1);
387
388 error = bwi_bbp_attach(sc);
389 if (error)
390 goto fail;
391
392 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
393 if (error)
394 goto fail;
395
396 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
397 error = bwi_set_clock_delay(sc);
398 if (error)
399 goto fail;
400
401 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
402 if (error)
403 goto fail;
404
405 error = bwi_get_pwron_delay(sc);
406 if (error)
407 goto fail;
408 }
409
410 error = bwi_bus_attach(sc);
411 if (error)
412 goto fail;
413
414 bwi_get_card_flags(sc);
415
416 bwi_led_attach(sc);
417
418 for (i = 0; i < sc->sc_nmac; ++i) {
419 struct bwi_regwin *old;
420
421 mac = &sc->sc_mac[i];
422 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
423 if (error)
424 goto fail;
425
426 error = bwi_mac_lateattach(mac);
427 if (error)
428 goto fail;
429
430 error = bwi_regwin_switch(sc, old, NULL);
431 if (error)
432 goto fail;
433 }
434
435 /*
436 * XXX First MAC is known to exist
437 * TODO2
438 */
439 mac = &sc->sc_mac[0];
440 phy = &mac->mac_phy;
441
442 bwi_bbp_power_off(sc);
443
444 error = bwi_dma_alloc(sc);
445 if (error)
446 goto fail;
447
448 error = bwi_mac_fw_alloc(mac);
449 if (error)
450 goto fail;
451
452 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0);
453
454 /*
455 * Setup ratesets, phytype, channels and get MAC address
456 */
457 if (phy->phy_mode == IEEE80211_MODE_11B ||
458 phy->phy_mode == IEEE80211_MODE_11G) {
459 if (phy->phy_mode == IEEE80211_MODE_11B) {
460 ic->ic_phytype = IEEE80211_T_DS;
461 } else {
462 ic->ic_phytype = IEEE80211_T_OFDM;
463 }
464
465 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr);
466 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) {
467 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr);
468 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) {
469 device_printf(dev,
470 "invalid MAC address: %6D\n",
471 ic->ic_macaddr, ":");
472 }
473 }
474 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
475 /* TODO:11A */
476 error = ENXIO;
477 goto fail;
478 } else {
479 panic("unknown phymode %d\n", phy->phy_mode);
480 }
481
482 /* Get locale */
483 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
484 BWI_SPROM_CARD_INFO_LOCALE);
485 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
486 /* XXX use locale */
487
488 ic->ic_softc = sc;
489
490 bwi_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
491 ic->ic_channels);
492
493 ic->ic_name = device_get_nameunit(dev);
494 ic->ic_caps = IEEE80211_C_STA |
495 IEEE80211_C_SHSLOT |
496 IEEE80211_C_SHPREAMBLE |
497 IEEE80211_C_WPA |
498 IEEE80211_C_BGSCAN |
499 IEEE80211_C_MONITOR;
500 ic->ic_opmode = IEEE80211_M_STA;
501
502 ic->ic_flags_ext |= IEEE80211_FEXT_SEQNO_OFFLOAD;
503
504 ieee80211_ifattach(ic);
505
506 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
507
508 /* override default methods */
509 ic->ic_vap_create = bwi_vap_create;
510 ic->ic_vap_delete = bwi_vap_delete;
511 ic->ic_raw_xmit = bwi_raw_xmit;
512 ic->ic_updateslot = bwi_updateslot;
513 ic->ic_scan_start = bwi_scan_start;
514 ic->ic_scan_end = bwi_scan_end;
515 ic->ic_getradiocaps = bwi_getradiocaps;
516 ic->ic_set_channel = bwi_set_channel;
517 ic->ic_transmit = bwi_transmit;
518 ic->ic_parent = bwi_parent;
519
520 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan);
521
522 ieee80211_radiotap_attach(ic,
523 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
524 BWI_TX_RADIOTAP_PRESENT,
525 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
526 BWI_RX_RADIOTAP_PRESENT);
527
528 /*
529 * Add sysctl nodes
530 */
531 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
532 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
533 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
534 "Firmware version");
535 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
536 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
537 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
538 "# ticks before LED enters idle state");
539 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
540 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
541 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
542 "Allow LED to blink");
543 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
544 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
545 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
546 "Enable software TX power calibration");
547 #ifdef BWI_DEBUG
548 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
549 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
550 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
551 #endif
552 if (bootverbose)
553 ieee80211_announce(ic);
554
555 return (0);
556 fail:
557 BWI_LOCK_DESTROY(sc);
558 return (error);
559 }
560
561 int
bwi_detach(struct bwi_softc * sc)562 bwi_detach(struct bwi_softc *sc)
563 {
564 struct ieee80211com *ic = &sc->sc_ic;
565 int i;
566
567 bwi_stop(sc, 1);
568 callout_drain(&sc->sc_led_blink_ch);
569 callout_drain(&sc->sc_calib_ch);
570 callout_drain(&sc->sc_watchdog_timer);
571 ieee80211_ifdetach(ic);
572
573 for (i = 0; i < sc->sc_nmac; ++i)
574 bwi_mac_detach(&sc->sc_mac[i]);
575 bwi_dma_free(sc);
576 taskqueue_free(sc->sc_tq);
577 mbufq_drain(&sc->sc_snd);
578
579 BWI_LOCK_DESTROY(sc);
580
581 return (0);
582 }
583
584 static struct ieee80211vap *
bwi_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])585 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
586 enum ieee80211_opmode opmode, int flags,
587 const uint8_t bssid[IEEE80211_ADDR_LEN],
588 const uint8_t mac[IEEE80211_ADDR_LEN])
589 {
590 struct bwi_vap *bvp;
591 struct ieee80211vap *vap;
592
593 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
594 return NULL;
595 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO);
596 vap = &bvp->bv_vap;
597 /* enable s/w bmiss handling for sta mode */
598 ieee80211_vap_setup(ic, vap, name, unit, opmode,
599 flags | IEEE80211_CLONE_NOBEACONS, bssid);
600
601 /* override default methods */
602 bvp->bv_newstate = vap->iv_newstate;
603 vap->iv_newstate = bwi_newstate;
604 #if 0
605 vap->iv_update_beacon = bwi_beacon_update;
606 #endif
607 ieee80211_ratectl_init(vap);
608
609 /* complete setup */
610 ieee80211_vap_attach(vap, ieee80211_media_change,
611 ieee80211_media_status, mac);
612 ic->ic_opmode = opmode;
613 return vap;
614 }
615
616 static void
bwi_vap_delete(struct ieee80211vap * vap)617 bwi_vap_delete(struct ieee80211vap *vap)
618 {
619 struct bwi_vap *bvp = BWI_VAP(vap);
620
621 ieee80211_ratectl_deinit(vap);
622 ieee80211_vap_detach(vap);
623 free(bvp, M_80211_VAP);
624 }
625
626 void
bwi_suspend(struct bwi_softc * sc)627 bwi_suspend(struct bwi_softc *sc)
628 {
629 bwi_stop(sc, 1);
630 }
631
632 void
bwi_resume(struct bwi_softc * sc)633 bwi_resume(struct bwi_softc *sc)
634 {
635
636 if (sc->sc_ic.ic_nrunning > 0)
637 bwi_init(sc);
638 }
639
640 int
bwi_shutdown(struct bwi_softc * sc)641 bwi_shutdown(struct bwi_softc *sc)
642 {
643 bwi_stop(sc, 1);
644 return 0;
645 }
646
647 static void
bwi_power_on(struct bwi_softc * sc,int with_pll)648 bwi_power_on(struct bwi_softc *sc, int with_pll)
649 {
650 uint32_t gpio_in, gpio_out, gpio_en;
651 uint16_t status;
652
653 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
654 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
655 goto back;
656
657 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
658 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
659
660 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
661 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
662 if (with_pll) {
663 /* Turn off PLL first */
664 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
665 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
666 }
667
668 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
669 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
670 DELAY(1000);
671
672 if (with_pll) {
673 /* Turn on PLL */
674 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
675 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
676 DELAY(5000);
677 }
678
679 back:
680 /* Clear "Signaled Target Abort" */
681 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
682 status &= ~PCIM_STATUS_STABORT;
683 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
684 }
685
686 static int
bwi_power_off(struct bwi_softc * sc,int with_pll)687 bwi_power_off(struct bwi_softc *sc, int with_pll)
688 {
689 uint32_t gpio_out, gpio_en;
690
691 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
692 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
693 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
694
695 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
696 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
697 if (with_pll) {
698 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
699 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
700 }
701
702 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
703 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
704 return 0;
705 }
706
707 int
bwi_regwin_switch(struct bwi_softc * sc,struct bwi_regwin * rw,struct bwi_regwin ** old_rw)708 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
709 struct bwi_regwin **old_rw)
710 {
711 int error;
712
713 if (old_rw != NULL)
714 *old_rw = NULL;
715
716 if (!BWI_REGWIN_EXIST(rw))
717 return EINVAL;
718
719 if (sc->sc_cur_regwin != rw) {
720 error = bwi_regwin_select(sc, rw->rw_id);
721 if (error) {
722 device_printf(sc->sc_dev, "can't select regwin %d\n",
723 rw->rw_id);
724 return error;
725 }
726 }
727
728 if (old_rw != NULL)
729 *old_rw = sc->sc_cur_regwin;
730 sc->sc_cur_regwin = rw;
731 return 0;
732 }
733
734 static int
bwi_regwin_select(struct bwi_softc * sc,int id)735 bwi_regwin_select(struct bwi_softc *sc, int id)
736 {
737 uint32_t win = BWI_PCIM_REGWIN(id);
738 int i;
739
740 #define RETRY_MAX 50
741 for (i = 0; i < RETRY_MAX; ++i) {
742 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
743 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
744 return 0;
745 DELAY(10);
746 }
747 #undef RETRY_MAX
748
749 return ENXIO;
750 }
751
752 static void
bwi_regwin_info(struct bwi_softc * sc,uint16_t * type,uint8_t * rev)753 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
754 {
755 uint32_t val;
756
757 val = CSR_READ_4(sc, BWI_ID_HI);
758 *type = BWI_ID_HI_REGWIN_TYPE(val);
759 *rev = BWI_ID_HI_REGWIN_REV(val);
760
761 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
762 "vendor 0x%04x\n", *type, *rev,
763 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
764 }
765
766 static int
bwi_bbp_attach(struct bwi_softc * sc)767 bwi_bbp_attach(struct bwi_softc *sc)
768 {
769 uint16_t bbp_id, rw_type;
770 uint8_t rw_rev;
771 uint32_t info;
772 int error, nregwin, i;
773
774 /*
775 * Get 0th regwin information
776 * NOTE: 0th regwin should exist
777 */
778 error = bwi_regwin_select(sc, 0);
779 if (error) {
780 device_printf(sc->sc_dev, "can't select regwin 0\n");
781 return error;
782 }
783 bwi_regwin_info(sc, &rw_type, &rw_rev);
784
785 /*
786 * Find out BBP id
787 */
788 bbp_id = 0;
789 info = 0;
790 if (rw_type == BWI_REGWIN_T_COM) {
791 info = CSR_READ_4(sc, BWI_INFO);
792 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
793
794 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
795
796 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
797 } else {
798 for (i = 0; i < nitems(bwi_bbpid_map); ++i) {
799 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min &&
800 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) {
801 bbp_id = bwi_bbpid_map[i].bbp_id;
802 break;
803 }
804 }
805 if (bbp_id == 0) {
806 device_printf(sc->sc_dev, "no BBP id for device id "
807 "0x%04x\n", sc->sc_pci_did);
808 return ENXIO;
809 }
810
811 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) |
812 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
813 }
814
815 /*
816 * Find out number of regwins
817 */
818 nregwin = 0;
819 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
820 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
821 } else {
822 for (i = 0; i < nitems(bwi_regwin_count); ++i) {
823 if (bwi_regwin_count[i].bbp_id == bbp_id) {
824 nregwin = bwi_regwin_count[i].nregwin;
825 break;
826 }
827 }
828 if (nregwin == 0) {
829 device_printf(sc->sc_dev, "no number of win for "
830 "BBP id 0x%04x\n", bbp_id);
831 return ENXIO;
832 }
833 }
834
835 /* Record BBP id/rev for later using */
836 sc->sc_bbp_id = bbp_id;
837 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
838 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
839 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
840 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
841
842 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
843 nregwin, sc->sc_cap);
844
845 /*
846 * Create rest of the regwins
847 */
848
849 /* Don't re-create common regwin, if it is already created */
850 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
851
852 for (; i < nregwin; ++i) {
853 /*
854 * Get regwin information
855 */
856 error = bwi_regwin_select(sc, i);
857 if (error) {
858 device_printf(sc->sc_dev,
859 "can't select regwin %d\n", i);
860 return error;
861 }
862 bwi_regwin_info(sc, &rw_type, &rw_rev);
863
864 /*
865 * Try attach:
866 * 1) Bus (PCI/PCIE) regwin
867 * 2) MAC regwin
868 * Ignore rest types of regwin
869 */
870 if (rw_type == BWI_REGWIN_T_BUSPCI ||
871 rw_type == BWI_REGWIN_T_BUSPCIE) {
872 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
873 device_printf(sc->sc_dev,
874 "bus regwin already exists\n");
875 } else {
876 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
877 rw_type, rw_rev);
878 }
879 } else if (rw_type == BWI_REGWIN_T_MAC) {
880 /* XXX ignore return value */
881 bwi_mac_attach(sc, i, rw_rev);
882 }
883 }
884
885 /* At least one MAC shold exist */
886 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
887 device_printf(sc->sc_dev, "no MAC was found\n");
888 return ENXIO;
889 }
890 KASSERT(sc->sc_nmac > 0, ("no mac's"));
891
892 /* Bus regwin must exist */
893 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
894 device_printf(sc->sc_dev, "no bus regwin was found\n");
895 return ENXIO;
896 }
897
898 /* Start with first MAC */
899 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
900 if (error)
901 return error;
902
903 return 0;
904 }
905
906 int
bwi_bus_init(struct bwi_softc * sc,struct bwi_mac * mac)907 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
908 {
909 struct bwi_regwin *old, *bus;
910 uint32_t val;
911 int error;
912
913 bus = &sc->sc_bus_regwin;
914 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin"));
915
916 /*
917 * Tell bus to generate requested interrupts
918 */
919 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
920 /*
921 * NOTE: Read BWI_FLAGS from MAC regwin
922 */
923 val = CSR_READ_4(sc, BWI_FLAGS);
924
925 error = bwi_regwin_switch(sc, bus, &old);
926 if (error)
927 return error;
928
929 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
930 } else {
931 uint32_t mac_mask;
932
933 mac_mask = 1 << mac->mac_id;
934
935 error = bwi_regwin_switch(sc, bus, &old);
936 if (error)
937 return error;
938
939 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
940 val |= mac_mask << 8;
941 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
942 }
943
944 if (sc->sc_flags & BWI_F_BUS_INITED)
945 goto back;
946
947 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
948 /*
949 * Enable prefetch and burst
950 */
951 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
952 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
953
954 if (bus->rw_rev < 5) {
955 struct bwi_regwin *com = &sc->sc_com_regwin;
956
957 /*
958 * Configure timeouts for bus operation
959 */
960
961 /*
962 * Set service timeout and request timeout
963 */
964 CSR_SETBITS_4(sc, BWI_CONF_LO,
965 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
966 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
967
968 /*
969 * If there is common regwin, we switch to that regwin
970 * and switch back to bus regwin once we have done.
971 */
972 if (BWI_REGWIN_EXIST(com)) {
973 error = bwi_regwin_switch(sc, com, NULL);
974 if (error)
975 return error;
976 }
977
978 /* Let bus know what we have changed */
979 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
980 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
981 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
982 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
983
984 if (BWI_REGWIN_EXIST(com)) {
985 error = bwi_regwin_switch(sc, bus, NULL);
986 if (error)
987 return error;
988 }
989 } else if (bus->rw_rev >= 11) {
990 /*
991 * Enable memory read multiple
992 */
993 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
994 }
995 } else {
996 /* TODO:PCIE */
997 }
998
999 sc->sc_flags |= BWI_F_BUS_INITED;
1000 back:
1001 return bwi_regwin_switch(sc, old, NULL);
1002 }
1003
1004 static void
bwi_get_card_flags(struct bwi_softc * sc)1005 bwi_get_card_flags(struct bwi_softc *sc)
1006 {
1007 #define PCI_VENDOR_APPLE 0x106b
1008 #define PCI_VENDOR_DELL 0x1028
1009 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1010 if (sc->sc_card_flags == 0xffff)
1011 sc->sc_card_flags = 0;
1012
1013 if (sc->sc_pci_subvid == PCI_VENDOR_DELL &&
1014 sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1015 sc->sc_pci_revid == 0x74)
1016 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST;
1017
1018 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1019 sc->sc_pci_subdid == 0x4e && /* XXX */
1020 sc->sc_pci_revid > 0x40)
1021 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1022
1023 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1024 #undef PCI_VENDOR_DELL
1025 #undef PCI_VENDOR_APPLE
1026 }
1027
1028 static void
bwi_get_eaddr(struct bwi_softc * sc,uint16_t eaddr_ofs,uint8_t * eaddr)1029 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1030 {
1031 int i;
1032
1033 for (i = 0; i < 3; ++i) {
1034 *((uint16_t *)eaddr + i) =
1035 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1036 }
1037 }
1038
1039 static void
bwi_get_clock_freq(struct bwi_softc * sc,struct bwi_clock_freq * freq)1040 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1041 {
1042 struct bwi_regwin *com;
1043 uint32_t val;
1044 u_int div;
1045 int src;
1046
1047 bzero(freq, sizeof(*freq));
1048 com = &sc->sc_com_regwin;
1049
1050 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist"));
1051 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin"));
1052 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode"));
1053
1054 /*
1055 * Calculate clock frequency
1056 */
1057 src = -1;
1058 div = 0;
1059 if (com->rw_rev < 6) {
1060 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1061 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1062 src = BWI_CLKSRC_PCI;
1063 div = 64;
1064 } else {
1065 src = BWI_CLKSRC_CS_OSC;
1066 div = 32;
1067 }
1068 } else if (com->rw_rev < 10) {
1069 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1070
1071 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1072 if (src == BWI_CLKSRC_LP_OSC) {
1073 div = 1;
1074 } else {
1075 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1076
1077 /* Unknown source */
1078 if (src >= BWI_CLKSRC_MAX)
1079 src = BWI_CLKSRC_CS_OSC;
1080 }
1081 } else {
1082 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1083
1084 src = BWI_CLKSRC_CS_OSC;
1085 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1086 }
1087
1088 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src));
1089 KASSERT(div != 0, ("div zero"));
1090
1091 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1092 src == BWI_CLKSRC_PCI ? "PCI" :
1093 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1094
1095 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1096 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1097
1098 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1099 freq->clkfreq_min, freq->clkfreq_max);
1100 }
1101
1102 static int
bwi_set_clock_mode(struct bwi_softc * sc,enum bwi_clock_mode clk_mode)1103 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1104 {
1105 struct bwi_regwin *old, *com;
1106 uint32_t clk_ctrl, clk_src;
1107 int error, pwr_off = 0;
1108
1109 com = &sc->sc_com_regwin;
1110 if (!BWI_REGWIN_EXIST(com))
1111 return 0;
1112
1113 if (com->rw_rev >= 10 || com->rw_rev < 6)
1114 return 0;
1115
1116 /*
1117 * For common regwin whose rev is [6, 10), the chip
1118 * must be capable to change clock mode.
1119 */
1120 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1121 return 0;
1122
1123 error = bwi_regwin_switch(sc, com, &old);
1124 if (error)
1125 return error;
1126
1127 if (clk_mode == BWI_CLOCK_MODE_FAST)
1128 bwi_power_on(sc, 0); /* Don't turn on PLL */
1129
1130 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1131 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1132
1133 switch (clk_mode) {
1134 case BWI_CLOCK_MODE_FAST:
1135 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1136 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1137 break;
1138 case BWI_CLOCK_MODE_SLOW:
1139 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1140 break;
1141 case BWI_CLOCK_MODE_DYN:
1142 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1143 BWI_CLOCK_CTRL_IGNPLL |
1144 BWI_CLOCK_CTRL_NODYN);
1145 if (clk_src != BWI_CLKSRC_CS_OSC) {
1146 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1147 pwr_off = 1;
1148 }
1149 break;
1150 }
1151 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1152
1153 if (pwr_off)
1154 bwi_power_off(sc, 0); /* Leave PLL as it is */
1155
1156 return bwi_regwin_switch(sc, old, NULL);
1157 }
1158
1159 static int
bwi_set_clock_delay(struct bwi_softc * sc)1160 bwi_set_clock_delay(struct bwi_softc *sc)
1161 {
1162 struct bwi_regwin *old, *com;
1163 int error;
1164
1165 com = &sc->sc_com_regwin;
1166 if (!BWI_REGWIN_EXIST(com))
1167 return 0;
1168
1169 error = bwi_regwin_switch(sc, com, &old);
1170 if (error)
1171 return error;
1172
1173 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1174 if (sc->sc_bbp_rev == 0)
1175 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1176 else if (sc->sc_bbp_rev == 1)
1177 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1178 }
1179
1180 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1181 if (com->rw_rev >= 10) {
1182 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1183 } else {
1184 struct bwi_clock_freq freq;
1185
1186 bwi_get_clock_freq(sc, &freq);
1187 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1188 howmany(freq.clkfreq_max * 150, 1000000));
1189 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1190 howmany(freq.clkfreq_max * 15, 1000000));
1191 }
1192 }
1193
1194 return bwi_regwin_switch(sc, old, NULL);
1195 }
1196
1197 static void
bwi_init(struct bwi_softc * sc)1198 bwi_init(struct bwi_softc *sc)
1199 {
1200 struct ieee80211com *ic = &sc->sc_ic;
1201
1202 BWI_LOCK(sc);
1203 bwi_init_statechg(sc, 1);
1204 BWI_UNLOCK(sc);
1205
1206 if (sc->sc_flags & BWI_F_RUNNING)
1207 ieee80211_start_all(ic); /* start all vap's */
1208 }
1209
1210 static void
bwi_init_statechg(struct bwi_softc * sc,int statechg)1211 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1212 {
1213 struct bwi_mac *mac;
1214 int error;
1215
1216 BWI_ASSERT_LOCKED(sc);
1217
1218 bwi_stop_locked(sc, statechg);
1219
1220 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1221
1222 /* TODO: 2 MAC */
1223
1224 mac = &sc->sc_mac[0];
1225 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1226 if (error) {
1227 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n",
1228 __func__, error);
1229 goto bad;
1230 }
1231 error = bwi_mac_init(mac);
1232 if (error) {
1233 device_printf(sc->sc_dev, "%s: error %d on MAC init\n",
1234 __func__, error);
1235 goto bad;
1236 }
1237
1238 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1239
1240 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1241 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr);
1242
1243 bwi_mac_reset_hwkeys(mac);
1244
1245 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1246 int i;
1247
1248 #define NRETRY 1000
1249 /*
1250 * Drain any possible pending TX status
1251 */
1252 for (i = 0; i < NRETRY; ++i) {
1253 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1254 BWI_TXSTATUS0_VALID) == 0)
1255 break;
1256 CSR_READ_4(sc, BWI_TXSTATUS1);
1257 }
1258 if (i == NRETRY)
1259 device_printf(sc->sc_dev,
1260 "%s: can't drain TX status\n", __func__);
1261 #undef NRETRY
1262 }
1263
1264 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1265 bwi_mac_updateslot(mac, 1);
1266
1267 /* Start MAC */
1268 error = bwi_mac_start(mac);
1269 if (error) {
1270 device_printf(sc->sc_dev, "%s: error %d starting MAC\n",
1271 __func__, error);
1272 goto bad;
1273 }
1274
1275 /* Clear stop flag before enabling interrupt */
1276 sc->sc_flags &= ~BWI_F_STOP;
1277 sc->sc_flags |= BWI_F_RUNNING;
1278 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1279
1280 /* Enable intrs */
1281 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1282 return;
1283 bad:
1284 bwi_stop_locked(sc, 1);
1285 }
1286
1287 static void
bwi_parent(struct ieee80211com * ic)1288 bwi_parent(struct ieee80211com *ic)
1289 {
1290 struct bwi_softc *sc = ic->ic_softc;
1291 int startall = 0;
1292
1293 BWI_LOCK(sc);
1294 if (ic->ic_nrunning > 0) {
1295 struct bwi_mac *mac;
1296 int promisc = -1;
1297
1298 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1299 ("current regwin type %d",
1300 sc->sc_cur_regwin->rw_type));
1301 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1302
1303 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) {
1304 promisc = 1;
1305 sc->sc_flags |= BWI_F_PROMISC;
1306 } else if (ic->ic_promisc == 0 &&
1307 (sc->sc_flags & BWI_F_PROMISC) != 0) {
1308 promisc = 0;
1309 sc->sc_flags &= ~BWI_F_PROMISC;
1310 }
1311
1312 if (promisc >= 0)
1313 bwi_mac_set_promisc(mac, promisc);
1314 }
1315 if (ic->ic_nrunning > 0) {
1316 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1317 bwi_init_statechg(sc, 1);
1318 startall = 1;
1319 }
1320 } else if (sc->sc_flags & BWI_F_RUNNING)
1321 bwi_stop_locked(sc, 1);
1322 BWI_UNLOCK(sc);
1323 if (startall)
1324 ieee80211_start_all(ic);
1325 }
1326
1327 static int
bwi_transmit(struct ieee80211com * ic,struct mbuf * m)1328 bwi_transmit(struct ieee80211com *ic, struct mbuf *m)
1329 {
1330 struct bwi_softc *sc = ic->ic_softc;
1331 int error;
1332
1333 BWI_LOCK(sc);
1334 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1335 BWI_UNLOCK(sc);
1336 return (ENXIO);
1337 }
1338 error = mbufq_enqueue(&sc->sc_snd, m);
1339 if (error) {
1340 BWI_UNLOCK(sc);
1341 return (error);
1342 }
1343 bwi_start_locked(sc);
1344 BWI_UNLOCK(sc);
1345 return (0);
1346 }
1347
1348 static void
bwi_start_locked(struct bwi_softc * sc)1349 bwi_start_locked(struct bwi_softc *sc)
1350 {
1351 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1352 struct ieee80211_frame *wh;
1353 struct ieee80211_node *ni;
1354 struct mbuf *m;
1355 int trans, idx;
1356
1357 BWI_ASSERT_LOCKED(sc);
1358
1359 trans = 0;
1360 idx = tbd->tbd_idx;
1361
1362 while (tbd->tbd_buf[idx].tb_mbuf == NULL &&
1363 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC &&
1364 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1365 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1366 wh = mtod(m, struct ieee80211_frame *);
1367 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 &&
1368 ieee80211_crypto_encap(ni, m) == NULL) {
1369 if_inc_counter(ni->ni_vap->iv_ifp,
1370 IFCOUNTER_OERRORS, 1);
1371 ieee80211_free_node(ni);
1372 m_freem(m);
1373 continue;
1374 }
1375 if (bwi_encap(sc, idx, m, ni) != 0) {
1376 /* 'm' is freed in bwi_encap() if we reach here */
1377 if (ni != NULL) {
1378 if_inc_counter(ni->ni_vap->iv_ifp,
1379 IFCOUNTER_OERRORS, 1);
1380 ieee80211_free_node(ni);
1381 } else
1382 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1383 continue;
1384 }
1385 trans = 1;
1386 tbd->tbd_used++;
1387 idx = (idx + 1) % BWI_TX_NDESC;
1388 }
1389
1390 tbd->tbd_idx = idx;
1391 if (trans)
1392 sc->sc_tx_timer = 5;
1393 }
1394
1395 static int
bwi_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)1396 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1397 const struct ieee80211_bpf_params *params)
1398 {
1399 struct ieee80211com *ic = ni->ni_ic;
1400 struct bwi_softc *sc = ic->ic_softc;
1401 /* XXX wme? */
1402 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1403 int idx, error;
1404
1405 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1406 m_freem(m);
1407 return ENETDOWN;
1408 }
1409
1410 BWI_LOCK(sc);
1411 idx = tbd->tbd_idx;
1412 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx));
1413 if (params == NULL) {
1414 /*
1415 * Legacy path; interpret frame contents to decide
1416 * precisely how to send the frame.
1417 */
1418 error = bwi_encap(sc, idx, m, ni);
1419 } else {
1420 /*
1421 * Caller supplied explicit parameters to use in
1422 * sending the frame.
1423 */
1424 error = bwi_encap_raw(sc, idx, m, ni, params);
1425 }
1426 if (error == 0) {
1427 tbd->tbd_used++;
1428 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC;
1429 sc->sc_tx_timer = 5;
1430 }
1431 BWI_UNLOCK(sc);
1432 return error;
1433 }
1434
1435 static void
bwi_watchdog(void * arg)1436 bwi_watchdog(void *arg)
1437 {
1438 struct bwi_softc *sc;
1439
1440 sc = arg;
1441 BWI_ASSERT_LOCKED(sc);
1442 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) {
1443 device_printf(sc->sc_dev, "watchdog timeout\n");
1444 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1445 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1446 }
1447 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1448 }
1449
1450 static void
bwi_stop(struct bwi_softc * sc,int statechg)1451 bwi_stop(struct bwi_softc *sc, int statechg)
1452 {
1453 BWI_LOCK(sc);
1454 bwi_stop_locked(sc, statechg);
1455 BWI_UNLOCK(sc);
1456 }
1457
1458 static void
bwi_stop_locked(struct bwi_softc * sc,int statechg)1459 bwi_stop_locked(struct bwi_softc *sc, int statechg)
1460 {
1461 struct bwi_mac *mac;
1462 int i, error, pwr_off = 0;
1463
1464 BWI_ASSERT_LOCKED(sc);
1465
1466 callout_stop(&sc->sc_calib_ch);
1467 callout_stop(&sc->sc_led_blink_ch);
1468 sc->sc_led_blinking = 0;
1469 sc->sc_flags |= BWI_F_STOP;
1470
1471 if (sc->sc_flags & BWI_F_RUNNING) {
1472 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1473 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1474 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1475
1476 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1477 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1478 bwi_mac_stop(mac);
1479 }
1480
1481 for (i = 0; i < sc->sc_nmac; ++i) {
1482 struct bwi_regwin *old_rw;
1483
1484 mac = &sc->sc_mac[i];
1485 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1486 continue;
1487
1488 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1489 if (error)
1490 continue;
1491
1492 bwi_mac_shutdown(mac);
1493 pwr_off = 1;
1494
1495 bwi_regwin_switch(sc, old_rw, NULL);
1496 }
1497
1498 if (pwr_off)
1499 bwi_bbp_power_off(sc);
1500
1501 sc->sc_tx_timer = 0;
1502 callout_stop(&sc->sc_watchdog_timer);
1503 sc->sc_flags &= ~BWI_F_RUNNING;
1504 }
1505
1506 void
bwi_intr(void * xsc)1507 bwi_intr(void *xsc)
1508 {
1509 struct bwi_softc *sc = xsc;
1510 struct bwi_mac *mac;
1511 uint32_t intr_status;
1512 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1513 int i, txrx_error, tx = 0, rx_data = -1;
1514
1515 BWI_LOCK(sc);
1516
1517 if ((sc->sc_flags & BWI_F_RUNNING) == 0 ||
1518 (sc->sc_flags & BWI_F_STOP)) {
1519 BWI_UNLOCK(sc);
1520 return;
1521 }
1522 /*
1523 * Get interrupt status
1524 */
1525 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1526 if (intr_status == 0xffffffff) { /* Not for us */
1527 BWI_UNLOCK(sc);
1528 return;
1529 }
1530
1531 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1532
1533 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1534 if (intr_status == 0) { /* Nothing is interesting */
1535 BWI_UNLOCK(sc);
1536 return;
1537 }
1538
1539 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1540 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1541 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1542
1543 txrx_error = 0;
1544 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1545 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1546 uint32_t mask;
1547
1548 if (BWI_TXRX_IS_RX(i))
1549 mask = BWI_TXRX_RX_INTRS;
1550 else
1551 mask = BWI_TXRX_TX_INTRS;
1552
1553 txrx_intr_status[i] =
1554 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1555
1556 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1557 i, txrx_intr_status[i]);
1558
1559 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1560 device_printf(sc->sc_dev,
1561 "%s: intr fatal TX/RX (%d) error 0x%08x\n",
1562 __func__, i, txrx_intr_status[i]);
1563 txrx_error = 1;
1564 }
1565 }
1566 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1567
1568 /*
1569 * Acknowledge interrupt
1570 */
1571 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1572
1573 for (i = 0; i < BWI_TXRX_NRING; ++i)
1574 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1575
1576 /* Disable all interrupts */
1577 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1578
1579 /*
1580 * http://bcm-specs.sipsolutions.net/Interrupts
1581 * Says for this bit (0x800):
1582 * "Fatal Error
1583 *
1584 * We got this one while testing things when by accident the
1585 * template ram wasn't set to big endian when it should have
1586 * been after writing the initial values. It keeps on being
1587 * triggered, the only way to stop it seems to shut down the
1588 * chip."
1589 *
1590 * Suggesting that we should never get it and if we do we're not
1591 * feeding TX packets into the MAC correctly if we do... Apparently,
1592 * it is valid only on mac version 5 and higher, but I couldn't
1593 * find a reference for that... Since I see them from time to time
1594 * on my card, this suggests an error in the tx path still...
1595 */
1596 if (intr_status & BWI_INTR_PHY_TXERR) {
1597 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1598 device_printf(sc->sc_dev, "%s: intr PHY TX error\n",
1599 __func__);
1600 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1601 BWI_UNLOCK(sc);
1602 return;
1603 }
1604 }
1605
1606 if (txrx_error) {
1607 /* TODO: reset device */
1608 }
1609
1610 if (intr_status & BWI_INTR_TBTT)
1611 bwi_mac_config_ps(mac);
1612
1613 if (intr_status & BWI_INTR_EO_ATIM)
1614 device_printf(sc->sc_dev, "EO_ATIM\n");
1615
1616 if (intr_status & BWI_INTR_PMQ) {
1617 for (;;) {
1618 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1619 break;
1620 }
1621 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1622 }
1623
1624 if (intr_status & BWI_INTR_NOISE)
1625 device_printf(sc->sc_dev, "intr noise\n");
1626
1627 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) {
1628 rx_data = sc->sc_rxeof(sc);
1629 if (sc->sc_flags & BWI_F_STOP) {
1630 BWI_UNLOCK(sc);
1631 return;
1632 }
1633 }
1634
1635 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1636 sc->sc_txeof_status(sc);
1637 tx = 1;
1638 }
1639
1640 if (intr_status & BWI_INTR_TX_DONE) {
1641 bwi_txeof(sc);
1642 tx = 1;
1643 }
1644
1645 /* Re-enable interrupts */
1646 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1647
1648 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1649 int evt = BWI_LED_EVENT_NONE;
1650
1651 if (tx && rx_data > 0) {
1652 if (sc->sc_rx_rate > sc->sc_tx_rate)
1653 evt = BWI_LED_EVENT_RX;
1654 else
1655 evt = BWI_LED_EVENT_TX;
1656 } else if (tx) {
1657 evt = BWI_LED_EVENT_TX;
1658 } else if (rx_data > 0) {
1659 evt = BWI_LED_EVENT_RX;
1660 } else if (rx_data == 0) {
1661 evt = BWI_LED_EVENT_POLL;
1662 }
1663
1664 if (evt != BWI_LED_EVENT_NONE)
1665 bwi_led_event(sc, evt);
1666 }
1667
1668 BWI_UNLOCK(sc);
1669 }
1670
1671 static void
bwi_scan_start(struct ieee80211com * ic)1672 bwi_scan_start(struct ieee80211com *ic)
1673 {
1674 struct bwi_softc *sc = ic->ic_softc;
1675
1676 BWI_LOCK(sc);
1677 /* Enable MAC beacon promiscuity */
1678 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1679 BWI_UNLOCK(sc);
1680 }
1681
1682 static void
bwi_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])1683 bwi_getradiocaps(struct ieee80211com *ic,
1684 int maxchans, int *nchans, struct ieee80211_channel chans[])
1685 {
1686 struct bwi_softc *sc = ic->ic_softc;
1687 struct bwi_mac *mac;
1688 struct bwi_phy *phy;
1689 uint8_t bands[IEEE80211_MODE_BYTES];
1690
1691 /*
1692 * XXX First MAC is known to exist
1693 * TODO2
1694 */
1695 mac = &sc->sc_mac[0];
1696 phy = &mac->mac_phy;
1697
1698 memset(bands, 0, sizeof(bands));
1699 switch (phy->phy_mode) {
1700 case IEEE80211_MODE_11G:
1701 setbit(bands, IEEE80211_MODE_11G);
1702 /* FALLTHROUGH */
1703 case IEEE80211_MODE_11B:
1704 setbit(bands, IEEE80211_MODE_11B);
1705 break;
1706 case IEEE80211_MODE_11A:
1707 /* TODO:11A */
1708 setbit(bands, IEEE80211_MODE_11A);
1709 device_printf(sc->sc_dev, "no 11a support\n");
1710 return;
1711 default:
1712 panic("unknown phymode %d\n", phy->phy_mode);
1713 }
1714
1715 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
1716 }
1717
1718 static void
bwi_set_channel(struct ieee80211com * ic)1719 bwi_set_channel(struct ieee80211com *ic)
1720 {
1721 struct bwi_softc *sc = ic->ic_softc;
1722 struct ieee80211_channel *c = ic->ic_curchan;
1723 struct bwi_mac *mac;
1724
1725 BWI_LOCK(sc);
1726 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1727 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1728 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1729 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0);
1730
1731 sc->sc_rates = ieee80211_get_ratetable(c);
1732 BWI_UNLOCK(sc);
1733 }
1734
1735 static void
bwi_scan_end(struct ieee80211com * ic)1736 bwi_scan_end(struct ieee80211com *ic)
1737 {
1738 struct bwi_softc *sc = ic->ic_softc;
1739
1740 BWI_LOCK(sc);
1741 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1742 BWI_UNLOCK(sc);
1743 }
1744
1745 static int
bwi_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)1746 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1747 {
1748 struct bwi_vap *bvp = BWI_VAP(vap);
1749 struct ieee80211com *ic= vap->iv_ic;
1750 struct bwi_softc *sc = ic->ic_softc;
1751 enum ieee80211_state ostate = vap->iv_state;
1752 struct bwi_mac *mac;
1753 int error;
1754
1755 BWI_LOCK(sc);
1756
1757 callout_stop(&sc->sc_calib_ch);
1758
1759 if (nstate == IEEE80211_S_INIT)
1760 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1761
1762 bwi_led_newstate(sc, nstate);
1763
1764 error = bvp->bv_newstate(vap, nstate, arg);
1765 if (error != 0)
1766 goto back;
1767
1768 /*
1769 * Clear the BSSID when we stop a STA
1770 */
1771 if (vap->iv_opmode == IEEE80211_M_STA) {
1772 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
1773 /*
1774 * Clear out the BSSID. If we reassociate to
1775 * the same AP, this will reinialize things
1776 * correctly...
1777 */
1778 if (ic->ic_opmode == IEEE80211_M_STA &&
1779 !(sc->sc_flags & BWI_F_STOP))
1780 bwi_set_bssid(sc, bwi_zero_addr);
1781 }
1782 }
1783
1784 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1785 /* Nothing to do */
1786 } else if (nstate == IEEE80211_S_RUN) {
1787 bwi_set_bssid(sc, vap->iv_bss->ni_bssid);
1788
1789 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1790 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1791 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1792
1793 /* Initial TX power calibration */
1794 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1795 #ifdef notyet
1796 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1797 #else
1798 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1799 #endif
1800
1801 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1802 }
1803 back:
1804 BWI_UNLOCK(sc);
1805
1806 return error;
1807 }
1808
1809 static int
bwi_dma_alloc(struct bwi_softc * sc)1810 bwi_dma_alloc(struct bwi_softc *sc)
1811 {
1812 int error, i, has_txstats;
1813 bus_addr_t lowaddr = 0;
1814 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1815 uint32_t txrx_ctrl_step = 0;
1816
1817 has_txstats = 0;
1818 for (i = 0; i < sc->sc_nmac; ++i) {
1819 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1820 has_txstats = 1;
1821 break;
1822 }
1823 }
1824
1825 switch (sc->sc_bus_space) {
1826 case BWI_BUS_SPACE_30BIT:
1827 case BWI_BUS_SPACE_32BIT:
1828 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1829 lowaddr = BWI_BUS_SPACE_MAXADDR;
1830 else
1831 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1832 desc_sz = sizeof(struct bwi_desc32);
1833 txrx_ctrl_step = 0x20;
1834
1835 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1836 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1837 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1838 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1839 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1840 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1841 sc->sc_rxeof = bwi_rxeof32;
1842 sc->sc_start_tx = bwi_start_tx32;
1843 if (has_txstats) {
1844 sc->sc_init_txstats = bwi_init_txstats32;
1845 sc->sc_free_txstats = bwi_free_txstats32;
1846 sc->sc_txeof_status = bwi_txeof_status32;
1847 }
1848 break;
1849
1850 case BWI_BUS_SPACE_64BIT:
1851 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1852 desc_sz = sizeof(struct bwi_desc64);
1853 txrx_ctrl_step = 0x40;
1854
1855 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1856 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1857 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1858 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1859 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1860 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1861 sc->sc_rxeof = bwi_rxeof64;
1862 sc->sc_start_tx = bwi_start_tx64;
1863 if (has_txstats) {
1864 sc->sc_init_txstats = bwi_init_txstats64;
1865 sc->sc_free_txstats = bwi_free_txstats64;
1866 sc->sc_txeof_status = bwi_txeof_status64;
1867 }
1868 break;
1869 }
1870
1871 KASSERT(lowaddr != 0, ("lowaddr zero"));
1872 KASSERT(desc_sz != 0, ("desc_sz zero"));
1873 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero"));
1874
1875 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1876 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1877
1878 /*
1879 * Create top level DMA tag
1880 */
1881 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1882 BWI_ALIGN, 0, /* alignment, bounds */
1883 lowaddr, /* lowaddr */
1884 BUS_SPACE_MAXADDR, /* highaddr */
1885 NULL, NULL, /* filter, filterarg */
1886 BUS_SPACE_MAXSIZE, /* maxsize */
1887 BUS_SPACE_UNRESTRICTED, /* nsegments */
1888 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1889 0, /* flags */
1890 NULL, NULL, /* lockfunc, lockarg */
1891 &sc->sc_parent_dtag);
1892 if (error) {
1893 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
1894 return error;
1895 }
1896
1897 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
1898
1899 /*
1900 * Create TX ring DMA stuffs
1901 */
1902 error = bus_dma_tag_create(sc->sc_parent_dtag,
1903 BWI_RING_ALIGN, 0,
1904 BUS_SPACE_MAXADDR,
1905 BUS_SPACE_MAXADDR,
1906 NULL, NULL,
1907 tx_ring_sz,
1908 1,
1909 tx_ring_sz,
1910 0,
1911 NULL, NULL,
1912 &sc->sc_txring_dtag);
1913 if (error) {
1914 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
1915 return error;
1916 }
1917
1918 for (i = 0; i < BWI_TX_NRING; ++i) {
1919 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
1920 &sc->sc_tx_rdata[i], tx_ring_sz,
1921 TXRX_CTRL(i));
1922 if (error) {
1923 device_printf(sc->sc_dev, "%dth TX ring "
1924 "DMA alloc failed\n", i);
1925 return error;
1926 }
1927 }
1928
1929 /*
1930 * Create RX ring DMA stuffs
1931 */
1932 error = bus_dma_tag_create(sc->sc_parent_dtag,
1933 BWI_RING_ALIGN, 0,
1934 BUS_SPACE_MAXADDR,
1935 BUS_SPACE_MAXADDR,
1936 NULL, NULL,
1937 rx_ring_sz,
1938 1,
1939 rx_ring_sz,
1940 0,
1941 NULL, NULL,
1942 &sc->sc_rxring_dtag);
1943 if (error) {
1944 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
1945 return error;
1946 }
1947
1948 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
1949 rx_ring_sz, TXRX_CTRL(0));
1950 if (error) {
1951 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
1952 return error;
1953 }
1954
1955 if (has_txstats) {
1956 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
1957 if (error) {
1958 device_printf(sc->sc_dev,
1959 "TX stats DMA alloc failed\n");
1960 return error;
1961 }
1962 }
1963
1964 #undef TXRX_CTRL
1965
1966 return bwi_dma_mbuf_create(sc);
1967 }
1968
1969 static void
bwi_dma_free(struct bwi_softc * sc)1970 bwi_dma_free(struct bwi_softc *sc)
1971 {
1972 if (sc->sc_txring_dtag != NULL) {
1973 int i;
1974
1975 for (i = 0; i < BWI_TX_NRING; ++i) {
1976 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
1977
1978 if (rd->rdata_desc != NULL) {
1979 bus_dmamap_unload(sc->sc_txring_dtag,
1980 rd->rdata_dmap);
1981 bus_dmamem_free(sc->sc_txring_dtag,
1982 rd->rdata_desc,
1983 rd->rdata_dmap);
1984 }
1985 }
1986 bus_dma_tag_destroy(sc->sc_txring_dtag);
1987 }
1988
1989 if (sc->sc_rxring_dtag != NULL) {
1990 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
1991
1992 if (rd->rdata_desc != NULL) {
1993 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
1994 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
1995 rd->rdata_dmap);
1996 }
1997 bus_dma_tag_destroy(sc->sc_rxring_dtag);
1998 }
1999
2000 bwi_dma_txstats_free(sc);
2001 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2002
2003 if (sc->sc_parent_dtag != NULL)
2004 bus_dma_tag_destroy(sc->sc_parent_dtag);
2005 }
2006
2007 static int
bwi_dma_ring_alloc(struct bwi_softc * sc,bus_dma_tag_t dtag,struct bwi_ring_data * rd,bus_size_t size,uint32_t txrx_ctrl)2008 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2009 struct bwi_ring_data *rd, bus_size_t size,
2010 uint32_t txrx_ctrl)
2011 {
2012 int error;
2013
2014 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2015 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2016 &rd->rdata_dmap);
2017 if (error) {
2018 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2019 return error;
2020 }
2021
2022 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2023 bwi_dma_ring_addr, &rd->rdata_paddr,
2024 BUS_DMA_NOWAIT);
2025 if (error) {
2026 device_printf(sc->sc_dev, "can't load DMA mem\n");
2027 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2028 rd->rdata_desc = NULL;
2029 return error;
2030 }
2031
2032 rd->rdata_txrx_ctrl = txrx_ctrl;
2033 return 0;
2034 }
2035
2036 static int
bwi_dma_txstats_alloc(struct bwi_softc * sc,uint32_t ctrl_base,bus_size_t desc_sz)2037 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2038 bus_size_t desc_sz)
2039 {
2040 struct bwi_txstats_data *st;
2041 bus_size_t dma_size;
2042 int error;
2043
2044 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO);
2045 if (st == NULL) {
2046 device_printf(sc->sc_dev, "can't allocate txstats data\n");
2047 return ENOMEM;
2048 }
2049 sc->sc_txstats = st;
2050
2051 /*
2052 * Create TX stats descriptor DMA stuffs
2053 */
2054 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2055
2056 error = bus_dma_tag_create(sc->sc_parent_dtag,
2057 BWI_RING_ALIGN,
2058 0,
2059 BUS_SPACE_MAXADDR,
2060 BUS_SPACE_MAXADDR,
2061 NULL, NULL,
2062 dma_size,
2063 1,
2064 dma_size,
2065 0,
2066 NULL, NULL,
2067 &st->stats_ring_dtag);
2068 if (error) {
2069 device_printf(sc->sc_dev, "can't create txstats ring "
2070 "DMA tag\n");
2071 return error;
2072 }
2073
2074 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2075 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2076 &st->stats_ring_dmap);
2077 if (error) {
2078 device_printf(sc->sc_dev, "can't allocate txstats ring "
2079 "DMA mem\n");
2080 bus_dma_tag_destroy(st->stats_ring_dtag);
2081 st->stats_ring_dtag = NULL;
2082 return error;
2083 }
2084
2085 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2086 st->stats_ring, dma_size,
2087 bwi_dma_ring_addr, &st->stats_ring_paddr,
2088 BUS_DMA_NOWAIT);
2089 if (error) {
2090 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2091 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2092 st->stats_ring_dmap);
2093 bus_dma_tag_destroy(st->stats_ring_dtag);
2094 st->stats_ring_dtag = NULL;
2095 return error;
2096 }
2097
2098 /*
2099 * Create TX stats DMA stuffs
2100 */
2101 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2102 BWI_ALIGN);
2103
2104 error = bus_dma_tag_create(sc->sc_parent_dtag,
2105 BWI_ALIGN,
2106 0,
2107 BUS_SPACE_MAXADDR,
2108 BUS_SPACE_MAXADDR,
2109 NULL, NULL,
2110 dma_size,
2111 1,
2112 dma_size,
2113 0,
2114 NULL, NULL,
2115 &st->stats_dtag);
2116 if (error) {
2117 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2118 return error;
2119 }
2120
2121 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2122 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2123 &st->stats_dmap);
2124 if (error) {
2125 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2126 bus_dma_tag_destroy(st->stats_dtag);
2127 st->stats_dtag = NULL;
2128 return error;
2129 }
2130
2131 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2132 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2133 BUS_DMA_NOWAIT);
2134 if (error) {
2135 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2136 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2137 bus_dma_tag_destroy(st->stats_dtag);
2138 st->stats_dtag = NULL;
2139 return error;
2140 }
2141
2142 st->stats_ctrl_base = ctrl_base;
2143 return 0;
2144 }
2145
2146 static void
bwi_dma_txstats_free(struct bwi_softc * sc)2147 bwi_dma_txstats_free(struct bwi_softc *sc)
2148 {
2149 struct bwi_txstats_data *st;
2150
2151 if (sc->sc_txstats == NULL)
2152 return;
2153 st = sc->sc_txstats;
2154
2155 if (st->stats_ring_dtag != NULL) {
2156 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2157 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2158 st->stats_ring_dmap);
2159 bus_dma_tag_destroy(st->stats_ring_dtag);
2160 }
2161
2162 if (st->stats_dtag != NULL) {
2163 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2164 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2165 bus_dma_tag_destroy(st->stats_dtag);
2166 }
2167
2168 free(st, M_DEVBUF);
2169 }
2170
2171 static void
bwi_dma_ring_addr(void * arg,bus_dma_segment_t * seg,int nseg,int error)2172 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2173 {
2174 KASSERT(nseg == 1, ("too many segments\n"));
2175 *((bus_addr_t *)arg) = seg->ds_addr;
2176 }
2177
2178 static int
bwi_dma_mbuf_create(struct bwi_softc * sc)2179 bwi_dma_mbuf_create(struct bwi_softc *sc)
2180 {
2181 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2182 int i, j, k, ntx, error;
2183
2184 /*
2185 * Create TX/RX mbuf DMA tag
2186 */
2187 error = bus_dma_tag_create(sc->sc_parent_dtag,
2188 1,
2189 0,
2190 BUS_SPACE_MAXADDR,
2191 BUS_SPACE_MAXADDR,
2192 NULL, NULL,
2193 MCLBYTES,
2194 1,
2195 MCLBYTES,
2196 BUS_DMA_ALLOCNOW,
2197 NULL, NULL,
2198 &sc->sc_buf_dtag);
2199 if (error) {
2200 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2201 return error;
2202 }
2203
2204 ntx = 0;
2205
2206 /*
2207 * Create TX mbuf DMA map
2208 */
2209 for (i = 0; i < BWI_TX_NRING; ++i) {
2210 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2211
2212 for (j = 0; j < BWI_TX_NDESC; ++j) {
2213 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2214 &tbd->tbd_buf[j].tb_dmap);
2215 if (error) {
2216 device_printf(sc->sc_dev, "can't create "
2217 "%dth tbd, %dth DMA map\n", i, j);
2218
2219 ntx = i;
2220 for (k = 0; k < j; ++k) {
2221 bus_dmamap_destroy(sc->sc_buf_dtag,
2222 tbd->tbd_buf[k].tb_dmap);
2223 }
2224 goto fail;
2225 }
2226 }
2227 }
2228 ntx = BWI_TX_NRING;
2229
2230 /*
2231 * Create RX mbuf DMA map and a spare DMA map
2232 */
2233 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2234 &rbd->rbd_tmp_dmap);
2235 if (error) {
2236 device_printf(sc->sc_dev,
2237 "can't create spare RX buf DMA map\n");
2238 goto fail;
2239 }
2240
2241 for (j = 0; j < BWI_RX_NDESC; ++j) {
2242 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2243 &rbd->rbd_buf[j].rb_dmap);
2244 if (error) {
2245 device_printf(sc->sc_dev, "can't create %dth "
2246 "RX buf DMA map\n", j);
2247
2248 for (k = 0; k < j; ++k) {
2249 bus_dmamap_destroy(sc->sc_buf_dtag,
2250 rbd->rbd_buf[j].rb_dmap);
2251 }
2252 bus_dmamap_destroy(sc->sc_buf_dtag,
2253 rbd->rbd_tmp_dmap);
2254 goto fail;
2255 }
2256 }
2257
2258 return 0;
2259 fail:
2260 bwi_dma_mbuf_destroy(sc, ntx, 0);
2261 return error;
2262 }
2263
2264 static void
bwi_dma_mbuf_destroy(struct bwi_softc * sc,int ntx,int nrx)2265 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2266 {
2267 int i, j;
2268
2269 if (sc->sc_buf_dtag == NULL)
2270 return;
2271
2272 for (i = 0; i < ntx; ++i) {
2273 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2274
2275 for (j = 0; j < BWI_TX_NDESC; ++j) {
2276 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2277
2278 if (tb->tb_mbuf != NULL) {
2279 bus_dmamap_unload(sc->sc_buf_dtag,
2280 tb->tb_dmap);
2281 m_freem(tb->tb_mbuf);
2282 }
2283 if (tb->tb_ni != NULL)
2284 ieee80211_free_node(tb->tb_ni);
2285 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2286 }
2287 }
2288
2289 if (nrx) {
2290 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2291
2292 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2293 for (j = 0; j < BWI_RX_NDESC; ++j) {
2294 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2295
2296 if (rb->rb_mbuf != NULL) {
2297 bus_dmamap_unload(sc->sc_buf_dtag,
2298 rb->rb_dmap);
2299 m_freem(rb->rb_mbuf);
2300 }
2301 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2302 }
2303 }
2304
2305 bus_dma_tag_destroy(sc->sc_buf_dtag);
2306 sc->sc_buf_dtag = NULL;
2307 }
2308
2309 static void
bwi_enable_intrs(struct bwi_softc * sc,uint32_t enable_intrs)2310 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2311 {
2312 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2313 }
2314
2315 static void
bwi_disable_intrs(struct bwi_softc * sc,uint32_t disable_intrs)2316 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2317 {
2318 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2319 }
2320
2321 static int
bwi_init_tx_ring32(struct bwi_softc * sc,int ring_idx)2322 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2323 {
2324 struct bwi_ring_data *rd;
2325 struct bwi_txbuf_data *tbd;
2326 uint32_t val, addr_hi, addr_lo;
2327
2328 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2329 rd = &sc->sc_tx_rdata[ring_idx];
2330 tbd = &sc->sc_tx_bdata[ring_idx];
2331
2332 tbd->tbd_idx = 0;
2333 tbd->tbd_used = 0;
2334
2335 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2336 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2337 BUS_DMASYNC_PREWRITE);
2338
2339 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2340 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2341
2342 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2343 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2344 BWI_TXRX32_RINGINFO_FUNC_MASK);
2345 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2346
2347 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2348 BWI_TXRX32_CTRL_ENABLE;
2349 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2350
2351 return 0;
2352 }
2353
2354 static void
bwi_init_rxdesc_ring32(struct bwi_softc * sc,uint32_t ctrl_base,bus_addr_t paddr,int hdr_size,int ndesc)2355 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2356 bus_addr_t paddr, int hdr_size, int ndesc)
2357 {
2358 uint32_t val, addr_hi, addr_lo;
2359
2360 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2361 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2362
2363 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2364 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2365 BWI_TXRX32_RINGINFO_FUNC_MASK);
2366 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2367
2368 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2369 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2370 BWI_TXRX32_CTRL_ENABLE;
2371 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2372
2373 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2374 (ndesc - 1) * sizeof(struct bwi_desc32));
2375 }
2376
2377 static int
bwi_init_rx_ring32(struct bwi_softc * sc)2378 bwi_init_rx_ring32(struct bwi_softc *sc)
2379 {
2380 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2381 int i, error;
2382
2383 sc->sc_rx_bdata.rbd_idx = 0;
2384
2385 for (i = 0; i < BWI_RX_NDESC; ++i) {
2386 error = bwi_newbuf(sc, i, 1);
2387 if (error) {
2388 device_printf(sc->sc_dev,
2389 "can't allocate %dth RX buffer\n", i);
2390 return error;
2391 }
2392 }
2393 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2394 BUS_DMASYNC_PREWRITE);
2395
2396 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2397 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2398 return 0;
2399 }
2400
2401 static int
bwi_init_txstats32(struct bwi_softc * sc)2402 bwi_init_txstats32(struct bwi_softc *sc)
2403 {
2404 struct bwi_txstats_data *st = sc->sc_txstats;
2405 bus_addr_t stats_paddr;
2406 int i;
2407
2408 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2409 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2410
2411 st->stats_idx = 0;
2412
2413 stats_paddr = st->stats_paddr;
2414 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2415 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2416 stats_paddr, sizeof(struct bwi_txstats), 0);
2417 stats_paddr += sizeof(struct bwi_txstats);
2418 }
2419 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2420 BUS_DMASYNC_PREWRITE);
2421
2422 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2423 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2424 return 0;
2425 }
2426
2427 static void
bwi_setup_rx_desc32(struct bwi_softc * sc,int buf_idx,bus_addr_t paddr,int buf_len)2428 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2429 int buf_len)
2430 {
2431 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2432
2433 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2434 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2435 paddr, buf_len, 0);
2436 }
2437
2438 static void
bwi_setup_tx_desc32(struct bwi_softc * sc,struct bwi_ring_data * rd,int buf_idx,bus_addr_t paddr,int buf_len)2439 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2440 int buf_idx, bus_addr_t paddr, int buf_len)
2441 {
2442 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
2443 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2444 paddr, buf_len, 1);
2445 }
2446
2447 static int
bwi_init_tx_ring64(struct bwi_softc * sc,int ring_idx)2448 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2449 {
2450 /* TODO:64 */
2451 return EOPNOTSUPP;
2452 }
2453
2454 static int
bwi_init_rx_ring64(struct bwi_softc * sc)2455 bwi_init_rx_ring64(struct bwi_softc *sc)
2456 {
2457 /* TODO:64 */
2458 return EOPNOTSUPP;
2459 }
2460
2461 static int
bwi_init_txstats64(struct bwi_softc * sc)2462 bwi_init_txstats64(struct bwi_softc *sc)
2463 {
2464 /* TODO:64 */
2465 return EOPNOTSUPP;
2466 }
2467
2468 static void
bwi_setup_rx_desc64(struct bwi_softc * sc,int buf_idx,bus_addr_t paddr,int buf_len)2469 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2470 int buf_len)
2471 {
2472 /* TODO:64 */
2473 }
2474
2475 static void
bwi_setup_tx_desc64(struct bwi_softc * sc,struct bwi_ring_data * rd,int buf_idx,bus_addr_t paddr,int buf_len)2476 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2477 int buf_idx, bus_addr_t paddr, int buf_len)
2478 {
2479 /* TODO:64 */
2480 }
2481
2482 static void
bwi_dma_buf_addr(void * arg,bus_dma_segment_t * seg,int nseg,bus_size_t mapsz __unused,int error)2483 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2484 bus_size_t mapsz __unused, int error)
2485 {
2486 if (!error) {
2487 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2488 *((bus_addr_t *)arg) = seg->ds_addr;
2489 }
2490 }
2491
2492 static int
bwi_newbuf(struct bwi_softc * sc,int buf_idx,int init)2493 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2494 {
2495 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2496 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2497 struct bwi_rxbuf_hdr *hdr;
2498 bus_dmamap_t map;
2499 bus_addr_t paddr;
2500 struct mbuf *m;
2501 int error;
2502
2503 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2504
2505 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2506 if (m == NULL) {
2507 error = ENOBUFS;
2508
2509 /*
2510 * If the NIC is up and running, we need to:
2511 * - Clear RX buffer's header.
2512 * - Restore RX descriptor settings.
2513 */
2514 if (init)
2515 return error;
2516 else
2517 goto back;
2518 }
2519 m->m_len = m->m_pkthdr.len = MCLBYTES;
2520
2521 /*
2522 * Try to load RX buf into temporary DMA map
2523 */
2524 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2525 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
2526 if (error) {
2527 m_freem(m);
2528
2529 /*
2530 * See the comment above
2531 */
2532 if (init)
2533 return error;
2534 else
2535 goto back;
2536 }
2537
2538 if (!init)
2539 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2540 rxbuf->rb_mbuf = m;
2541 rxbuf->rb_paddr = paddr;
2542
2543 /*
2544 * Swap RX buf's DMA map with the loaded temporary one
2545 */
2546 map = rxbuf->rb_dmap;
2547 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2548 rbd->rbd_tmp_dmap = map;
2549
2550 back:
2551 /*
2552 * Clear RX buf header
2553 */
2554 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2555 bzero(hdr, sizeof(*hdr));
2556 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2557
2558 /*
2559 * Setup RX buf descriptor
2560 */
2561 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2562 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2563 return error;
2564 }
2565
2566 static void
bwi_set_addr_filter(struct bwi_softc * sc,uint16_t addr_ofs,const uint8_t * addr)2567 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2568 const uint8_t *addr)
2569 {
2570 int i;
2571
2572 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2573 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2574
2575 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2576 uint16_t addr_val;
2577
2578 addr_val = (uint16_t)addr[i * 2] |
2579 (((uint16_t)addr[(i * 2) + 1]) << 8);
2580 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2581 }
2582 }
2583
2584 static int
bwi_rxeof(struct bwi_softc * sc,int end_idx)2585 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2586 {
2587 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2588 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2589 struct ieee80211com *ic = &sc->sc_ic;
2590 int idx, rx_data = 0;
2591
2592 idx = rbd->rbd_idx;
2593 while (idx != end_idx) {
2594 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2595 struct bwi_rxbuf_hdr *hdr;
2596 struct ieee80211_frame_min *wh;
2597 struct ieee80211_node *ni;
2598 struct mbuf *m;
2599 uint32_t plcp;
2600 uint16_t flags2;
2601 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate;
2602
2603 m = rb->rb_mbuf;
2604 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2605 BUS_DMASYNC_POSTREAD);
2606
2607 if (bwi_newbuf(sc, idx, 0)) {
2608 counter_u64_add(ic->ic_ierrors, 1);
2609 goto next;
2610 }
2611
2612 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2613 flags2 = le16toh(hdr->rxh_flags2);
2614
2615 hdr_extra = 0;
2616 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2617 hdr_extra = 2;
2618 wh_ofs = hdr_extra + 6; /* XXX magic number */
2619
2620 buflen = le16toh(hdr->rxh_buflen);
2621 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2622 device_printf(sc->sc_dev,
2623 "%s: zero length data, hdr_extra %d\n",
2624 __func__, hdr_extra);
2625 counter_u64_add(ic->ic_ierrors, 1);
2626 m_freem(m);
2627 goto next;
2628 }
2629
2630 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp));
2631 rssi = bwi_calc_rssi(sc, hdr);
2632 noise = bwi_calc_noise(sc);
2633
2634 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2635 m_adj(m, sizeof(*hdr) + wh_ofs);
2636
2637 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2638 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM);
2639 else
2640 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK);
2641
2642 /* RX radio tap */
2643 if (ieee80211_radiotap_active(ic))
2644 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise);
2645
2646 m_adj(m, -IEEE80211_CRC_LEN);
2647
2648 BWI_UNLOCK(sc);
2649
2650 wh = mtod(m, struct ieee80211_frame_min *);
2651 ni = ieee80211_find_rxnode(ic, wh);
2652 if (ni != NULL) {
2653 type = ieee80211_input(ni, m, rssi - noise, noise);
2654 ieee80211_free_node(ni);
2655 } else
2656 type = ieee80211_input_all(ic, m, rssi - noise, noise);
2657 if (type == IEEE80211_FC0_TYPE_DATA) {
2658 rx_data = 1;
2659 sc->sc_rx_rate = rate;
2660 }
2661
2662 BWI_LOCK(sc);
2663 next:
2664 idx = (idx + 1) % BWI_RX_NDESC;
2665
2666 if (sc->sc_flags & BWI_F_STOP) {
2667 /*
2668 * Take the fast lane, don't do
2669 * any damage to softc
2670 */
2671 return -1;
2672 }
2673 }
2674
2675 rbd->rbd_idx = idx;
2676 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2677 BUS_DMASYNC_PREWRITE);
2678
2679 return rx_data;
2680 }
2681
2682 static int
bwi_rxeof32(struct bwi_softc * sc)2683 bwi_rxeof32(struct bwi_softc *sc)
2684 {
2685 uint32_t val, rx_ctrl;
2686 int end_idx, rx_data;
2687
2688 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2689
2690 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2691 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2692 sizeof(struct bwi_desc32);
2693
2694 rx_data = bwi_rxeof(sc, end_idx);
2695 if (rx_data >= 0) {
2696 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2697 end_idx * sizeof(struct bwi_desc32));
2698 }
2699 return rx_data;
2700 }
2701
2702 static int
bwi_rxeof64(struct bwi_softc * sc)2703 bwi_rxeof64(struct bwi_softc *sc)
2704 {
2705 /* TODO:64 */
2706 return 0;
2707 }
2708
2709 static void
bwi_reset_rx_ring32(struct bwi_softc * sc,uint32_t rx_ctrl)2710 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2711 {
2712 int i;
2713
2714 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2715
2716 #define NRETRY 10
2717
2718 for (i = 0; i < NRETRY; ++i) {
2719 uint32_t status;
2720
2721 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2722 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2723 BWI_RX32_STATUS_STATE_DISABLED)
2724 break;
2725
2726 DELAY(1000);
2727 }
2728 if (i == NRETRY)
2729 device_printf(sc->sc_dev, "reset rx ring timedout\n");
2730
2731 #undef NRETRY
2732
2733 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2734 }
2735
2736 static void
bwi_free_txstats32(struct bwi_softc * sc)2737 bwi_free_txstats32(struct bwi_softc *sc)
2738 {
2739 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2740 }
2741
2742 static void
bwi_free_rx_ring32(struct bwi_softc * sc)2743 bwi_free_rx_ring32(struct bwi_softc *sc)
2744 {
2745 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2746 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2747 int i;
2748
2749 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2750
2751 for (i = 0; i < BWI_RX_NDESC; ++i) {
2752 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2753
2754 if (rb->rb_mbuf != NULL) {
2755 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2756 m_freem(rb->rb_mbuf);
2757 rb->rb_mbuf = NULL;
2758 }
2759 }
2760 }
2761
2762 static void
bwi_free_tx_ring32(struct bwi_softc * sc,int ring_idx)2763 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2764 {
2765 struct bwi_ring_data *rd;
2766 struct bwi_txbuf_data *tbd;
2767 uint32_t state, val;
2768 int i;
2769
2770 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2771 rd = &sc->sc_tx_rdata[ring_idx];
2772 tbd = &sc->sc_tx_bdata[ring_idx];
2773
2774 #define NRETRY 10
2775
2776 for (i = 0; i < NRETRY; ++i) {
2777 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2778 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2779 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2780 state == BWI_TX32_STATUS_STATE_IDLE ||
2781 state == BWI_TX32_STATUS_STATE_STOPPED)
2782 break;
2783
2784 DELAY(1000);
2785 }
2786 if (i == NRETRY) {
2787 device_printf(sc->sc_dev,
2788 "%s: wait for TX ring(%d) stable timed out\n",
2789 __func__, ring_idx);
2790 }
2791
2792 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2793 for (i = 0; i < NRETRY; ++i) {
2794 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2795 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2796 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2797 break;
2798
2799 DELAY(1000);
2800 }
2801 if (i == NRETRY)
2802 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n",
2803 __func__, ring_idx);
2804
2805 #undef NRETRY
2806
2807 DELAY(1000);
2808
2809 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2810
2811 for (i = 0; i < BWI_TX_NDESC; ++i) {
2812 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2813
2814 if (tb->tb_mbuf != NULL) {
2815 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2816 m_freem(tb->tb_mbuf);
2817 tb->tb_mbuf = NULL;
2818 }
2819 if (tb->tb_ni != NULL) {
2820 ieee80211_free_node(tb->tb_ni);
2821 tb->tb_ni = NULL;
2822 }
2823 }
2824 }
2825
2826 static void
bwi_free_txstats64(struct bwi_softc * sc)2827 bwi_free_txstats64(struct bwi_softc *sc)
2828 {
2829 /* TODO:64 */
2830 }
2831
2832 static void
bwi_free_rx_ring64(struct bwi_softc * sc)2833 bwi_free_rx_ring64(struct bwi_softc *sc)
2834 {
2835 /* TODO:64 */
2836 }
2837
2838 static void
bwi_free_tx_ring64(struct bwi_softc * sc,int ring_idx)2839 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2840 {
2841 /* TODO:64 */
2842 }
2843
2844 /* XXX does not belong here */
2845 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
2846 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
2847
2848 static __inline void
bwi_ofdm_plcp_header(uint32_t * plcp0,int pkt_len,uint8_t rate)2849 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
2850 {
2851 uint32_t plcp;
2852
2853 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM),
2854 IEEE80211_OFDM_PLCP_RATE_MASK) |
2855 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
2856 *plcp0 = htole32(plcp);
2857 }
2858
2859 static __inline void
bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr * plcp,int pkt_len,uint8_t rate)2860 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
2861 uint8_t rate)
2862 {
2863 int len, service, pkt_bitlen;
2864
2865 pkt_bitlen = pkt_len * NBBY;
2866 len = howmany(pkt_bitlen * 2, rate);
2867
2868 service = IEEE80211_PLCP_SERVICE_LOCKED;
2869 if (rate == (11 * 2)) {
2870 int pkt_bitlen1;
2871
2872 /*
2873 * PLCP service field needs to be adjusted,
2874 * if TX rate is 11Mbytes/s
2875 */
2876 pkt_bitlen1 = len * 11;
2877 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
2878 service |= IEEE80211_PLCP_SERVICE_LENEXT7;
2879 }
2880
2881 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK);
2882 plcp->i_service = service;
2883 plcp->i_length = htole16(len);
2884 /* NOTE: do NOT touch i_crc */
2885 }
2886
2887 static __inline void
bwi_plcp_header(const struct ieee80211_rate_table * rt,void * plcp,int pkt_len,uint8_t rate)2888 bwi_plcp_header(const struct ieee80211_rate_table *rt,
2889 void *plcp, int pkt_len, uint8_t rate)
2890 {
2891 enum ieee80211_phytype modtype;
2892
2893 /*
2894 * Assume caller has zeroed 'plcp'
2895 */
2896 modtype = ieee80211_rate2phytype(rt, rate);
2897 if (modtype == IEEE80211_T_OFDM)
2898 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
2899 else if (modtype == IEEE80211_T_DS)
2900 bwi_ds_plcp_header(plcp, pkt_len, rate);
2901 else
2902 panic("unsupported modulation type %u\n", modtype);
2903 }
2904
2905 /*
2906 * @brief Encapsulate a frame for transmit.
2907 *
2908 * Note that this must be called inside the same lock / path
2909 * as the crypto encap call in the transmit path.
2910 */
2911 static int
bwi_encap(struct bwi_softc * sc,int idx,struct mbuf * m,struct ieee80211_node * ni)2912 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2913 struct ieee80211_node *ni)
2914 {
2915 struct ieee80211vap *vap = ni->ni_vap;
2916 struct ieee80211com *ic = &sc->sc_ic;
2917 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2918 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2919 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2920 struct bwi_mac *mac;
2921 struct bwi_txbuf_hdr *hdr;
2922 struct ieee80211_frame *wh;
2923 const struct ieee80211_txparam *tp = ni->ni_txparms;
2924 uint8_t rate, rate_fb;
2925 uint32_t mac_ctrl;
2926 uint16_t phy_ctrl;
2927 bus_addr_t paddr;
2928 int type, ismcast, pkt_len, error;
2929 #if 0
2930 const uint8_t *p;
2931 int i;
2932 #endif
2933
2934 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
2935 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
2936 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2937
2938 wh = mtod(m, struct ieee80211_frame *);
2939 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2940 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2941
2942 /* Get 802.11 frame len before prepending TX header */
2943 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2944
2945 /*
2946 * Assign sequence number - must be done in lock-step with
2947 * cipher encap.
2948 */
2949 ieee80211_output_seqno_assign(ni, -1, m);
2950
2951 /*
2952 * Find TX rate
2953 */
2954 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) {
2955 rate = rate_fb = tp->mgmtrate;
2956 } else if (ismcast) {
2957 rate = rate_fb = tp->mcastrate;
2958 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
2959 rate = rate_fb = tp->ucastrate;
2960 } else {
2961 ieee80211_ratectl_rate(ni, NULL, pkt_len);
2962 rate = ieee80211_node_get_txrate_dot11rate(ni);
2963 /* TODO: assign rate_fb the previous rate, if available */
2964 rate_fb = rate;
2965 }
2966 tb->tb_rate[0] = rate;
2967 tb->tb_rate[1] = rate_fb;
2968 sc->sc_tx_rate = rate;
2969
2970 /*
2971 * TX radio tap
2972 */
2973 if (ieee80211_radiotap_active_vap(vap)) {
2974 sc->sc_tx_th.wt_flags = 0;
2975 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
2976 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2977 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS &&
2978 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
2979 rate != (1 * 2)) {
2980 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2981 }
2982 sc->sc_tx_th.wt_rate = rate;
2983
2984 ieee80211_radiotap_tx(vap, m);
2985 }
2986
2987 /*
2988 * Setup the embedded TX header
2989 */
2990 M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
2991 if (m == NULL) {
2992 device_printf(sc->sc_dev, "%s: prepend TX header failed\n",
2993 __func__);
2994 return ENOBUFS;
2995 }
2996 hdr = mtod(m, struct bwi_txbuf_hdr *);
2997
2998 bzero(hdr, sizeof(*hdr));
2999
3000 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3001 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3002
3003 if (!ismcast) {
3004 uint16_t dur;
3005
3006 dur = ieee80211_ack_duration(sc->sc_rates, rate,
3007 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3008
3009 hdr->txh_fb_duration = htole16(dur);
3010 }
3011
3012 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3013 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3014
3015 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3016 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3017
3018 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3019 BWI_TXH_PHY_C_ANTMODE_MASK);
3020 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM)
3021 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3022 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3023 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3024
3025 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3026 if (!ismcast)
3027 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3028 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM)
3029 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3030
3031 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3032 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3033
3034 /* Catch any further usage */
3035 hdr = NULL;
3036 wh = NULL;
3037
3038 /* DMA load */
3039 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3040 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3041 if (error && error != EFBIG) {
3042 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
3043 __func__, error);
3044 goto back;
3045 }
3046
3047 if (error) { /* error == EFBIG */
3048 struct mbuf *m_new;
3049
3050 m_new = m_defrag(m, M_NOWAIT);
3051 if (m_new == NULL) {
3052 device_printf(sc->sc_dev,
3053 "%s: can't defrag TX buffer\n", __func__);
3054 error = ENOBUFS;
3055 goto back;
3056 } else {
3057 m = m_new;
3058 }
3059
3060 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3061 bwi_dma_buf_addr, &paddr,
3062 BUS_DMA_NOWAIT);
3063 if (error) {
3064 device_printf(sc->sc_dev,
3065 "%s: can't load TX buffer (2) %d\n",
3066 __func__, error);
3067 goto back;
3068 }
3069 }
3070 error = 0;
3071
3072 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3073
3074 tb->tb_mbuf = m;
3075 tb->tb_ni = ni;
3076
3077 #if 0
3078 p = mtod(m, const uint8_t *);
3079 for (i = 0; i < m->m_pkthdr.len; ++i) {
3080 if (i != 0 && i % 8 == 0)
3081 printf("\n");
3082 printf("%02x ", p[i]);
3083 }
3084 printf("\n");
3085 #endif
3086 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3087 idx, pkt_len, m->m_pkthdr.len);
3088
3089 /* Setup TX descriptor */
3090 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3091 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3092 BUS_DMASYNC_PREWRITE);
3093
3094 /* Kick start */
3095 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3096
3097 back:
3098 if (error)
3099 m_freem(m);
3100 return error;
3101 }
3102
3103 static int
bwi_encap_raw(struct bwi_softc * sc,int idx,struct mbuf * m,struct ieee80211_node * ni,const struct ieee80211_bpf_params * params)3104 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m,
3105 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3106 {
3107 struct ieee80211vap *vap = ni->ni_vap;
3108 struct ieee80211com *ic = ni->ni_ic;
3109 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3110 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3111 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3112 struct bwi_mac *mac;
3113 struct bwi_txbuf_hdr *hdr;
3114 struct ieee80211_frame *wh;
3115 uint8_t rate, rate_fb;
3116 uint32_t mac_ctrl;
3117 uint16_t phy_ctrl;
3118 bus_addr_t paddr;
3119 int ismcast, pkt_len, error;
3120
3121 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3122 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3123 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3124
3125 wh = mtod(m, struct ieee80211_frame *);
3126 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3127
3128 /* Get 802.11 frame len before prepending TX header */
3129 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3130
3131 /* Assign sequence number. */
3132 ieee80211_output_seqno_assign(ni, -1, m);
3133
3134 /*
3135 * Find TX rate
3136 */
3137 rate = params->ibp_rate0;
3138 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3139 /* XXX fall back to mcast/mgmt rate? */
3140 m_freem(m);
3141 return EINVAL;
3142 }
3143 if (params->ibp_try1 != 0) {
3144 rate_fb = params->ibp_rate1;
3145 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) {
3146 /* XXX fall back to rate0? */
3147 m_freem(m);
3148 return EINVAL;
3149 }
3150 } else
3151 rate_fb = rate;
3152 tb->tb_rate[0] = rate;
3153 tb->tb_rate[1] = rate_fb;
3154 sc->sc_tx_rate = rate;
3155
3156 /*
3157 * TX radio tap
3158 */
3159 if (ieee80211_radiotap_active_vap(vap)) {
3160 sc->sc_tx_th.wt_flags = 0;
3161 /* XXX IEEE80211_BPF_CRYPTO */
3162 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3163 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3164 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3165 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3166 sc->sc_tx_th.wt_rate = rate;
3167
3168 ieee80211_radiotap_tx(vap, m);
3169 }
3170
3171 /*
3172 * Setup the embedded TX header
3173 */
3174 M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
3175 if (m == NULL) {
3176 device_printf(sc->sc_dev, "%s: prepend TX header failed\n",
3177 __func__);
3178 return ENOBUFS;
3179 }
3180 hdr = mtod(m, struct bwi_txbuf_hdr *);
3181
3182 bzero(hdr, sizeof(*hdr));
3183
3184 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3185 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3186
3187 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3188 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
3189 uint16_t dur;
3190
3191 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0);
3192
3193 hdr->txh_fb_duration = htole16(dur);
3194 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3195 }
3196
3197 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3198 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3199
3200 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3201 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3202
3203 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3204 BWI_TXH_PHY_C_ANTMODE_MASK);
3205 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) {
3206 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3207 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3208 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3209 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3210
3211 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3212 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3213
3214 /* Catch any further usage */
3215 hdr = NULL;
3216 wh = NULL;
3217
3218 /* DMA load */
3219 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3220 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3221 if (error != 0) {
3222 struct mbuf *m_new;
3223
3224 if (error != EFBIG) {
3225 device_printf(sc->sc_dev,
3226 "%s: can't load TX buffer (1) %d\n",
3227 __func__, error);
3228 goto back;
3229 }
3230 m_new = m_defrag(m, M_NOWAIT);
3231 if (m_new == NULL) {
3232 device_printf(sc->sc_dev,
3233 "%s: can't defrag TX buffer\n", __func__);
3234 error = ENOBUFS;
3235 goto back;
3236 }
3237 m = m_new;
3238 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3239 bwi_dma_buf_addr, &paddr,
3240 BUS_DMA_NOWAIT);
3241 if (error) {
3242 device_printf(sc->sc_dev,
3243 "%s: can't load TX buffer (2) %d\n",
3244 __func__, error);
3245 goto back;
3246 }
3247 }
3248
3249 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3250
3251 tb->tb_mbuf = m;
3252 tb->tb_ni = ni;
3253
3254 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3255 idx, pkt_len, m->m_pkthdr.len);
3256
3257 /* Setup TX descriptor */
3258 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3259 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3260 BUS_DMASYNC_PREWRITE);
3261
3262 /* Kick start */
3263 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3264 back:
3265 if (error)
3266 m_freem(m);
3267 return error;
3268 }
3269
3270 static void
bwi_start_tx32(struct bwi_softc * sc,uint32_t tx_ctrl,int idx)3271 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3272 {
3273 idx = (idx + 1) % BWI_TX_NDESC;
3274 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3275 idx * sizeof(struct bwi_desc32));
3276 }
3277
3278 static void
bwi_start_tx64(struct bwi_softc * sc,uint32_t tx_ctrl,int idx)3279 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3280 {
3281 /* TODO:64 */
3282 }
3283
3284 static void
bwi_txeof_status32(struct bwi_softc * sc)3285 bwi_txeof_status32(struct bwi_softc *sc)
3286 {
3287 uint32_t val, ctrl_base;
3288 int end_idx;
3289
3290 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3291
3292 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3293 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3294 sizeof(struct bwi_desc32);
3295
3296 bwi_txeof_status(sc, end_idx);
3297
3298 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3299 end_idx * sizeof(struct bwi_desc32));
3300
3301 bwi_start_locked(sc);
3302 }
3303
3304 static void
bwi_txeof_status64(struct bwi_softc * sc)3305 bwi_txeof_status64(struct bwi_softc *sc)
3306 {
3307 /* TODO:64 */
3308 }
3309
3310 static void
_bwi_txeof(struct bwi_softc * sc,uint16_t tx_id,int acked,int data_txcnt)3311 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3312 {
3313 struct bwi_txbuf_data *tbd;
3314 struct bwi_txbuf *tb;
3315 int ring_idx, buf_idx;
3316 struct ieee80211_node *ni;
3317
3318 if (tx_id == 0) {
3319 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__);
3320 return;
3321 }
3322
3323 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3324 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3325
3326 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx));
3327 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
3328
3329 tbd = &sc->sc_tx_bdata[ring_idx];
3330 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used));
3331 tbd->tbd_used--;
3332
3333 tb = &tbd->tbd_buf[buf_idx];
3334 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3335 "acked %d, data_txcnt %d, ni %p\n",
3336 buf_idx, acked, data_txcnt, tb->tb_ni);
3337
3338 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3339
3340 if ((ni = tb->tb_ni) != NULL) {
3341 const struct bwi_txbuf_hdr *hdr =
3342 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *);
3343 struct ieee80211_ratectl_tx_status txs;
3344
3345 /* NB: update rate control only for unicast frames */
3346 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) {
3347 /*
3348 * Feed back 'acked and data_txcnt'. Note that the
3349 * generic AMRR code only understands one tx rate
3350 * and the estimator doesn't handle real retry counts
3351 * well so to avoid over-aggressive downshifting we
3352 * treat any number of retries as "1".
3353 */
3354 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY;
3355 txs.long_retries = acked;
3356 if (data_txcnt > 1)
3357 txs.status = IEEE80211_RATECTL_TX_SUCCESS;
3358 else {
3359 txs.status =
3360 IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
3361 }
3362 ieee80211_ratectl_tx_complete(ni, &txs);
3363 }
3364 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked);
3365 tb->tb_ni = NULL;
3366 } else
3367 m_freem(tb->tb_mbuf);
3368 tb->tb_mbuf = NULL;
3369
3370 if (tbd->tbd_used == 0)
3371 sc->sc_tx_timer = 0;
3372 }
3373
3374 static void
bwi_txeof_status(struct bwi_softc * sc,int end_idx)3375 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3376 {
3377 struct bwi_txstats_data *st = sc->sc_txstats;
3378 int idx;
3379
3380 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3381
3382 idx = st->stats_idx;
3383 while (idx != end_idx) {
3384 const struct bwi_txstats *stats = &st->stats[idx];
3385
3386 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3387 int data_txcnt;
3388
3389 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3390 BWI_TXS_TXCNT_DATA);
3391 _bwi_txeof(sc, le16toh(stats->txs_id),
3392 stats->txs_flags & BWI_TXS_F_ACKED,
3393 data_txcnt);
3394 }
3395 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3396 }
3397 st->stats_idx = idx;
3398 }
3399
3400 static void
bwi_txeof(struct bwi_softc * sc)3401 bwi_txeof(struct bwi_softc *sc)
3402 {
3403
3404 for (;;) {
3405 uint32_t tx_status0, tx_status1 __unused;
3406 uint16_t tx_id;
3407 int data_txcnt;
3408
3409 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3410 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3411 break;
3412 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3413
3414 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3415 data_txcnt = __SHIFTOUT(tx_status0,
3416 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3417
3418 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3419 continue;
3420
3421 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED,
3422 data_txcnt);
3423 }
3424
3425 bwi_start_locked(sc);
3426 }
3427
3428 static int
bwi_bbp_power_on(struct bwi_softc * sc,enum bwi_clock_mode clk_mode)3429 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3430 {
3431 bwi_power_on(sc, 1);
3432 return bwi_set_clock_mode(sc, clk_mode);
3433 }
3434
3435 static void
bwi_bbp_power_off(struct bwi_softc * sc)3436 bwi_bbp_power_off(struct bwi_softc *sc)
3437 {
3438 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3439 bwi_power_off(sc, 1);
3440 }
3441
3442 static int
bwi_get_pwron_delay(struct bwi_softc * sc)3443 bwi_get_pwron_delay(struct bwi_softc *sc)
3444 {
3445 struct bwi_regwin *com, *old;
3446 struct bwi_clock_freq freq;
3447 uint32_t val;
3448 int error;
3449
3450 com = &sc->sc_com_regwin;
3451 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin"));
3452
3453 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3454 return 0;
3455
3456 error = bwi_regwin_switch(sc, com, &old);
3457 if (error)
3458 return error;
3459
3460 bwi_get_clock_freq(sc, &freq);
3461
3462 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3463 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3464 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3465
3466 return bwi_regwin_switch(sc, old, NULL);
3467 }
3468
3469 static int
bwi_bus_attach(struct bwi_softc * sc)3470 bwi_bus_attach(struct bwi_softc *sc)
3471 {
3472 struct bwi_regwin *bus, *old;
3473 int error;
3474
3475 bus = &sc->sc_bus_regwin;
3476
3477 error = bwi_regwin_switch(sc, bus, &old);
3478 if (error)
3479 return error;
3480
3481 if (!bwi_regwin_is_enabled(sc, bus))
3482 bwi_regwin_enable(sc, bus, 0);
3483
3484 /* Disable interripts */
3485 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3486
3487 return bwi_regwin_switch(sc, old, NULL);
3488 }
3489
3490 static const char *
bwi_regwin_name(const struct bwi_regwin * rw)3491 bwi_regwin_name(const struct bwi_regwin *rw)
3492 {
3493 switch (rw->rw_type) {
3494 case BWI_REGWIN_T_COM:
3495 return "COM";
3496 case BWI_REGWIN_T_BUSPCI:
3497 return "PCI";
3498 case BWI_REGWIN_T_MAC:
3499 return "MAC";
3500 case BWI_REGWIN_T_BUSPCIE:
3501 return "PCIE";
3502 }
3503 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3504 return NULL;
3505 }
3506
3507 static uint32_t
bwi_regwin_disable_bits(struct bwi_softc * sc)3508 bwi_regwin_disable_bits(struct bwi_softc *sc)
3509 {
3510 uint32_t busrev;
3511
3512 /* XXX cache this */
3513 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3514 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3515 "bus rev %u\n", busrev);
3516
3517 if (busrev == BWI_BUSREV_0)
3518 return BWI_STATE_LO_DISABLE1;
3519 else if (busrev == BWI_BUSREV_1)
3520 return BWI_STATE_LO_DISABLE2;
3521 else
3522 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3523 }
3524
3525 int
bwi_regwin_is_enabled(struct bwi_softc * sc,struct bwi_regwin * rw)3526 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3527 {
3528 uint32_t val, disable_bits;
3529
3530 disable_bits = bwi_regwin_disable_bits(sc);
3531 val = CSR_READ_4(sc, BWI_STATE_LO);
3532
3533 if ((val & (BWI_STATE_LO_CLOCK |
3534 BWI_STATE_LO_RESET |
3535 disable_bits)) == BWI_STATE_LO_CLOCK) {
3536 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3537 bwi_regwin_name(rw));
3538 return 1;
3539 } else {
3540 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3541 bwi_regwin_name(rw));
3542 return 0;
3543 }
3544 }
3545
3546 void
bwi_regwin_disable(struct bwi_softc * sc,struct bwi_regwin * rw,uint32_t flags)3547 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3548 {
3549 uint32_t state_lo, disable_bits;
3550 int i;
3551
3552 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3553
3554 /*
3555 * If current regwin is in 'reset' state, it was already disabled.
3556 */
3557 if (state_lo & BWI_STATE_LO_RESET) {
3558 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3559 "%s was already disabled\n", bwi_regwin_name(rw));
3560 return;
3561 }
3562
3563 disable_bits = bwi_regwin_disable_bits(sc);
3564
3565 /*
3566 * Disable normal clock
3567 */
3568 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3569 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3570
3571 /*
3572 * Wait until normal clock is disabled
3573 */
3574 #define NRETRY 1000
3575 for (i = 0; i < NRETRY; ++i) {
3576 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3577 if (state_lo & disable_bits)
3578 break;
3579 DELAY(10);
3580 }
3581 if (i == NRETRY) {
3582 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3583 bwi_regwin_name(rw));
3584 }
3585
3586 for (i = 0; i < NRETRY; ++i) {
3587 uint32_t state_hi;
3588
3589 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3590 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3591 break;
3592 DELAY(10);
3593 }
3594 if (i == NRETRY) {
3595 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3596 bwi_regwin_name(rw));
3597 }
3598 #undef NRETRY
3599
3600 /*
3601 * Reset and disable regwin with gated clock
3602 */
3603 state_lo = BWI_STATE_LO_RESET | disable_bits |
3604 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3605 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3606 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3607
3608 /* Flush pending bus write */
3609 CSR_READ_4(sc, BWI_STATE_LO);
3610 DELAY(1);
3611
3612 /* Reset and disable regwin */
3613 state_lo = BWI_STATE_LO_RESET | disable_bits |
3614 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3615 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3616
3617 /* Flush pending bus write */
3618 CSR_READ_4(sc, BWI_STATE_LO);
3619 DELAY(1);
3620 }
3621
3622 void
bwi_regwin_enable(struct bwi_softc * sc,struct bwi_regwin * rw,uint32_t flags)3623 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3624 {
3625 uint32_t state_lo, state_hi, imstate;
3626
3627 bwi_regwin_disable(sc, rw, flags);
3628
3629 /* Reset regwin with gated clock */
3630 state_lo = BWI_STATE_LO_RESET |
3631 BWI_STATE_LO_CLOCK |
3632 BWI_STATE_LO_GATED_CLOCK |
3633 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3634 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3635
3636 /* Flush pending bus write */
3637 CSR_READ_4(sc, BWI_STATE_LO);
3638 DELAY(1);
3639
3640 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3641 if (state_hi & BWI_STATE_HI_SERROR)
3642 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3643
3644 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3645 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3646 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3647 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3648 }
3649
3650 /* Enable regwin with gated clock */
3651 state_lo = BWI_STATE_LO_CLOCK |
3652 BWI_STATE_LO_GATED_CLOCK |
3653 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3654 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3655
3656 /* Flush pending bus write */
3657 CSR_READ_4(sc, BWI_STATE_LO);
3658 DELAY(1);
3659
3660 /* Enable regwin with normal clock */
3661 state_lo = BWI_STATE_LO_CLOCK |
3662 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3663 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3664
3665 /* Flush pending bus write */
3666 CSR_READ_4(sc, BWI_STATE_LO);
3667 DELAY(1);
3668 }
3669
3670 static void
bwi_set_bssid(struct bwi_softc * sc,const uint8_t * bssid)3671 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3672 {
3673 struct bwi_mac *mac;
3674 struct bwi_myaddr_bssid buf;
3675 const uint8_t *p;
3676 uint32_t val;
3677 int n, i;
3678
3679 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3680 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3681 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3682
3683 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3684
3685 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr));
3686 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3687
3688 n = sizeof(buf) / sizeof(val);
3689 p = (const uint8_t *)&buf;
3690 for (i = 0; i < n; ++i) {
3691 int j;
3692
3693 val = 0;
3694 for (j = 0; j < sizeof(val); ++j)
3695 val |= ((uint32_t)(*p++)) << (j * 8);
3696
3697 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3698 }
3699 }
3700
3701 static void
bwi_updateslot(struct ieee80211com * ic)3702 bwi_updateslot(struct ieee80211com *ic)
3703 {
3704 struct bwi_softc *sc = ic->ic_softc;
3705 struct bwi_mac *mac;
3706
3707 BWI_LOCK(sc);
3708 if (sc->sc_flags & BWI_F_RUNNING) {
3709 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3710
3711 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3712 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3713 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3714
3715 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3716 }
3717 BWI_UNLOCK(sc);
3718 }
3719
3720 static void
bwi_calibrate(void * xsc)3721 bwi_calibrate(void *xsc)
3722 {
3723 struct bwi_softc *sc = xsc;
3724 struct bwi_mac *mac;
3725
3726 BWI_ASSERT_LOCKED(sc);
3727
3728 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR,
3729 ("opmode %d", sc->sc_ic.ic_opmode));
3730
3731 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3732 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3733 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3734
3735 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3736 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3737
3738 /* XXX 15 seconds */
3739 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3740 }
3741
3742 static int
bwi_calc_rssi(struct bwi_softc * sc,const struct bwi_rxbuf_hdr * hdr)3743 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3744 {
3745 struct bwi_mac *mac;
3746
3747 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3748 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3749 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3750
3751 return bwi_rf_calc_rssi(mac, hdr);
3752 }
3753
3754 static int
bwi_calc_noise(struct bwi_softc * sc)3755 bwi_calc_noise(struct bwi_softc *sc)
3756 {
3757 struct bwi_mac *mac;
3758
3759 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3760 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3761 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3762
3763 return bwi_rf_calc_noise(mac);
3764 }
3765
3766 static __inline uint8_t
bwi_plcp2rate(const uint32_t plcp0,enum ieee80211_phytype type)3767 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type)
3768 {
3769 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK;
3770 return (ieee80211_plcp2rate(plcp, type));
3771 }
3772
3773 static void
bwi_rx_radiotap(struct bwi_softc * sc,struct mbuf * m,struct bwi_rxbuf_hdr * hdr,const void * plcp,int rate,int rssi,int noise)3774 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3775 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise)
3776 {
3777 const struct ieee80211_frame_min *wh;
3778
3779 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3780 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3781 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3782
3783 wh = mtod(m, const struct ieee80211_frame_min *);
3784 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3785 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3786
3787 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian conversion */
3788 sc->sc_rx_th.wr_rate = rate;
3789 sc->sc_rx_th.wr_antsignal = rssi;
3790 sc->sc_rx_th.wr_antnoise = noise;
3791 }
3792
3793 static void
bwi_led_attach(struct bwi_softc * sc)3794 bwi_led_attach(struct bwi_softc *sc)
3795 {
3796 const uint8_t *led_act = NULL;
3797 uint16_t gpio, val[BWI_LED_MAX];
3798 int i;
3799
3800 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) {
3801 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3802 led_act = bwi_vendor_led_act[i].led_act;
3803 break;
3804 }
3805 }
3806 if (led_act == NULL)
3807 led_act = bwi_default_led_act;
3808
3809 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3810 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3811 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3812
3813 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3814 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3815 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3816
3817 for (i = 0; i < BWI_LED_MAX; ++i) {
3818 struct bwi_led *led = &sc->sc_leds[i];
3819
3820 if (val[i] == 0xff) {
3821 led->l_act = led_act[i];
3822 } else {
3823 if (val[i] & BWI_LED_ACT_LOW)
3824 led->l_flags |= BWI_LED_F_ACTLOW;
3825 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3826 }
3827 led->l_mask = (1 << i);
3828
3829 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3830 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3831 led->l_act == BWI_LED_ACT_BLINK) {
3832 led->l_flags |= BWI_LED_F_BLINK;
3833 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3834 led->l_flags |= BWI_LED_F_POLLABLE;
3835 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3836 led->l_flags |= BWI_LED_F_SLOW;
3837
3838 if (sc->sc_blink_led == NULL) {
3839 sc->sc_blink_led = led;
3840 if (led->l_flags & BWI_LED_F_SLOW)
3841 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3842 }
3843 }
3844
3845 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3846 "%dth led, act %d, lowact %d\n", i,
3847 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3848 }
3849 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
3850 }
3851
3852 static __inline uint16_t
bwi_led_onoff(const struct bwi_led * led,uint16_t val,int on)3853 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3854 {
3855 if (led->l_flags & BWI_LED_F_ACTLOW)
3856 on = !on;
3857 if (on)
3858 val |= led->l_mask;
3859 else
3860 val &= ~led->l_mask;
3861 return val;
3862 }
3863
3864 static void
bwi_led_newstate(struct bwi_softc * sc,enum ieee80211_state nstate)3865 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3866 {
3867 struct ieee80211com *ic = &sc->sc_ic;
3868 uint16_t val;
3869 int i;
3870
3871 if (nstate == IEEE80211_S_INIT) {
3872 callout_stop(&sc->sc_led_blink_ch);
3873 sc->sc_led_blinking = 0;
3874 }
3875
3876 if ((sc->sc_flags & BWI_F_RUNNING) == 0)
3877 return;
3878
3879 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3880 for (i = 0; i < BWI_LED_MAX; ++i) {
3881 struct bwi_led *led = &sc->sc_leds[i];
3882 int on;
3883
3884 if (led->l_act == BWI_LED_ACT_UNKN ||
3885 led->l_act == BWI_LED_ACT_NULL)
3886 continue;
3887
3888 if ((led->l_flags & BWI_LED_F_BLINK) &&
3889 nstate != IEEE80211_S_INIT)
3890 continue;
3891
3892 switch (led->l_act) {
3893 case BWI_LED_ACT_ON: /* Always on */
3894 on = 1;
3895 break;
3896 case BWI_LED_ACT_OFF: /* Always off */
3897 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3898 on = 0;
3899 break;
3900 default:
3901 on = 1;
3902 switch (nstate) {
3903 case IEEE80211_S_INIT:
3904 on = 0;
3905 break;
3906 case IEEE80211_S_RUN:
3907 if (led->l_act == BWI_LED_ACT_11G &&
3908 ic->ic_curmode != IEEE80211_MODE_11G)
3909 on = 0;
3910 break;
3911 default:
3912 if (led->l_act == BWI_LED_ACT_ASSOC)
3913 on = 0;
3914 break;
3915 }
3916 break;
3917 }
3918
3919 val = bwi_led_onoff(led, val, on);
3920 }
3921 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3922 }
3923 static void
bwi_led_event(struct bwi_softc * sc,int event)3924 bwi_led_event(struct bwi_softc *sc, int event)
3925 {
3926 struct bwi_led *led = sc->sc_blink_led;
3927 int rate;
3928
3929 if (event == BWI_LED_EVENT_POLL) {
3930 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3931 return;
3932 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3933 return;
3934 }
3935
3936 sc->sc_led_ticks = ticks;
3937 if (sc->sc_led_blinking)
3938 return;
3939
3940 switch (event) {
3941 case BWI_LED_EVENT_RX:
3942 rate = sc->sc_rx_rate;
3943 break;
3944 case BWI_LED_EVENT_TX:
3945 rate = sc->sc_tx_rate;
3946 break;
3947 case BWI_LED_EVENT_POLL:
3948 rate = 0;
3949 break;
3950 default:
3951 panic("unknown LED event %d\n", event);
3952 break;
3953 }
3954 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3955 bwi_led_duration[rate].off_dur);
3956 }
3957
3958 static void
bwi_led_blink_start(struct bwi_softc * sc,int on_dur,int off_dur)3959 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3960 {
3961 struct bwi_led *led = sc->sc_blink_led;
3962 uint16_t val;
3963
3964 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3965 val = bwi_led_onoff(led, val, 1);
3966 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3967
3968 if (led->l_flags & BWI_LED_F_SLOW) {
3969 BWI_LED_SLOWDOWN(on_dur);
3970 BWI_LED_SLOWDOWN(off_dur);
3971 }
3972
3973 sc->sc_led_blinking = 1;
3974 sc->sc_led_blink_offdur = off_dur;
3975
3976 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3977 }
3978
3979 static void
bwi_led_blink_next(void * xsc)3980 bwi_led_blink_next(void *xsc)
3981 {
3982 struct bwi_softc *sc = xsc;
3983 uint16_t val;
3984
3985 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3986 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3987 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3988
3989 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3990 bwi_led_blink_end, sc);
3991 }
3992
3993 static void
bwi_led_blink_end(void * xsc)3994 bwi_led_blink_end(void *xsc)
3995 {
3996 struct bwi_softc *sc = xsc;
3997 sc->sc_led_blinking = 0;
3998 }
3999
4000 static void
bwi_restart(void * xsc,int pending)4001 bwi_restart(void *xsc, int pending)
4002 {
4003 struct bwi_softc *sc = xsc;
4004
4005 device_printf(sc->sc_dev, "%s begin, help!\n", __func__);
4006 BWI_LOCK(sc);
4007 bwi_init_statechg(sc, 0);
4008 #if 0
4009 bwi_start_locked(sc);
4010 #endif
4011 BWI_UNLOCK(sc);
4012 }
4013