1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 13#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 14#include <dt-bindings/clock/qcom,sm8350-videocc.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc8280xp.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/phy/phy-qcom-qmp.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sm8350-videocc.h> 24#include <dt-bindings/soc/qcom,gpr.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/sound/qcom,q6afe.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 clocks { 36 xo_board_clk: xo-board-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <32764>; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a78c"; 55 reg = <0x0 0x0>; 56 clocks = <&cpufreq_hw 0>; 57 enable-method = "psci"; 58 capacity-dmips-mhz = <981>; 59 dynamic-power-coefficient = <549>; 60 next-level-cache = <&l2_0>; 61 power-domains = <&cpu_pd0>; 62 power-domain-names = "psci"; 63 qcom,freq-domain = <&cpufreq_hw 0>; 64 operating-points-v2 = <&cpu0_opp_table>; 65 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 66 #cooling-cells = <2>; 67 l2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <2>; 70 cache-unified; 71 next-level-cache = <&l3_0>; 72 l3_0: l3-cache { 73 compatible = "cache"; 74 cache-level = <3>; 75 cache-unified; 76 }; 77 }; 78 }; 79 80 cpu1: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a78c"; 83 reg = <0x0 0x100>; 84 clocks = <&cpufreq_hw 0>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <981>; 87 dynamic-power-coefficient = <549>; 88 next-level-cache = <&l2_100>; 89 power-domains = <&cpu_pd1>; 90 power-domain-names = "psci"; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 operating-points-v2 = <&cpu0_opp_table>; 93 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 94 #cooling-cells = <2>; 95 l2_100: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 next-level-cache = <&l3_0>; 100 }; 101 }; 102 103 cpu2: cpu@200 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a78c"; 106 reg = <0x0 0x200>; 107 clocks = <&cpufreq_hw 0>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <981>; 110 dynamic-power-coefficient = <549>; 111 next-level-cache = <&l2_200>; 112 power-domains = <&cpu_pd2>; 113 power-domain-names = "psci"; 114 qcom,freq-domain = <&cpufreq_hw 0>; 115 operating-points-v2 = <&cpu0_opp_table>; 116 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 117 #cooling-cells = <2>; 118 l2_200: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&l3_0>; 123 }; 124 }; 125 126 cpu3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a78c"; 129 reg = <0x0 0x300>; 130 clocks = <&cpufreq_hw 0>; 131 enable-method = "psci"; 132 capacity-dmips-mhz = <981>; 133 dynamic-power-coefficient = <549>; 134 next-level-cache = <&l2_300>; 135 power-domains = <&cpu_pd3>; 136 power-domain-names = "psci"; 137 qcom,freq-domain = <&cpufreq_hw 0>; 138 operating-points-v2 = <&cpu0_opp_table>; 139 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 140 #cooling-cells = <2>; 141 l2_300: l2-cache { 142 compatible = "cache"; 143 cache-level = <2>; 144 cache-unified; 145 next-level-cache = <&l3_0>; 146 }; 147 }; 148 149 cpu4: cpu@400 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-x1c"; 152 reg = <0x0 0x400>; 153 clocks = <&cpufreq_hw 1>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <1024>; 156 dynamic-power-coefficient = <590>; 157 next-level-cache = <&l2_400>; 158 power-domains = <&cpu_pd4>; 159 power-domain-names = "psci"; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 operating-points-v2 = <&cpu4_opp_table>; 162 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 163 #cooling-cells = <2>; 164 l2_400: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&l3_0>; 169 }; 170 }; 171 172 cpu5: cpu@500 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-x1c"; 175 reg = <0x0 0x500>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <1024>; 179 dynamic-power-coefficient = <590>; 180 next-level-cache = <&l2_500>; 181 power-domains = <&cpu_pd5>; 182 power-domain-names = "psci"; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 operating-points-v2 = <&cpu4_opp_table>; 185 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 186 #cooling-cells = <2>; 187 l2_500: l2-cache { 188 compatible = "cache"; 189 cache-level = <2>; 190 cache-unified; 191 next-level-cache = <&l3_0>; 192 }; 193 }; 194 195 cpu6: cpu@600 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-x1c"; 198 reg = <0x0 0x600>; 199 clocks = <&cpufreq_hw 1>; 200 enable-method = "psci"; 201 capacity-dmips-mhz = <1024>; 202 dynamic-power-coefficient = <590>; 203 next-level-cache = <&l2_600>; 204 power-domains = <&cpu_pd6>; 205 power-domain-names = "psci"; 206 qcom,freq-domain = <&cpufreq_hw 1>; 207 operating-points-v2 = <&cpu4_opp_table>; 208 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 209 #cooling-cells = <2>; 210 l2_600: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&l3_0>; 215 }; 216 }; 217 218 cpu7: cpu@700 { 219 device_type = "cpu"; 220 compatible = "arm,cortex-x1c"; 221 reg = <0x0 0x700>; 222 clocks = <&cpufreq_hw 1>; 223 enable-method = "psci"; 224 capacity-dmips-mhz = <1024>; 225 dynamic-power-coefficient = <590>; 226 next-level-cache = <&l2_700>; 227 power-domains = <&cpu_pd7>; 228 power-domain-names = "psci"; 229 qcom,freq-domain = <&cpufreq_hw 1>; 230 operating-points-v2 = <&cpu4_opp_table>; 231 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 232 #cooling-cells = <2>; 233 l2_700: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&l3_0>; 238 }; 239 }; 240 241 cpu-map { 242 cluster0 { 243 core0 { 244 cpu = <&cpu0>; 245 }; 246 247 core1 { 248 cpu = <&cpu1>; 249 }; 250 251 core2 { 252 cpu = <&cpu2>; 253 }; 254 255 core3 { 256 cpu = <&cpu3>; 257 }; 258 259 core4 { 260 cpu = <&cpu4>; 261 }; 262 263 core5 { 264 cpu = <&cpu5>; 265 }; 266 267 core6 { 268 cpu = <&cpu6>; 269 }; 270 271 core7 { 272 cpu = <&cpu7>; 273 }; 274 }; 275 }; 276 277 idle-states { 278 entry-method = "psci"; 279 280 little_cpu_sleep_0: cpu-sleep-0-0 { 281 compatible = "arm,idle-state"; 282 idle-state-name = "little-rail-power-collapse"; 283 arm,psci-suspend-param = <0x40000004>; 284 entry-latency-us = <355>; 285 exit-latency-us = <909>; 286 min-residency-us = <3934>; 287 local-timer-stop; 288 }; 289 290 big_cpu_sleep_0: cpu-sleep-1-0 { 291 compatible = "arm,idle-state"; 292 idle-state-name = "big-rail-power-collapse"; 293 arm,psci-suspend-param = <0x40000004>; 294 entry-latency-us = <241>; 295 exit-latency-us = <1461>; 296 min-residency-us = <4488>; 297 local-timer-stop; 298 }; 299 }; 300 301 domain-idle-states { 302 cluster_sleep_0: cluster-sleep-0 { 303 compatible = "domain-idle-state"; 304 arm,psci-suspend-param = <0x4100c344>; 305 entry-latency-us = <3263>; 306 exit-latency-us = <6562>; 307 min-residency-us = <9987>; 308 }; 309 }; 310 }; 311 312 firmware { 313 scm: scm { 314 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 315 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 316 qcom,dload-mode = <&tcsr 0x13000>; 317 }; 318 }; 319 320 clk_virt: interconnect-clk-virt { 321 compatible = "qcom,sc8280xp-clk-virt"; 322 #interconnect-cells = <2>; 323 qcom,bcm-voters = <&apps_bcm_voter>; 324 }; 325 326 mc_virt: interconnect-mc-virt { 327 compatible = "qcom,sc8280xp-mc-virt"; 328 #interconnect-cells = <2>; 329 qcom,bcm-voters = <&apps_bcm_voter>; 330 }; 331 332 memory@80000000 { 333 device_type = "memory"; 334 /* We expect the bootloader to fill in the size */ 335 reg = <0x0 0x80000000 0x0 0x0>; 336 }; 337 338 cpu0_opp_table: opp-table-cpu0 { 339 compatible = "operating-points-v2"; 340 opp-shared; 341 342 opp-300000000 { 343 opp-hz = /bits/ 64 <300000000>; 344 opp-peak-kBps = <(300000 * 32)>; 345 }; 346 opp-403200000 { 347 opp-hz = /bits/ 64 <403200000>; 348 opp-peak-kBps = <(384000 * 32)>; 349 }; 350 opp-499200000 { 351 opp-hz = /bits/ 64 <499200000>; 352 opp-peak-kBps = <(480000 * 32)>; 353 }; 354 opp-595200000 { 355 opp-hz = /bits/ 64 <595200000>; 356 opp-peak-kBps = <(576000 * 32)>; 357 }; 358 opp-691200000 { 359 opp-hz = /bits/ 64 <691200000>; 360 opp-peak-kBps = <(672000 * 32)>; 361 }; 362 opp-806400000 { 363 opp-hz = /bits/ 64 <806400000>; 364 opp-peak-kBps = <(768000 * 32)>; 365 }; 366 opp-902400000 { 367 opp-hz = /bits/ 64 <902400000>; 368 opp-peak-kBps = <(864000 * 32)>; 369 }; 370 opp-1017600000 { 371 opp-hz = /bits/ 64 <1017600000>; 372 opp-peak-kBps = <(960000 * 32)>; 373 }; 374 opp-1113600000 { 375 opp-hz = /bits/ 64 <1113600000>; 376 opp-peak-kBps = <(1075200 * 32)>; 377 }; 378 opp-1209600000 { 379 opp-hz = /bits/ 64 <1209600000>; 380 opp-peak-kBps = <(1171200 * 32)>; 381 }; 382 opp-1324800000 { 383 opp-hz = /bits/ 64 <1324800000>; 384 opp-peak-kBps = <(1267200 * 32)>; 385 }; 386 opp-1440000000 { 387 opp-hz = /bits/ 64 <1440000000>; 388 opp-peak-kBps = <(1363200 * 32)>; 389 }; 390 opp-1555200000 { 391 opp-hz = /bits/ 64 <1555200000>; 392 opp-peak-kBps = <(1536000 * 32)>; 393 }; 394 opp-1670400000 { 395 opp-hz = /bits/ 64 <1670400000>; 396 opp-peak-kBps = <(1612800 * 32)>; 397 }; 398 opp-1785600000 { 399 opp-hz = /bits/ 64 <1785600000>; 400 opp-peak-kBps = <(1689600 * 32)>; 401 }; 402 opp-1881600000 { 403 opp-hz = /bits/ 64 <1881600000>; 404 opp-peak-kBps = <(1689600 * 32)>; 405 }; 406 opp-1996800000 { 407 opp-hz = /bits/ 64 <1996800000>; 408 opp-peak-kBps = <(1689600 * 32)>; 409 }; 410 opp-2112000000 { 411 opp-hz = /bits/ 64 <2112000000>; 412 opp-peak-kBps = <(1689600 * 32)>; 413 }; 414 opp-2227200000 { 415 opp-hz = /bits/ 64 <2227200000>; 416 opp-peak-kBps = <(1689600 * 32)>; 417 }; 418 opp-2342400000 { 419 opp-hz = /bits/ 64 <2342400000>; 420 opp-peak-kBps = <(1689600 * 32)>; 421 }; 422 opp-2438400000 { 423 opp-hz = /bits/ 64 <2438400000>; 424 opp-peak-kBps = <(1689600 * 32)>; 425 }; 426 }; 427 428 cpu4_opp_table: opp-table-cpu4 { 429 compatible = "operating-points-v2"; 430 opp-shared; 431 432 opp-825600000 { 433 opp-hz = /bits/ 64 <825600000>; 434 opp-peak-kBps = <(768000 * 32)>; 435 }; 436 opp-940800000 { 437 opp-hz = /bits/ 64 <940800000>; 438 opp-peak-kBps = <(864000 * 32)>; 439 }; 440 opp-1056000000 { 441 opp-hz = /bits/ 64 <1056000000>; 442 opp-peak-kBps = <(960000 * 32)>; 443 }; 444 opp-1171200000 { 445 opp-hz = /bits/ 64 <1171200000>; 446 opp-peak-kBps = <(1171200 * 32)>; 447 }; 448 opp-1286400000 { 449 opp-hz = /bits/ 64 <1286400000>; 450 opp-peak-kBps = <(1267200 * 32)>; 451 }; 452 opp-1401600000 { 453 opp-hz = /bits/ 64 <1401600000>; 454 opp-peak-kBps = <(1363200 * 32)>; 455 }; 456 opp-1516800000 { 457 opp-hz = /bits/ 64 <1516800000>; 458 opp-peak-kBps = <(1459200 * 32)>; 459 }; 460 opp-1632000000 { 461 opp-hz = /bits/ 64 <1632000000>; 462 opp-peak-kBps = <(1612800 * 32)>; 463 }; 464 opp-1747200000 { 465 opp-hz = /bits/ 64 <1747200000>; 466 opp-peak-kBps = <(1689600 * 32)>; 467 }; 468 opp-1862400000 { 469 opp-hz = /bits/ 64 <1862400000>; 470 opp-peak-kBps = <(1689600 * 32)>; 471 }; 472 opp-1977600000 { 473 opp-hz = /bits/ 64 <1977600000>; 474 opp-peak-kBps = <(1689600 * 32)>; 475 }; 476 opp-2073600000 { 477 opp-hz = /bits/ 64 <2073600000>; 478 opp-peak-kBps = <(1689600 * 32)>; 479 }; 480 opp-2169600000 { 481 opp-hz = /bits/ 64 <2169600000>; 482 opp-peak-kBps = <(1689600 * 32)>; 483 }; 484 opp-2284800000 { 485 opp-hz = /bits/ 64 <2284800000>; 486 opp-peak-kBps = <(1689600 * 32)>; 487 }; 488 opp-2400000000 { 489 opp-hz = /bits/ 64 <2400000000>; 490 opp-peak-kBps = <(1689600 * 32)>; 491 }; 492 opp-2496000000 { 493 opp-hz = /bits/ 64 <2496000000>; 494 opp-peak-kBps = <(1689600 * 32)>; 495 }; 496 opp-2592000000 { 497 opp-hz = /bits/ 64 <2592000000>; 498 opp-peak-kBps = <(1689600 * 32)>; 499 }; 500 opp-2688000000 { 501 opp-hz = /bits/ 64 <2688000000>; 502 opp-peak-kBps = <(1689600 * 32)>; 503 }; 504 opp-2803200000 { 505 opp-hz = /bits/ 64 <2803200000>; 506 opp-peak-kBps = <(1689600 * 32)>; 507 }; 508 opp-2899200000 { 509 opp-hz = /bits/ 64 <2899200000>; 510 opp-peak-kBps = <(1689600 * 32)>; 511 }; 512 opp-2995200000 { 513 opp-hz = /bits/ 64 <2995200000>; 514 opp-peak-kBps = <(1689600 * 32)>; 515 }; 516 }; 517 518 qup_opp_table_100mhz: opp-table-qup100mhz { 519 compatible = "operating-points-v2"; 520 521 opp-75000000 { 522 opp-hz = /bits/ 64 <75000000>; 523 required-opps = <&rpmhpd_opp_low_svs>; 524 }; 525 526 opp-100000000 { 527 opp-hz = /bits/ 64 <100000000>; 528 required-opps = <&rpmhpd_opp_svs>; 529 }; 530 }; 531 532 pmu { 533 compatible = "arm,armv8-pmuv3"; 534 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 535 }; 536 537 psci { 538 compatible = "arm,psci-1.0"; 539 method = "smc"; 540 541 cpu_pd0: power-domain-cpu0 { 542 #power-domain-cells = <0>; 543 power-domains = <&cluster_pd>; 544 domain-idle-states = <&little_cpu_sleep_0>; 545 }; 546 547 cpu_pd1: power-domain-cpu1 { 548 #power-domain-cells = <0>; 549 power-domains = <&cluster_pd>; 550 domain-idle-states = <&little_cpu_sleep_0>; 551 }; 552 553 cpu_pd2: power-domain-cpu2 { 554 #power-domain-cells = <0>; 555 power-domains = <&cluster_pd>; 556 domain-idle-states = <&little_cpu_sleep_0>; 557 }; 558 559 cpu_pd3: power-domain-cpu3 { 560 #power-domain-cells = <0>; 561 power-domains = <&cluster_pd>; 562 domain-idle-states = <&little_cpu_sleep_0>; 563 }; 564 565 cpu_pd4: power-domain-cpu4 { 566 #power-domain-cells = <0>; 567 power-domains = <&cluster_pd>; 568 domain-idle-states = <&big_cpu_sleep_0>; 569 }; 570 571 cpu_pd5: power-domain-cpu5 { 572 #power-domain-cells = <0>; 573 power-domains = <&cluster_pd>; 574 domain-idle-states = <&big_cpu_sleep_0>; 575 }; 576 577 cpu_pd6: power-domain-cpu6 { 578 #power-domain-cells = <0>; 579 power-domains = <&cluster_pd>; 580 domain-idle-states = <&big_cpu_sleep_0>; 581 }; 582 583 cpu_pd7: power-domain-cpu7 { 584 #power-domain-cells = <0>; 585 power-domains = <&cluster_pd>; 586 domain-idle-states = <&big_cpu_sleep_0>; 587 }; 588 589 cluster_pd: power-domain-cpu-cluster0 { 590 #power-domain-cells = <0>; 591 domain-idle-states = <&cluster_sleep_0>; 592 }; 593 }; 594 595 reserved-memory { 596 #address-cells = <2>; 597 #size-cells = <2>; 598 ranges; 599 600 reserved-region@80000000 { 601 reg = <0 0x80000000 0 0x860000>; 602 no-map; 603 }; 604 605 cmd_db: cmd-db-region@80860000 { 606 compatible = "qcom,cmd-db"; 607 reg = <0 0x80860000 0 0x20000>; 608 no-map; 609 }; 610 611 reserved-region@80880000 { 612 reg = <0 0x80880000 0 0x80000>; 613 no-map; 614 }; 615 616 smem_mem: smem-region@80900000 { 617 compatible = "qcom,smem"; 618 reg = <0 0x80900000 0 0x200000>; 619 no-map; 620 hwlocks = <&tcsr_mutex 3>; 621 }; 622 623 reserved-region@80b00000 { 624 reg = <0 0x80b00000 0 0x100000>; 625 no-map; 626 }; 627 628 reserved-region@83b00000 { 629 reg = <0 0x83b00000 0 0x1700000>; 630 no-map; 631 }; 632 633 reserved-region@85b00000 { 634 reg = <0 0x85b00000 0 0xc00000>; 635 no-map; 636 }; 637 638 pil_video_mem: video-region@86700000 { 639 reg = <0 0x86700000 0 0x500000>; 640 no-map; 641 }; 642 643 pil_adsp_mem: adsp-region@86c00000 { 644 reg = <0 0x86c00000 0 0x2000000>; 645 no-map; 646 }; 647 648 pil_slpi_mem: slpi-region@88c00000 { 649 reg = <0 0x88c00000 0 0x1500000>; 650 no-map; 651 }; 652 653 pil_nsp0_mem: cdsp0-region@8a100000 { 654 reg = <0 0x8a100000 0 0x1e00000>; 655 no-map; 656 }; 657 658 pil_gpu_mem: gpu-mem@8bf00000 { 659 reg = <0 0x8bf00000 0 0x2000>; 660 no-map; 661 }; 662 663 pil_nsp1_mem: cdsp1-region@8c600000 { 664 reg = <0 0x8c600000 0 0x1e00000>; 665 no-map; 666 }; 667 668 reserved-region@aeb00000 { 669 reg = <0 0xaeb00000 0 0x16600000>; 670 no-map; 671 }; 672 }; 673 674 smp2p-adsp { 675 compatible = "qcom,smp2p"; 676 qcom,smem = <443>, <429>; 677 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 678 IPCC_MPROC_SIGNAL_SMP2P 679 IRQ_TYPE_EDGE_RISING>; 680 mboxes = <&ipcc IPCC_CLIENT_LPASS 681 IPCC_MPROC_SIGNAL_SMP2P>; 682 683 qcom,local-pid = <0>; 684 qcom,remote-pid = <2>; 685 686 smp2p_adsp_out: master-kernel { 687 qcom,entry-name = "master-kernel"; 688 #qcom,smem-state-cells = <1>; 689 }; 690 691 smp2p_adsp_in: slave-kernel { 692 qcom,entry-name = "slave-kernel"; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 }; 696 }; 697 698 smp2p-nsp0 { 699 compatible = "qcom,smp2p"; 700 qcom,smem = <94>, <432>; 701 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 mboxes = <&ipcc IPCC_CLIENT_CDSP 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,local-pid = <0>; 708 qcom,remote-pid = <5>; 709 710 smp2p_nsp0_out: master-kernel { 711 qcom,entry-name = "master-kernel"; 712 #qcom,smem-state-cells = <1>; 713 }; 714 715 smp2p_nsp0_in: slave-kernel { 716 qcom,entry-name = "slave-kernel"; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 }; 721 722 smp2p-nsp1 { 723 compatible = "qcom,smp2p"; 724 qcom,smem = <617>, <616>; 725 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 726 IPCC_MPROC_SIGNAL_SMP2P 727 IRQ_TYPE_EDGE_RISING>; 728 mboxes = <&ipcc IPCC_CLIENT_NSP1 729 IPCC_MPROC_SIGNAL_SMP2P>; 730 731 qcom,local-pid = <0>; 732 qcom,remote-pid = <12>; 733 734 smp2p_nsp1_out: master-kernel { 735 qcom,entry-name = "master-kernel"; 736 #qcom,smem-state-cells = <1>; 737 }; 738 739 smp2p_nsp1_in: slave-kernel { 740 qcom,entry-name = "slave-kernel"; 741 interrupt-controller; 742 #interrupt-cells = <2>; 743 }; 744 }; 745 746 smp2p-slpi { 747 compatible = "qcom,smp2p"; 748 qcom,smem = <481>, <430>; 749 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 750 IPCC_MPROC_SIGNAL_SMP2P 751 IRQ_TYPE_EDGE_RISING>; 752 mboxes = <&ipcc IPCC_CLIENT_SLPI 753 IPCC_MPROC_SIGNAL_SMP2P>; 754 755 qcom,local-pid = <0>; 756 qcom,remote-pid = <3>; 757 758 smp2p_slpi_out: master-kernel { 759 qcom,entry-name = "master-kernel"; 760 #qcom,smem-state-cells = <1>; 761 }; 762 763 smp2p_slpi_in: slave-kernel { 764 qcom,entry-name = "slave-kernel"; 765 interrupt-controller; 766 #interrupt-cells = <2>; 767 }; 768 }; 769 770 soc: soc@0 { 771 compatible = "simple-bus"; 772 #address-cells = <2>; 773 #size-cells = <2>; 774 ranges = <0 0 0 0 0x10 0>; 775 dma-ranges = <0 0 0 0 0x10 0>; 776 777 ethernet0: ethernet@20000 { 778 compatible = "qcom,sc8280xp-ethqos"; 779 reg = <0x0 0x00020000 0x0 0x10000>, 780 <0x0 0x00036000 0x0 0x100>; 781 reg-names = "stmmaceth", "rgmii"; 782 783 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 784 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 785 <&gcc GCC_EMAC0_PTP_CLK>, 786 <&gcc GCC_EMAC0_RGMII_CLK>; 787 clock-names = "stmmaceth", 788 "pclk", 789 "ptp_ref", 790 "rgmii"; 791 792 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 794 interrupt-names = "macirq", "eth_lpi"; 795 796 iommus = <&apps_smmu 0x4c0 0xf>; 797 power-domains = <&gcc EMAC_0_GDSC>; 798 799 snps,tso; 800 snps,pbl = <32>; 801 rx-fifo-depth = <4096>; 802 tx-fifo-depth = <4096>; 803 804 status = "disabled"; 805 }; 806 807 gcc: clock-controller@100000 { 808 compatible = "qcom,gcc-sc8280xp"; 809 reg = <0x0 0x00100000 0x0 0x1f0000>; 810 #clock-cells = <1>; 811 #reset-cells = <1>; 812 #power-domain-cells = <1>; 813 clocks = <&rpmhcc RPMH_CXO_CLK>, 814 <&sleep_clk>, 815 <0>, 816 <0>, 817 <0>, 818 <0>, 819 <0>, 820 <0>, 821 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 822 <0>, 823 <0>, 824 <0>, 825 <0>, 826 <0>, 827 <0>, 828 <0>, 829 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 830 <0>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <0>, 836 <0>, 837 <0>, 838 <0>, 839 <&pcie2a_phy>, 840 <&pcie2b_phy>, 841 <&pcie3a_phy>, 842 <&pcie3b_phy>, 843 <&pcie4_phy>, 844 <0>, 845 <0>; 846 power-domains = <&rpmhpd SC8280XP_CX>; 847 }; 848 849 ipcc: mailbox@408000 { 850 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 851 reg = <0 0x00408000 0 0x1000>; 852 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 853 interrupt-controller; 854 #interrupt-cells = <3>; 855 #mbox-cells = <2>; 856 }; 857 858 qfprom: efuse@784000 { 859 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; 860 reg = <0 0x00784000 0 0x3000>; 861 #address-cells = <1>; 862 #size-cells = <1>; 863 864 gpu_speed_bin: gpu-speed-bin@18b { 865 reg = <0x18b 0x1>; 866 bits = <5 3>; 867 }; 868 }; 869 870 gpi_dma2: dma-controller@800000 { 871 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 872 reg = <0 0x00800000 0 0x60000>; 873 874 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 886 887 dma-channels = <12>; 888 dma-channel-mask = <0xfff>; 889 #dma-cells = <3>; 890 891 iommus = <&apps_smmu 0xb6 0x0>; 892 893 status = "disabled"; 894 }; 895 896 qup2: geniqup@8c0000 { 897 compatible = "qcom,geni-se-qup"; 898 reg = <0 0x008c0000 0 0x2000>; 899 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 900 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 901 clock-names = "m-ahb", "s-ahb"; 902 iommus = <&apps_smmu 0xa3 0>; 903 904 #address-cells = <2>; 905 #size-cells = <2>; 906 ranges; 907 908 status = "disabled"; 909 910 i2c16: i2c@880000 { 911 compatible = "qcom,geni-i2c"; 912 reg = <0 0x00880000 0 0x4000>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 916 clock-names = "se"; 917 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 918 power-domains = <&rpmhpd SC8280XP_CX>; 919 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 921 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 922 interconnect-names = "qup-core", "qup-config", "qup-memory"; 923 924 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 925 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 926 dma-names = "tx", 927 "rx"; 928 929 status = "disabled"; 930 }; 931 932 spi16: spi@880000 { 933 compatible = "qcom,geni-spi"; 934 reg = <0 0x00880000 0 0x4000>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 938 clock-names = "se"; 939 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 940 power-domains = <&rpmhpd SC8280XP_CX>; 941 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 942 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 943 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 944 interconnect-names = "qup-core", "qup-config", "qup-memory"; 945 946 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 947 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 948 dma-names = "tx", 949 "rx"; 950 951 status = "disabled"; 952 }; 953 954 i2c17: i2c@884000 { 955 compatible = "qcom,geni-i2c"; 956 reg = <0 0x00884000 0 0x4000>; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 960 clock-names = "se"; 961 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 962 power-domains = <&rpmhpd SC8280XP_CX>; 963 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 964 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 965 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 966 interconnect-names = "qup-core", "qup-config", "qup-memory"; 967 968 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 969 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 970 dma-names = "tx", 971 "rx"; 972 973 status = "disabled"; 974 }; 975 976 spi17: spi@884000 { 977 compatible = "qcom,geni-spi"; 978 reg = <0 0x00884000 0 0x4000>; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 982 clock-names = "se"; 983 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 984 power-domains = <&rpmhpd SC8280XP_CX>; 985 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 986 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 987 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 988 interconnect-names = "qup-core", "qup-config", "qup-memory"; 989 990 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 991 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 992 dma-names = "tx", 993 "rx"; 994 995 status = "disabled"; 996 }; 997 998 uart17: serial@884000 { 999 compatible = "qcom,geni-uart"; 1000 reg = <0 0x00884000 0 0x4000>; 1001 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1002 clock-names = "se"; 1003 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1004 operating-points-v2 = <&qup_opp_table_100mhz>; 1005 power-domains = <&rpmhpd SC8280XP_CX>; 1006 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1007 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1008 interconnect-names = "qup-core", "qup-config"; 1009 status = "disabled"; 1010 }; 1011 1012 i2c18: i2c@888000 { 1013 compatible = "qcom,geni-i2c"; 1014 reg = <0 0x00888000 0 0x4000>; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1018 clock-names = "se"; 1019 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1020 power-domains = <&rpmhpd SC8280XP_CX>; 1021 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1022 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1023 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1024 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1025 1026 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1027 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1028 dma-names = "tx", 1029 "rx"; 1030 1031 status = "disabled"; 1032 }; 1033 1034 spi18: spi@888000 { 1035 compatible = "qcom,geni-spi"; 1036 reg = <0 0x00888000 0 0x4000>; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1040 clock-names = "se"; 1041 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1042 power-domains = <&rpmhpd SC8280XP_CX>; 1043 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1044 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1045 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1046 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1047 1048 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1049 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1050 dma-names = "tx", 1051 "rx"; 1052 1053 status = "disabled"; 1054 }; 1055 1056 uart18: serial@888000 { 1057 compatible = "qcom,geni-uart"; 1058 reg = <0 0x00888000 0 0x4000>; 1059 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1060 clock-names = "se"; 1061 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1062 operating-points-v2 = <&qup_opp_table_100mhz>; 1063 power-domains = <&rpmhpd SC8280XP_CX>; 1064 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1065 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1066 interconnect-names = "qup-core", "qup-config"; 1067 1068 pinctrl-0 = <&qup_uart18_default>; 1069 pinctrl-names = "default"; 1070 1071 status = "disabled"; 1072 }; 1073 1074 i2c19: i2c@88c000 { 1075 compatible = "qcom,geni-i2c"; 1076 reg = <0 0x0088c000 0 0x4000>; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1080 clock-names = "se"; 1081 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1082 power-domains = <&rpmhpd SC8280XP_CX>; 1083 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1085 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1086 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1087 1088 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1089 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1090 dma-names = "tx", 1091 "rx"; 1092 1093 status = "disabled"; 1094 }; 1095 1096 spi19: spi@88c000 { 1097 compatible = "qcom,geni-spi"; 1098 reg = <0 0x0088c000 0 0x4000>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1102 clock-names = "se"; 1103 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1104 power-domains = <&rpmhpd SC8280XP_CX>; 1105 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1106 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1107 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1108 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1109 1110 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1111 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1112 dma-names = "tx", 1113 "rx"; 1114 1115 status = "disabled"; 1116 }; 1117 1118 i2c20: i2c@890000 { 1119 compatible = "qcom,geni-i2c"; 1120 reg = <0 0x00890000 0 0x4000>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1124 clock-names = "se"; 1125 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1126 power-domains = <&rpmhpd SC8280XP_CX>; 1127 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1128 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1129 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1130 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1131 1132 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1133 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1134 dma-names = "tx", 1135 "rx"; 1136 1137 status = "disabled"; 1138 }; 1139 1140 spi20: spi@890000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x00890000 0 0x4000>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1146 clock-names = "se"; 1147 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1148 power-domains = <&rpmhpd SC8280XP_CX>; 1149 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1150 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1151 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1152 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1153 1154 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1155 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1156 dma-names = "tx", 1157 "rx"; 1158 1159 status = "disabled"; 1160 }; 1161 1162 i2c21: i2c@894000 { 1163 compatible = "qcom,geni-i2c"; 1164 reg = <0 0x00894000 0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1167 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 power-domains = <&rpmhpd SC8280XP_CX>; 1171 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1172 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1173 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1174 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1175 1176 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1177 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1178 dma-names = "tx", 1179 "rx"; 1180 1181 status = "disabled"; 1182 }; 1183 1184 spi21: spi@894000 { 1185 compatible = "qcom,geni-spi"; 1186 reg = <0 0x00894000 0 0x4000>; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1190 clock-names = "se"; 1191 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1192 power-domains = <&rpmhpd SC8280XP_CX>; 1193 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1194 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1195 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1196 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1197 1198 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1199 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1200 dma-names = "tx", 1201 "rx"; 1202 1203 status = "disabled"; 1204 }; 1205 1206 i2c22: i2c@898000 { 1207 compatible = "qcom,geni-i2c"; 1208 reg = <0 0x00898000 0 0x4000>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 clock-names = "se"; 1212 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1213 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1214 power-domains = <&rpmhpd SC8280XP_CX>; 1215 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1216 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1217 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1218 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1219 1220 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1221 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1222 dma-names = "tx", 1223 "rx"; 1224 1225 status = "disabled"; 1226 }; 1227 1228 spi22: spi@898000 { 1229 compatible = "qcom,geni-spi"; 1230 reg = <0 0x00898000 0 0x4000>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1234 clock-names = "se"; 1235 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1236 power-domains = <&rpmhpd SC8280XP_CX>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1238 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1239 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1240 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1241 1242 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1243 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1244 dma-names = "tx", 1245 "rx"; 1246 1247 status = "disabled"; 1248 }; 1249 1250 i2c23: i2c@89c000 { 1251 compatible = "qcom,geni-i2c"; 1252 reg = <0 0x0089c000 0 0x4000>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 clock-names = "se"; 1256 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1257 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1258 power-domains = <&rpmhpd SC8280XP_CX>; 1259 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1260 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1261 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1262 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1263 1264 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1265 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1266 dma-names = "tx", 1267 "rx"; 1268 1269 status = "disabled"; 1270 }; 1271 1272 spi23: spi@89c000 { 1273 compatible = "qcom,geni-spi"; 1274 reg = <0 0x0089c000 0 0x4000>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1278 clock-names = "se"; 1279 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1280 power-domains = <&rpmhpd SC8280XP_CX>; 1281 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1282 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1283 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1284 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1285 1286 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1287 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1288 dma-names = "tx", 1289 "rx"; 1290 1291 status = "disabled"; 1292 }; 1293 }; 1294 1295 gpi_dma0: dma-controller@900000 { 1296 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 1297 reg = <0 0x00900000 0 0x60000>; 1298 1299 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1312 1313 dma-channels = <13>; 1314 dma-channel-mask = <0x1fff>; 1315 #dma-cells = <3>; 1316 1317 iommus = <&apps_smmu 0x576 0x0>; 1318 1319 status = "disabled"; 1320 }; 1321 1322 qup0: geniqup@9c0000 { 1323 compatible = "qcom,geni-se-qup"; 1324 reg = <0 0x009c0000 0 0x6000>; 1325 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1326 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1327 clock-names = "m-ahb", "s-ahb"; 1328 iommus = <&apps_smmu 0x563 0>; 1329 1330 #address-cells = <2>; 1331 #size-cells = <2>; 1332 ranges; 1333 1334 status = "disabled"; 1335 1336 i2c0: i2c@980000 { 1337 compatible = "qcom,geni-i2c"; 1338 reg = <0 0x00980000 0 0x4000>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 clock-names = "se"; 1342 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1343 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1344 power-domains = <&rpmhpd SC8280XP_CX>; 1345 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1346 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1347 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1348 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1349 1350 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1351 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1352 dma-names = "tx", 1353 "rx"; 1354 1355 status = "disabled"; 1356 }; 1357 1358 spi0: spi@980000 { 1359 compatible = "qcom,geni-spi"; 1360 reg = <0 0x00980000 0 0x4000>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1364 clock-names = "se"; 1365 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1366 power-domains = <&rpmhpd SC8280XP_CX>; 1367 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1368 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1369 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1370 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1371 1372 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1373 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1374 dma-names = "tx", 1375 "rx"; 1376 1377 status = "disabled"; 1378 }; 1379 1380 i2c1: i2c@984000 { 1381 compatible = "qcom,geni-i2c"; 1382 reg = <0 0x00984000 0 0x4000>; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 clock-names = "se"; 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1387 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1388 power-domains = <&rpmhpd SC8280XP_CX>; 1389 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1390 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1391 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1392 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1393 1394 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1395 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1396 dma-names = "tx", 1397 "rx"; 1398 1399 status = "disabled"; 1400 }; 1401 1402 spi1: spi@984000 { 1403 compatible = "qcom,geni-spi"; 1404 reg = <0 0x00984000 0 0x4000>; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1408 clock-names = "se"; 1409 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1410 power-domains = <&rpmhpd SC8280XP_CX>; 1411 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1412 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1413 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1414 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1415 1416 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1417 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1418 dma-names = "tx", 1419 "rx"; 1420 1421 status = "disabled"; 1422 }; 1423 1424 i2c2: i2c@988000 { 1425 compatible = "qcom,geni-i2c"; 1426 reg = <0 0x00988000 0 0x4000>; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 clock-names = "se"; 1430 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1431 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1432 power-domains = <&rpmhpd SC8280XP_CX>; 1433 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1434 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1435 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1436 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1437 1438 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1439 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1440 dma-names = "tx", 1441 "rx"; 1442 1443 status = "disabled"; 1444 }; 1445 1446 spi2: spi@988000 { 1447 compatible = "qcom,geni-spi"; 1448 reg = <0 0x00988000 0 0x4000>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1452 clock-names = "se"; 1453 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1454 power-domains = <&rpmhpd SC8280XP_CX>; 1455 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1456 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1457 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1458 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1459 1460 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1461 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1462 dma-names = "tx", 1463 "rx"; 1464 1465 status = "disabled"; 1466 }; 1467 1468 uart2: serial@988000 { 1469 compatible = "qcom,geni-uart"; 1470 reg = <0 0x00988000 0 0x4000>; 1471 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1472 clock-names = "se"; 1473 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1474 operating-points-v2 = <&qup_opp_table_100mhz>; 1475 power-domains = <&rpmhpd SC8280XP_CX>; 1476 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1477 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1478 interconnect-names = "qup-core", "qup-config"; 1479 status = "disabled"; 1480 }; 1481 1482 i2c3: i2c@98c000 { 1483 compatible = "qcom,geni-i2c"; 1484 reg = <0 0x0098c000 0 0x4000>; 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 clock-names = "se"; 1488 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1489 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1490 power-domains = <&rpmhpd SC8280XP_CX>; 1491 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1492 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1493 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1494 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1495 1496 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1497 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1498 dma-names = "tx", 1499 "rx"; 1500 1501 status = "disabled"; 1502 }; 1503 1504 spi3: spi@98c000 { 1505 compatible = "qcom,geni-spi"; 1506 reg = <0 0x0098c000 0 0x4000>; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1510 clock-names = "se"; 1511 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1512 power-domains = <&rpmhpd SC8280XP_CX>; 1513 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1514 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1515 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1516 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1517 1518 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1519 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1520 dma-names = "tx", 1521 "rx"; 1522 1523 status = "disabled"; 1524 }; 1525 1526 i2c4: i2c@990000 { 1527 compatible = "qcom,geni-i2c"; 1528 reg = <0 0x00990000 0 0x4000>; 1529 clock-names = "se"; 1530 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1531 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 power-domains = <&rpmhpd SC8280XP_CX>; 1535 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1536 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1537 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1538 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1539 1540 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1541 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1542 dma-names = "tx", 1543 "rx"; 1544 1545 status = "disabled"; 1546 }; 1547 1548 spi4: spi@990000 { 1549 compatible = "qcom,geni-spi"; 1550 reg = <0 0x00990000 0 0x4000>; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1554 clock-names = "se"; 1555 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1556 power-domains = <&rpmhpd SC8280XP_CX>; 1557 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1558 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1559 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1560 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1561 1562 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1563 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1564 dma-names = "tx", 1565 "rx"; 1566 1567 status = "disabled"; 1568 }; 1569 1570 i2c5: i2c@994000 { 1571 compatible = "qcom,geni-i2c"; 1572 reg = <0 0x00994000 0 0x4000>; 1573 #address-cells = <1>; 1574 #size-cells = <0>; 1575 clock-names = "se"; 1576 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1577 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1578 power-domains = <&rpmhpd SC8280XP_CX>; 1579 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1580 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1581 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1582 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1583 1584 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1585 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1586 dma-names = "tx", 1587 "rx"; 1588 1589 status = "disabled"; 1590 }; 1591 1592 spi5: spi@994000 { 1593 compatible = "qcom,geni-spi"; 1594 reg = <0 0x00994000 0 0x4000>; 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1598 clock-names = "se"; 1599 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1600 power-domains = <&rpmhpd SC8280XP_CX>; 1601 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1602 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1603 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1604 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1605 1606 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1607 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1608 dma-names = "tx", 1609 "rx"; 1610 1611 status = "disabled"; 1612 }; 1613 1614 i2c6: i2c@998000 { 1615 compatible = "qcom,geni-i2c"; 1616 reg = <0 0x00998000 0 0x4000>; 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1621 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1622 power-domains = <&rpmhpd SC8280XP_CX>; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1624 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1625 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1626 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1627 1628 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1629 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1630 dma-names = "tx", 1631 "rx"; 1632 1633 status = "disabled"; 1634 }; 1635 1636 spi6: spi@998000 { 1637 compatible = "qcom,geni-spi"; 1638 reg = <0 0x00998000 0 0x4000>; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1642 clock-names = "se"; 1643 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1644 power-domains = <&rpmhpd SC8280XP_CX>; 1645 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1646 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1647 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1648 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1649 1650 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1651 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1652 dma-names = "tx", 1653 "rx"; 1654 1655 status = "disabled"; 1656 }; 1657 1658 i2c7: i2c@99c000 { 1659 compatible = "qcom,geni-i2c"; 1660 reg = <0 0x0099c000 0 0x4000>; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 clock-names = "se"; 1664 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1665 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1666 power-domains = <&rpmhpd SC8280XP_CX>; 1667 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1668 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1669 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1670 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1671 1672 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1673 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1674 dma-names = "tx", 1675 "rx"; 1676 1677 status = "disabled"; 1678 }; 1679 1680 spi7: spi@99c000 { 1681 compatible = "qcom,geni-spi"; 1682 reg = <0 0x0099c000 0 0x4000>; 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1686 clock-names = "se"; 1687 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1688 power-domains = <&rpmhpd SC8280XP_CX>; 1689 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1690 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1691 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1692 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1693 1694 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1695 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1696 dma-names = "tx", 1697 "rx"; 1698 1699 status = "disabled"; 1700 }; 1701 }; 1702 1703 gpi_dma1: dma-controller@a00000 { 1704 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 1705 reg = <0 0x00a00000 0 0x60000>; 1706 1707 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1719 1720 dma-channels = <12>; 1721 dma-channel-mask = <0xfff>; 1722 #dma-cells = <3>; 1723 1724 iommus = <&apps_smmu 0x96 0x0>; 1725 1726 status = "disabled"; 1727 }; 1728 1729 qup1: geniqup@ac0000 { 1730 compatible = "qcom,geni-se-qup"; 1731 reg = <0 0x00ac0000 0 0x6000>; 1732 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1733 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1734 clock-names = "m-ahb", "s-ahb"; 1735 iommus = <&apps_smmu 0x83 0>; 1736 1737 #address-cells = <2>; 1738 #size-cells = <2>; 1739 ranges; 1740 1741 status = "disabled"; 1742 1743 i2c8: i2c@a80000 { 1744 compatible = "qcom,geni-i2c"; 1745 reg = <0 0x00a80000 0 0x4000>; 1746 #address-cells = <1>; 1747 #size-cells = <0>; 1748 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1749 clock-names = "se"; 1750 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1751 power-domains = <&rpmhpd SC8280XP_CX>; 1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1753 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1754 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1755 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1756 1757 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1758 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1759 dma-names = "tx", 1760 "rx"; 1761 1762 status = "disabled"; 1763 }; 1764 1765 spi8: spi@a80000 { 1766 compatible = "qcom,geni-spi"; 1767 reg = <0 0x00a80000 0 0x4000>; 1768 #address-cells = <1>; 1769 #size-cells = <0>; 1770 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1771 clock-names = "se"; 1772 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1773 power-domains = <&rpmhpd SC8280XP_CX>; 1774 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1775 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1776 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1777 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1778 1779 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1780 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1781 dma-names = "tx", 1782 "rx"; 1783 1784 status = "disabled"; 1785 }; 1786 1787 i2c9: i2c@a84000 { 1788 compatible = "qcom,geni-i2c"; 1789 reg = <0 0x00a84000 0 0x4000>; 1790 #address-cells = <1>; 1791 #size-cells = <0>; 1792 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1793 clock-names = "se"; 1794 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1795 power-domains = <&rpmhpd SC8280XP_CX>; 1796 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1797 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1798 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1799 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1800 1801 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1802 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1803 dma-names = "tx", 1804 "rx"; 1805 1806 status = "disabled"; 1807 }; 1808 1809 spi9: spi@a84000 { 1810 compatible = "qcom,geni-spi"; 1811 reg = <0 0x00a84000 0 0x4000>; 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1815 clock-names = "se"; 1816 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1817 power-domains = <&rpmhpd SC8280XP_CX>; 1818 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1819 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1820 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1821 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1822 1823 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1824 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1825 dma-names = "tx", 1826 "rx"; 1827 1828 status = "disabled"; 1829 }; 1830 1831 i2c10: i2c@a88000 { 1832 compatible = "qcom,geni-i2c"; 1833 reg = <0 0x00a88000 0 0x4000>; 1834 #address-cells = <1>; 1835 #size-cells = <0>; 1836 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1837 clock-names = "se"; 1838 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1839 power-domains = <&rpmhpd SC8280XP_CX>; 1840 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1841 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1842 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1843 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1844 1845 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1846 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1847 dma-names = "tx", 1848 "rx"; 1849 1850 status = "disabled"; 1851 }; 1852 1853 spi10: spi@a88000 { 1854 compatible = "qcom,geni-spi"; 1855 reg = <0 0x00a88000 0 0x4000>; 1856 #address-cells = <1>; 1857 #size-cells = <0>; 1858 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1859 clock-names = "se"; 1860 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1861 power-domains = <&rpmhpd SC8280XP_CX>; 1862 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1863 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1864 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1865 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1866 1867 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1868 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1869 dma-names = "tx", 1870 "rx"; 1871 1872 status = "disabled"; 1873 }; 1874 1875 i2c11: i2c@a8c000 { 1876 compatible = "qcom,geni-i2c"; 1877 reg = <0 0x00a8c000 0 0x4000>; 1878 #address-cells = <1>; 1879 #size-cells = <0>; 1880 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1881 clock-names = "se"; 1882 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1883 power-domains = <&rpmhpd SC8280XP_CX>; 1884 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1885 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1886 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1887 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1888 1889 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1890 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1891 dma-names = "tx", 1892 "rx"; 1893 1894 status = "disabled"; 1895 }; 1896 1897 spi11: spi@a8c000 { 1898 compatible = "qcom,geni-spi"; 1899 reg = <0 0x00a8c000 0 0x4000>; 1900 #address-cells = <1>; 1901 #size-cells = <0>; 1902 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1903 clock-names = "se"; 1904 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1905 power-domains = <&rpmhpd SC8280XP_CX>; 1906 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1907 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1908 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1909 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1910 1911 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1912 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1913 dma-names = "tx", 1914 "rx"; 1915 1916 status = "disabled"; 1917 }; 1918 1919 i2c12: i2c@a90000 { 1920 compatible = "qcom,geni-i2c"; 1921 reg = <0 0x00a90000 0 0x4000>; 1922 #address-cells = <1>; 1923 #size-cells = <0>; 1924 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1925 clock-names = "se"; 1926 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1927 power-domains = <&rpmhpd SC8280XP_CX>; 1928 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1929 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1930 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1931 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1932 1933 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1934 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1935 dma-names = "tx", 1936 "rx"; 1937 1938 status = "disabled"; 1939 }; 1940 1941 spi12: spi@a90000 { 1942 compatible = "qcom,geni-spi"; 1943 reg = <0 0x00a90000 0 0x4000>; 1944 #address-cells = <1>; 1945 #size-cells = <0>; 1946 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1947 clock-names = "se"; 1948 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1949 power-domains = <&rpmhpd SC8280XP_CX>; 1950 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1952 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1953 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1954 1955 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1956 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1957 dma-names = "tx", 1958 "rx"; 1959 1960 status = "disabled"; 1961 }; 1962 1963 i2c13: i2c@a94000 { 1964 compatible = "qcom,geni-i2c"; 1965 reg = <0 0x00a94000 0 0x4000>; 1966 #address-cells = <1>; 1967 #size-cells = <0>; 1968 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1969 clock-names = "se"; 1970 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1971 power-domains = <&rpmhpd SC8280XP_CX>; 1972 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1974 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1975 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1976 1977 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1978 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1979 dma-names = "tx", 1980 "rx"; 1981 1982 status = "disabled"; 1983 }; 1984 1985 spi13: spi@a94000 { 1986 compatible = "qcom,geni-spi"; 1987 reg = <0 0x00a94000 0 0x4000>; 1988 #address-cells = <1>; 1989 #size-cells = <0>; 1990 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1991 clock-names = "se"; 1992 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1993 power-domains = <&rpmhpd SC8280XP_CX>; 1994 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1995 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1996 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1997 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1998 1999 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2000 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2001 dma-names = "tx", 2002 "rx"; 2003 2004 status = "disabled"; 2005 }; 2006 2007 i2c14: i2c@a98000 { 2008 compatible = "qcom,geni-i2c"; 2009 reg = <0 0x00a98000 0 0x4000>; 2010 #address-cells = <1>; 2011 #size-cells = <0>; 2012 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2013 clock-names = "se"; 2014 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2015 power-domains = <&rpmhpd SC8280XP_CX>; 2016 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2017 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2018 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2019 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2020 2021 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2022 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2023 dma-names = "tx", 2024 "rx"; 2025 2026 status = "disabled"; 2027 }; 2028 2029 spi14: spi@a98000 { 2030 compatible = "qcom,geni-spi"; 2031 reg = <0 0x00a98000 0 0x4000>; 2032 #address-cells = <1>; 2033 #size-cells = <0>; 2034 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2035 clock-names = "se"; 2036 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2037 power-domains = <&rpmhpd SC8280XP_CX>; 2038 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2039 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2040 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2041 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2042 2043 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2044 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2045 dma-names = "tx", 2046 "rx"; 2047 2048 status = "disabled"; 2049 }; 2050 2051 i2c15: i2c@a9c000 { 2052 compatible = "qcom,geni-i2c"; 2053 reg = <0 0x00a9c000 0 0x4000>; 2054 #address-cells = <1>; 2055 #size-cells = <0>; 2056 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2057 clock-names = "se"; 2058 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2059 power-domains = <&rpmhpd SC8280XP_CX>; 2060 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2061 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2062 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2063 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2064 2065 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2066 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2067 dma-names = "tx", 2068 "rx"; 2069 2070 status = "disabled"; 2071 }; 2072 2073 spi15: spi@a9c000 { 2074 compatible = "qcom,geni-spi"; 2075 reg = <0 0x00a9c000 0 0x4000>; 2076 #address-cells = <1>; 2077 #size-cells = <0>; 2078 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2079 clock-names = "se"; 2080 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2081 power-domains = <&rpmhpd SC8280XP_CX>; 2082 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2083 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2084 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2085 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2086 2087 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2088 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2089 dma-names = "tx", 2090 "rx"; 2091 2092 status = "disabled"; 2093 }; 2094 }; 2095 2096 rng: rng@10d3000 { 2097 compatible = "qcom,prng-ee"; 2098 reg = <0 0x010d3000 0 0x1000>; 2099 clocks = <&rpmhcc RPMH_HWKM_CLK>; 2100 clock-names = "core"; 2101 }; 2102 2103 config_noc: interconnect@1500000 { 2104 compatible = "qcom,sc8280xp-config-noc"; 2105 reg = <0 0x01500000 0 0x2c000>; 2106 2107 #interconnect-cells = <2>; 2108 qcom,bcm-voters = <&apps_bcm_voter>; 2109 }; 2110 2111 system_noc: interconnect@1680000 { 2112 compatible = "qcom,sc8280xp-system-noc"; 2113 reg = <0 0x01680000 0 0x1a400>; 2114 2115 #interconnect-cells = <2>; 2116 qcom,bcm-voters = <&apps_bcm_voter>; 2117 }; 2118 2119 aggre1_noc: interconnect@16c0000 { 2120 compatible = "qcom,sc8280xp-aggre1-noc"; 2121 reg = <0 0x016c0000 0 0x3af80>; 2122 2123 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2124 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2125 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2126 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 2127 <&gcc GCC_AGGRE_USB4_AXI_CLK>, 2128 <&gcc GCC_AGGRE_USB4_1_AXI_CLK>, 2129 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 2130 <&rpmhcc RPMH_IPA_CLK>; 2131 2132 #interconnect-cells = <2>; 2133 qcom,bcm-voters = <&apps_bcm_voter>; 2134 }; 2135 2136 aggre2_noc: interconnect@1700000 { 2137 compatible = "qcom,sc8280xp-aggre2-noc"; 2138 reg = <0 0x01700000 0 0x3af80>; 2139 2140 clocks = <&gcc GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK>, 2141 <&gcc GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK>, 2142 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2143 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 2144 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2145 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2146 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2147 2148 #interconnect-cells = <2>; 2149 qcom,bcm-voters = <&apps_bcm_voter>; 2150 }; 2151 2152 mmss_noc: interconnect@1740000 { 2153 compatible = "qcom,sc8280xp-mmss-noc"; 2154 reg = <0 0x01740000 0 0x1fa80>; 2155 2156 #interconnect-cells = <2>; 2157 qcom,bcm-voters = <&apps_bcm_voter>; 2158 }; 2159 2160 pcie4: pcie@1c00000 { 2161 device_type = "pci"; 2162 compatible = "qcom,pcie-sc8280xp"; 2163 reg = <0x0 0x01c00000 0x0 0x3000>, 2164 <0x0 0x30000000 0x0 0xf1d>, 2165 <0x0 0x30000f20 0x0 0xa8>, 2166 <0x0 0x30001000 0x0 0x1000>, 2167 <0x0 0x30100000 0x0 0x100000>, 2168 <0x0 0x01c03000 0x0 0x1000>; 2169 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2170 #address-cells = <3>; 2171 #size-cells = <2>; 2172 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 2173 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 2174 bus-range = <0x00 0xff>; 2175 2176 dma-coherent; 2177 2178 linux,pci-domain = <6>; 2179 num-lanes = <1>; 2180 2181 msi-map = <0x0 &its 0xe0000 0x10000>; 2182 2183 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 2187 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2188 2189 #interrupt-cells = <1>; 2190 interrupt-map-mask = <0 0 0 0x7>; 2191 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2192 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2193 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2194 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2195 2196 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2197 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2198 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2199 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2200 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2201 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2202 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2203 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 2204 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 2205 clock-names = "aux", 2206 "cfg", 2207 "bus_master", 2208 "bus_slave", 2209 "slave_q2a", 2210 "ddrss_sf_tbu", 2211 "noc_aggr_4", 2212 "noc_aggr_south_sf", 2213 "cnoc_qx"; 2214 2215 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2216 assigned-clock-rates = <19200000>; 2217 2218 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 2219 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 2220 interconnect-names = "pcie-mem", "cpu-pcie"; 2221 2222 resets = <&gcc GCC_PCIE_4_BCR>; 2223 reset-names = "pci"; 2224 2225 power-domains = <&gcc PCIE_4_GDSC>; 2226 required-opps = <&rpmhpd_opp_nom>; 2227 2228 status = "disabled"; 2229 2230 pcie4_port0: pcie@0 { 2231 device_type = "pci"; 2232 reg = <0x0 0x0 0x0 0x0 0x0>; 2233 bus-range = <0x01 0xff>; 2234 2235 phys = <&pcie4_phy>; 2236 2237 #address-cells = <3>; 2238 #size-cells = <2>; 2239 ranges; 2240 }; 2241 }; 2242 2243 pcie4_phy: phy@1c06000 { 2244 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 2245 reg = <0x0 0x01c06000 0x0 0x2000>; 2246 2247 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2248 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2249 <&gcc GCC_PCIE_4_CLKREF_CLK>, 2250 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 2251 <&gcc GCC_PCIE_4_PIPE_CLK>, 2252 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 2253 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2254 "pipe", "pipediv2"; 2255 2256 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 2257 assigned-clock-rates = <100000000>; 2258 2259 power-domains = <&gcc PCIE_4_GDSC>; 2260 2261 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 2262 reset-names = "phy"; 2263 2264 #clock-cells = <0>; 2265 clock-output-names = "pcie_4_pipe_clk"; 2266 2267 #phy-cells = <0>; 2268 2269 status = "disabled"; 2270 }; 2271 2272 pcie3b: pcie@1c08000 { 2273 device_type = "pci"; 2274 compatible = "qcom,pcie-sc8280xp"; 2275 reg = <0x0 0x01c08000 0x0 0x3000>, 2276 <0x0 0x32000000 0x0 0xf1d>, 2277 <0x0 0x32000f20 0x0 0xa8>, 2278 <0x0 0x32001000 0x0 0x1000>, 2279 <0x0 0x32100000 0x0 0x100000>, 2280 <0x0 0x01c0b000 0x0 0x1000>; 2281 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2282 #address-cells = <3>; 2283 #size-cells = <2>; 2284 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 2285 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 2286 bus-range = <0x00 0xff>; 2287 2288 dma-coherent; 2289 2290 linux,pci-domain = <5>; 2291 num-lanes = <2>; 2292 2293 msi-map = <0x0 &its 0xd0000 0x10000>; 2294 2295 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2296 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2297 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2298 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2299 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2300 2301 #interrupt-cells = <1>; 2302 interrupt-map-mask = <0 0 0 0x7>; 2303 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 2304 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2305 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 2306 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 2307 2308 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 2309 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 2310 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 2311 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 2312 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 2313 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2314 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2315 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2316 clock-names = "aux", 2317 "cfg", 2318 "bus_master", 2319 "bus_slave", 2320 "slave_q2a", 2321 "ddrss_sf_tbu", 2322 "noc_aggr_4", 2323 "noc_aggr_south_sf"; 2324 2325 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 2326 assigned-clock-rates = <19200000>; 2327 2328 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 2329 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 2330 interconnect-names = "pcie-mem", "cpu-pcie"; 2331 2332 resets = <&gcc GCC_PCIE_3B_BCR>; 2333 reset-names = "pci"; 2334 2335 power-domains = <&gcc PCIE_3B_GDSC>; 2336 required-opps = <&rpmhpd_opp_nom>; 2337 2338 status = "disabled"; 2339 2340 pcie3b_port0: pcie@0 { 2341 device_type = "pci"; 2342 reg = <0x0 0x0 0x0 0x0 0x0>; 2343 bus-range = <0x01 0xff>; 2344 2345 phys = <&pcie3b_phy>; 2346 2347 #address-cells = <3>; 2348 #size-cells = <2>; 2349 ranges; 2350 }; 2351 }; 2352 2353 pcie3b_phy: phy@1c0e000 { 2354 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2355 reg = <0x0 0x01c0e000 0x0 0x2000>; 2356 2357 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 2358 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 2359 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2360 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 2361 <&gcc GCC_PCIE_3B_PIPE_CLK>, 2362 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 2363 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2364 "pipe", "pipediv2"; 2365 2366 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 2367 assigned-clock-rates = <100000000>; 2368 2369 power-domains = <&gcc PCIE_3B_GDSC>; 2370 2371 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 2372 reset-names = "phy"; 2373 2374 #clock-cells = <0>; 2375 clock-output-names = "pcie_3b_pipe_clk"; 2376 2377 #phy-cells = <0>; 2378 2379 status = "disabled"; 2380 }; 2381 2382 pcie3a: pcie@1c10000 { 2383 device_type = "pci"; 2384 compatible = "qcom,pcie-sc8280xp"; 2385 reg = <0x0 0x01c10000 0x0 0x3000>, 2386 <0x0 0x34000000 0x0 0xf1d>, 2387 <0x0 0x34000f20 0x0 0xa8>, 2388 <0x0 0x34001000 0x0 0x1000>, 2389 <0x0 0x34100000 0x0 0x100000>, 2390 <0x0 0x01c13000 0x0 0x1000>; 2391 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2392 #address-cells = <3>; 2393 #size-cells = <2>; 2394 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 2395 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 2396 bus-range = <0x00 0xff>; 2397 2398 dma-coherent; 2399 2400 linux,pci-domain = <4>; 2401 num-lanes = <4>; 2402 2403 msi-map = <0x0 &its 0xc0000 0x10000>; 2404 2405 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2406 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2407 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2408 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2409 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2410 2411 #interrupt-cells = <1>; 2412 interrupt-map-mask = <0 0 0 0x7>; 2413 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 2414 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 2415 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 2416 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 2417 2418 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2419 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2420 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 2421 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 2422 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 2423 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2424 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2425 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2426 clock-names = "aux", 2427 "cfg", 2428 "bus_master", 2429 "bus_slave", 2430 "slave_q2a", 2431 "ddrss_sf_tbu", 2432 "noc_aggr_4", 2433 "noc_aggr_south_sf"; 2434 2435 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 2436 assigned-clock-rates = <19200000>; 2437 2438 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 2439 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 2440 interconnect-names = "pcie-mem", "cpu-pcie"; 2441 2442 resets = <&gcc GCC_PCIE_3A_BCR>; 2443 reset-names = "pci"; 2444 2445 power-domains = <&gcc PCIE_3A_GDSC>; 2446 required-opps = <&rpmhpd_opp_nom>; 2447 2448 status = "disabled"; 2449 2450 pcie3a_port0: pcie@0 { 2451 device_type = "pci"; 2452 reg = <0x0 0x0 0x0 0x0 0x0>; 2453 bus-range = <0x01 0xff>; 2454 2455 phys = <&pcie3a_phy>; 2456 2457 #address-cells = <3>; 2458 #size-cells = <2>; 2459 ranges; 2460 }; 2461 }; 2462 2463 pcie3a_phy: phy@1c14000 { 2464 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2465 reg = <0x0 0x01c14000 0x0 0x2000>, 2466 <0x0 0x01c16000 0x0 0x2000>; 2467 2468 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2469 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2470 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2471 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 2472 <&gcc GCC_PCIE_3A_PIPE_CLK>, 2473 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 2474 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2475 "pipe", "pipediv2"; 2476 2477 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 2478 assigned-clock-rates = <100000000>; 2479 2480 power-domains = <&gcc PCIE_3A_GDSC>; 2481 2482 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 2483 reset-names = "phy"; 2484 2485 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2486 2487 #clock-cells = <0>; 2488 clock-output-names = "pcie_3a_pipe_clk"; 2489 2490 #phy-cells = <0>; 2491 2492 status = "disabled"; 2493 }; 2494 2495 pcie2b: pcie@1c18000 { 2496 device_type = "pci"; 2497 compatible = "qcom,pcie-sc8280xp"; 2498 reg = <0x0 0x01c18000 0x0 0x3000>, 2499 <0x0 0x38000000 0x0 0xf1d>, 2500 <0x0 0x38000f20 0x0 0xa8>, 2501 <0x0 0x38001000 0x0 0x1000>, 2502 <0x0 0x38100000 0x0 0x100000>, 2503 <0x0 0x01c1b000 0x0 0x1000>; 2504 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2505 #address-cells = <3>; 2506 #size-cells = <2>; 2507 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2508 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2509 bus-range = <0x00 0xff>; 2510 2511 dma-coherent; 2512 2513 linux,pci-domain = <3>; 2514 num-lanes = <2>; 2515 2516 msi-map = <0x0 &its 0xb0000 0x10000>; 2517 2518 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2520 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2522 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2523 2524 #interrupt-cells = <1>; 2525 interrupt-map-mask = <0 0 0 0x7>; 2526 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2527 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2528 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2529 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2530 2531 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2532 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2533 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2534 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2535 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2536 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2537 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2538 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2539 clock-names = "aux", 2540 "cfg", 2541 "bus_master", 2542 "bus_slave", 2543 "slave_q2a", 2544 "ddrss_sf_tbu", 2545 "noc_aggr_4", 2546 "noc_aggr_south_sf"; 2547 2548 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2549 assigned-clock-rates = <19200000>; 2550 2551 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2552 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2553 interconnect-names = "pcie-mem", "cpu-pcie"; 2554 2555 resets = <&gcc GCC_PCIE_2B_BCR>; 2556 reset-names = "pci"; 2557 2558 power-domains = <&gcc PCIE_2B_GDSC>; 2559 required-opps = <&rpmhpd_opp_nom>; 2560 2561 status = "disabled"; 2562 2563 pcie2b_port0: pcie@0 { 2564 device_type = "pci"; 2565 reg = <0x0 0x0 0x0 0x0 0x0>; 2566 bus-range = <0x01 0xff>; 2567 2568 phys = <&pcie2b_phy>; 2569 2570 #address-cells = <3>; 2571 #size-cells = <2>; 2572 ranges; 2573 }; 2574 }; 2575 2576 pcie2b_phy: phy@1c1e000 { 2577 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2578 reg = <0x0 0x01c1e000 0x0 0x2000>; 2579 2580 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2581 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2582 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2583 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2584 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2585 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2586 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2587 "pipe", "pipediv2"; 2588 2589 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2590 assigned-clock-rates = <100000000>; 2591 2592 power-domains = <&gcc PCIE_2B_GDSC>; 2593 2594 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2595 reset-names = "phy"; 2596 2597 #clock-cells = <0>; 2598 clock-output-names = "pcie_2b_pipe_clk"; 2599 2600 #phy-cells = <0>; 2601 2602 status = "disabled"; 2603 }; 2604 2605 pcie2a: pcie@1c20000 { 2606 device_type = "pci"; 2607 compatible = "qcom,pcie-sc8280xp"; 2608 reg = <0x0 0x01c20000 0x0 0x3000>, 2609 <0x0 0x3c000000 0x0 0xf1d>, 2610 <0x0 0x3c000f20 0x0 0xa8>, 2611 <0x0 0x3c001000 0x0 0x1000>, 2612 <0x0 0x3c100000 0x0 0x100000>, 2613 <0x0 0x01c23000 0x0 0x1000>; 2614 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2615 #address-cells = <3>; 2616 #size-cells = <2>; 2617 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2618 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2619 bus-range = <0x00 0xff>; 2620 2621 dma-coherent; 2622 2623 linux,pci-domain = <2>; 2624 num-lanes = <4>; 2625 2626 msi-map = <0x0 &its 0xa0000 0x10000>; 2627 2628 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2629 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2630 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2631 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2632 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2633 2634 #interrupt-cells = <1>; 2635 interrupt-map-mask = <0 0 0 0x7>; 2636 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2637 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2638 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2639 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2640 2641 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2642 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2643 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2644 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2645 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2646 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2647 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2648 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2649 clock-names = "aux", 2650 "cfg", 2651 "bus_master", 2652 "bus_slave", 2653 "slave_q2a", 2654 "ddrss_sf_tbu", 2655 "noc_aggr_4", 2656 "noc_aggr_south_sf"; 2657 2658 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2659 assigned-clock-rates = <19200000>; 2660 2661 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2662 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2663 interconnect-names = "pcie-mem", "cpu-pcie"; 2664 2665 resets = <&gcc GCC_PCIE_2A_BCR>; 2666 reset-names = "pci"; 2667 2668 power-domains = <&gcc PCIE_2A_GDSC>; 2669 required-opps = <&rpmhpd_opp_nom>; 2670 2671 status = "disabled"; 2672 2673 pcie2a_port0: pcie@0 { 2674 device_type = "pci"; 2675 reg = <0x0 0x0 0x0 0x0 0x0>; 2676 bus-range = <0x01 0xff>; 2677 2678 phys = <&pcie2a_phy>; 2679 2680 #address-cells = <3>; 2681 #size-cells = <2>; 2682 ranges; 2683 }; 2684 }; 2685 2686 pcie2a_phy: phy@1c24000 { 2687 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2688 reg = <0x0 0x01c24000 0x0 0x2000>, 2689 <0x0 0x01c26000 0x0 0x2000>; 2690 2691 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2692 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2693 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2694 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2695 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2696 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2697 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2698 "pipe", "pipediv2"; 2699 2700 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2701 assigned-clock-rates = <100000000>; 2702 2703 power-domains = <&gcc PCIE_2A_GDSC>; 2704 2705 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2706 reset-names = "phy"; 2707 2708 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2709 2710 #clock-cells = <0>; 2711 clock-output-names = "pcie_2a_pipe_clk"; 2712 2713 #phy-cells = <0>; 2714 2715 status = "disabled"; 2716 }; 2717 2718 ufs_mem_hc: ufshc@1d84000 { 2719 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2720 "jedec,ufs-2.0"; 2721 reg = <0 0x01d84000 0 0x3000>; 2722 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2723 phys = <&ufs_mem_phy>; 2724 phy-names = "ufsphy"; 2725 lanes-per-direction = <2>; 2726 #reset-cells = <1>; 2727 resets = <&gcc GCC_UFS_PHY_BCR>; 2728 reset-names = "rst"; 2729 2730 power-domains = <&gcc UFS_PHY_GDSC>; 2731 required-opps = <&rpmhpd_opp_nom>; 2732 2733 iommus = <&apps_smmu 0xe0 0x0>; 2734 dma-coherent; 2735 2736 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2737 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2738 <&gcc GCC_UFS_PHY_AHB_CLK>, 2739 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2740 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2741 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2742 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2743 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2744 clock-names = "core_clk", 2745 "bus_aggr_clk", 2746 "iface_clk", 2747 "core_clk_unipro", 2748 "ref_clk", 2749 "tx_lane0_sync_clk", 2750 "rx_lane0_sync_clk", 2751 "rx_lane1_sync_clk"; 2752 freq-table-hz = <75000000 300000000>, 2753 <0 0>, 2754 <0 0>, 2755 <75000000 300000000>, 2756 <0 0>, 2757 <0 0>, 2758 <0 0>, 2759 <0 0>; 2760 status = "disabled"; 2761 }; 2762 2763 ufs_mem_phy: phy@1d87000 { 2764 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2765 reg = <0 0x01d87000 0 0x1000>; 2766 2767 clocks = <&rpmhcc RPMH_CXO_CLK>, 2768 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2769 <&gcc GCC_UFS_CARD_CLKREF_CLK>; 2770 clock-names = "ref", 2771 "ref_aux", 2772 "qref"; 2773 2774 power-domains = <&gcc UFS_PHY_GDSC>; 2775 2776 resets = <&ufs_mem_hc 0>; 2777 reset-names = "ufsphy"; 2778 2779 #phy-cells = <0>; 2780 2781 status = "disabled"; 2782 }; 2783 2784 ufs_card_hc: ufshc@1da4000 { 2785 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2786 "jedec,ufs-2.0"; 2787 reg = <0 0x01da4000 0 0x3000>; 2788 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2789 phys = <&ufs_card_phy>; 2790 phy-names = "ufsphy"; 2791 lanes-per-direction = <2>; 2792 #reset-cells = <1>; 2793 resets = <&gcc GCC_UFS_CARD_BCR>; 2794 reset-names = "rst"; 2795 2796 power-domains = <&gcc UFS_CARD_GDSC>; 2797 2798 iommus = <&apps_smmu 0x4a0 0x0>; 2799 dma-coherent; 2800 2801 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2802 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2803 <&gcc GCC_UFS_CARD_AHB_CLK>, 2804 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2805 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2806 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2807 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2808 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2809 clock-names = "core_clk", 2810 "bus_aggr_clk", 2811 "iface_clk", 2812 "core_clk_unipro", 2813 "ref_clk", 2814 "tx_lane0_sync_clk", 2815 "rx_lane0_sync_clk", 2816 "rx_lane1_sync_clk"; 2817 freq-table-hz = <75000000 300000000>, 2818 <0 0>, 2819 <0 0>, 2820 <75000000 300000000>, 2821 <0 0>, 2822 <0 0>, 2823 <0 0>, 2824 <0 0>; 2825 status = "disabled"; 2826 }; 2827 2828 ufs_card_phy: phy@1da7000 { 2829 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2830 reg = <0 0x01da7000 0 0x1000>; 2831 2832 clocks = <&rpmhcc RPMH_CXO_CLK>, 2833 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, 2834 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; 2835 clock-names = "ref", 2836 "ref_aux", 2837 "qref"; 2838 2839 power-domains = <&gcc UFS_CARD_GDSC>; 2840 2841 resets = <&ufs_card_hc 0>; 2842 reset-names = "ufsphy"; 2843 2844 #phy-cells = <0>; 2845 2846 status = "disabled"; 2847 }; 2848 2849 tcsr_mutex: hwlock@1f40000 { 2850 compatible = "qcom,tcsr-mutex"; 2851 reg = <0x0 0x01f40000 0x0 0x20000>; 2852 #hwlock-cells = <1>; 2853 }; 2854 2855 tcsr: syscon@1fc0000 { 2856 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2857 reg = <0x0 0x01fc0000 0x0 0x30000>; 2858 }; 2859 2860 remoteproc_slpi: remoteproc@2400000 { 2861 compatible = "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas"; 2862 reg = <0 0x02400000 0 0x10000>; 2863 2864 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2865 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2866 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2867 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2868 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2869 interrupt-names = "wdog", 2870 "fatal", 2871 "ready", 2872 "handover", 2873 "stop-ack"; 2874 2875 clocks = <&rpmhcc RPMH_CXO_CLK>; 2876 clock-names = "xo"; 2877 2878 power-domains = <&rpmhpd SC8280XP_LCX>, 2879 <&rpmhpd SC8280XP_LMX>; 2880 power-domain-names = "lcx", "lmx"; 2881 2882 memory-region = <&pil_slpi_mem>; 2883 2884 qcom,qmp = <&aoss_qmp>; 2885 2886 qcom,smem-states = <&smp2p_slpi_out 0>; 2887 qcom,smem-state-names = "stop"; 2888 2889 status = "disabled"; 2890 2891 glink-edge { 2892 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2893 IPCC_MPROC_SIGNAL_GLINK_QMP 2894 IRQ_TYPE_EDGE_RISING>; 2895 mboxes = <&ipcc IPCC_CLIENT_SLPI 2896 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2897 2898 label = "slpi"; 2899 qcom,remote-pid = <3>; 2900 2901 fastrpc { 2902 compatible = "qcom,fastrpc"; 2903 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2904 label = "sdsp"; 2905 qcom,non-secure-domain; 2906 #address-cells = <1>; 2907 #size-cells = <0>; 2908 2909 compute-cb@1 { 2910 compatible = "qcom,fastrpc-compute-cb"; 2911 reg = <1>; 2912 iommus = <&apps_smmu 0x0521 0x0>; 2913 }; 2914 2915 compute-cb@2 { 2916 compatible = "qcom,fastrpc-compute-cb"; 2917 reg = <2>; 2918 iommus = <&apps_smmu 0x0522 0x0>; 2919 }; 2920 2921 compute-cb@3 { 2922 compatible = "qcom,fastrpc-compute-cb"; 2923 reg = <3>; 2924 iommus = <&apps_smmu 0x0523 0x0>; 2925 }; 2926 }; 2927 }; 2928 }; 2929 2930 remoteproc_adsp: remoteproc@3000000 { 2931 compatible = "qcom,sc8280xp-adsp-pas"; 2932 reg = <0 0x03000000 0 0x10000>; 2933 2934 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2935 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2936 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2937 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2938 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2939 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2940 interrupt-names = "wdog", "fatal", "ready", 2941 "handover", "stop-ack", "shutdown-ack"; 2942 2943 clocks = <&rpmhcc RPMH_CXO_CLK>; 2944 clock-names = "xo"; 2945 2946 power-domains = <&rpmhpd SC8280XP_LCX>, 2947 <&rpmhpd SC8280XP_LMX>; 2948 power-domain-names = "lcx", "lmx"; 2949 2950 memory-region = <&pil_adsp_mem>; 2951 2952 qcom,qmp = <&aoss_qmp>; 2953 2954 qcom,smem-states = <&smp2p_adsp_out 0>; 2955 qcom,smem-state-names = "stop"; 2956 2957 status = "disabled"; 2958 2959 glink-edge { 2960 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2961 IPCC_MPROC_SIGNAL_GLINK_QMP 2962 IRQ_TYPE_EDGE_RISING>; 2963 mboxes = <&ipcc IPCC_CLIENT_LPASS 2964 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2965 2966 label = "lpass"; 2967 qcom,remote-pid = <2>; 2968 2969 fastrpc { 2970 compatible = "qcom,fastrpc"; 2971 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2972 label = "adsp"; 2973 qcom,non-secure-domain; 2974 #address-cells = <1>; 2975 #size-cells = <0>; 2976 2977 compute-cb@3 { 2978 compatible = "qcom,fastrpc-compute-cb"; 2979 reg = <3>; 2980 iommus = <&apps_smmu 0x0c03 0x0>; 2981 }; 2982 2983 compute-cb@4 { 2984 compatible = "qcom,fastrpc-compute-cb"; 2985 reg = <4>; 2986 iommus = <&apps_smmu 0x0c04 0x0>; 2987 }; 2988 2989 compute-cb@5 { 2990 compatible = "qcom,fastrpc-compute-cb"; 2991 reg = <5>; 2992 iommus = <&apps_smmu 0x0c05 0x0>; 2993 }; 2994 }; 2995 2996 gpr { 2997 compatible = "qcom,gpr"; 2998 qcom,glink-channels = "adsp_apps"; 2999 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 3000 qcom,intents = <512 20>; 3001 #address-cells = <1>; 3002 #size-cells = <0>; 3003 3004 q6apm: service@1 { 3005 compatible = "qcom,q6apm"; 3006 reg = <GPR_APM_MODULE_IID>; 3007 #sound-dai-cells = <0>; 3008 qcom,protection-domain = "avs/audio", 3009 "msm/adsp/audio_pd"; 3010 q6apmdai: dais { 3011 compatible = "qcom,q6apm-dais"; 3012 iommus = <&apps_smmu 0x0c01 0x0>; 3013 }; 3014 3015 q6apmbedai: bedais { 3016 compatible = "qcom,q6apm-lpass-dais"; 3017 #sound-dai-cells = <1>; 3018 }; 3019 }; 3020 3021 q6prm: service@2 { 3022 compatible = "qcom,q6prm"; 3023 reg = <GPR_PRM_MODULE_IID>; 3024 qcom,protection-domain = "avs/audio", 3025 "msm/adsp/audio_pd"; 3026 q6prmcc: clock-controller { 3027 compatible = "qcom,q6prm-lpass-clocks"; 3028 #clock-cells = <2>; 3029 }; 3030 }; 3031 }; 3032 }; 3033 }; 3034 3035 rxmacro: rxmacro@3200000 { 3036 compatible = "qcom,sc8280xp-lpass-rx-macro"; 3037 reg = <0 0x03200000 0 0x1000>; 3038 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3039 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3040 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3041 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3042 <&vamacro>; 3043 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3044 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3045 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3046 assigned-clock-rates = <19200000>, <19200000>; 3047 3048 clock-output-names = "mclk"; 3049 #clock-cells = <0>; 3050 #sound-dai-cells = <1>; 3051 3052 pinctrl-names = "default"; 3053 pinctrl-0 = <&rx_swr_default>; 3054 3055 status = "disabled"; 3056 }; 3057 3058 swr1: soundwire@3210000 { 3059 compatible = "qcom,soundwire-v1.6.0"; 3060 reg = <0 0x03210000 0 0x2000>; 3061 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 3062 clocks = <&rxmacro>; 3063 clock-names = "iface"; 3064 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 3065 reset-names = "swr_audio_cgcr"; 3066 label = "RX"; 3067 3068 qcom,din-ports = <0>; 3069 qcom,dout-ports = <5>; 3070 3071 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 3072 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 3073 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 3074 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 3075 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 3076 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 3077 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 3078 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 3079 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3080 3081 #sound-dai-cells = <1>; 3082 #address-cells = <2>; 3083 #size-cells = <0>; 3084 3085 status = "disabled"; 3086 }; 3087 3088 txmacro: txmacro@3220000 { 3089 compatible = "qcom,sc8280xp-lpass-tx-macro"; 3090 reg = <0 0x03220000 0 0x1000>; 3091 pinctrl-names = "default"; 3092 pinctrl-0 = <&tx_swr_default>; 3093 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3094 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3095 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3096 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3097 <&vamacro>; 3098 3099 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3100 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3101 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3102 assigned-clock-rates = <19200000>, <19200000>; 3103 clock-output-names = "mclk"; 3104 3105 #clock-cells = <0>; 3106 #sound-dai-cells = <1>; 3107 3108 status = "disabled"; 3109 }; 3110 3111 wsamacro: codec@3240000 { 3112 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 3113 reg = <0 0x03240000 0 0x1000>; 3114 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3115 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3116 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3117 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3118 <&vamacro>; 3119 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3120 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3121 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3122 assigned-clock-rates = <19200000>, <19200000>; 3123 3124 #clock-cells = <0>; 3125 clock-output-names = "mclk"; 3126 #sound-dai-cells = <1>; 3127 3128 pinctrl-names = "default"; 3129 pinctrl-0 = <&wsa_swr_default>; 3130 3131 status = "disabled"; 3132 }; 3133 3134 swr0: soundwire@3250000 { 3135 reg = <0 0x03250000 0 0x2000>; 3136 compatible = "qcom,soundwire-v1.6.0"; 3137 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3138 clocks = <&wsamacro>; 3139 clock-names = "iface"; 3140 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 3141 reset-names = "swr_audio_cgcr"; 3142 label = "WSA"; 3143 3144 qcom,din-ports = <2>; 3145 qcom,dout-ports = <6>; 3146 3147 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 3148 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 3149 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 3150 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3151 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3152 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3153 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 3154 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3155 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3156 3157 #sound-dai-cells = <1>; 3158 #address-cells = <2>; 3159 #size-cells = <0>; 3160 3161 status = "disabled"; 3162 }; 3163 3164 lpass_audiocc: clock-controller@32a9000 { 3165 compatible = "qcom,sc8280xp-lpassaudiocc"; 3166 reg = <0 0x032a9000 0 0x1000>; 3167 #clock-cells = <1>; 3168 #reset-cells = <1>; 3169 }; 3170 3171 swr2: soundwire@3330000 { 3172 compatible = "qcom,soundwire-v1.6.0"; 3173 reg = <0 0x03330000 0 0x2000>; 3174 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3176 interrupt-names = "core", "wakeup"; 3177 3178 clocks = <&txmacro>; 3179 clock-names = "iface"; 3180 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 3181 reset-names = "swr_audio_cgcr"; 3182 label = "TX"; 3183 #sound-dai-cells = <1>; 3184 #address-cells = <2>; 3185 #size-cells = <0>; 3186 3187 qcom,din-ports = <4>; 3188 qcom,dout-ports = <0>; 3189 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3190 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 3191 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3192 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3193 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3194 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3195 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3196 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3197 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 3198 3199 status = "disabled"; 3200 }; 3201 3202 vamacro: codec@3370000 { 3203 compatible = "qcom,sc8280xp-lpass-va-macro"; 3204 reg = <0 0x03370000 0 0x1000>; 3205 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3206 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3207 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3208 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3209 clock-names = "mclk", "macro", "dcodec", "npl"; 3210 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3211 assigned-clock-rates = <19200000>; 3212 3213 #clock-cells = <0>; 3214 clock-output-names = "fsgen"; 3215 #sound-dai-cells = <1>; 3216 3217 status = "disabled"; 3218 }; 3219 3220 lpass_tlmm: pinctrl@33c0000 { 3221 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 3222 reg = <0 0x33c0000 0x0 0x20000>, 3223 <0 0x3550000 0x0 0x10000>; 3224 gpio-controller; 3225 #gpio-cells = <2>; 3226 gpio-ranges = <&lpass_tlmm 0 0 19>; 3227 3228 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3229 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3230 clock-names = "core", "audio"; 3231 3232 status = "disabled"; 3233 3234 tx_swr_default: tx-swr-default-state { 3235 clk-pins { 3236 pins = "gpio0"; 3237 function = "swr_tx_clk"; 3238 drive-strength = <2>; 3239 slew-rate = <1>; 3240 bias-disable; 3241 }; 3242 3243 data-pins { 3244 pins = "gpio1", "gpio2"; 3245 function = "swr_tx_data"; 3246 drive-strength = <2>; 3247 slew-rate = <1>; 3248 bias-bus-hold; 3249 }; 3250 }; 3251 3252 rx_swr_default: rx-swr-default-state { 3253 clk-pins { 3254 pins = "gpio3"; 3255 function = "swr_rx_clk"; 3256 drive-strength = <2>; 3257 slew-rate = <1>; 3258 bias-disable; 3259 }; 3260 3261 data-pins { 3262 pins = "gpio4", "gpio5"; 3263 function = "swr_rx_data"; 3264 drive-strength = <2>; 3265 slew-rate = <1>; 3266 bias-bus-hold; 3267 }; 3268 }; 3269 3270 dmic01_default: dmic01-default-state { 3271 clk-pins { 3272 pins = "gpio6"; 3273 function = "dmic1_clk"; 3274 drive-strength = <8>; 3275 output-high; 3276 }; 3277 3278 data-pins { 3279 pins = "gpio7"; 3280 function = "dmic1_data"; 3281 drive-strength = <8>; 3282 input-enable; 3283 }; 3284 }; 3285 3286 dmic01_sleep: dmic01-sleep-state { 3287 clk-pins { 3288 pins = "gpio6"; 3289 function = "dmic1_clk"; 3290 drive-strength = <2>; 3291 bias-disable; 3292 output-low; 3293 }; 3294 3295 data-pins { 3296 pins = "gpio7"; 3297 function = "dmic1_data"; 3298 drive-strength = <2>; 3299 bias-pull-down; 3300 input-enable; 3301 }; 3302 }; 3303 3304 dmic23_default: dmic23-default-state { 3305 clk-pins { 3306 pins = "gpio8"; 3307 function = "dmic2_clk"; 3308 drive-strength = <8>; 3309 output-high; 3310 }; 3311 3312 data-pins { 3313 pins = "gpio9"; 3314 function = "dmic2_data"; 3315 drive-strength = <8>; 3316 input-enable; 3317 }; 3318 }; 3319 3320 dmic23_sleep: dmic23-sleep-state { 3321 clk-pins { 3322 pins = "gpio8"; 3323 function = "dmic2_clk"; 3324 drive-strength = <2>; 3325 bias-disable; 3326 output-low; 3327 }; 3328 3329 data-pins { 3330 pins = "gpio9"; 3331 function = "dmic2_data"; 3332 drive-strength = <2>; 3333 bias-pull-down; 3334 input-enable; 3335 }; 3336 }; 3337 3338 wsa_swr_default: wsa-swr-default-state { 3339 clk-pins { 3340 pins = "gpio10"; 3341 function = "wsa_swr_clk"; 3342 drive-strength = <2>; 3343 slew-rate = <1>; 3344 bias-disable; 3345 }; 3346 3347 data-pins { 3348 pins = "gpio11"; 3349 function = "wsa_swr_data"; 3350 drive-strength = <2>; 3351 slew-rate = <1>; 3352 bias-bus-hold; 3353 }; 3354 }; 3355 3356 wsa2_swr_default: wsa2-swr-default-state { 3357 clk-pins { 3358 pins = "gpio15"; 3359 function = "wsa2_swr_clk"; 3360 drive-strength = <2>; 3361 slew-rate = <1>; 3362 bias-disable; 3363 }; 3364 3365 data-pins { 3366 pins = "gpio16"; 3367 function = "wsa2_swr_data"; 3368 drive-strength = <2>; 3369 slew-rate = <1>; 3370 bias-bus-hold; 3371 }; 3372 }; 3373 }; 3374 3375 lpasscc: clock-controller@33e0000 { 3376 compatible = "qcom,sc8280xp-lpasscc"; 3377 reg = <0 0x033e0000 0 0x12000>; 3378 #clock-cells = <1>; 3379 #reset-cells = <1>; 3380 }; 3381 3382 lpass_noc: interconnect@3c40000 { 3383 compatible = "qcom,sc8280xp-lpass-ag-noc"; 3384 reg = <0 0x03c40000 0 0xf080>; 3385 3386 #interconnect-cells = <2>; 3387 qcom,bcm-voters = <&apps_bcm_voter>; 3388 }; 3389 3390 gpu: gpu@3d00000 { 3391 compatible = "qcom,adreno-690.0", "qcom,adreno"; 3392 3393 reg = <0 0x03d00000 0 0x40000>, 3394 <0 0x03d9e000 0 0x1000>, 3395 <0 0x03d61000 0 0x800>; 3396 reg-names = "kgsl_3d0_reg_memory", 3397 "cx_mem", 3398 "cx_dbgc"; 3399 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3400 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 3401 operating-points-v2 = <&gpu_opp_table>; 3402 3403 qcom,gmu = <&gmu>; 3404 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3405 interconnect-names = "gfx-mem"; 3406 #cooling-cells = <2>; 3407 3408 status = "disabled"; 3409 3410 gpu_zap_shader: zap-shader { 3411 memory-region = <&pil_gpu_mem>; 3412 }; 3413 3414 gpu_opp_table: opp-table { 3415 compatible = "operating-points-v2"; 3416 3417 opp-270000000 { 3418 opp-hz = /bits/ 64 <270000000>; 3419 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3420 opp-peak-kBps = <451000>; 3421 }; 3422 3423 opp-410000000 { 3424 opp-hz = /bits/ 64 <410000000>; 3425 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3426 opp-peak-kBps = <1555000>; 3427 }; 3428 3429 opp-500000000 { 3430 opp-hz = /bits/ 64 <500000000>; 3431 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3432 opp-peak-kBps = <1555000>; 3433 }; 3434 3435 opp-547000000 { 3436 opp-hz = /bits/ 64 <547000000>; 3437 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3438 opp-peak-kBps = <1555000>; 3439 }; 3440 3441 opp-606000000 { 3442 opp-hz = /bits/ 64 <606000000>; 3443 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3444 opp-peak-kBps = <2736000>; 3445 }; 3446 3447 opp-640000000 { 3448 opp-hz = /bits/ 64 <640000000>; 3449 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3450 opp-peak-kBps = <2736000>; 3451 }; 3452 3453 opp-655000000 { 3454 opp-hz = /bits/ 64 <655000000>; 3455 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3456 opp-peak-kBps = <2736000>; 3457 }; 3458 3459 opp-690000000 { 3460 opp-hz = /bits/ 64 <690000000>; 3461 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3462 opp-peak-kBps = <2736000>; 3463 }; 3464 }; 3465 }; 3466 3467 gmu: gmu@3d6a000 { 3468 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 3469 reg = <0 0x03d6a000 0 0x34000>, 3470 <0 0x03de0000 0 0x10000>, 3471 <0 0x0b290000 0 0x10000>; 3472 reg-names = "gmu", "rscc", "gmu_pdc"; 3473 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3475 interrupt-names = "hfi", "gmu"; 3476 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3477 <&gpucc GPU_CC_CXO_CLK>, 3478 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3479 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3480 <&gpucc GPU_CC_AHB_CLK>, 3481 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3482 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 3483 clock-names = "gmu", 3484 "cxo", 3485 "axi", 3486 "memnoc", 3487 "ahb", 3488 "hub", 3489 "smmu_vote"; 3490 power-domains = <&gpucc GPU_CC_CX_GDSC>, 3491 <&gpucc GPU_CC_GX_GDSC>; 3492 power-domain-names = "cx", 3493 "gx"; 3494 iommus = <&gpu_smmu 5 0xc00>; 3495 operating-points-v2 = <&gmu_opp_table>; 3496 3497 gmu_opp_table: opp-table { 3498 compatible = "operating-points-v2"; 3499 3500 opp-200000000 { 3501 opp-hz = /bits/ 64 <200000000>; 3502 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3503 }; 3504 3505 opp-500000000 { 3506 opp-hz = /bits/ 64 <500000000>; 3507 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3508 }; 3509 }; 3510 }; 3511 3512 gpucc: clock-controller@3d90000 { 3513 compatible = "qcom,sc8280xp-gpucc"; 3514 reg = <0 0x03d90000 0 0x9000>; 3515 clocks = <&rpmhcc RPMH_CXO_CLK>, 3516 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3517 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3518 clock-names = "bi_tcxo", 3519 "gcc_gpu_gpll0_clk_src", 3520 "gcc_gpu_gpll0_div_clk_src"; 3521 3522 power-domains = <&rpmhpd SC8280XP_GFX>; 3523 #clock-cells = <1>; 3524 #reset-cells = <1>; 3525 #power-domain-cells = <1>; 3526 }; 3527 3528 gpu_smmu: iommu@3da0000 { 3529 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 3530 "qcom,smmu-500", "arm,mmu-500"; 3531 reg = <0 0x03da0000 0 0x20000>; 3532 #iommu-cells = <2>; 3533 #global-interrupts = <2>; 3534 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3535 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3536 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3537 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3539 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3540 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3541 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 3548 3549 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3550 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3551 <&gpucc GPU_CC_AHB_CLK>, 3552 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3553 <&gpucc GPU_CC_CX_GMU_CLK>, 3554 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3555 <&gpucc GPU_CC_HUB_AON_CLK>; 3556 clock-names = "gcc_gpu_memnoc_gfx_clk", 3557 "gcc_gpu_snoc_dvm_gfx_clk", 3558 "gpu_cc_ahb_clk", 3559 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3560 "gpu_cc_cx_gmu_clk", 3561 "gpu_cc_hub_cx_int_clk", 3562 "gpu_cc_hub_aon_clk"; 3563 3564 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3565 dma-coherent; 3566 }; 3567 3568 sdc2: mmc@8804000 { 3569 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3570 reg = <0 0x08804000 0 0x1000>; 3571 3572 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3573 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3574 interrupt-names = "hc_irq", "pwr_irq"; 3575 3576 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3577 <&gcc GCC_SDCC2_APPS_CLK>, 3578 <&rpmhcc RPMH_CXO_CLK>; 3579 clock-names = "iface", "core", "xo"; 3580 resets = <&gcc GCC_SDCC2_BCR>; 3581 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3582 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3583 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3584 iommus = <&apps_smmu 0x4e0 0x0>; 3585 power-domains = <&rpmhpd SC8280XP_CX>; 3586 operating-points-v2 = <&sdc2_opp_table>; 3587 bus-width = <4>; 3588 dma-coherent; 3589 3590 status = "disabled"; 3591 3592 sdc2_opp_table: opp-table { 3593 compatible = "operating-points-v2"; 3594 3595 opp-100000000 { 3596 opp-hz = /bits/ 64 <100000000>; 3597 required-opps = <&rpmhpd_opp_low_svs>; 3598 opp-peak-kBps = <1800000 400000>; 3599 opp-avg-kBps = <100000 0>; 3600 }; 3601 3602 opp-202000000 { 3603 opp-hz = /bits/ 64 <202000000>; 3604 required-opps = <&rpmhpd_opp_svs_l1>; 3605 opp-peak-kBps = <5400000 1600000>; 3606 opp-avg-kBps = <200000 0>; 3607 }; 3608 }; 3609 }; 3610 3611 usb_0_hsphy: phy@88e5000 { 3612 compatible = "qcom,sc8280xp-usb-hs-phy", 3613 "qcom,usb-snps-hs-5nm-phy"; 3614 reg = <0 0x088e5000 0 0x400>; 3615 clocks = <&rpmhcc RPMH_CXO_CLK>; 3616 clock-names = "ref"; 3617 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3618 3619 #phy-cells = <0>; 3620 3621 status = "disabled"; 3622 }; 3623 3624 usb_2_hsphy0: phy@88e7000 { 3625 compatible = "qcom,sc8280xp-usb-hs-phy", 3626 "qcom,usb-snps-hs-5nm-phy"; 3627 reg = <0 0x088e7000 0 0x400>; 3628 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 3629 clock-names = "ref"; 3630 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 3631 3632 #phy-cells = <0>; 3633 3634 status = "disabled"; 3635 }; 3636 3637 usb_2_hsphy1: phy@88e8000 { 3638 compatible = "qcom,sc8280xp-usb-hs-phy", 3639 "qcom,usb-snps-hs-5nm-phy"; 3640 reg = <0 0x088e8000 0 0x400>; 3641 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 3642 clock-names = "ref"; 3643 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 3644 3645 #phy-cells = <0>; 3646 3647 status = "disabled"; 3648 }; 3649 3650 usb_2_hsphy2: phy@88e9000 { 3651 compatible = "qcom,sc8280xp-usb-hs-phy", 3652 "qcom,usb-snps-hs-5nm-phy"; 3653 reg = <0 0x088e9000 0 0x400>; 3654 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 3655 clock-names = "ref"; 3656 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 3657 3658 #phy-cells = <0>; 3659 3660 status = "disabled"; 3661 }; 3662 3663 usb_2_hsphy3: phy@88ea000 { 3664 compatible = "qcom,sc8280xp-usb-hs-phy", 3665 "qcom,usb-snps-hs-5nm-phy"; 3666 reg = <0 0x088ea000 0 0x400>; 3667 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 3668 clock-names = "ref"; 3669 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 3670 3671 #phy-cells = <0>; 3672 3673 status = "disabled"; 3674 }; 3675 3676 usb_0_qmpphy: phy@88eb000 { 3677 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3678 reg = <0 0x088eb000 0 0x4000>; 3679 3680 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3681 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3682 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3683 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3684 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3685 3686 power-domains = <&gcc USB30_PRIM_GDSC>; 3687 3688 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3689 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3690 reset-names = "phy", "common"; 3691 3692 #clock-cells = <1>; 3693 #phy-cells = <1>; 3694 3695 status = "disabled"; 3696 3697 ports { 3698 #address-cells = <1>; 3699 #size-cells = <0>; 3700 3701 port@0 { 3702 reg = <0>; 3703 3704 usb_0_qmpphy_out: endpoint {}; 3705 }; 3706 3707 port@1 { 3708 reg = <1>; 3709 3710 usb_0_qmpphy_usb_ss_in: endpoint { 3711 remote-endpoint = <&usb_0_dwc3_ss>; 3712 }; 3713 }; 3714 3715 port@2 { 3716 reg = <2>; 3717 3718 usb_0_qmpphy_dp_in: endpoint {}; 3719 }; 3720 }; 3721 }; 3722 3723 usb_2_qmpphy0: phy@88ef000 { 3724 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3725 reg = <0 0x088ef000 0 0x2000>; 3726 3727 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3728 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 3729 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3730 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 3731 clock-names = "aux", "ref", "com_aux", "pipe"; 3732 3733 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 3734 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 3735 reset-names = "phy", "phy_phy"; 3736 3737 power-domains = <&gcc USB30_MP_GDSC>; 3738 3739 #clock-cells = <0>; 3740 clock-output-names = "usb2_phy0_pipe_clk"; 3741 3742 #phy-cells = <0>; 3743 3744 status = "disabled"; 3745 }; 3746 3747 usb_2_qmpphy1: phy@88f1000 { 3748 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3749 reg = <0 0x088f1000 0 0x2000>; 3750 3751 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3752 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 3753 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3754 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 3755 clock-names = "aux", "ref", "com_aux", "pipe"; 3756 3757 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 3758 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 3759 reset-names = "phy", "phy_phy"; 3760 3761 power-domains = <&gcc USB30_MP_GDSC>; 3762 3763 #clock-cells = <0>; 3764 clock-output-names = "usb2_phy1_pipe_clk"; 3765 3766 #phy-cells = <0>; 3767 3768 status = "disabled"; 3769 }; 3770 3771 refgen: regulator@8900000 { 3772 compatible = "qcom,sc8280xp-refgen-regulator", 3773 "qcom,sm8250-refgen-regulator"; 3774 reg = <0x0 0x08900000 0x0 0x96>; 3775 }; 3776 3777 usb_1_hsphy: phy@8902000 { 3778 compatible = "qcom,sc8280xp-usb-hs-phy", 3779 "qcom,usb-snps-hs-5nm-phy"; 3780 reg = <0 0x08902000 0 0x400>; 3781 #phy-cells = <0>; 3782 3783 clocks = <&rpmhcc RPMH_CXO_CLK>; 3784 clock-names = "ref"; 3785 3786 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3787 3788 status = "disabled"; 3789 }; 3790 3791 usb_1_qmpphy: phy@8903000 { 3792 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3793 reg = <0 0x08903000 0 0x4000>; 3794 3795 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3796 <&gcc GCC_USB4_CLKREF_CLK>, 3797 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3798 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3799 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3800 3801 power-domains = <&gcc USB30_SEC_GDSC>; 3802 3803 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3804 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3805 reset-names = "phy", "common"; 3806 3807 #clock-cells = <1>; 3808 #phy-cells = <1>; 3809 3810 status = "disabled"; 3811 3812 ports { 3813 #address-cells = <1>; 3814 #size-cells = <0>; 3815 3816 port@0 { 3817 reg = <0>; 3818 3819 usb_1_qmpphy_out: endpoint {}; 3820 }; 3821 3822 port@1 { 3823 reg = <1>; 3824 3825 usb_1_qmpphy_usb_ss_in: endpoint { 3826 remote-endpoint = <&usb_1_dwc3_ss>; 3827 }; 3828 }; 3829 3830 port@2 { 3831 reg = <2>; 3832 3833 usb_1_qmpphy_dp_in: endpoint {}; 3834 }; 3835 }; 3836 }; 3837 3838 mdss1_dp0_phy: phy@8909a00 { 3839 compatible = "qcom,sc8280xp-dp-phy"; 3840 reg = <0 0x08909a00 0 0x19c>, 3841 <0 0x08909200 0 0xec>, 3842 <0 0x08909600 0 0xec>, 3843 <0 0x08909000 0 0x1c8>; 3844 3845 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3846 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3847 clock-names = "aux", "cfg_ahb"; 3848 power-domains = <&rpmhpd SC8280XP_MX>; 3849 3850 #clock-cells = <1>; 3851 #phy-cells = <0>; 3852 3853 status = "disabled"; 3854 }; 3855 3856 mdss1_dp1_phy: phy@890ca00 { 3857 compatible = "qcom,sc8280xp-dp-phy"; 3858 reg = <0 0x0890ca00 0 0x19c>, 3859 <0 0x0890c200 0 0xec>, 3860 <0 0x0890c600 0 0xec>, 3861 <0 0x0890c000 0 0x1c8>; 3862 3863 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3864 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3865 clock-names = "aux", "cfg_ahb"; 3866 power-domains = <&rpmhpd SC8280XP_MX>; 3867 3868 #clock-cells = <1>; 3869 #phy-cells = <0>; 3870 3871 status = "disabled"; 3872 }; 3873 3874 pmu@9091000 { 3875 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3876 reg = <0 0x09091000 0 0x1000>; 3877 3878 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3879 3880 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3881 3882 operating-points-v2 = <&llcc_bwmon_opp_table>; 3883 3884 llcc_bwmon_opp_table: opp-table { 3885 compatible = "operating-points-v2"; 3886 3887 opp-0 { 3888 opp-peak-kBps = <762000>; 3889 }; 3890 opp-1 { 3891 opp-peak-kBps = <1720000>; 3892 }; 3893 opp-2 { 3894 opp-peak-kBps = <2086000>; 3895 }; 3896 opp-3 { 3897 opp-peak-kBps = <2597000>; 3898 }; 3899 opp-4 { 3900 opp-peak-kBps = <2929000>; 3901 }; 3902 opp-5 { 3903 opp-peak-kBps = <3879000>; 3904 }; 3905 opp-6 { 3906 opp-peak-kBps = <5161000>; 3907 }; 3908 opp-7 { 3909 opp-peak-kBps = <5931000>; 3910 }; 3911 opp-8 { 3912 opp-peak-kBps = <6515000>; 3913 }; 3914 opp-9 { 3915 opp-peak-kBps = <7980000>; 3916 }; 3917 opp-10 { 3918 opp-peak-kBps = <8136000>; 3919 }; 3920 opp-11 { 3921 opp-peak-kBps = <10437000>; 3922 }; 3923 opp-12 { 3924 opp-peak-kBps = <12191000>; 3925 }; 3926 }; 3927 }; 3928 3929 pmu@90b6400 { 3930 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3931 reg = <0 0x090b6400 0 0x600>; 3932 3933 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3934 3935 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3936 operating-points-v2 = <&cpu_bwmon_opp_table>; 3937 3938 cpu_bwmon_opp_table: opp-table { 3939 compatible = "operating-points-v2"; 3940 3941 opp-0 { 3942 opp-peak-kBps = <2288000>; 3943 }; 3944 opp-1 { 3945 opp-peak-kBps = <4577000>; 3946 }; 3947 opp-2 { 3948 opp-peak-kBps = <7110000>; 3949 }; 3950 opp-3 { 3951 opp-peak-kBps = <9155000>; 3952 }; 3953 opp-4 { 3954 opp-peak-kBps = <12298000>; 3955 }; 3956 opp-5 { 3957 opp-peak-kBps = <14236000>; 3958 }; 3959 opp-6 { 3960 opp-peak-kBps = <15258001>; 3961 }; 3962 }; 3963 }; 3964 3965 dc_noc: interconnect@90e0000 { 3966 compatible = "qcom,sc8280xp-dc-noc"; 3967 reg = <0 0x090e0000 0 0x5080>; 3968 3969 #interconnect-cells = <2>; 3970 qcom,bcm-voters = <&apps_bcm_voter>; 3971 }; 3972 3973 gem_noc: interconnect@9100000 { 3974 compatible = "qcom,sc8280xp-gem-noc"; 3975 reg = <0 0x09100000 0 0xb8400>; 3976 3977 #interconnect-cells = <2>; 3978 qcom,bcm-voters = <&apps_bcm_voter>; 3979 }; 3980 3981 system-cache-controller@9200000 { 3982 compatible = "qcom,sc8280xp-llcc"; 3983 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3984 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3985 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3986 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3987 <0 0x09600000 0 0x58000>; 3988 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3989 "llcc3_base", "llcc4_base", "llcc5_base", 3990 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3991 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3992 }; 3993 3994 usb_2: usb@a4f8800 { 3995 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; 3996 reg = <0 0x0a4f8800 0 0x400>; 3997 #address-cells = <2>; 3998 #size-cells = <2>; 3999 ranges; 4000 4001 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4002 <&gcc GCC_USB30_MP_MASTER_CLK>, 4003 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4004 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4005 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4006 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4007 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4008 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4009 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4010 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4011 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4012 4013 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4014 <&gcc GCC_USB30_MP_MASTER_CLK>; 4015 assigned-clock-rates = <19200000>, <200000000>; 4016 4017 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4018 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4019 <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, 4020 <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 4021 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4022 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4023 <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>, 4024 <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>, 4025 <&pdc 127 IRQ_TYPE_EDGE_BOTH>, 4026 <&pdc 126 IRQ_TYPE_EDGE_BOTH>, 4027 <&pdc 129 IRQ_TYPE_EDGE_BOTH>, 4028 <&pdc 128 IRQ_TYPE_EDGE_BOTH>, 4029 <&pdc 131 IRQ_TYPE_EDGE_BOTH>, 4030 <&pdc 130 IRQ_TYPE_EDGE_BOTH>, 4031 <&pdc 133 IRQ_TYPE_EDGE_BOTH>, 4032 <&pdc 132 IRQ_TYPE_EDGE_BOTH>, 4033 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 4034 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4035 4036 interrupt-names = "pwr_event_1", "pwr_event_2", 4037 "pwr_event_3", "pwr_event_4", 4038 "hs_phy_1", "hs_phy_2", 4039 "hs_phy_3", "hs_phy_4", 4040 "dp_hs_phy_1", "dm_hs_phy_1", 4041 "dp_hs_phy_2", "dm_hs_phy_2", 4042 "dp_hs_phy_3", "dm_hs_phy_3", 4043 "dp_hs_phy_4", "dm_hs_phy_4", 4044 "ss_phy_1", "ss_phy_2"; 4045 4046 power-domains = <&gcc USB30_MP_GDSC>; 4047 required-opps = <&rpmhpd_opp_nom>; 4048 4049 resets = <&gcc GCC_USB30_MP_BCR>; 4050 4051 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, 4052 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; 4053 interconnect-names = "usb-ddr", "apps-usb"; 4054 4055 wakeup-source; 4056 4057 status = "disabled"; 4058 4059 usb_2_dwc3: usb@a400000 { 4060 compatible = "snps,dwc3"; 4061 reg = <0 0x0a400000 0 0xcd00>; 4062 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4063 iommus = <&apps_smmu 0x800 0x0>; 4064 phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, 4065 <&usb_2_hsphy1>, <&usb_2_qmpphy1>, 4066 <&usb_2_hsphy2>, 4067 <&usb_2_hsphy3>; 4068 phy-names = "usb2-0", "usb3-0", 4069 "usb2-1", "usb3-1", 4070 "usb2-2", 4071 "usb2-3"; 4072 dr_mode = "host"; 4073 snps,dis-u1-entry-quirk; 4074 snps,dis-u2-entry-quirk; 4075 }; 4076 }; 4077 4078 usb_0: usb@a6f8800 { 4079 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 4080 reg = <0 0x0a6f8800 0 0x400>; 4081 #address-cells = <2>; 4082 #size-cells = <2>; 4083 ranges; 4084 4085 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4086 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4087 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4088 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4089 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4090 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4091 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4092 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4093 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4094 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4095 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4096 4097 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4098 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4099 assigned-clock-rates = <19200000>, <200000000>; 4100 4101 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 4102 <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 4103 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4104 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4105 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 4106 interrupt-names = "pwr_event", 4107 "hs_phy_irq", 4108 "dp_hs_phy_irq", 4109 "dm_hs_phy_irq", 4110 "ss_phy_irq"; 4111 4112 power-domains = <&gcc USB30_PRIM_GDSC>; 4113 required-opps = <&rpmhpd_opp_nom>; 4114 4115 resets = <&gcc GCC_USB30_PRIM_BCR>; 4116 4117 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4118 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4119 interconnect-names = "usb-ddr", "apps-usb"; 4120 4121 wakeup-source; 4122 4123 status = "disabled"; 4124 4125 usb_0_dwc3: usb@a600000 { 4126 compatible = "snps,dwc3"; 4127 reg = <0 0x0a600000 0 0xcd00>; 4128 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 4129 iommus = <&apps_smmu 0x820 0x0>; 4130 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 4131 phy-names = "usb2-phy", "usb3-phy"; 4132 snps,dis-u1-entry-quirk; 4133 snps,dis-u2-entry-quirk; 4134 4135 ports { 4136 #address-cells = <1>; 4137 #size-cells = <0>; 4138 4139 port@0 { 4140 reg = <0>; 4141 4142 usb_0_dwc3_hs: endpoint { 4143 }; 4144 }; 4145 4146 port@1 { 4147 reg = <1>; 4148 4149 usb_0_dwc3_ss: endpoint { 4150 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 4151 }; 4152 }; 4153 }; 4154 }; 4155 }; 4156 4157 usb_1: usb@a8f8800 { 4158 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 4159 reg = <0 0x0a8f8800 0 0x400>; 4160 #address-cells = <2>; 4161 #size-cells = <2>; 4162 ranges; 4163 4164 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4165 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4166 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4167 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4168 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4169 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4170 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4171 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4172 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4173 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4174 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4175 4176 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4177 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4178 assigned-clock-rates = <19200000>, <200000000>; 4179 4180 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 4181 <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 4182 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4183 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 4184 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 4185 interrupt-names = "pwr_event", 4186 "hs_phy_irq", 4187 "dp_hs_phy_irq", 4188 "dm_hs_phy_irq", 4189 "ss_phy_irq"; 4190 4191 power-domains = <&gcc USB30_SEC_GDSC>; 4192 required-opps = <&rpmhpd_opp_nom>; 4193 4194 resets = <&gcc GCC_USB30_SEC_BCR>; 4195 4196 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 4197 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4198 interconnect-names = "usb-ddr", "apps-usb"; 4199 4200 wakeup-source; 4201 4202 status = "disabled"; 4203 4204 usb_1_dwc3: usb@a800000 { 4205 compatible = "snps,dwc3"; 4206 reg = <0 0x0a800000 0 0xcd00>; 4207 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 4208 iommus = <&apps_smmu 0x860 0x0>; 4209 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4210 phy-names = "usb2-phy", "usb3-phy"; 4211 snps,dis-u1-entry-quirk; 4212 snps,dis-u2-entry-quirk; 4213 4214 ports { 4215 #address-cells = <1>; 4216 #size-cells = <0>; 4217 4218 port@0 { 4219 reg = <0>; 4220 4221 usb_1_dwc3_hs: endpoint { 4222 }; 4223 }; 4224 4225 port@1 { 4226 reg = <1>; 4227 4228 usb_1_dwc3_ss: endpoint { 4229 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4230 }; 4231 }; 4232 }; 4233 }; 4234 }; 4235 4236 iris: video-codec@aa00000 { 4237 compatible = "qcom,sc8280xp-iris", "qcom,sm8250-venus"; 4238 reg = <0x0 0x0aa00000 0x0 0x100000>; 4239 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4240 4241 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4242 <&videocc VIDEO_CC_MVS0C_CLK>, 4243 <&videocc VIDEO_CC_MVS0_CLK>; 4244 clock-names = "iface", 4245 "core", 4246 "vcodec0_core"; 4247 power-domains = <&videocc MVS0C_GDSC>, 4248 <&videocc MVS0_GDSC>, 4249 <&rpmhpd SC8280XP_MX>, 4250 <&rpmhpd SC8280XP_MMCX>; 4251 power-domain-names = "venus", 4252 "vcodec0", 4253 "mx", 4254 "mmcx"; 4255 4256 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 4257 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 4258 reset-names = "bus", "core"; 4259 4260 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4261 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4262 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4263 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4264 interconnect-names = "cpu-cfg", 4265 "video-mem"; 4266 4267 operating-points-v2 = <&iris_opp_table>; 4268 iommus = <&apps_smmu 0x2a00 0x400>; 4269 memory-region = <&pil_video_mem>; 4270 4271 status = "disabled"; 4272 4273 iris_opp_table: opp-table { 4274 compatible = "operating-points-v2"; 4275 4276 opp-240000000 { 4277 opp-hz = /bits/ 64 <240000000>; 4278 required-opps = <&rpmhpd_opp_svs>, 4279 <&rpmhpd_opp_low_svs>; 4280 }; 4281 4282 opp-338000000 { 4283 opp-hz = /bits/ 64 <338000000>; 4284 required-opps = <&rpmhpd_opp_svs>, 4285 <&rpmhpd_opp_svs>; 4286 }; 4287 4288 opp-366000000 { 4289 opp-hz = /bits/ 64 <366000000>; 4290 required-opps = <&rpmhpd_opp_svs_l1>, 4291 <&rpmhpd_opp_svs_l1>; 4292 }; 4293 4294 opp-444000000 { 4295 opp-hz = /bits/ 64 <444000000>; 4296 required-opps = <&rpmhpd_opp_svs_l1>, 4297 <&rpmhpd_opp_nom>; 4298 }; 4299 4300 opp-533000000 { 4301 opp-hz = /bits/ 64 <533000000>; 4302 required-opps = <&rpmhpd_opp_nom>, 4303 <&rpmhpd_opp_turbo>; 4304 }; 4305 4306 opp-560000000 { 4307 opp-hz = /bits/ 64 <560000000>; 4308 required-opps = <&rpmhpd_opp_nom>, 4309 <&rpmhpd_opp_turbo_l1>; 4310 }; 4311 }; 4312 }; 4313 4314 videocc: clock-controller@abf0000 { 4315 compatible = "qcom,sc8280xp-videocc"; 4316 reg = <0 0x0abf0000 0 0x10000>; 4317 clocks = <&rpmhcc RPMH_CXO_CLK>, 4318 <&rpmhcc RPMH_CXO_CLK_A>, 4319 <&sleep_clk>; 4320 power-domains = <&rpmhpd SC8280XP_MMCX>; 4321 required-opps = <&rpmhpd_opp_low_svs>; 4322 #clock-cells = <1>; 4323 #reset-cells = <1>; 4324 #power-domain-cells = <1>; 4325 }; 4326 4327 cci0: cci@ac4a000 { 4328 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4329 reg = <0 0x0ac4a000 0 0x1000>; 4330 4331 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4332 4333 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4334 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4335 <&camcc CAMCC_CPAS_AHB_CLK>, 4336 <&camcc CAMCC_CCI_0_CLK>; 4337 clock-names = "camnoc_axi", 4338 "slow_ahb_src", 4339 "cpas_ahb", 4340 "cci"; 4341 4342 power-domains = <&camcc TITAN_TOP_GDSC>; 4343 4344 pinctrl-0 = <&cci0_default>; 4345 pinctrl-1 = <&cci0_sleep>; 4346 pinctrl-names = "default", "sleep"; 4347 4348 #address-cells = <1>; 4349 #size-cells = <0>; 4350 4351 status = "disabled"; 4352 4353 cci0_i2c0: i2c-bus@0 { 4354 reg = <0>; 4355 clock-frequency = <1000000>; 4356 #address-cells = <1>; 4357 #size-cells = <0>; 4358 }; 4359 4360 cci0_i2c1: i2c-bus@1 { 4361 reg = <1>; 4362 clock-frequency = <1000000>; 4363 #address-cells = <1>; 4364 #size-cells = <0>; 4365 }; 4366 }; 4367 4368 cci1: cci@ac4b000 { 4369 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4370 reg = <0 0x0ac4b000 0 0x1000>; 4371 4372 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4373 4374 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4375 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4376 <&camcc CAMCC_CPAS_AHB_CLK>, 4377 <&camcc CAMCC_CCI_1_CLK>; 4378 clock-names = "camnoc_axi", 4379 "slow_ahb_src", 4380 "cpas_ahb", 4381 "cci"; 4382 4383 power-domains = <&camcc TITAN_TOP_GDSC>; 4384 4385 pinctrl-0 = <&cci1_default>; 4386 pinctrl-1 = <&cci1_sleep>; 4387 pinctrl-names = "default", "sleep"; 4388 4389 #address-cells = <1>; 4390 #size-cells = <0>; 4391 4392 status = "disabled"; 4393 4394 cci1_i2c0: i2c-bus@0 { 4395 reg = <0>; 4396 clock-frequency = <1000000>; 4397 #address-cells = <1>; 4398 #size-cells = <0>; 4399 }; 4400 4401 cci1_i2c1: i2c-bus@1 { 4402 reg = <1>; 4403 clock-frequency = <1000000>; 4404 #address-cells = <1>; 4405 #size-cells = <0>; 4406 }; 4407 }; 4408 4409 cci2: cci@ac4c000 { 4410 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4411 reg = <0 0x0ac4c000 0 0x1000>; 4412 4413 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 4414 4415 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4416 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4417 <&camcc CAMCC_CPAS_AHB_CLK>, 4418 <&camcc CAMCC_CCI_2_CLK>; 4419 clock-names = "camnoc_axi", 4420 "slow_ahb_src", 4421 "cpas_ahb", 4422 "cci"; 4423 power-domains = <&camcc TITAN_TOP_GDSC>; 4424 4425 pinctrl-0 = <&cci2_default>; 4426 pinctrl-1 = <&cci2_sleep>; 4427 pinctrl-names = "default", "sleep"; 4428 4429 #address-cells = <1>; 4430 #size-cells = <0>; 4431 4432 status = "disabled"; 4433 4434 cci2_i2c0: i2c-bus@0 { 4435 reg = <0>; 4436 clock-frequency = <1000000>; 4437 #address-cells = <1>; 4438 #size-cells = <0>; 4439 }; 4440 4441 cci2_i2c1: i2c-bus@1 { 4442 reg = <1>; 4443 clock-frequency = <1000000>; 4444 #address-cells = <1>; 4445 #size-cells = <0>; 4446 }; 4447 }; 4448 4449 cci3: cci@ac4d000 { 4450 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4451 reg = <0 0x0ac4d000 0 0x1000>; 4452 4453 interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; 4454 4455 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4456 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4457 <&camcc CAMCC_CPAS_AHB_CLK>, 4458 <&camcc CAMCC_CCI_3_CLK>; 4459 clock-names = "camnoc_axi", 4460 "slow_ahb_src", 4461 "cpas_ahb", 4462 "cci"; 4463 4464 power-domains = <&camcc TITAN_TOP_GDSC>; 4465 4466 pinctrl-0 = <&cci3_default>; 4467 pinctrl-1 = <&cci3_sleep>; 4468 pinctrl-names = "default", "sleep"; 4469 4470 #address-cells = <1>; 4471 #size-cells = <0>; 4472 4473 status = "disabled"; 4474 4475 cci3_i2c0: i2c-bus@0 { 4476 reg = <0>; 4477 clock-frequency = <1000000>; 4478 #address-cells = <1>; 4479 #size-cells = <0>; 4480 }; 4481 4482 cci3_i2c1: i2c-bus@1 { 4483 reg = <1>; 4484 clock-frequency = <1000000>; 4485 #address-cells = <1>; 4486 #size-cells = <0>; 4487 }; 4488 }; 4489 4490 camss: camss@ac5a000 { 4491 compatible = "qcom,sc8280xp-camss"; 4492 4493 reg = <0 0x0ac5a000 0 0x2000>, 4494 <0 0x0ac5c000 0 0x2000>, 4495 <0 0x0ac65000 0 0x2000>, 4496 <0 0x0ac67000 0 0x2000>, 4497 <0 0x0acaf000 0 0x4000>, 4498 <0 0x0acb3000 0 0x1000>, 4499 <0 0x0acb6000 0 0x4000>, 4500 <0 0x0acba000 0 0x1000>, 4501 <0 0x0acbd000 0 0x4000>, 4502 <0 0x0acc1000 0 0x1000>, 4503 <0 0x0acc4000 0 0x4000>, 4504 <0 0x0acc8000 0 0x1000>, 4505 <0 0x0accb000 0 0x4000>, 4506 <0 0x0accf000 0 0x1000>, 4507 <0 0x0acd2000 0 0x4000>, 4508 <0 0x0acd6000 0 0x1000>, 4509 <0 0x0acd9000 0 0x4000>, 4510 <0 0x0acdd000 0 0x1000>, 4511 <0 0x0ace0000 0 0x4000>, 4512 <0 0x0ace4000 0 0x1000>; 4513 reg-names = "csiphy2", 4514 "csiphy3", 4515 "csiphy0", 4516 "csiphy1", 4517 "vfe0", 4518 "csid0", 4519 "vfe1", 4520 "csid1", 4521 "vfe2", 4522 "csid2", 4523 "vfe_lite0", 4524 "csid0_lite", 4525 "vfe_lite1", 4526 "csid1_lite", 4527 "vfe_lite2", 4528 "csid2_lite", 4529 "vfe_lite3", 4530 "csid3_lite", 4531 "vfe3", 4532 "csid3"; 4533 4534 interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4535 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 4536 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4537 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4538 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4539 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4540 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4541 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4542 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4543 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4544 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4545 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4546 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 4547 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 4548 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 4549 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 4550 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 4551 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 4552 <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>, 4553 <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>; 4554 interrupt-names = "csid1_lite", 4555 "vfe_lite1", 4556 "csiphy3", 4557 "csid0", 4558 "vfe0", 4559 "csid1", 4560 "vfe1", 4561 "csid0_lite", 4562 "vfe_lite0", 4563 "csiphy0", 4564 "csiphy1", 4565 "csiphy2", 4566 "csid2", 4567 "vfe2", 4568 "csid3_lite", 4569 "csid2_lite", 4570 "vfe_lite3", 4571 "vfe_lite2", 4572 "csid3", 4573 "vfe3"; 4574 4575 power-domains = <&camcc IFE_0_GDSC>, 4576 <&camcc IFE_1_GDSC>, 4577 <&camcc IFE_2_GDSC>, 4578 <&camcc IFE_3_GDSC>, 4579 <&camcc TITAN_TOP_GDSC>; 4580 power-domain-names = "ife0", 4581 "ife1", 4582 "ife2", 4583 "ife3", 4584 "top"; 4585 4586 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4587 <&camcc CAMCC_CPAS_AHB_CLK>, 4588 <&camcc CAMCC_CSIPHY0_CLK>, 4589 <&camcc CAMCC_CSI0PHYTIMER_CLK>, 4590 <&camcc CAMCC_CSIPHY1_CLK>, 4591 <&camcc CAMCC_CSI1PHYTIMER_CLK>, 4592 <&camcc CAMCC_CSIPHY2_CLK>, 4593 <&camcc CAMCC_CSI2PHYTIMER_CLK>, 4594 <&camcc CAMCC_CSIPHY3_CLK>, 4595 <&camcc CAMCC_CSI3PHYTIMER_CLK>, 4596 <&camcc CAMCC_IFE_0_AXI_CLK>, 4597 <&camcc CAMCC_IFE_0_CLK>, 4598 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, 4599 <&camcc CAMCC_IFE_0_CSID_CLK>, 4600 <&camcc CAMCC_IFE_1_AXI_CLK>, 4601 <&camcc CAMCC_IFE_1_CLK>, 4602 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, 4603 <&camcc CAMCC_IFE_1_CSID_CLK>, 4604 <&camcc CAMCC_IFE_2_AXI_CLK>, 4605 <&camcc CAMCC_IFE_2_CLK>, 4606 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, 4607 <&camcc CAMCC_IFE_2_CSID_CLK>, 4608 <&camcc CAMCC_IFE_3_AXI_CLK>, 4609 <&camcc CAMCC_IFE_3_CLK>, 4610 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, 4611 <&camcc CAMCC_IFE_3_CSID_CLK>, 4612 <&camcc CAMCC_IFE_LITE_0_CLK>, 4613 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, 4614 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, 4615 <&camcc CAMCC_IFE_LITE_1_CLK>, 4616 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, 4617 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, 4618 <&camcc CAMCC_IFE_LITE_2_CLK>, 4619 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, 4620 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, 4621 <&camcc CAMCC_IFE_LITE_3_CLK>, 4622 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, 4623 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, 4624 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4625 <&gcc GCC_CAMERA_SF_AXI_CLK>; 4626 clock-names = "camnoc_axi", 4627 "cpas_ahb", 4628 "csiphy0", 4629 "csiphy0_timer", 4630 "csiphy1", 4631 "csiphy1_timer", 4632 "csiphy2", 4633 "csiphy2_timer", 4634 "csiphy3", 4635 "csiphy3_timer", 4636 "vfe0_axi", 4637 "vfe0", 4638 "vfe0_cphy_rx", 4639 "vfe0_csid", 4640 "vfe1_axi", 4641 "vfe1", 4642 "vfe1_cphy_rx", 4643 "vfe1_csid", 4644 "vfe2_axi", 4645 "vfe2", 4646 "vfe2_cphy_rx", 4647 "vfe2_csid", 4648 "vfe3_axi", 4649 "vfe3", 4650 "vfe3_cphy_rx", 4651 "vfe3_csid", 4652 "vfe_lite0", 4653 "vfe_lite0_cphy_rx", 4654 "vfe_lite0_csid", 4655 "vfe_lite1", 4656 "vfe_lite1_cphy_rx", 4657 "vfe_lite1_csid", 4658 "vfe_lite2", 4659 "vfe_lite2_cphy_rx", 4660 "vfe_lite2_csid", 4661 "vfe_lite3", 4662 "vfe_lite3_cphy_rx", 4663 "vfe_lite3_csid", 4664 "gcc_axi_hf", 4665 "gcc_axi_sf"; 4666 4667 iommus = <&apps_smmu 0x2000 0x4e0>, 4668 <&apps_smmu 0x2020 0x4e0>, 4669 <&apps_smmu 0x2040 0x4e0>, 4670 <&apps_smmu 0x2060 0x4e0>, 4671 <&apps_smmu 0x2080 0x4e0>, 4672 <&apps_smmu 0x20e0 0x4e0>, 4673 <&apps_smmu 0x20c0 0x4e0>, 4674 <&apps_smmu 0x20a0 0x4e0>, 4675 <&apps_smmu 0x2400 0x4e0>, 4676 <&apps_smmu 0x2420 0x4e0>, 4677 <&apps_smmu 0x2440 0x4e0>, 4678 <&apps_smmu 0x2460 0x4e0>, 4679 <&apps_smmu 0x2480 0x4e0>, 4680 <&apps_smmu 0x24e0 0x4e0>, 4681 <&apps_smmu 0x24c0 0x4e0>, 4682 <&apps_smmu 0x24a0 0x4e0>; 4683 4684 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, 4685 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, 4686 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, 4687 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; 4688 interconnect-names = "cam_ahb", 4689 "cam_hf_mnoc", 4690 "cam_sf_mnoc", 4691 "cam_sf_icp_mnoc"; 4692 4693 status = "disabled"; 4694 4695 ports { 4696 #address-cells = <1>; 4697 #size-cells = <0>; 4698 4699 port@0 { 4700 reg = <0>; 4701 #address-cells = <1>; 4702 #size-cells = <0>; 4703 }; 4704 4705 port@1 { 4706 reg = <1>; 4707 #address-cells = <1>; 4708 #size-cells = <0>; 4709 }; 4710 4711 port@2 { 4712 reg = <2>; 4713 #address-cells = <1>; 4714 #size-cells = <0>; 4715 }; 4716 4717 port@3 { 4718 reg = <3>; 4719 #address-cells = <1>; 4720 #size-cells = <0>; 4721 }; 4722 }; 4723 }; 4724 4725 camcc: clock-controller@ad00000 { 4726 compatible = "qcom,sc8280xp-camcc"; 4727 reg = <0 0x0ad00000 0 0x20000>; 4728 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4729 <&rpmhcc RPMH_CXO_CLK>, 4730 <&rpmhcc RPMH_CXO_CLK_A>, 4731 <&sleep_clk>; 4732 power-domains = <&rpmhpd SC8280XP_MMCX>; 4733 required-opps = <&rpmhpd_opp_low_svs>; 4734 #clock-cells = <1>; 4735 #reset-cells = <1>; 4736 #power-domain-cells = <1>; 4737 }; 4738 4739 mdss0: display-subsystem@ae00000 { 4740 compatible = "qcom,sc8280xp-mdss"; 4741 reg = <0 0x0ae00000 0 0x1000>; 4742 reg-names = "mdss"; 4743 4744 clocks = <&gcc GCC_DISP_AHB_CLK>, 4745 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4746 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 4747 clock-names = "iface", 4748 "ahb", 4749 "core"; 4750 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4751 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 4752 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 4753 interconnect-names = "mdp0-mem", "mdp1-mem"; 4754 iommus = <&apps_smmu 0x1000 0x402>; 4755 power-domains = <&dispcc0 MDSS_GDSC>; 4756 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 4757 4758 interrupt-controller; 4759 #interrupt-cells = <1>; 4760 #address-cells = <2>; 4761 #size-cells = <2>; 4762 ranges; 4763 4764 status = "disabled"; 4765 4766 mdss0_mdp: display-controller@ae01000 { 4767 compatible = "qcom,sc8280xp-dpu"; 4768 reg = <0 0x0ae01000 0 0x8f000>, 4769 <0 0x0aeb0000 0 0x3000>; 4770 reg-names = "mdp", "vbif"; 4771 4772 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4773 <&gcc GCC_DISP_SF_AXI_CLK>, 4774 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4775 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 4776 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 4777 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4778 clock-names = "bus", 4779 "nrt_bus", 4780 "iface", 4781 "lut", 4782 "core", 4783 "vsync"; 4784 interrupt-parent = <&mdss0>; 4785 interrupts = <0>; 4786 power-domains = <&rpmhpd SC8280XP_MMCX>; 4787 4788 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4789 assigned-clock-rates = <19200000>; 4790 operating-points-v2 = <&mdss0_mdp_opp_table>; 4791 4792 ports { 4793 #address-cells = <1>; 4794 #size-cells = <0>; 4795 4796 port@0 { 4797 reg = <0>; 4798 4799 mdss0_intf0_out: endpoint { 4800 remote-endpoint = <&mdss0_dp0_in>; 4801 }; 4802 }; 4803 4804 port@1 { 4805 reg = <1>; 4806 4807 mdss0_intf1_out: endpoint { 4808 remote-endpoint = <&mdss0_dsi0_in>; 4809 }; 4810 }; 4811 4812 port@2 { 4813 reg = <2>; 4814 4815 mdss0_intf2_out: endpoint { 4816 remote-endpoint = <&mdss0_dsi1_in>; 4817 }; 4818 }; 4819 4820 port@4 { 4821 reg = <4>; 4822 4823 mdss0_intf4_out: endpoint { 4824 remote-endpoint = <&mdss0_dp1_in>; 4825 }; 4826 }; 4827 4828 port@5 { 4829 reg = <5>; 4830 4831 mdss0_intf5_out: endpoint { 4832 remote-endpoint = <&mdss0_dp3_in>; 4833 }; 4834 }; 4835 4836 port@6 { 4837 reg = <6>; 4838 4839 mdss0_intf6_out: endpoint { 4840 remote-endpoint = <&mdss0_dp2_in>; 4841 }; 4842 }; 4843 }; 4844 4845 mdss0_mdp_opp_table: opp-table { 4846 compatible = "operating-points-v2"; 4847 4848 opp-200000000 { 4849 opp-hz = /bits/ 64 <200000000>; 4850 required-opps = <&rpmhpd_opp_low_svs>; 4851 }; 4852 4853 opp-300000000 { 4854 opp-hz = /bits/ 64 <300000000>; 4855 required-opps = <&rpmhpd_opp_svs>; 4856 }; 4857 4858 opp-375000000 { 4859 opp-hz = /bits/ 64 <375000000>; 4860 required-opps = <&rpmhpd_opp_svs_l1>; 4861 }; 4862 4863 opp-500000000 { 4864 opp-hz = /bits/ 64 <500000000>; 4865 required-opps = <&rpmhpd_opp_nom>; 4866 }; 4867 opp-600000000 { 4868 opp-hz = /bits/ 64 <600000000>; 4869 required-opps = <&rpmhpd_opp_turbo_l1>; 4870 }; 4871 }; 4872 }; 4873 4874 mdss0_dp0: displayport-controller@ae90000 { 4875 compatible = "qcom,sc8280xp-dp"; 4876 reg = <0 0xae90000 0 0x200>, 4877 <0 0xae90200 0 0x200>, 4878 <0 0xae90400 0 0x600>, 4879 <0 0xae91000 0 0x400>, 4880 <0 0xae91400 0 0x400>; 4881 interrupt-parent = <&mdss0>; 4882 interrupts = <12>; 4883 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4884 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4885 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4886 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4887 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 4888 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 4889 clock-names = "core_iface", "core_aux", 4890 "ctrl_link", 4891 "ctrl_link_iface", 4892 "stream_pixel", 4893 "stream_1_pixel"; 4894 4895 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4896 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 4897 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 4898 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4899 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4900 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4901 4902 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4903 phy-names = "dp"; 4904 4905 #sound-dai-cells = <0>; 4906 4907 operating-points-v2 = <&mdss0_dp0_opp_table>; 4908 power-domains = <&rpmhpd SC8280XP_MMCX>; 4909 4910 status = "disabled"; 4911 4912 ports { 4913 #address-cells = <1>; 4914 #size-cells = <0>; 4915 4916 port@0 { 4917 reg = <0>; 4918 4919 mdss0_dp0_in: endpoint { 4920 remote-endpoint = <&mdss0_intf0_out>; 4921 }; 4922 }; 4923 4924 port@1 { 4925 reg = <1>; 4926 4927 mdss0_dp0_out: endpoint { 4928 }; 4929 }; 4930 }; 4931 4932 mdss0_dp0_opp_table: opp-table { 4933 compatible = "operating-points-v2"; 4934 4935 opp-162000000 { 4936 opp-hz = /bits/ 64 <162000000>; 4937 required-opps = <&rpmhpd_opp_low_svs>; 4938 }; 4939 4940 opp-270000000 { 4941 opp-hz = /bits/ 64 <270000000>; 4942 required-opps = <&rpmhpd_opp_svs>; 4943 }; 4944 4945 opp-540000000 { 4946 opp-hz = /bits/ 64 <540000000>; 4947 required-opps = <&rpmhpd_opp_svs_l1>; 4948 }; 4949 4950 opp-810000000 { 4951 opp-hz = /bits/ 64 <810000000>; 4952 required-opps = <&rpmhpd_opp_nom>; 4953 }; 4954 }; 4955 }; 4956 4957 mdss0_dsi0: dsi@ae94000 { 4958 compatible = "qcom,sc8280xp-dsi-ctrl", 4959 "qcom,sa8775p-dsi-ctrl", 4960 "qcom,mdss-dsi-ctrl"; 4961 reg = <0 0x0ae94000 0 0x400>; 4962 reg-names = "dsi_ctrl"; 4963 4964 interrupt-parent = <&mdss0>; 4965 interrupts = <4>; 4966 4967 clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>, 4968 <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>, 4969 <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>, 4970 <&dispcc0 DISP_CC_MDSS_ESC0_CLK>, 4971 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4972 <&gcc GCC_DISP_HF_AXI_CLK>; 4973 clock-names = "byte", 4974 "byte_intf", 4975 "pixel", 4976 "core", 4977 "iface", 4978 "bus"; 4979 4980 assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>, 4981 <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>; 4982 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 4983 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; 4984 4985 operating-points-v2 = <&dsi_opp_table>; 4986 power-domains = <&rpmhpd SC8280XP_MMCX>; 4987 4988 refgen-supply = <&refgen>; 4989 4990 phys = <&mdss0_dsi0_phy>; 4991 phy-names = "dsi"; 4992 4993 #address-cells = <1>; 4994 #size-cells = <0>; 4995 4996 status = "disabled"; 4997 4998 ports { 4999 #address-cells = <1>; 5000 #size-cells = <0>; 5001 5002 port@0 { 5003 reg = <0>; 5004 5005 mdss0_dsi0_in: endpoint { 5006 remote-endpoint = <&mdss0_intf1_out>; 5007 }; 5008 }; 5009 5010 port@1 { 5011 reg = <1>; 5012 5013 mdss0_dsi0_out: endpoint { 5014 }; 5015 }; 5016 }; 5017 5018 dsi_opp_table: opp-table { 5019 compatible = "operating-points-v2"; 5020 5021 opp-187500000 { 5022 opp-hz = /bits/ 64 <187500000>; 5023 required-opps = <&rpmhpd_opp_low_svs>; 5024 }; 5025 5026 opp-300000000 { 5027 opp-hz = /bits/ 64 <300000000>; 5028 required-opps = <&rpmhpd_opp_svs>; 5029 }; 5030 5031 opp-358000000 { 5032 opp-hz = /bits/ 64 <358000000>; 5033 required-opps = <&rpmhpd_opp_svs_l1>; 5034 }; 5035 }; 5036 }; 5037 5038 mdss0_dsi0_phy: phy@ae94400 { 5039 compatible = "qcom,sc8280xp-dsi-phy-5nm", 5040 "qcom,sa8775p-dsi-phy-5nm"; 5041 reg = <0 0x0ae94400 0 0x200>, 5042 <0 0x0ae94600 0 0x280>, 5043 <0 0x0ae94900 0 0x280>; 5044 reg-names = "dsi_phy", 5045 "dsi_phy_lane", 5046 "dsi_pll"; 5047 5048 #clock-cells = <1>; 5049 #phy-cells = <0>; 5050 5051 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5052 <&rpmhcc RPMH_CXO_CLK>; 5053 clock-names = "iface", "ref"; 5054 5055 status = "disabled"; 5056 }; 5057 5058 mdss0_dsi1: dsi@ae96000 { 5059 compatible = "qcom,sc8280xp-dsi-ctrl", 5060 "qcom,sa8775p-dsi-ctrl", 5061 "qcom,mdss-dsi-ctrl"; 5062 reg = <0 0x0ae96000 0 0x400>; 5063 reg-names = "dsi_ctrl"; 5064 5065 interrupt-parent = <&mdss0>; 5066 interrupts = <5>; 5067 5068 clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>, 5069 <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>, 5070 <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>, 5071 <&dispcc0 DISP_CC_MDSS_ESC1_CLK>, 5072 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5073 <&gcc GCC_DISP_HF_AXI_CLK>; 5074 clock-names = "byte", 5075 "byte_intf", 5076 "pixel", 5077 "core", 5078 "iface", 5079 "bus"; 5080 5081 assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>, 5082 <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>; 5083 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5084 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5085 5086 operating-points-v2 = <&dsi_opp_table>; 5087 power-domains = <&rpmhpd SC8280XP_MMCX>; 5088 5089 refgen-supply = <&refgen>; 5090 5091 phys = <&mdss0_dsi1_phy>; 5092 phy-names = "dsi"; 5093 5094 #address-cells = <1>; 5095 #size-cells = <0>; 5096 5097 status = "disabled"; 5098 5099 ports { 5100 #address-cells = <1>; 5101 #size-cells = <0>; 5102 5103 port@0 { 5104 reg = <0>; 5105 5106 mdss0_dsi1_in: endpoint { 5107 remote-endpoint = <&mdss0_intf2_out>; 5108 }; 5109 }; 5110 5111 port@1 { 5112 reg = <1>; 5113 5114 mdss0_dsi1_out: endpoint { 5115 }; 5116 }; 5117 }; 5118 }; 5119 5120 mdss0_dsi1_phy: phy@ae96400 { 5121 compatible = "qcom,sc8280xp-dsi-phy-5nm", 5122 "qcom,sa8775p-dsi-phy-5nm"; 5123 reg = <0 0x0ae96400 0 0x200>, 5124 <0 0x0ae96600 0 0x280>, 5125 <0 0x0ae96900 0 0x280>; 5126 reg-names = "dsi_phy", 5127 "dsi_phy_lane", 5128 "dsi_pll"; 5129 5130 #clock-cells = <1>; 5131 #phy-cells = <0>; 5132 5133 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5134 <&rpmhcc RPMH_CXO_CLK>; 5135 clock-names = "iface", "ref"; 5136 5137 status = "disabled"; 5138 }; 5139 5140 mdss0_dp1: displayport-controller@ae98000 { 5141 compatible = "qcom,sc8280xp-dp"; 5142 reg = <0 0xae98000 0 0x200>, 5143 <0 0xae98200 0 0x200>, 5144 <0 0xae98400 0 0x600>, 5145 <0 0xae99000 0 0x400>, 5146 <0 0xae99400 0 0x400>; 5147 interrupt-parent = <&mdss0>; 5148 interrupts = <13>; 5149 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5150 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 5151 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 5152 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5153 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5154 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5155 clock-names = "core_iface", "core_aux", 5156 "ctrl_link", 5157 "ctrl_link_iface", "stream_pixel", 5158 "stream_1_pixel"; 5159 5160 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5161 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5162 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5163 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5164 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5165 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5166 5167 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 5168 phy-names = "dp"; 5169 5170 #sound-dai-cells = <0>; 5171 5172 operating-points-v2 = <&mdss0_dp1_opp_table>; 5173 power-domains = <&rpmhpd SC8280XP_MMCX>; 5174 5175 status = "disabled"; 5176 5177 ports { 5178 #address-cells = <1>; 5179 #size-cells = <0>; 5180 5181 port@0 { 5182 reg = <0>; 5183 5184 mdss0_dp1_in: endpoint { 5185 remote-endpoint = <&mdss0_intf4_out>; 5186 }; 5187 }; 5188 5189 port@1 { 5190 reg = <1>; 5191 5192 mdss0_dp1_out: endpoint { 5193 }; 5194 }; 5195 }; 5196 5197 mdss0_dp1_opp_table: opp-table { 5198 compatible = "operating-points-v2"; 5199 5200 opp-162000000 { 5201 opp-hz = /bits/ 64 <162000000>; 5202 required-opps = <&rpmhpd_opp_low_svs>; 5203 }; 5204 5205 opp-270000000 { 5206 opp-hz = /bits/ 64 <270000000>; 5207 required-opps = <&rpmhpd_opp_svs>; 5208 }; 5209 5210 opp-540000000 { 5211 opp-hz = /bits/ 64 <540000000>; 5212 required-opps = <&rpmhpd_opp_svs_l1>; 5213 }; 5214 5215 opp-810000000 { 5216 opp-hz = /bits/ 64 <810000000>; 5217 required-opps = <&rpmhpd_opp_nom>; 5218 }; 5219 }; 5220 }; 5221 5222 mdss0_dp2: displayport-controller@ae9a000 { 5223 compatible = "qcom,sc8280xp-dp"; 5224 reg = <0 0xae9a000 0 0x200>, 5225 <0 0xae9a200 0 0x200>, 5226 <0 0xae9a400 0 0x600>, 5227 <0 0xae9b000 0 0x400>, 5228 <0 0xae9b400 0 0x400>; 5229 5230 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5231 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5232 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 5233 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5234 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 5235 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 5236 clock-names = "core_iface", "core_aux", 5237 "ctrl_link", 5238 "ctrl_link_iface", "stream_pixel", 5239 "stream_1_pixel"; 5240 interrupt-parent = <&mdss0>; 5241 interrupts = <14>; 5242 phys = <&mdss0_dp2_phy>; 5243 phy-names = "dp"; 5244 power-domains = <&rpmhpd SC8280XP_MMCX>; 5245 5246 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5247 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 5248 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 5249 assigned-clock-parents = <&mdss0_dp2_phy 0>, 5250 <&mdss0_dp2_phy 1>, 5251 <&mdss0_dp2_phy 1>; 5252 operating-points-v2 = <&mdss0_dp2_opp_table>; 5253 5254 #sound-dai-cells = <0>; 5255 5256 status = "disabled"; 5257 5258 ports { 5259 #address-cells = <1>; 5260 #size-cells = <0>; 5261 5262 port@0 { 5263 reg = <0>; 5264 mdss0_dp2_in: endpoint { 5265 remote-endpoint = <&mdss0_intf6_out>; 5266 }; 5267 }; 5268 5269 port@1 { 5270 reg = <1>; 5271 5272 mdss0_dp2_out: endpoint { 5273 }; 5274 }; 5275 }; 5276 5277 mdss0_dp2_opp_table: opp-table { 5278 compatible = "operating-points-v2"; 5279 5280 opp-162000000 { 5281 opp-hz = /bits/ 64 <162000000>; 5282 required-opps = <&rpmhpd_opp_low_svs>; 5283 }; 5284 5285 opp-270000000 { 5286 opp-hz = /bits/ 64 <270000000>; 5287 required-opps = <&rpmhpd_opp_svs>; 5288 }; 5289 5290 opp-540000000 { 5291 opp-hz = /bits/ 64 <540000000>; 5292 required-opps = <&rpmhpd_opp_svs_l1>; 5293 }; 5294 5295 opp-810000000 { 5296 opp-hz = /bits/ 64 <810000000>; 5297 required-opps = <&rpmhpd_opp_nom>; 5298 }; 5299 }; 5300 }; 5301 5302 mdss0_dp3: displayport-controller@aea0000 { 5303 compatible = "qcom,sc8280xp-dp"; 5304 reg = <0 0xaea0000 0 0x200>, 5305 <0 0xaea0200 0 0x200>, 5306 <0 0xaea0400 0 0x600>, 5307 <0 0xaea1000 0 0x400>, 5308 <0 0xaea1400 0 0x400>; 5309 5310 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5311 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5312 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 5313 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5314 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5315 clock-names = "core_iface", "core_aux", 5316 "ctrl_link", 5317 "ctrl_link_iface", "stream_pixel"; 5318 interrupt-parent = <&mdss0>; 5319 interrupts = <15>; 5320 phys = <&mdss0_dp3_phy>; 5321 phy-names = "dp"; 5322 power-domains = <&rpmhpd SC8280XP_MMCX>; 5323 5324 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5325 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5326 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 5327 operating-points-v2 = <&mdss0_dp3_opp_table>; 5328 5329 #sound-dai-cells = <0>; 5330 5331 status = "disabled"; 5332 5333 ports { 5334 #address-cells = <1>; 5335 #size-cells = <0>; 5336 5337 port@0 { 5338 reg = <0>; 5339 mdss0_dp3_in: endpoint { 5340 remote-endpoint = <&mdss0_intf5_out>; 5341 }; 5342 }; 5343 5344 port@1 { 5345 reg = <1>; 5346 5347 mdss0_dp3_out: endpoint { 5348 }; 5349 }; 5350 }; 5351 5352 mdss0_dp3_opp_table: opp-table { 5353 compatible = "operating-points-v2"; 5354 5355 opp-162000000 { 5356 opp-hz = /bits/ 64 <162000000>; 5357 required-opps = <&rpmhpd_opp_low_svs>; 5358 }; 5359 5360 opp-270000000 { 5361 opp-hz = /bits/ 64 <270000000>; 5362 required-opps = <&rpmhpd_opp_svs>; 5363 }; 5364 5365 opp-540000000 { 5366 opp-hz = /bits/ 64 <540000000>; 5367 required-opps = <&rpmhpd_opp_svs_l1>; 5368 }; 5369 5370 opp-810000000 { 5371 opp-hz = /bits/ 64 <810000000>; 5372 required-opps = <&rpmhpd_opp_nom>; 5373 }; 5374 }; 5375 }; 5376 }; 5377 5378 mdss0_dp2_phy: phy@aec2a00 { 5379 compatible = "qcom,sc8280xp-dp-phy"; 5380 reg = <0 0x0aec2a00 0 0x19c>, 5381 <0 0x0aec2200 0 0xec>, 5382 <0 0x0aec2600 0 0xec>, 5383 <0 0x0aec2000 0 0x1c8>; 5384 5385 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5386 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 5387 clock-names = "aux", "cfg_ahb"; 5388 power-domains = <&rpmhpd SC8280XP_MX>; 5389 5390 #clock-cells = <1>; 5391 #phy-cells = <0>; 5392 5393 status = "disabled"; 5394 }; 5395 5396 mdss0_dp3_phy: phy@aec5a00 { 5397 compatible = "qcom,sc8280xp-dp-phy"; 5398 reg = <0 0x0aec5a00 0 0x19c>, 5399 <0 0x0aec5200 0 0xec>, 5400 <0 0x0aec5600 0 0xec>, 5401 <0 0x0aec5000 0 0x1c8>; 5402 5403 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5404 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 5405 clock-names = "aux", "cfg_ahb"; 5406 power-domains = <&rpmhpd SC8280XP_MX>; 5407 5408 #clock-cells = <1>; 5409 #phy-cells = <0>; 5410 5411 status = "disabled"; 5412 }; 5413 5414 dispcc0: clock-controller@af00000 { 5415 compatible = "qcom,sc8280xp-dispcc0"; 5416 reg = <0 0x0af00000 0 0x20000>; 5417 5418 clocks = <&gcc GCC_DISP_AHB_CLK>, 5419 <&rpmhcc RPMH_CXO_CLK>, 5420 <&sleep_clk>, 5421 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5422 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5423 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5424 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5425 <&mdss0_dp2_phy 0>, 5426 <&mdss0_dp2_phy 1>, 5427 <&mdss0_dp3_phy 0>, 5428 <&mdss0_dp3_phy 1>, 5429 <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5430 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, 5431 <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5432 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5433 power-domains = <&rpmhpd SC8280XP_MMCX>; 5434 5435 #clock-cells = <1>; 5436 #power-domain-cells = <1>; 5437 #reset-cells = <1>; 5438 5439 status = "disabled"; 5440 }; 5441 5442 pdc: interrupt-controller@b220000 { 5443 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 5444 reg = <0 0x0b220000 0 0x10000>, <0 0x17c000f0 0 0x60>; 5445 qcom,pdc-ranges = <0 480 40>, 5446 <40 140 14>, 5447 <54 263 1>, 5448 <55 306 4>, 5449 <59 312 3>, 5450 <62 374 2>, 5451 <64 434 2>, 5452 <66 438 3>, 5453 <69 86 1>, 5454 <70 520 54>, 5455 <124 609 28>, 5456 <159 638 1>, 5457 <160 720 8>, 5458 <168 801 1>, 5459 <169 728 30>, 5460 <199 416 2>, 5461 <201 449 1>, 5462 <202 89 1>, 5463 <203 451 1>, 5464 <204 462 1>, 5465 <205 264 1>, 5466 <206 579 1>, 5467 <207 653 1>, 5468 <208 656 1>, 5469 <209 659 1>, 5470 <210 122 1>, 5471 <211 699 1>, 5472 <212 705 1>, 5473 <213 450 1>, 5474 <214 643 2>, 5475 <216 646 5>, 5476 <221 390 5>, 5477 <226 700 3>, 5478 <229 240 3>, 5479 <232 269 1>, 5480 <233 377 1>, 5481 <234 372 1>, 5482 <235 138 1>, 5483 <236 857 1>, 5484 <237 860 1>, 5485 <238 137 1>, 5486 <239 668 1>, 5487 <240 366 1>, 5488 <241 949 1>, 5489 <242 815 5>, 5490 <247 769 1>, 5491 <248 768 1>, 5492 <249 663 1>, 5493 <250 799 2>, 5494 <252 798 1>, 5495 <253 765 1>, 5496 <254 763 1>, 5497 <255 454 3>, 5498 <258 139 1>, 5499 <259 786 2>, 5500 <261 370 2>, 5501 <263 158 2>; 5502 #interrupt-cells = <2>; 5503 interrupt-parent = <&intc>; 5504 interrupt-controller; 5505 }; 5506 5507 tsens2: thermal-sensor@c251000 { 5508 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5509 reg = <0 0x0c251000 0 0x1ff>, 5510 <0 0x0c224000 0 0x8>; 5511 #qcom,sensors = <11>; 5512 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, 5513 <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; 5514 interrupt-names = "uplow", "critical"; 5515 #thermal-sensor-cells = <1>; 5516 }; 5517 5518 tsens3: thermal-sensor@c252000 { 5519 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5520 reg = <0 0x0c252000 0 0x1ff>, 5521 <0 0x0c225000 0 0x8>; 5522 #qcom,sensors = <5>; 5523 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, 5524 <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; 5525 interrupt-names = "uplow", "critical"; 5526 #thermal-sensor-cells = <1>; 5527 }; 5528 5529 tsens0: thermal-sensor@c263000 { 5530 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5531 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5532 <0 0x0c222000 0 0x8>; /* SROT */ 5533 #qcom,sensors = <14>; 5534 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 5535 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 5536 interrupt-names = "uplow", "critical"; 5537 #thermal-sensor-cells = <1>; 5538 }; 5539 5540 restart@c264000 { 5541 compatible = "qcom,pshold"; 5542 reg = <0 0x0c264000 0 0x4>; 5543 /* TZ seems to block access */ 5544 status = "reserved"; 5545 }; 5546 5547 tsens1: thermal-sensor@c265000 { 5548 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5549 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5550 <0 0x0c223000 0 0x8>; /* SROT */ 5551 #qcom,sensors = <16>; 5552 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 5553 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 5554 interrupt-names = "uplow", "critical"; 5555 #thermal-sensor-cells = <1>; 5556 }; 5557 5558 aoss_qmp: power-management@c300000 { 5559 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 5560 reg = <0 0x0c300000 0 0x400>; 5561 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 5562 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5563 5564 #clock-cells = <0>; 5565 }; 5566 5567 sram@c3f0000 { 5568 compatible = "qcom,rpmh-stats"; 5569 reg = <0 0x0c3f0000 0 0x400>; 5570 qcom,qmp = <&aoss_qmp>; 5571 }; 5572 5573 spmi_bus: spmi@c440000 { 5574 compatible = "qcom,spmi-pmic-arb"; 5575 reg = <0 0x0c440000 0 0x1100>, 5576 <0 0x0c600000 0 0x2000000>, 5577 <0 0x0e600000 0 0x100000>, 5578 <0 0x0e700000 0 0xa0000>, 5579 <0 0x0c40a000 0 0x26000>; 5580 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5581 interrupt-names = "periph_irq"; 5582 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5583 qcom,ee = <0>; 5584 qcom,channel = <0>; 5585 #address-cells = <2>; 5586 #size-cells = <0>; 5587 interrupt-controller; 5588 #interrupt-cells = <4>; 5589 }; 5590 5591 tlmm: pinctrl@f100000 { 5592 compatible = "qcom,sc8280xp-tlmm"; 5593 reg = <0 0x0f100000 0 0x300000>; 5594 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5595 gpio-controller; 5596 #gpio-cells = <2>; 5597 interrupt-controller; 5598 #interrupt-cells = <2>; 5599 gpio-ranges = <&tlmm 0 0 230>; 5600 wakeup-parent = <&pdc>; 5601 5602 cam_mclk0_default: cam-mclk0-default-state { 5603 pins = "gpio119"; 5604 function = "cam_mclk"; 5605 drive-strength = <6>; 5606 bias-disable; 5607 }; 5608 5609 cam_mclk1_default: cam-mclk1-default-state { 5610 pins = "gpio120"; 5611 function = "cam_mclk"; 5612 drive-strength = <6>; 5613 bias-disable; 5614 }; 5615 5616 cam_mclk2_default: cam-mclk2-default-state { 5617 pins = "gpio16"; 5618 function = "cam_mclk"; 5619 drive-strength = <6>; 5620 bias-disable; 5621 }; 5622 5623 cam_mclk3_default: cam-mclk3-default-state { 5624 pins = "gpio17"; 5625 function = "cam_mclk"; 5626 drive-strength = <6>; 5627 bias-disable; 5628 }; 5629 5630 cam_mclk4_default: cam-mclk4-default-state { 5631 pins = "gpio6"; 5632 function = "cam_mclk"; 5633 drive-strength = <6>; 5634 bias-disable; 5635 }; 5636 5637 cam_mclk5_default: cam-mclk5-default-state { 5638 pins = "gpio7"; 5639 function = "cam_mclk"; 5640 drive-strength = <6>; 5641 bias-disable; 5642 }; 5643 5644 cam_mclk6_default: cam-mclk6-default-state { 5645 pins = "gpio33"; 5646 function = "cam_mclk"; 5647 drive-strength = <6>; 5648 bias-disable; 5649 }; 5650 5651 cam_mclk7_default: cam-mclk7-default-state { 5652 pins = "gpio34"; 5653 function = "cam_mclk"; 5654 drive-strength = <6>; 5655 bias-disable; 5656 }; 5657 5658 cci0_default: cci0-default-state { 5659 cci0_i2c0_default: cci0-i2c0-default-pins { 5660 /* cci_i2c_sda0, cci_i2c_scl0 */ 5661 pins = "gpio113", "gpio114"; 5662 function = "cci_i2c"; 5663 drive-strength = <2>; 5664 bias-pull-up; 5665 }; 5666 5667 cci0_i2c1_default: cci0-i2c1-default-pins { 5668 /* cci_i2c_sda1, cci_i2c_scl1 */ 5669 pins = "gpio115", "gpio116"; 5670 function = "cci_i2c"; 5671 drive-strength = <2>; 5672 bias-pull-up; 5673 }; 5674 }; 5675 5676 cci0_sleep: cci0-sleep-state { 5677 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 5678 /* cci_i2c_sda0, cci_i2c_scl0 */ 5679 pins = "gpio113", "gpio114"; 5680 function = "cci_i2c"; 5681 drive-strength = <2>; 5682 bias-pull-down; 5683 }; 5684 5685 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 5686 /* cci_i2c_sda1, cci_i2c_scl1 */ 5687 pins = "gpio115", "gpio116"; 5688 function = "cci_i2c"; 5689 drive-strength = <2>; 5690 bias-pull-down; 5691 }; 5692 }; 5693 5694 cci1_default: cci1-default-state { 5695 cci1_i2c0_default: cci1-i2c0-default-pins { 5696 /* cci_i2c_sda2, cci_i2c_scl2 */ 5697 pins = "gpio10","gpio11"; 5698 function = "cci_i2c"; 5699 drive-strength = <2>; 5700 bias-pull-up; 5701 }; 5702 5703 cci1_i2c1_default: cci1-i2c1-default-pins { 5704 /* cci_i2c_sda3, cci_i2c_scl3 */ 5705 pins = "gpio123","gpio124"; 5706 function = "cci_i2c"; 5707 drive-strength = <2>; 5708 bias-pull-up; 5709 }; 5710 }; 5711 5712 cci1_sleep: cci1-sleep-state { 5713 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 5714 /* cci_i2c_sda2, cci_i2c_scl2 */ 5715 pins = "gpio10","gpio11"; 5716 function = "cci_i2c"; 5717 drive-strength = <2>; 5718 bias-pull-down; 5719 }; 5720 5721 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 5722 /* cci_i2c_sda3, cci_i2c_scl3 */ 5723 pins = "gpio123","gpio124"; 5724 function = "cci_i2c"; 5725 drive-strength = <2>; 5726 bias-pull-down; 5727 }; 5728 }; 5729 5730 cci2_default: cci2-default-state { 5731 cci2_i2c0_default: cci2-i2c0-default-pins { 5732 /* cci_i2c_sda4, cci_i2c_scl4 */ 5733 pins = "gpio117","gpio118"; 5734 function = "cci_i2c"; 5735 drive-strength = <2>; 5736 bias-pull-up; 5737 }; 5738 5739 cci2_i2c1_default: cci2-i2c1-default-pins { 5740 /* cci_i2c_sda5, cci_i2c_scl5 */ 5741 pins = "gpio12","gpio13"; 5742 function = "cci_i2c"; 5743 drive-strength = <2>; 5744 bias-pull-up; 5745 }; 5746 }; 5747 5748 cci2_sleep: cci2-sleep-state { 5749 cci2_i2c0_sleep: cci2-i2c0-sleep-pins { 5750 /* cci_i2c_sda4, cci_i2c_scl4 */ 5751 pins = "gpio117","gpio118"; 5752 function = "cci_i2c"; 5753 drive-strength = <2>; 5754 bias-pull-down; 5755 }; 5756 5757 cci2_i2c1_sleep: cci2-i2c1-sleep-pins { 5758 /* cci_i2c_sda5, cci_i2c_scl5 */ 5759 pins = "gpio12","gpio13"; 5760 function = "cci_i2c"; 5761 drive-strength = <2>; 5762 bias-pull-down; 5763 }; 5764 }; 5765 5766 cci3_default: cci3-default-state { 5767 cci3_i2c0_default: cci3-i2c0-default-pins { 5768 /* cci_i2c_sda6, cci_i2c_scl6 */ 5769 pins = "gpio145","gpio146"; 5770 function = "cci_i2c"; 5771 drive-strength = <2>; 5772 bias-pull-up; 5773 }; 5774 5775 cci3_i2c1_default: cci3-i2c1-default-pins { 5776 /* cci_i2c_sda7, cci_i2c_scl7 */ 5777 pins = "gpio164","gpio165"; 5778 function = "cci_i2c"; 5779 drive-strength = <2>; 5780 bias-pull-up; 5781 }; 5782 }; 5783 5784 cci3_sleep: cci3-sleep-state { 5785 cci3_i2c0_sleep: cci3-i2c0-sleep-pins { 5786 /* cci_i2c_sda6, cci_i2c_scl6 */ 5787 pins = "gpio145","gpio146"; 5788 function = "cci_i2c"; 5789 drive-strength = <2>; 5790 bias-pull-down; 5791 }; 5792 5793 cci3_i2c1_sleep: cci3-i2c1-sleep-pins { 5794 /* cci_i2c_sda7, cci_i2c_scl7 */ 5795 pins = "gpio164","gpio165"; 5796 function = "cci_i2c"; 5797 drive-strength = <2>; 5798 bias-pull-down; 5799 }; 5800 }; 5801 5802 qup_uart18_default: qup-uart18-default-state { 5803 cts-pins { 5804 pins = "gpio66"; 5805 function = "qup18"; 5806 drive-strength = <2>; 5807 bias-disable; 5808 }; 5809 5810 rts-pins { 5811 pins = "gpio67"; 5812 function = "qup18"; 5813 drive-strength = <2>; 5814 bias-disable; 5815 }; 5816 5817 tx-pins { 5818 pins = "gpio68"; 5819 function = "qup18"; 5820 drive-strength = <2>; 5821 bias-disable; 5822 }; 5823 5824 rx-pins { 5825 pins = "gpio69"; 5826 function = "qup18"; 5827 drive-strength = <2>; 5828 bias-disable; 5829 }; 5830 }; 5831 }; 5832 5833 pcie_smmu: iommu@14f80000 { 5834 compatible = "arm,smmu-v3"; 5835 reg = <0 0x14f80000 0 0x80000>; 5836 #iommu-cells = <1>; 5837 interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>, 5838 <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>, 5839 <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>; 5840 interrupt-names = "eventq", 5841 "gerror", 5842 "cmdq-sync"; 5843 dma-coherent; 5844 status = "reserved"; /* Controlled by QHEE. */ 5845 }; 5846 5847 apps_smmu: iommu@15000000 { 5848 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 5849 reg = <0 0x15000000 0 0x100000>; 5850 #iommu-cells = <2>; 5851 #global-interrupts = <2>; 5852 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5853 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5854 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5855 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5856 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5857 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5858 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5859 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5860 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5861 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5862 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5863 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5864 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5865 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5866 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5867 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5868 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5869 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5870 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5871 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5872 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5873 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5874 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5875 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5876 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5877 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5878 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5879 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5880 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5881 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5882 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5883 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5884 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5885 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5886 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5887 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5888 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5889 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5890 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5891 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5892 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5893 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5894 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5895 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5896 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5897 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5898 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5899 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5900 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5901 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5902 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5903 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5904 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5905 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5906 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5907 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5908 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5909 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5910 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5911 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5912 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5913 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5914 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5915 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5916 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5917 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5918 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5919 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5920 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5921 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5922 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5923 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5924 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5925 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5926 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5927 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5928 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5929 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5930 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5931 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5932 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5933 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5934 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5935 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5936 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5937 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5938 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5939 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5940 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5941 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5942 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5943 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5944 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5945 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 5946 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5947 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 5948 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5949 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5950 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 5951 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 5952 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 5953 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 5954 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5955 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 5956 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 5957 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 5958 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 5959 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 5960 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 5961 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 5962 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 5963 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 5964 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 5965 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 5966 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 5967 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 5968 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 5969 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 5970 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 5971 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 5972 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 5973 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 5974 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 5975 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 5976 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 5977 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 5978 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 5979 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 5980 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 5981 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 5982 dma-coherent; 5983 }; 5984 5985 intc: interrupt-controller@17a00000 { 5986 compatible = "arm,gic-v3"; 5987 interrupt-controller; 5988 #interrupt-cells = <3>; 5989 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5990 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5991 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5992 #redistributor-regions = <1>; 5993 redistributor-stride = <0 0x20000>; 5994 5995 #address-cells = <2>; 5996 #size-cells = <2>; 5997 ranges; 5998 5999 its: msi-controller@17a40000 { 6000 compatible = "arm,gic-v3-its"; 6001 reg = <0 0x17a40000 0 0x20000>; 6002 msi-controller; 6003 #msi-cells = <1>; 6004 }; 6005 }; 6006 6007 watchdog@17c10000 { 6008 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 6009 reg = <0 0x17c10000 0 0x1000>; 6010 clocks = <&sleep_clk>; 6011 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6012 }; 6013 6014 timer@17c20000 { 6015 compatible = "arm,armv7-timer-mem"; 6016 reg = <0x0 0x17c20000 0x0 0x1000>; 6017 #address-cells = <1>; 6018 #size-cells = <1>; 6019 ranges = <0x0 0x0 0x0 0x20000000>; 6020 6021 frame@17c21000 { 6022 frame-number = <0>; 6023 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6024 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6025 reg = <0x17c21000 0x1000>, 6026 <0x17c22000 0x1000>; 6027 }; 6028 6029 frame@17c23000 { 6030 frame-number = <1>; 6031 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6032 reg = <0x17c23000 0x1000>; 6033 status = "disabled"; 6034 }; 6035 6036 frame@17c25000 { 6037 frame-number = <2>; 6038 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6039 reg = <0x17c25000 0x1000>; 6040 status = "disabled"; 6041 }; 6042 6043 frame@17c27000 { 6044 frame-number = <3>; 6045 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6046 reg = <0x17c26000 0x1000>; 6047 status = "disabled"; 6048 }; 6049 6050 frame@17c29000 { 6051 frame-number = <4>; 6052 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6053 reg = <0x17c29000 0x1000>; 6054 status = "disabled"; 6055 }; 6056 6057 frame@17c2b000 { 6058 frame-number = <5>; 6059 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6060 reg = <0x17c2b000 0x1000>; 6061 status = "disabled"; 6062 }; 6063 6064 frame@17c2d000 { 6065 frame-number = <6>; 6066 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6067 reg = <0x17c2d000 0x1000>; 6068 status = "disabled"; 6069 }; 6070 }; 6071 6072 apps_rsc: rsc@18200000 { 6073 compatible = "qcom,rpmh-rsc"; 6074 reg = <0x0 0x18200000 0x0 0x10000>, 6075 <0x0 0x18210000 0x0 0x10000>, 6076 <0x0 0x18220000 0x0 0x10000>; 6077 reg-names = "drv-0", "drv-1", "drv-2"; 6078 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6079 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6080 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6081 qcom,tcs-offset = <0xd00>; 6082 qcom,drv-id = <2>; 6083 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 6084 <WAKE_TCS 3>, <CONTROL_TCS 1>; 6085 label = "apps_rsc"; 6086 power-domains = <&cluster_pd>; 6087 6088 apps_bcm_voter: bcm-voter { 6089 compatible = "qcom,bcm-voter"; 6090 }; 6091 6092 rpmhcc: clock-controller { 6093 compatible = "qcom,sc8280xp-rpmh-clk"; 6094 #clock-cells = <1>; 6095 clock-names = "xo"; 6096 clocks = <&xo_board_clk>; 6097 }; 6098 6099 rpmhpd: power-controller { 6100 compatible = "qcom,sc8280xp-rpmhpd"; 6101 #power-domain-cells = <1>; 6102 operating-points-v2 = <&rpmhpd_opp_table>; 6103 6104 rpmhpd_opp_table: opp-table { 6105 compatible = "operating-points-v2"; 6106 6107 rpmhpd_opp_ret: opp1 { 6108 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6109 }; 6110 6111 rpmhpd_opp_min_svs: opp2 { 6112 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6113 }; 6114 6115 rpmhpd_opp_low_svs: opp3 { 6116 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6117 }; 6118 6119 rpmhpd_opp_svs: opp4 { 6120 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6121 }; 6122 6123 rpmhpd_opp_svs_l1: opp5 { 6124 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6125 }; 6126 6127 rpmhpd_opp_nom: opp6 { 6128 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6129 }; 6130 6131 rpmhpd_opp_nom_l1: opp7 { 6132 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6133 }; 6134 6135 rpmhpd_opp_nom_l2: opp8 { 6136 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6137 }; 6138 6139 rpmhpd_opp_turbo: opp9 { 6140 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6141 }; 6142 6143 rpmhpd_opp_turbo_l1: opp10 { 6144 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6145 }; 6146 }; 6147 }; 6148 }; 6149 6150 epss_l3: interconnect@18590000 { 6151 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 6152 reg = <0 0x18590000 0 0x1000>; 6153 6154 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6155 clock-names = "xo", "alternate"; 6156 6157 #interconnect-cells = <1>; 6158 }; 6159 6160 cpufreq_hw: cpufreq@18591000 { 6161 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 6162 reg = <0 0x18591000 0 0x1000>, 6163 <0 0x18592000 0 0x1000>; 6164 reg-names = "freq-domain0", "freq-domain1"; 6165 6166 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6167 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 6168 interrupt-names = "dcvsh-irq-0", 6169 "dcvsh-irq-1"; 6170 6171 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6172 clock-names = "xo", "alternate"; 6173 6174 #freq-domain-cells = <1>; 6175 #clock-cells = <1>; 6176 }; 6177 6178 nspa_noc: interconnect@1b0c0000 { 6179 compatible = "qcom,sc8280xp-nspa-noc"; 6180 reg = <0 0x1b0c0000 0 0x10000>; 6181 6182 #interconnect-cells = <2>; 6183 qcom,bcm-voters = <&apps_bcm_voter>; 6184 }; 6185 6186 remoteproc_nsp0: remoteproc@1b300000 { 6187 compatible = "qcom,sc8280xp-nsp0-pas"; 6188 reg = <0 0x1b300000 0 0x10000>; 6189 6190 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 6191 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 6192 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 6193 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 6194 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 6195 interrupt-names = "wdog", "fatal", "ready", 6196 "handover", "stop-ack"; 6197 6198 clocks = <&rpmhcc RPMH_CXO_CLK>; 6199 clock-names = "xo"; 6200 6201 power-domains = <&rpmhpd SC8280XP_NSP>, 6202 <&rpmhpd SC8280XP_CX>, 6203 <&rpmhpd SC8280XP_MXC>; 6204 power-domain-names = "nsp", 6205 "cx", 6206 "mxc"; 6207 6208 memory-region = <&pil_nsp0_mem>; 6209 6210 qcom,smem-states = <&smp2p_nsp0_out 0>; 6211 qcom,smem-state-names = "stop"; 6212 6213 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 6214 6215 status = "disabled"; 6216 6217 glink-edge { 6218 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 6219 IPCC_MPROC_SIGNAL_GLINK_QMP 6220 IRQ_TYPE_EDGE_RISING>; 6221 mboxes = <&ipcc IPCC_CLIENT_CDSP 6222 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6223 6224 label = "nsp0"; 6225 qcom,remote-pid = <5>; 6226 6227 fastrpc { 6228 compatible = "qcom,fastrpc"; 6229 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6230 label = "cdsp"; 6231 #address-cells = <1>; 6232 #size-cells = <0>; 6233 6234 compute-cb@1 { 6235 compatible = "qcom,fastrpc-compute-cb"; 6236 reg = <1>; 6237 iommus = <&apps_smmu 0x3181 0x0420>; 6238 }; 6239 6240 compute-cb@2 { 6241 compatible = "qcom,fastrpc-compute-cb"; 6242 reg = <2>; 6243 iommus = <&apps_smmu 0x3182 0x0420>; 6244 }; 6245 6246 compute-cb@3 { 6247 compatible = "qcom,fastrpc-compute-cb"; 6248 reg = <3>; 6249 iommus = <&apps_smmu 0x3183 0x0420>; 6250 }; 6251 6252 compute-cb@4 { 6253 compatible = "qcom,fastrpc-compute-cb"; 6254 reg = <4>; 6255 iommus = <&apps_smmu 0x3184 0x0420>; 6256 }; 6257 6258 compute-cb@5 { 6259 compatible = "qcom,fastrpc-compute-cb"; 6260 reg = <5>; 6261 iommus = <&apps_smmu 0x3185 0x0420>; 6262 }; 6263 6264 compute-cb@6 { 6265 compatible = "qcom,fastrpc-compute-cb"; 6266 reg = <6>; 6267 iommus = <&apps_smmu 0x3186 0x0420>; 6268 }; 6269 6270 compute-cb@7 { 6271 compatible = "qcom,fastrpc-compute-cb"; 6272 reg = <7>; 6273 iommus = <&apps_smmu 0x3187 0x0420>; 6274 }; 6275 6276 compute-cb@8 { 6277 compatible = "qcom,fastrpc-compute-cb"; 6278 reg = <8>; 6279 iommus = <&apps_smmu 0x3188 0x0420>; 6280 }; 6281 6282 compute-cb@9 { 6283 compatible = "qcom,fastrpc-compute-cb"; 6284 reg = <9>; 6285 iommus = <&apps_smmu 0x318b 0x0420>; 6286 }; 6287 6288 compute-cb@10 { 6289 compatible = "qcom,fastrpc-compute-cb"; 6290 reg = <10>; 6291 iommus = <&apps_smmu 0x318b 0x0420>; 6292 }; 6293 6294 compute-cb@11 { 6295 compatible = "qcom,fastrpc-compute-cb"; 6296 reg = <11>; 6297 iommus = <&apps_smmu 0x318c 0x0420>; 6298 }; 6299 6300 compute-cb@12 { 6301 compatible = "qcom,fastrpc-compute-cb"; 6302 reg = <12>; 6303 iommus = <&apps_smmu 0x318d 0x0420>; 6304 }; 6305 6306 compute-cb@13 { 6307 compatible = "qcom,fastrpc-compute-cb"; 6308 reg = <13>; 6309 iommus = <&apps_smmu 0x318e 0x0420>; 6310 }; 6311 6312 compute-cb@14 { 6313 compatible = "qcom,fastrpc-compute-cb"; 6314 reg = <14>; 6315 iommus = <&apps_smmu 0x318f 0x0420>; 6316 }; 6317 }; 6318 }; 6319 }; 6320 6321 nspb_noc: interconnect@210c0000 { 6322 compatible = "qcom,sc8280xp-nspb-noc"; 6323 reg = <0 0x210c0000 0 0x10000>; 6324 6325 #interconnect-cells = <2>; 6326 qcom,bcm-voters = <&apps_bcm_voter>; 6327 }; 6328 6329 remoteproc_nsp1: remoteproc@21300000 { 6330 compatible = "qcom,sc8280xp-nsp1-pas"; 6331 reg = <0 0x21300000 0 0x10000>; 6332 6333 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>, 6334 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 6335 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 6336 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 6337 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 6338 interrupt-names = "wdog", "fatal", "ready", 6339 "handover", "stop-ack"; 6340 6341 clocks = <&rpmhcc RPMH_CXO_CLK>; 6342 clock-names = "xo"; 6343 6344 power-domains = <&rpmhpd SC8280XP_NSP>, 6345 <&rpmhpd SC8280XP_CX>, 6346 <&rpmhpd SC8280XP_MXC>; 6347 power-domain-names = "nsp", 6348 "cx", 6349 "mxc"; 6350 6351 memory-region = <&pil_nsp1_mem>; 6352 6353 qcom,smem-states = <&smp2p_nsp1_out 0>; 6354 qcom,smem-state-names = "stop"; 6355 6356 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 6357 6358 status = "disabled"; 6359 6360 glink-edge { 6361 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 6362 IPCC_MPROC_SIGNAL_GLINK_QMP 6363 IRQ_TYPE_EDGE_RISING>; 6364 mboxes = <&ipcc IPCC_CLIENT_NSP1 6365 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6366 6367 label = "nsp1"; 6368 qcom,remote-pid = <12>; 6369 }; 6370 }; 6371 6372 mdss1: display-subsystem@22000000 { 6373 compatible = "qcom,sc8280xp-mdss"; 6374 reg = <0 0x22000000 0 0x1000>; 6375 reg-names = "mdss"; 6376 6377 clocks = <&gcc GCC_DISP_AHB_CLK>, 6378 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6379 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 6380 clock-names = "iface", 6381 "ahb", 6382 "core"; 6383 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 6384 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 6385 interconnect-names = "mdp0-mem", "mdp1-mem"; 6386 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 6387 6388 iommus = <&apps_smmu 0x1800 0x402>; 6389 power-domains = <&dispcc1 MDSS_GDSC>; 6390 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 6391 6392 interrupt-controller; 6393 #interrupt-cells = <1>; 6394 #address-cells = <2>; 6395 #size-cells = <2>; 6396 ranges; 6397 6398 status = "disabled"; 6399 6400 mdss1_mdp: display-controller@22001000 { 6401 compatible = "qcom,sc8280xp-dpu"; 6402 reg = <0 0x22001000 0 0x8f000>, 6403 <0 0x220b0000 0 0x3000>; 6404 reg-names = "mdp", "vbif"; 6405 6406 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 6407 <&gcc GCC_DISP_SF_AXI_CLK>, 6408 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6409 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 6410 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 6411 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 6412 clock-names = "bus", 6413 "nrt_bus", 6414 "iface", 6415 "lut", 6416 "core", 6417 "vsync"; 6418 interrupt-parent = <&mdss1>; 6419 interrupts = <0>; 6420 power-domains = <&rpmhpd SC8280XP_MMCX>; 6421 6422 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 6423 assigned-clock-rates = <19200000>; 6424 operating-points-v2 = <&mdss1_mdp_opp_table>; 6425 6426 ports { 6427 #address-cells = <1>; 6428 #size-cells = <0>; 6429 6430 port@0 { 6431 reg = <0>; 6432 6433 mdss1_intf0_out: endpoint { 6434 remote-endpoint = <&mdss1_dp0_in>; 6435 }; 6436 }; 6437 6438 port@1 { 6439 reg = <1>; 6440 6441 mdss1_intf1_out: endpoint { 6442 remote-endpoint = <&mdss1_dsi0_in>; 6443 }; 6444 }; 6445 6446 port@2 { 6447 reg = <2>; 6448 6449 mdss1_intf2_out: endpoint { 6450 remote-endpoint = <&mdss1_dsi1_in>; 6451 }; 6452 }; 6453 6454 port@4 { 6455 reg = <4>; 6456 6457 mdss1_intf4_out: endpoint { 6458 remote-endpoint = <&mdss1_dp1_in>; 6459 }; 6460 }; 6461 6462 port@5 { 6463 reg = <5>; 6464 6465 mdss1_intf5_out: endpoint { 6466 remote-endpoint = <&mdss1_dp3_in>; 6467 }; 6468 }; 6469 6470 port@6 { 6471 reg = <6>; 6472 6473 mdss1_intf6_out: endpoint { 6474 remote-endpoint = <&mdss1_dp2_in>; 6475 }; 6476 }; 6477 }; 6478 6479 mdss1_mdp_opp_table: opp-table { 6480 compatible = "operating-points-v2"; 6481 6482 opp-200000000 { 6483 opp-hz = /bits/ 64 <200000000>; 6484 required-opps = <&rpmhpd_opp_low_svs>; 6485 }; 6486 6487 opp-300000000 { 6488 opp-hz = /bits/ 64 <300000000>; 6489 required-opps = <&rpmhpd_opp_svs>; 6490 }; 6491 6492 opp-375000000 { 6493 opp-hz = /bits/ 64 <375000000>; 6494 required-opps = <&rpmhpd_opp_svs_l1>; 6495 }; 6496 6497 opp-500000000 { 6498 opp-hz = /bits/ 64 <500000000>; 6499 required-opps = <&rpmhpd_opp_nom>; 6500 }; 6501 opp-600000000 { 6502 opp-hz = /bits/ 64 <600000000>; 6503 required-opps = <&rpmhpd_opp_turbo_l1>; 6504 }; 6505 }; 6506 }; 6507 6508 mdss1_dp0: displayport-controller@22090000 { 6509 compatible = "qcom,sc8280xp-dp"; 6510 reg = <0 0x22090000 0 0x200>, 6511 <0 0x22090200 0 0x200>, 6512 <0 0x22090400 0 0x600>, 6513 <0 0x22091000 0 0x400>, 6514 <0 0x22091400 0 0x400>; 6515 6516 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6517 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 6518 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 6519 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 6520 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 6521 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 6522 clock-names = "core_iface", "core_aux", 6523 "ctrl_link", 6524 "ctrl_link_iface", "stream_pixel", 6525 "stream_1_pixel"; 6526 interrupt-parent = <&mdss1>; 6527 interrupts = <12>; 6528 phys = <&mdss1_dp0_phy>; 6529 phy-names = "dp"; 6530 power-domains = <&rpmhpd SC8280XP_MMCX>; 6531 6532 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 6533 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 6534 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 6535 assigned-clock-parents = <&mdss1_dp0_phy 0>, 6536 <&mdss1_dp0_phy 1>, 6537 <&mdss1_dp0_phy 1>; 6538 operating-points-v2 = <&mdss1_dp0_opp_table>; 6539 6540 #sound-dai-cells = <0>; 6541 6542 status = "disabled"; 6543 6544 ports { 6545 #address-cells = <1>; 6546 #size-cells = <0>; 6547 6548 port@0 { 6549 reg = <0>; 6550 mdss1_dp0_in: endpoint { 6551 remote-endpoint = <&mdss1_intf0_out>; 6552 }; 6553 }; 6554 6555 port@1 { 6556 reg = <1>; 6557 6558 mdss1_dp0_out: endpoint { 6559 }; 6560 }; 6561 }; 6562 6563 mdss1_dp0_opp_table: opp-table { 6564 compatible = "operating-points-v2"; 6565 6566 opp-162000000 { 6567 opp-hz = /bits/ 64 <162000000>; 6568 required-opps = <&rpmhpd_opp_low_svs>; 6569 }; 6570 6571 opp-270000000 { 6572 opp-hz = /bits/ 64 <270000000>; 6573 required-opps = <&rpmhpd_opp_svs>; 6574 }; 6575 6576 opp-540000000 { 6577 opp-hz = /bits/ 64 <540000000>; 6578 required-opps = <&rpmhpd_opp_svs_l1>; 6579 }; 6580 6581 opp-810000000 { 6582 opp-hz = /bits/ 64 <810000000>; 6583 required-opps = <&rpmhpd_opp_nom>; 6584 }; 6585 }; 6586 }; 6587 6588 mdss1_dsi0: dsi@22094000 { 6589 compatible = "qcom,sc8280xp-dsi-ctrl", 6590 "qcom,sa8775p-dsi-ctrl", 6591 "qcom,mdss-dsi-ctrl"; 6592 reg = <0 0x22094000 0 0x400>; 6593 reg-names = "dsi_ctrl"; 6594 6595 interrupt-parent = <&mdss1>; 6596 interrupts = <4>; 6597 6598 clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK>, 6599 <&dispcc1 DISP_CC_MDSS_BYTE0_INTF_CLK>, 6600 <&dispcc1 DISP_CC_MDSS_PCLK0_CLK>, 6601 <&dispcc1 DISP_CC_MDSS_ESC0_CLK>, 6602 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6603 <&gcc GCC_DISP_HF_AXI_CLK>; 6604 clock-names = "byte", 6605 "byte_intf", 6606 "pixel", 6607 "core", 6608 "iface", 6609 "bus"; 6610 6611 assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK_SRC>, 6612 <&dispcc1 DISP_CC_MDSS_PCLK0_CLK_SRC>; 6613 assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, 6614 <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>; 6615 6616 operating-points-v2 = <&dsi_opp_table>; 6617 power-domains = <&rpmhpd SC8280XP_MMCX>; 6618 6619 refgen-supply = <&refgen>; 6620 6621 phys = <&mdss1_dsi0_phy>; 6622 phy-names = "dsi"; 6623 6624 #address-cells = <1>; 6625 #size-cells = <0>; 6626 6627 status = "disabled"; 6628 6629 ports { 6630 #address-cells = <1>; 6631 #size-cells = <0>; 6632 6633 port@0 { 6634 reg = <0>; 6635 6636 mdss1_dsi0_in: endpoint { 6637 remote-endpoint = <&mdss1_intf1_out>; 6638 }; 6639 }; 6640 6641 port@1 { 6642 reg = <1>; 6643 6644 mdss1_dsi0_out: endpoint { 6645 }; 6646 }; 6647 }; 6648 }; 6649 6650 mdss1_dsi0_phy: phy@22094400 { 6651 compatible = "qcom,sc8280xp-dsi-phy-5nm", 6652 "qcom,sa8775p-dsi-phy-5nm"; 6653 reg = <0 0x22094400 0 0x200>, 6654 <0 0x22094600 0 0x280>, 6655 <0 0x22094900 0 0x280>; 6656 reg-names = "dsi_phy", 6657 "dsi_phy_lane", 6658 "dsi_pll"; 6659 6660 #clock-cells = <1>; 6661 #phy-cells = <0>; 6662 6663 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6664 <&rpmhcc RPMH_CXO_CLK>; 6665 clock-names = "iface", "ref"; 6666 6667 status = "disabled"; 6668 }; 6669 6670 mdss1_dsi1: dsi@22096000 { 6671 compatible = "qcom,sc8280xp-dsi-ctrl", 6672 "qcom,sa8775p-dsi-ctrl", 6673 "qcom,mdss-dsi-ctrl"; 6674 reg = <0 0x22096000 0 0x400>; 6675 reg-names = "dsi_ctrl"; 6676 6677 interrupt-parent = <&mdss1>; 6678 interrupts = <5>; 6679 6680 clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK>, 6681 <&dispcc1 DISP_CC_MDSS_BYTE1_INTF_CLK>, 6682 <&dispcc1 DISP_CC_MDSS_PCLK1_CLK>, 6683 <&dispcc1 DISP_CC_MDSS_ESC1_CLK>, 6684 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6685 <&gcc GCC_DISP_HF_AXI_CLK>; 6686 clock-names = "byte", 6687 "byte_intf", 6688 "pixel", 6689 "core", 6690 "iface", 6691 "bus"; 6692 6693 assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK_SRC>, 6694 <&dispcc1 DISP_CC_MDSS_PCLK1_CLK_SRC>; 6695 assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, 6696 <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; 6697 6698 operating-points-v2 = <&dsi_opp_table>; 6699 power-domains = <&rpmhpd SC8280XP_MMCX>; 6700 6701 refgen-supply = <&refgen>; 6702 6703 phys = <&mdss1_dsi1_phy>; 6704 phy-names = "dsi"; 6705 6706 #address-cells = <1>; 6707 #size-cells = <0>; 6708 6709 status = "disabled"; 6710 6711 ports { 6712 #address-cells = <1>; 6713 #size-cells = <0>; 6714 6715 port@0 { 6716 reg = <0>; 6717 6718 mdss1_dsi1_in: endpoint { 6719 remote-endpoint = <&mdss1_intf2_out>; 6720 }; 6721 }; 6722 6723 port@1 { 6724 reg = <1>; 6725 6726 mdss1_dsi1_out: endpoint { 6727 }; 6728 }; 6729 }; 6730 }; 6731 6732 mdss1_dsi1_phy: phy@22096400 { 6733 compatible = "qcom,sc8280xp-dsi-phy-5nm", 6734 "qcom,sa8775p-dsi-phy-5nm"; 6735 reg = <0 0x22096400 0 0x200>, 6736 <0 0x22096600 0 0x280>, 6737 <0 0x22096900 0 0x280>; 6738 reg-names = "dsi_phy", 6739 "dsi_phy_lane", 6740 "dsi_pll"; 6741 6742 #clock-cells = <1>; 6743 #phy-cells = <0>; 6744 6745 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6746 <&rpmhcc RPMH_CXO_CLK>; 6747 clock-names = "iface", "ref"; 6748 6749 status = "disabled"; 6750 }; 6751 6752 mdss1_dp1: displayport-controller@22098000 { 6753 compatible = "qcom,sc8280xp-dp"; 6754 reg = <0 0x22098000 0 0x200>, 6755 <0 0x22098200 0 0x200>, 6756 <0 0x22098400 0 0x600>, 6757 <0 0x22099000 0 0x400>, 6758 <0 0x22099400 0 0x400>; 6759 6760 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6761 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 6762 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 6763 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 6764 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 6765 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 6766 clock-names = "core_iface", "core_aux", 6767 "ctrl_link", 6768 "ctrl_link_iface", "stream_pixel", 6769 "stream_1_pixel"; 6770 interrupt-parent = <&mdss1>; 6771 interrupts = <13>; 6772 phys = <&mdss1_dp1_phy>; 6773 phy-names = "dp"; 6774 power-domains = <&rpmhpd SC8280XP_MMCX>; 6775 6776 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 6777 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 6778 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 6779 assigned-clock-parents = <&mdss1_dp1_phy 0>, 6780 <&mdss1_dp1_phy 1>, 6781 <&mdss1_dp1_phy 1>; 6782 operating-points-v2 = <&mdss1_dp1_opp_table>; 6783 6784 #sound-dai-cells = <0>; 6785 6786 status = "disabled"; 6787 6788 ports { 6789 #address-cells = <1>; 6790 #size-cells = <0>; 6791 6792 port@0 { 6793 reg = <0>; 6794 mdss1_dp1_in: endpoint { 6795 remote-endpoint = <&mdss1_intf4_out>; 6796 }; 6797 }; 6798 6799 port@1 { 6800 reg = <1>; 6801 6802 mdss1_dp1_out: endpoint { 6803 }; 6804 }; 6805 }; 6806 6807 mdss1_dp1_opp_table: opp-table { 6808 compatible = "operating-points-v2"; 6809 6810 opp-162000000 { 6811 opp-hz = /bits/ 64 <162000000>; 6812 required-opps = <&rpmhpd_opp_low_svs>; 6813 }; 6814 6815 opp-270000000 { 6816 opp-hz = /bits/ 64 <270000000>; 6817 required-opps = <&rpmhpd_opp_svs>; 6818 }; 6819 6820 opp-540000000 { 6821 opp-hz = /bits/ 64 <540000000>; 6822 required-opps = <&rpmhpd_opp_svs_l1>; 6823 }; 6824 6825 opp-810000000 { 6826 opp-hz = /bits/ 64 <810000000>; 6827 required-opps = <&rpmhpd_opp_nom>; 6828 }; 6829 }; 6830 }; 6831 6832 mdss1_dp2: displayport-controller@2209a000 { 6833 compatible = "qcom,sc8280xp-dp"; 6834 reg = <0 0x2209a000 0 0x200>, 6835 <0 0x2209a200 0 0x200>, 6836 <0 0x2209a400 0 0x600>, 6837 <0 0x2209b000 0 0x400>, 6838 <0 0x2209b400 0 0x400>; 6839 6840 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6841 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 6842 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 6843 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 6844 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 6845 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 6846 clock-names = "core_iface", "core_aux", 6847 "ctrl_link", 6848 "ctrl_link_iface", "stream_pixel", 6849 "stream_1_pixel"; 6850 interrupt-parent = <&mdss1>; 6851 interrupts = <14>; 6852 phys = <&mdss1_dp2_phy>; 6853 phy-names = "dp"; 6854 power-domains = <&rpmhpd SC8280XP_MMCX>; 6855 6856 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 6857 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 6858 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 6859 assigned-clock-parents = <&mdss1_dp2_phy 0>, 6860 <&mdss1_dp2_phy 1>, 6861 <&mdss1_dp2_phy 1>; 6862 operating-points-v2 = <&mdss1_dp2_opp_table>; 6863 6864 #sound-dai-cells = <0>; 6865 6866 status = "disabled"; 6867 6868 ports { 6869 #address-cells = <1>; 6870 #size-cells = <0>; 6871 6872 port@0 { 6873 reg = <0>; 6874 mdss1_dp2_in: endpoint { 6875 remote-endpoint = <&mdss1_intf6_out>; 6876 }; 6877 }; 6878 6879 port@1 { 6880 reg = <1>; 6881 6882 mdss1_dp2_out: endpoint { 6883 }; 6884 }; 6885 }; 6886 6887 mdss1_dp2_opp_table: opp-table { 6888 compatible = "operating-points-v2"; 6889 6890 opp-162000000 { 6891 opp-hz = /bits/ 64 <162000000>; 6892 required-opps = <&rpmhpd_opp_low_svs>; 6893 }; 6894 6895 opp-270000000 { 6896 opp-hz = /bits/ 64 <270000000>; 6897 required-opps = <&rpmhpd_opp_svs>; 6898 }; 6899 6900 opp-540000000 { 6901 opp-hz = /bits/ 64 <540000000>; 6902 required-opps = <&rpmhpd_opp_svs_l1>; 6903 }; 6904 6905 opp-810000000 { 6906 opp-hz = /bits/ 64 <810000000>; 6907 required-opps = <&rpmhpd_opp_nom>; 6908 }; 6909 }; 6910 }; 6911 6912 mdss1_dp3: displayport-controller@220a0000 { 6913 compatible = "qcom,sc8280xp-dp"; 6914 reg = <0 0x220a0000 0 0x200>, 6915 <0 0x220a0200 0 0x200>, 6916 <0 0x220a0400 0 0x600>, 6917 <0 0x220a1000 0 0x400>, 6918 <0 0x220a1400 0 0x400>; 6919 6920 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6921 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 6922 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 6923 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 6924 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 6925 clock-names = "core_iface", "core_aux", 6926 "ctrl_link", 6927 "ctrl_link_iface", "stream_pixel"; 6928 interrupt-parent = <&mdss1>; 6929 interrupts = <15>; 6930 phys = <&mdss1_dp3_phy>; 6931 phy-names = "dp"; 6932 power-domains = <&rpmhpd SC8280XP_MMCX>; 6933 6934 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 6935 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 6936 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 6937 operating-points-v2 = <&mdss1_dp3_opp_table>; 6938 6939 #sound-dai-cells = <0>; 6940 6941 status = "disabled"; 6942 6943 ports { 6944 #address-cells = <1>; 6945 #size-cells = <0>; 6946 6947 port@0 { 6948 reg = <0>; 6949 mdss1_dp3_in: endpoint { 6950 remote-endpoint = <&mdss1_intf5_out>; 6951 }; 6952 }; 6953 6954 port@1 { 6955 reg = <1>; 6956 6957 mdss1_dp3_out: endpoint { 6958 }; 6959 }; 6960 }; 6961 6962 mdss1_dp3_opp_table: opp-table { 6963 compatible = "operating-points-v2"; 6964 6965 opp-162000000 { 6966 opp-hz = /bits/ 64 <162000000>; 6967 required-opps = <&rpmhpd_opp_low_svs>; 6968 }; 6969 6970 opp-270000000 { 6971 opp-hz = /bits/ 64 <270000000>; 6972 required-opps = <&rpmhpd_opp_svs>; 6973 }; 6974 6975 opp-540000000 { 6976 opp-hz = /bits/ 64 <540000000>; 6977 required-opps = <&rpmhpd_opp_svs_l1>; 6978 }; 6979 6980 opp-810000000 { 6981 opp-hz = /bits/ 64 <810000000>; 6982 required-opps = <&rpmhpd_opp_nom>; 6983 }; 6984 }; 6985 }; 6986 }; 6987 6988 mdss1_dp2_phy: phy@220c2a00 { 6989 compatible = "qcom,sc8280xp-dp-phy"; 6990 reg = <0 0x220c2a00 0 0x19c>, 6991 <0 0x220c2200 0 0xec>, 6992 <0 0x220c2600 0 0xec>, 6993 <0 0x220c2000 0 0x1c8>; 6994 6995 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 6996 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 6997 clock-names = "aux", "cfg_ahb"; 6998 power-domains = <&rpmhpd SC8280XP_MX>; 6999 7000 #clock-cells = <1>; 7001 #phy-cells = <0>; 7002 7003 status = "disabled"; 7004 }; 7005 7006 mdss1_dp3_phy: phy@220c5a00 { 7007 compatible = "qcom,sc8280xp-dp-phy"; 7008 reg = <0 0x220c5a00 0 0x19c>, 7009 <0 0x220c5200 0 0xec>, 7010 <0 0x220c5600 0 0xec>, 7011 <0 0x220c5000 0 0x1c8>; 7012 7013 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 7014 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 7015 clock-names = "aux", "cfg_ahb"; 7016 power-domains = <&rpmhpd SC8280XP_MX>; 7017 7018 #clock-cells = <1>; 7019 #phy-cells = <0>; 7020 7021 status = "disabled"; 7022 }; 7023 7024 dispcc1: clock-controller@22100000 { 7025 compatible = "qcom,sc8280xp-dispcc1"; 7026 reg = <0 0x22100000 0 0x20000>; 7027 7028 clocks = <&gcc GCC_DISP_AHB_CLK>, 7029 <&rpmhcc RPMH_CXO_CLK>, 7030 <0>, 7031 <&mdss1_dp0_phy 0>, 7032 <&mdss1_dp0_phy 1>, 7033 <&mdss1_dp1_phy 0>, 7034 <&mdss1_dp1_phy 1>, 7035 <&mdss1_dp2_phy 0>, 7036 <&mdss1_dp2_phy 1>, 7037 <&mdss1_dp3_phy 0>, 7038 <&mdss1_dp3_phy 1>, 7039 <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>, 7040 <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>, 7041 <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, 7042 <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; 7043 power-domains = <&rpmhpd SC8280XP_MMCX>; 7044 7045 #clock-cells = <1>; 7046 #power-domain-cells = <1>; 7047 #reset-cells = <1>; 7048 7049 status = "disabled"; 7050 }; 7051 7052 ethernet1: ethernet@23000000 { 7053 compatible = "qcom,sc8280xp-ethqos"; 7054 reg = <0x0 0x23000000 0x0 0x10000>, 7055 <0x0 0x23016000 0x0 0x100>; 7056 reg-names = "stmmaceth", "rgmii"; 7057 7058 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 7059 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 7060 <&gcc GCC_EMAC1_PTP_CLK>, 7061 <&gcc GCC_EMAC1_RGMII_CLK>; 7062 clock-names = "stmmaceth", 7063 "pclk", 7064 "ptp_ref", 7065 "rgmii"; 7066 7067 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 7068 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 7069 interrupt-names = "macirq", "eth_lpi"; 7070 7071 iommus = <&apps_smmu 0x40 0xf>; 7072 power-domains = <&gcc EMAC_1_GDSC>; 7073 7074 snps,tso; 7075 snps,pbl = <32>; 7076 rx-fifo-depth = <4096>; 7077 tx-fifo-depth = <4096>; 7078 7079 status = "disabled"; 7080 }; 7081 }; 7082 7083 sound: sound { 7084 }; 7085 7086 thermal-zones { 7087 cpu0-thermal { 7088 thermal-sensors = <&tsens0 1>; 7089 7090 trips { 7091 cpu-crit { 7092 temperature = <110000>; 7093 hysteresis = <1000>; 7094 type = "critical"; 7095 }; 7096 }; 7097 }; 7098 7099 cpu1-thermal { 7100 thermal-sensors = <&tsens0 2>; 7101 7102 trips { 7103 cpu-crit { 7104 temperature = <110000>; 7105 hysteresis = <1000>; 7106 type = "critical"; 7107 }; 7108 }; 7109 }; 7110 7111 cpu2-thermal { 7112 thermal-sensors = <&tsens0 3>; 7113 7114 trips { 7115 cpu-crit { 7116 temperature = <110000>; 7117 hysteresis = <1000>; 7118 type = "critical"; 7119 }; 7120 }; 7121 }; 7122 7123 cpu3-thermal { 7124 thermal-sensors = <&tsens0 4>; 7125 7126 trips { 7127 cpu-crit { 7128 temperature = <110000>; 7129 hysteresis = <1000>; 7130 type = "critical"; 7131 }; 7132 }; 7133 }; 7134 7135 cpu4-thermal { 7136 thermal-sensors = <&tsens0 5>; 7137 7138 trips { 7139 cpu-crit { 7140 temperature = <110000>; 7141 hysteresis = <1000>; 7142 type = "critical"; 7143 }; 7144 }; 7145 }; 7146 7147 cpu5-thermal { 7148 thermal-sensors = <&tsens0 6>; 7149 7150 trips { 7151 cpu-crit { 7152 temperature = <110000>; 7153 hysteresis = <1000>; 7154 type = "critical"; 7155 }; 7156 }; 7157 }; 7158 7159 cpu6-thermal { 7160 thermal-sensors = <&tsens0 7>; 7161 7162 trips { 7163 cpu-crit { 7164 temperature = <110000>; 7165 hysteresis = <1000>; 7166 type = "critical"; 7167 }; 7168 }; 7169 }; 7170 7171 cpu7-thermal { 7172 thermal-sensors = <&tsens0 8>; 7173 7174 trips { 7175 cpu-crit { 7176 temperature = <110000>; 7177 hysteresis = <1000>; 7178 type = "critical"; 7179 }; 7180 }; 7181 }; 7182 7183 cluster0-thermal { 7184 thermal-sensors = <&tsens0 9>; 7185 7186 trips { 7187 cpu-crit { 7188 temperature = <110000>; 7189 hysteresis = <1000>; 7190 type = "critical"; 7191 }; 7192 }; 7193 }; 7194 7195 gpu-thermal { 7196 polling-delay-passive = <250>; 7197 7198 thermal-sensors = <&tsens2 2>; 7199 7200 cooling-maps { 7201 map0 { 7202 trip = <&gpu_alert0>; 7203 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7204 }; 7205 }; 7206 7207 trips { 7208 gpu_alert0: trip-point0 { 7209 temperature = <85000>; 7210 hysteresis = <1000>; 7211 type = "passive"; 7212 }; 7213 7214 trip-point1 { 7215 temperature = <110000>; 7216 hysteresis = <1000>; 7217 type = "critical"; 7218 }; 7219 }; 7220 }; 7221 7222 mem-thermal { 7223 thermal-sensors = <&tsens1 15>; 7224 7225 trips { 7226 trip-point0 { 7227 temperature = <90000>; 7228 hysteresis = <2000>; 7229 type = "hot"; 7230 }; 7231 }; 7232 }; 7233 }; 7234 7235 timer { 7236 compatible = "arm,armv8-timer"; 7237 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 7238 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 7239 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 7240 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 7241 }; 7242}; 7243