1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #ifndef __MT76_CONNAC_MCU_H
5 #define __MT76_CONNAC_MCU_H
6
7 #include "mt76_connac.h"
8
9 #define FW_FEATURE_SET_ENCRYPT BIT(0)
10 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1)
11 #define FW_FEATURE_ENCRY_MODE BIT(4)
12 #define FW_FEATURE_OVERRIDE_ADDR BIT(5)
13 #define FW_FEATURE_NON_DL BIT(6)
14
15 #define DL_MODE_ENCRYPT BIT(0)
16 #define DL_MODE_KEY_IDX GENMASK(2, 1)
17 #define DL_MODE_RESET_SEC_IV BIT(3)
18 #define DL_MODE_WORKING_PDA_CR4 BIT(4)
19 #define DL_MODE_VALID_RAM_ENTRY BIT(5)
20 #define DL_CONFIG_ENCRY_MODE_SEL BIT(6)
21 #define DL_MODE_NEED_RSP BIT(31)
22
23 #define FW_START_OVERRIDE BIT(0)
24 #define FW_START_WORKING_PDA_CR4 BIT(2)
25 #define FW_START_WORKING_PDA_DSP BIT(3)
26
27 #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0)
28 #define PATCH_SEC_TYPE_MASK GENMASK(15, 0)
29 #define PATCH_SEC_TYPE_INFO 0x2
30
31 #define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24)
32 #define PATCH_SEC_ENC_TYPE_PLAIN 0x00
33 #define PATCH_SEC_ENC_TYPE_AES 0x01
34 #define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02
35 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0)
36 #define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0)
37
38 enum {
39 FW_TYPE_DEFAULT = 0,
40 FW_TYPE_CLC = 2,
41 FW_TYPE_MAX_NUM = 255
42 };
43
44 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
45 #define MCU_PKT_ID 0xa0
46
47 struct mt76_connac2_mcu_txd {
48 __le32 txd[8];
49
50 __le16 len;
51 __le16 pq_id;
52
53 u8 cid;
54 u8 pkt_type;
55 u8 set_query; /* FW don't care */
56 u8 seq;
57
58 u8 uc_d2b0_rev;
59 u8 ext_cid;
60 u8 s2d_index;
61 u8 ext_cid_ack;
62
63 u32 rsv[5];
64 } __packed __aligned(4);
65
66 /**
67 * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for connac2 and connac3
68 * @txd: hardware descriptor
69 * @len: total length not including txd
70 * @cid: command identifier
71 * @pkt_type: must be 0xa0 (cmd packet by long format)
72 * @frag_n: fragment number
73 * @seq: sequence number
74 * @checksum: 0 mean there is no checksum
75 * @s2d_index: index for command source and destination
76 * Definition | value | note
77 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM
78 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM
79 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA
80 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM
81 *
82 * @option: command option
83 * BIT[0]: UNI_CMD_OPT_BIT_ACK
84 * set to 1 to request a fw reply
85 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY
86 * is set, mcu firmware will send response event EID = 0x01
87 * (UNI_EVENT_ID_CMD_RESULT) to the host.
88 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD
89 * 0: original command
90 * 1: unified command
91 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY
92 * 0: QUERY command
93 * 1: SET command
94 */
95 struct mt76_connac2_mcu_uni_txd {
96 __le32 txd[8];
97
98 /* DW1 */
99 __le16 len;
100 __le16 cid;
101
102 /* DW2 */
103 u8 rsv;
104 u8 pkt_type;
105 u8 frag_n;
106 u8 seq;
107
108 /* DW3 */
109 __le16 checksum;
110 u8 s2d_index;
111 u8 option;
112
113 /* DW4 */
114 u8 rsv1[4];
115 } __packed __aligned(4);
116
117 struct mt76_connac2_mcu_rxd {
118 /* New members MUST be added within the struct_group() macro below. */
119 struct_group_tagged(mt76_connac2_mcu_rxd_hdr, hdr,
120 __le32 rxd[6];
121
122 __le16 len;
123 __le16 pkt_type_id;
124
125 u8 eid;
126 u8 seq;
127 u8 option;
128 u8 rsv;
129 u8 ext_eid;
130 u8 rsv1[2];
131 u8 s2d_index;
132 );
133
134 #if defined(__linux__)
135 u8 tlv[];
136 #elif defined(__FreeBSD__)
137 u8 tlv[0];
138 #endif
139 };
140 static_assert(offsetof(struct mt76_connac2_mcu_rxd, tlv) == sizeof(struct mt76_connac2_mcu_rxd_hdr),
141 "struct member likely outside of struct_group_tagged()");
142
143 struct mt76_connac2_patch_hdr {
144 char build_date[16];
145 char platform[4];
146 __be32 hw_sw_ver;
147 __be32 patch_ver;
148 __be16 checksum;
149 u16 rsv;
150 struct {
151 __be32 patch_ver;
152 __be32 subsys;
153 __be32 feature;
154 __be32 n_region;
155 __be32 crc;
156 u32 rsv[11];
157 } desc;
158 } __packed;
159
160 struct mt76_connac2_patch_sec {
161 __be32 type;
162 __be32 offs;
163 __be32 size;
164 union {
165 __be32 spec[13];
166 struct {
167 __be32 addr;
168 __be32 len;
169 __be32 sec_key_idx;
170 __be32 align_len;
171 u32 rsv[9];
172 } info;
173 };
174 } __packed;
175
176 struct mt76_connac2_fw_trailer {
177 u8 chip_id;
178 u8 eco_code;
179 u8 n_region;
180 u8 format_ver;
181 u8 format_flag;
182 u8 rsv[2];
183 char fw_ver[10];
184 char build_date[15];
185 __le32 crc;
186 } __packed;
187
188 struct mt76_connac2_fw_region {
189 __le32 decomp_crc;
190 __le32 decomp_len;
191 __le32 decomp_blk_sz;
192 u8 rsv[4];
193 __le32 addr;
194 __le32 len;
195 u8 feature_set;
196 u8 type;
197 u8 rsv1[14];
198 } __packed;
199
200 struct tlv {
201 __le16 tag;
202 __le16 len;
203 u8 data[];
204 } __packed;
205
206 struct bss_info_omac {
207 __le16 tag;
208 __le16 len;
209 u8 hw_bss_idx;
210 u8 omac_idx;
211 u8 band_idx;
212 u8 rsv0;
213 __le32 conn_type;
214 u32 rsv1;
215 } __packed;
216
217 struct bss_info_basic {
218 __le16 tag;
219 __le16 len;
220 __le32 network_type;
221 u8 active;
222 u8 rsv0;
223 __le16 bcn_interval;
224 u8 bssid[ETH_ALEN];
225 u8 wmm_idx;
226 u8 dtim_period;
227 u8 bmc_wcid_lo;
228 u8 cipher;
229 u8 phy_mode;
230 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
231 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
232 u8 bmc_wcid_hi; /* high Byte and version */
233 u8 rsv[2];
234 } __packed;
235
236 struct bss_info_rf_ch {
237 __le16 tag;
238 __le16 len;
239 u8 pri_ch;
240 u8 center_ch0;
241 u8 center_ch1;
242 u8 bw;
243 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */
244 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */
245 u8 rsv[2];
246 } __packed;
247
248 struct bss_info_ext_bss {
249 __le16 tag;
250 __le16 len;
251 __le32 mbss_tsf_offset; /* in unit of us */
252 u8 rsv[8];
253 } __packed;
254
255 enum {
256 BSS_INFO_OMAC,
257 BSS_INFO_BASIC,
258 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
259 BSS_INFO_PM, /* sta only */
260 BSS_INFO_UAPSD, /* sta only */
261 BSS_INFO_ROAM_DETECT, /* obsoleted */
262 BSS_INFO_LQ_RM, /* obsoleted */
263 BSS_INFO_EXT_BSS,
264 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */
265 BSS_INFO_SYNC_MODE, /* obsoleted */
266 BSS_INFO_RA,
267 BSS_INFO_HW_AMSDU,
268 BSS_INFO_BSS_COLOR,
269 BSS_INFO_HE_BASIC,
270 BSS_INFO_PROTECT_INFO,
271 BSS_INFO_OFFLOAD,
272 BSS_INFO_11V_MBSSID,
273 BSS_INFO_MAX_NUM
274 };
275
276 /* sta_rec */
277
278 struct sta_ntlv_hdr {
279 u8 rsv[2];
280 __le16 tlv_num;
281 } __packed;
282
283 struct sta_req_hdr {
284 u8 bss_idx;
285 u8 wlan_idx_lo;
286 __le16 tlv_num;
287 u8 is_tlv_append;
288 u8 muar_idx;
289 u8 wlan_idx_hi;
290 u8 rsv;
291 } __packed;
292
293 struct sta_rec_basic {
294 __le16 tag;
295 __le16 len;
296 __le32 conn_type;
297 u8 conn_state;
298 u8 qos;
299 __le16 aid;
300 u8 peer_addr[ETH_ALEN];
301 #define EXTRA_INFO_VER BIT(0)
302 #define EXTRA_INFO_NEW BIT(1)
303 __le16 extra_info;
304 } __packed;
305
306 struct sta_rec_ht {
307 __le16 tag;
308 __le16 len;
309 __le16 ht_cap;
310 u16 rsv;
311 } __packed;
312
313 struct sta_rec_vht {
314 __le16 tag;
315 __le16 len;
316 __le32 vht_cap;
317 __le16 vht_rx_mcs_map;
318 __le16 vht_tx_mcs_map;
319 /* mt7915 - mt7921 */
320 u8 rts_bw_sig;
321 u8 rsv[3];
322 } __packed;
323
324 struct sta_rec_uapsd {
325 __le16 tag;
326 __le16 len;
327 u8 dac_map;
328 u8 tac_map;
329 u8 max_sp;
330 u8 rsv0;
331 __le16 listen_interval;
332 u8 rsv1[2];
333 } __packed;
334
335 struct sta_rec_ba {
336 __le16 tag;
337 __le16 len;
338 u8 tid;
339 u8 ba_type;
340 u8 amsdu;
341 u8 ba_en;
342 __le16 ssn;
343 __le16 winsize;
344 } __packed;
345
346 struct sta_rec_he {
347 __le16 tag;
348 __le16 len;
349
350 __le32 he_cap;
351
352 u8 t_frame_dur;
353 u8 max_ampdu_exp;
354 u8 bw_set;
355 u8 device_class;
356 u8 dcm_tx_mode;
357 u8 dcm_tx_max_nss;
358 u8 dcm_rx_mode;
359 u8 dcm_rx_max_nss;
360 u8 dcm_max_ru;
361 u8 punc_pream_rx;
362 u8 pkt_ext;
363 u8 rsv1;
364
365 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
366
367 u8 rsv2[2];
368 } __packed;
369
370 struct sta_rec_he_v2 {
371 __le16 tag;
372 __le16 len;
373 u8 he_mac_cap[6];
374 u8 he_phy_cap[11];
375 u8 pkt_ext;
376 /* 0: BW80, 1: BW160, 2: BW8080 */
377 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
378 } __packed;
379
380 struct sta_rec_amsdu {
381 __le16 tag;
382 __le16 len;
383 u8 max_amsdu_num;
384 u8 max_mpdu_size;
385 u8 amsdu_en;
386 u8 rsv;
387 } __packed;
388
389 struct sta_rec_state {
390 __le16 tag;
391 __le16 len;
392 __le32 flags;
393 u8 state;
394 u8 vht_opmode;
395 u8 action;
396 u8 rsv[1];
397 } __packed;
398
399 #define RA_LEGACY_OFDM GENMASK(13, 6)
400 #define RA_LEGACY_CCK GENMASK(3, 0)
401 #define HT_MCS_MASK_NUM 10
402 struct sta_rec_ra_info {
403 __le16 tag;
404 __le16 len;
405 __le16 legacy;
406 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
407 } __packed;
408
409 struct sta_rec_phy {
410 __le16 tag;
411 __le16 len;
412 __le16 basic_rate;
413 u8 phy_type;
414 u8 ampdu;
415 u8 rts_policy;
416 u8 rcpi;
417 u8 max_ampdu_len; /* connac3 */
418 u8 rsv[1];
419 } __packed;
420
421 struct sta_rec_he_6g_capa {
422 __le16 tag;
423 __le16 len;
424 __le16 capa;
425 u8 rsv[2];
426 } __packed;
427
428 struct sta_rec_pn_info {
429 __le16 tag;
430 __le16 len;
431 u8 pn[6];
432 u8 tsc_type;
433 u8 rsv;
434 } __packed;
435
436 struct sec_key {
437 u8 cipher_id;
438 u8 cipher_len;
439 u8 key_id;
440 u8 key_len;
441 u8 key[32];
442 } __packed;
443
444 struct sta_rec_sec {
445 __le16 tag;
446 __le16 len;
447 u8 add;
448 u8 n_cipher;
449 u8 rsv[2];
450
451 struct sec_key key[2];
452 } __packed;
453
454 struct sta_rec_bf {
455 __le16 tag;
456 __le16 len;
457
458 __le16 pfmu; /* 0xffff: no access right for PFMU */
459 bool su_mu; /* 0: SU, 1: MU */
460 u8 bf_cap; /* 0: iBF, 1: eBF */
461 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
462 u8 ndpa_rate;
463 u8 ndp_rate;
464 u8 rept_poll_rate;
465 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
466 u8 ncol;
467 u8 nrow;
468 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
469
470 u8 mem_total;
471 u8 mem_20m;
472 struct {
473 u8 row;
474 u8 col: 6, row_msb: 2;
475 } mem[4];
476
477 __le16 smart_ant;
478 u8 se_idx;
479 u8 auto_sounding; /* b7: low traffic indicator
480 * b6: Stop sounding for this entry
481 * b5 ~ b0: postpone sounding
482 */
483 u8 ibf_timeout;
484 u8 ibf_dbw;
485 u8 ibf_ncol;
486 u8 ibf_nrow;
487 u8 nrow_gt_bw80;
488 u8 ncol_gt_bw80;
489 u8 ru_start_idx;
490 u8 ru_end_idx;
491
492 bool trigger_su;
493 bool trigger_mu;
494 bool ng16_su;
495 bool ng16_mu;
496 bool codebook42_su;
497 bool codebook75_mu;
498
499 u8 he_ltf;
500 u8 rsv[3];
501 } __packed;
502
503 struct sta_rec_bfee {
504 __le16 tag;
505 __le16 len;
506 bool fb_identity_matrix; /* 1: feedback identity matrix */
507 bool ignore_feedback; /* 1: ignore */
508 u8 rsv[2];
509 } __packed;
510
511 struct sta_rec_muru {
512 __le16 tag;
513 __le16 len;
514
515 struct {
516 bool ofdma_dl_en;
517 bool ofdma_ul_en;
518 bool mimo_dl_en;
519 bool mimo_ul_en;
520 u8 rsv[4];
521 } cfg;
522
523 struct {
524 u8 punc_pream_rx;
525 bool he_20m_in_40m_2g;
526 bool he_20m_in_160m;
527 bool he_80m_in_160m;
528 bool lt16_sigb;
529 bool rx_su_comp_sigb;
530 bool rx_su_non_comp_sigb;
531 u8 rsv;
532 } ofdma_dl;
533
534 struct {
535 u8 t_frame_dur;
536 u8 mu_cascading;
537 u8 uo_ra;
538 u8 he_2x996_tone;
539 u8 rx_t_frame_11ac;
540 u8 rx_ctrl_frame_to_mbss;
541 u8 rsv[2];
542 } ofdma_ul;
543
544 struct {
545 bool vht_mu_bfee;
546 bool partial_bw_dl_mimo;
547 u8 rsv[2];
548 } mimo_dl;
549
550 struct {
551 bool full_ul_mimo;
552 bool partial_ul_mimo;
553 u8 rsv[2];
554 } mimo_ul;
555 } __packed;
556
557 struct sta_rec_remove {
558 __le16 tag;
559 __le16 len;
560 u8 action;
561 u8 pad[3];
562 } __packed;
563
564 struct sta_phy {
565 u8 type;
566 u8 flag;
567 u8 stbc;
568 u8 sgi;
569 u8 bw;
570 u8 ldpc;
571 u8 mcs;
572 u8 nss;
573 u8 he_ltf;
574 };
575
576 struct sta_rec_ra {
577 __le16 tag;
578 __le16 len;
579
580 u8 valid;
581 u8 auto_rate;
582 u8 phy_mode;
583 u8 channel;
584 u8 bw;
585 u8 disable_cck;
586 u8 ht_mcs32;
587 u8 ht_gf;
588 u8 ht_mcs[4];
589 u8 mmps_mode;
590 u8 gband_256;
591 u8 af;
592 u8 auth_wapi_mode;
593 u8 rate_len;
594
595 u8 supp_mode;
596 u8 supp_cck_rate;
597 u8 supp_ofdm_rate;
598 __le32 supp_ht_mcs;
599 __le16 supp_vht_mcs[4];
600
601 u8 op_mode;
602 u8 op_vht_chan_width;
603 u8 op_vht_rx_nss;
604 u8 op_vht_rx_nss_type;
605
606 __le32 sta_cap;
607
608 struct sta_phy phy;
609 } __packed;
610
611 struct sta_rec_ra_fixed {
612 __le16 tag;
613 __le16 len;
614
615 __le32 field;
616 u8 op_mode;
617 u8 op_vht_chan_width;
618 u8 op_vht_rx_nss;
619 u8 op_vht_rx_nss_type;
620
621 struct sta_phy phy;
622
623 u8 spe_idx;
624 u8 short_preamble;
625 u8 is_5g;
626 u8 mmps_mode;
627 } __packed;
628
629 struct sta_rec_tx_proc {
630 __le16 tag;
631 __le16 len;
632 __le32 flag;
633 } __packed;
634
635 /* wtbl_rec */
636
637 struct wtbl_req_hdr {
638 u8 wlan_idx_lo;
639 u8 operation;
640 __le16 tlv_num;
641 u8 wlan_idx_hi;
642 u8 rsv[3];
643 } __packed;
644
645 struct wtbl_generic {
646 __le16 tag;
647 __le16 len;
648 u8 peer_addr[ETH_ALEN];
649 u8 muar_idx;
650 u8 skip_tx;
651 u8 cf_ack;
652 u8 qos;
653 u8 mesh;
654 u8 adm;
655 __le16 partial_aid;
656 u8 baf_en;
657 u8 aad_om;
658 } __packed;
659
660 struct wtbl_rx {
661 __le16 tag;
662 __le16 len;
663 u8 rcid;
664 u8 rca1;
665 u8 rca2;
666 u8 rv;
667 u8 rsv[4];
668 } __packed;
669
670 struct wtbl_ht {
671 __le16 tag;
672 __le16 len;
673 u8 ht;
674 u8 ldpc;
675 u8 af;
676 u8 mm;
677 u8 rsv[4];
678 } __packed;
679
680 struct wtbl_vht {
681 __le16 tag;
682 __le16 len;
683 u8 ldpc;
684 u8 dyn_bw;
685 u8 vht;
686 u8 txop_ps;
687 u8 rsv[4];
688 } __packed;
689
690 struct wtbl_tx_ps {
691 __le16 tag;
692 __le16 len;
693 u8 txps;
694 u8 rsv[3];
695 } __packed;
696
697 struct wtbl_hdr_trans {
698 __le16 tag;
699 __le16 len;
700 u8 to_ds;
701 u8 from_ds;
702 u8 no_rx_trans;
703 u8 rsv;
704 } __packed;
705
706 struct wtbl_ba {
707 __le16 tag;
708 __le16 len;
709 /* common */
710 u8 tid;
711 u8 ba_type;
712 u8 rsv0[2];
713 /* originator only */
714 __le16 sn;
715 u8 ba_en;
716 u8 ba_winsize_idx;
717 /* originator & recipient */
718 __le16 ba_winsize;
719 /* recipient only */
720 u8 peer_addr[ETH_ALEN];
721 u8 rst_ba_tid;
722 u8 rst_ba_sel;
723 u8 rst_ba_sb;
724 u8 band_idx;
725 u8 rsv1[4];
726 } __packed;
727
728 struct wtbl_smps {
729 __le16 tag;
730 __le16 len;
731 u8 smps;
732 u8 rsv[3];
733 } __packed;
734
735 /* mt7615 only */
736
737 struct wtbl_bf {
738 __le16 tag;
739 __le16 len;
740 u8 ibf;
741 u8 ebf;
742 u8 ibf_vht;
743 u8 ebf_vht;
744 u8 gid;
745 u8 pfmu_idx;
746 u8 rsv[2];
747 } __packed;
748
749 struct wtbl_pn {
750 __le16 tag;
751 __le16 len;
752 u8 pn[6];
753 u8 rsv[2];
754 } __packed;
755
756 struct wtbl_spe {
757 __le16 tag;
758 __le16 len;
759 u8 spe_idx;
760 u8 rsv[3];
761 } __packed;
762
763 struct wtbl_raw {
764 __le16 tag;
765 __le16 len;
766 u8 wtbl_idx;
767 u8 dw;
768 u8 rsv[2];
769 __le32 msk;
770 __le32 val;
771 } __packed;
772
773 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
774 sizeof(struct wtbl_generic) + \
775 sizeof(struct wtbl_rx) + \
776 sizeof(struct wtbl_ht) + \
777 sizeof(struct wtbl_vht) + \
778 sizeof(struct wtbl_tx_ps) + \
779 sizeof(struct wtbl_hdr_trans) +\
780 sizeof(struct wtbl_ba) + \
781 sizeof(struct wtbl_bf) + \
782 sizeof(struct wtbl_smps) + \
783 sizeof(struct wtbl_pn) + \
784 sizeof(struct wtbl_spe))
785
786 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
787 sizeof(struct sta_rec_basic) + \
788 sizeof(struct sta_rec_bf) + \
789 sizeof(struct sta_rec_ht) + \
790 sizeof(struct sta_rec_he) + \
791 sizeof(struct sta_rec_ba) + \
792 sizeof(struct sta_rec_vht) + \
793 sizeof(struct sta_rec_uapsd) + \
794 sizeof(struct sta_rec_amsdu) + \
795 sizeof(struct sta_rec_muru) + \
796 sizeof(struct sta_rec_bfee) + \
797 sizeof(struct sta_rec_ra) + \
798 sizeof(struct sta_rec_sec) + \
799 sizeof(struct sta_rec_ra_fixed) + \
800 sizeof(struct sta_rec_he_6g_capa) + \
801 sizeof(struct sta_rec_pn_info) + \
802 sizeof(struct sta_rec_tx_proc) + \
803 sizeof(struct tlv) + \
804 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
805
806 enum {
807 STA_REC_BASIC,
808 STA_REC_RA,
809 STA_REC_RA_CMM_INFO,
810 STA_REC_RA_UPDATE,
811 STA_REC_BF,
812 STA_REC_AMSDU,
813 STA_REC_BA,
814 STA_REC_STATE,
815 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
816 STA_REC_HT,
817 STA_REC_VHT,
818 STA_REC_APPS,
819 STA_REC_KEY,
820 STA_REC_WTBL,
821 STA_REC_HE,
822 STA_REC_HW_AMSDU,
823 STA_REC_WTBL_AADOM,
824 STA_REC_KEY_V2,
825 STA_REC_MURU,
826 STA_REC_MUEDCA,
827 STA_REC_BFEE,
828 STA_REC_PHY = 0x15,
829 STA_REC_HE_6G = 0x17,
830 STA_REC_HE_V2 = 0x19,
831 STA_REC_MLD = 0x20,
832 STA_REC_EHT_MLD = 0x21,
833 STA_REC_EHT = 0x22,
834 STA_REC_MLD_OFF = 0x23,
835 STA_REC_REMOVE = 0x25,
836 STA_REC_PN_INFO = 0x26,
837 STA_REC_KEY_V3 = 0x27,
838 STA_REC_HDRT = 0x28,
839 STA_REC_HDR_TRANS = 0x2B,
840 STA_REC_MAX_NUM
841 };
842
843 enum {
844 WTBL_GENERIC,
845 WTBL_RX,
846 WTBL_HT,
847 WTBL_VHT,
848 WTBL_PEER_PS, /* not used */
849 WTBL_TX_PS,
850 WTBL_HDR_TRANS,
851 WTBL_SEC_KEY,
852 WTBL_BA,
853 WTBL_RDG, /* obsoleted */
854 WTBL_PROTECT, /* not used */
855 WTBL_CLEAR, /* not used */
856 WTBL_BF,
857 WTBL_SMPS,
858 WTBL_RAW_DATA, /* debug only */
859 WTBL_PN,
860 WTBL_SPE,
861 WTBL_MAX_NUM
862 };
863
864 #define STA_TYPE_STA BIT(0)
865 #define STA_TYPE_AP BIT(1)
866 #define STA_TYPE_ADHOC BIT(2)
867 #define STA_TYPE_WDS BIT(4)
868 #define STA_TYPE_BC BIT(5)
869
870 #define NETWORK_INFRA BIT(16)
871 #define NETWORK_P2P BIT(17)
872 #define NETWORK_IBSS BIT(18)
873 #define NETWORK_WDS BIT(21)
874
875 #define SCAN_FUNC_RANDOM_MAC BIT(0)
876 #define SCAN_FUNC_RNR_SCAN BIT(3)
877 #define SCAN_FUNC_SPLIT_SCAN BIT(5)
878
879 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
880 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
881 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
882 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
883 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
884 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
885 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
886
887 #define CONN_STATE_DISCONNECT 0
888 #define CONN_STATE_CONNECT 1
889 #define CONN_STATE_PORT_SECURE 2
890
891 /* HE MAC */
892 #define STA_REC_HE_CAP_HTC BIT(0)
893 #define STA_REC_HE_CAP_BQR BIT(1)
894 #define STA_REC_HE_CAP_BSR BIT(2)
895 #define STA_REC_HE_CAP_OM BIT(3)
896 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
897 /* HE PHY */
898 #define STA_REC_HE_CAP_DUAL_BAND BIT(5)
899 #define STA_REC_HE_CAP_LDPC BIT(6)
900 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
901 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
902 /* STBC */
903 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
904 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
905 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
906 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
907 /* GI */
908 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
909 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
910 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
911 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
912 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
913 /* 242 TONE */
914 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
915 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
916 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
917
918 #define PHY_MODE_A BIT(0)
919 #define PHY_MODE_B BIT(1)
920 #define PHY_MODE_G BIT(2)
921 #define PHY_MODE_GN BIT(3)
922 #define PHY_MODE_AN BIT(4)
923 #define PHY_MODE_AC BIT(5)
924 #define PHY_MODE_AX_24G BIT(6)
925 #define PHY_MODE_AX_5G BIT(7)
926
927 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */
928 #define PHY_MODE_BE_24G BIT(1)
929 #define PHY_MODE_BE_5G BIT(2)
930 #define PHY_MODE_BE_6G BIT(3)
931
932 #define MODE_CCK BIT(0)
933 #define MODE_OFDM BIT(1)
934 #define MODE_HT BIT(2)
935 #define MODE_VHT BIT(3)
936 #define MODE_HE BIT(4)
937 #define MODE_EHT BIT(5)
938
939 #define STA_CAP_WMM BIT(0)
940 #define STA_CAP_SGI_20 BIT(4)
941 #define STA_CAP_SGI_40 BIT(5)
942 #define STA_CAP_TX_STBC BIT(6)
943 #define STA_CAP_RX_STBC BIT(7)
944 #define STA_CAP_VHT_SGI_80 BIT(16)
945 #define STA_CAP_VHT_SGI_160 BIT(17)
946 #define STA_CAP_VHT_TX_STBC BIT(18)
947 #define STA_CAP_VHT_RX_STBC BIT(19)
948 #define STA_CAP_VHT_LDPC BIT(23)
949 #define STA_CAP_LDPC BIT(24)
950 #define STA_CAP_HT BIT(26)
951 #define STA_CAP_VHT BIT(27)
952 #define STA_CAP_HE BIT(28)
953
954 enum {
955 PHY_TYPE_HR_DSSS_INDEX = 0,
956 PHY_TYPE_ERP_INDEX,
957 PHY_TYPE_ERP_P2P_INDEX,
958 PHY_TYPE_OFDM_INDEX,
959 PHY_TYPE_HT_INDEX,
960 PHY_TYPE_VHT_INDEX,
961 PHY_TYPE_HE_INDEX,
962 PHY_TYPE_BE_INDEX,
963 PHY_TYPE_INDEX_NUM
964 };
965
966 #define HR_DSSS_ERP_BASIC_RATE GENMASK(3, 0)
967 #define OFDM_BASIC_RATE (BIT(6) | BIT(8) | BIT(10))
968
969 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX)
970 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX)
971 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX)
972 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX)
973 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX)
974 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX)
975 #define PHY_TYPE_BIT_BE BIT(PHY_TYPE_BE_INDEX)
976
977 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6)
978 #define MT_WTBL_RATE_MCS GENMASK(5, 0)
979 #define MT_WTBL_RATE_NSS GENMASK(12, 10)
980 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4)
981 #define MT_WTBL_RATE_GI GENMASK(3, 0)
982
983 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
984 #define MT_WTBL_W5_SHORT_GI_20 BIT(8)
985 #define MT_WTBL_W5_SHORT_GI_40 BIT(9)
986 #define MT_WTBL_W5_SHORT_GI_80 BIT(10)
987 #define MT_WTBL_W5_SHORT_GI_160 BIT(11)
988 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
989 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
990 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
991 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
992
993 enum {
994 WTBL_RESET_AND_SET = 1,
995 WTBL_SET,
996 WTBL_QUERY,
997 WTBL_RESET_ALL
998 };
999
1000 enum {
1001 MT_BA_TYPE_INVALID,
1002 MT_BA_TYPE_ORIGINATOR,
1003 MT_BA_TYPE_RECIPIENT
1004 };
1005
1006 enum {
1007 RST_BA_MAC_TID_MATCH,
1008 RST_BA_MAC_MATCH,
1009 RST_BA_NO_MATCH
1010 };
1011
1012 enum {
1013 DEV_INFO_ACTIVE,
1014 DEV_INFO_MAX_NUM
1015 };
1016
1017 /* event table */
1018 enum {
1019 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
1020 MCU_EVENT_FW_START = 0x01,
1021 MCU_EVENT_GENERIC = 0x01,
1022 MCU_EVENT_ACCESS_REG = 0x02,
1023 MCU_EVENT_MT_PATCH_SEM = 0x04,
1024 MCU_EVENT_REG_ACCESS = 0x05,
1025 MCU_EVENT_LP_INFO = 0x07,
1026 MCU_EVENT_SCAN_DONE = 0x0d,
1027 MCU_EVENT_TX_DONE = 0x0f,
1028 MCU_EVENT_ROC = 0x10,
1029 MCU_EVENT_BSS_ABSENCE = 0x11,
1030 MCU_EVENT_BSS_BEACON_LOSS = 0x13,
1031 MCU_EVENT_CH_PRIVILEGE = 0x18,
1032 MCU_EVENT_SCHED_SCAN_DONE = 0x23,
1033 MCU_EVENT_DBG_MSG = 0x27,
1034 MCU_EVENT_RSSI_NOTIFY = 0x96,
1035 MCU_EVENT_TXPWR = 0xd0,
1036 MCU_EVENT_EXT = 0xed,
1037 MCU_EVENT_RESTART_DL = 0xef,
1038 MCU_EVENT_COREDUMP = 0xf0,
1039 };
1040
1041 /* ext event table */
1042 enum {
1043 MCU_EXT_EVENT_PS_SYNC = 0x5,
1044 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
1045 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
1046 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
1047 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
1048 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
1049 MCU_EXT_EVENT_WA_TX_STAT = 0x74,
1050 MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
1051 MCU_EXT_EVENT_WF_RF_PIN_CTRL = 0x9a,
1052 MCU_EXT_EVENT_MURU_CTRL = 0x9f,
1053 };
1054
1055 /* unified event table */
1056 enum {
1057 MCU_UNI_EVENT_RESULT = 0x01,
1058 MCU_UNI_EVENT_HIF_CTRL = 0x03,
1059 MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04,
1060 MCU_UNI_EVENT_ACCESS_REG = 0x6,
1061 MCU_UNI_EVENT_IE_COUNTDOWN = 0x09,
1062 MCU_UNI_EVENT_COREDUMP = 0x0a,
1063 MCU_UNI_EVENT_BSS_BEACON_LOSS = 0x0c,
1064 MCU_UNI_EVENT_SCAN_DONE = 0x0e,
1065 MCU_UNI_EVENT_RDD_REPORT = 0x11,
1066 MCU_UNI_EVENT_ROC = 0x27,
1067 MCU_UNI_EVENT_TX_DONE = 0x2d,
1068 MCU_UNI_EVENT_THERMAL = 0x35,
1069 MCU_UNI_EVENT_RSSI_MONITOR = 0x41,
1070 MCU_UNI_EVENT_NIC_CAPAB = 0x43,
1071 MCU_UNI_EVENT_WED_RRO = 0x57,
1072 MCU_UNI_EVENT_PER_STA_INFO = 0x6d,
1073 MCU_UNI_EVENT_ALL_STA_INFO = 0x6e,
1074 MCU_UNI_EVENT_SDO = 0x83,
1075 };
1076
1077 #define MCU_UNI_CMD_EVENT BIT(1)
1078 #define MCU_UNI_CMD_UNSOLICITED_EVENT BIT(2)
1079
1080 enum {
1081 MCU_Q_QUERY,
1082 MCU_Q_SET,
1083 MCU_Q_RESERVED,
1084 MCU_Q_NA
1085 };
1086
1087 enum {
1088 MCU_S2D_H2N,
1089 MCU_S2D_C2N,
1090 MCU_S2D_H2C,
1091 MCU_S2D_H2CN
1092 };
1093
1094 enum {
1095 PATCH_NOT_DL_SEM_FAIL,
1096 PATCH_IS_DL,
1097 PATCH_NOT_DL_SEM_SUCCESS,
1098 PATCH_REL_SEM_SUCCESS
1099 };
1100
1101 enum {
1102 FW_STATE_INITIAL,
1103 FW_STATE_FW_DOWNLOAD,
1104 FW_STATE_NORMAL_OPERATION,
1105 FW_STATE_NORMAL_TRX,
1106 FW_STATE_RDY = 7
1107 };
1108
1109 enum {
1110 CH_SWITCH_NORMAL = 0,
1111 CH_SWITCH_SCAN = 3,
1112 CH_SWITCH_MCC = 4,
1113 CH_SWITCH_DFS = 5,
1114 CH_SWITCH_BACKGROUND_SCAN_START = 6,
1115 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1116 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1117 CH_SWITCH_SCAN_BYPASS_DPD = 9
1118 };
1119
1120 enum {
1121 THERMAL_SENSOR_TEMP_QUERY,
1122 THERMAL_SENSOR_MANUAL_CTRL,
1123 THERMAL_SENSOR_INFO_QUERY,
1124 THERMAL_SENSOR_TASK_CTRL,
1125 };
1126
1127 enum mcu_cipher_type {
1128 MCU_CIPHER_NONE = 0,
1129 MCU_CIPHER_WEP40,
1130 MCU_CIPHER_WEP104,
1131 MCU_CIPHER_WEP128,
1132 MCU_CIPHER_TKIP,
1133 MCU_CIPHER_AES_CCMP,
1134 MCU_CIPHER_CCMP_256,
1135 MCU_CIPHER_GCMP,
1136 MCU_CIPHER_GCMP_256,
1137 MCU_CIPHER_WAPI,
1138 MCU_CIPHER_BIP_CMAC_128,
1139 MCU_CIPHER_BIP_CMAC_256,
1140 MCU_CIPHER_BCN_PROT_CMAC_128,
1141 MCU_CIPHER_BCN_PROT_CMAC_256,
1142 MCU_CIPHER_BCN_PROT_GMAC_128,
1143 MCU_CIPHER_BCN_PROT_GMAC_256,
1144 MCU_CIPHER_BIP_GMAC_128,
1145 MCU_CIPHER_BIP_GMAC_256,
1146 };
1147
1148 enum {
1149 EE_MODE_EFUSE,
1150 EE_MODE_BUFFER,
1151 };
1152
1153 enum {
1154 EE_FORMAT_BIN,
1155 EE_FORMAT_WHOLE,
1156 EE_FORMAT_MULTIPLE,
1157 };
1158
1159 enum {
1160 MCU_PHY_STATE_TX_RATE,
1161 MCU_PHY_STATE_RX_RATE,
1162 MCU_PHY_STATE_RSSI,
1163 MCU_PHY_STATE_CONTENTION_RX_RATE,
1164 MCU_PHY_STATE_OFDMLQ_CNINFO,
1165 };
1166
1167 #define MCU_CMD_ACK BIT(0)
1168 #define MCU_CMD_UNI BIT(1)
1169 #define MCU_CMD_SET BIT(2)
1170
1171 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \
1172 MCU_CMD_SET)
1173 #define MCU_CMD_UNI_QUERY_ACK (MCU_CMD_ACK | MCU_CMD_UNI)
1174
1175 #define __MCU_CMD_FIELD_ID GENMASK(7, 0)
1176 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8)
1177 #define __MCU_CMD_FIELD_QUERY BIT(16)
1178 #define __MCU_CMD_FIELD_UNI BIT(17)
1179 #define __MCU_CMD_FIELD_CE BIT(18)
1180 #define __MCU_CMD_FIELD_WA BIT(19)
1181 #define __MCU_CMD_FIELD_WM BIT(20)
1182
1183 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \
1184 MCU_CMD_##_t)
1185 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \
1186 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1187 MCU_EXT_CMD_##_t))
1188 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1189 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \
1190 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1191 MCU_UNI_CMD_##_t))
1192
1193 #define MCU_UNI_QUERY(_t) (__MCU_CMD_FIELD_UNI | __MCU_CMD_FIELD_QUERY | \
1194 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1195 MCU_UNI_CMD_##_t))
1196
1197 #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \
1198 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1199 MCU_CE_CMD_##_t))
1200 #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1201
1202 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
1203 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
1204 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \
1205 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1206 MCU_WA_PARAM_CMD_##_t))
1207
1208 #define MCU_WM_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1209 __MCU_CMD_FIELD_WM)
1210 #define MCU_WM_UNI_CMD_QUERY(_t) (MCU_UNI_CMD(_t) | \
1211 __MCU_CMD_FIELD_QUERY | \
1212 __MCU_CMD_FIELD_WM)
1213 #define MCU_WA_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1214 __MCU_CMD_FIELD_WA)
1215 #define MCU_WMWA_UNI_CMD(_t) (MCU_WM_UNI_CMD(_t) | \
1216 __MCU_CMD_FIELD_WA)
1217
1218 enum {
1219 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
1220 MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
1221 MCU_EXT_CMD_RF_TEST = 0x04,
1222 MCU_EXT_CMD_ID_RADIO_ON_OFF_CTRL = 0x05,
1223 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
1224 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
1225 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
1226 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
1227 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
1228 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
1229 MCU_EXT_CMD_THERMAL_PROT = 0x23,
1230 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
1231 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
1232 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
1233 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
1234 MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
1235 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
1236 MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
1237 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
1238 MCU_EXT_CMD_ATE_CTRL = 0x3d,
1239 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
1240 MCU_EXT_CMD_DBDC_CTRL = 0x45,
1241 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
1242 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
1243 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
1244 MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
1245 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a,
1246 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
1247 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f,
1248 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
1249 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
1250 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
1251 MCU_EXT_CMD_TXDPD_CAL = 0x60,
1252 MCU_EXT_CMD_CAL_CACHE = 0x67,
1253 MCU_EXT_CMD_RED_ENABLE = 0x68,
1254 MCU_EXT_CMD_CP_SUPPORT = 0x75,
1255 MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
1256 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
1257 MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
1258 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
1259 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94,
1260 MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
1261 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
1262 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
1263 MCU_EXT_CMD_MURU_CTRL = 0x9f,
1264 MCU_EXT_CMD_SET_SPR = 0xa8,
1265 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
1266 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
1267 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
1268 MCU_EXT_CMD_WF_RF_PIN_CTRL = 0xbd,
1269 };
1270
1271 enum {
1272 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01,
1273 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02,
1274 MCU_UNI_CMD_STA_REC_UPDATE = 0x03,
1275 MCU_UNI_CMD_EDCA_UPDATE = 0x04,
1276 MCU_UNI_CMD_SUSPEND = 0x05,
1277 MCU_UNI_CMD_OFFLOAD = 0x06,
1278 MCU_UNI_CMD_HIF_CTRL = 0x07,
1279 MCU_UNI_CMD_BAND_CONFIG = 0x08,
1280 MCU_UNI_CMD_REPT_MUAR = 0x09,
1281 MCU_UNI_CMD_WSYS_CONFIG = 0x0b,
1282 MCU_UNI_CMD_REG_ACCESS = 0x0d,
1283 MCU_UNI_CMD_CHIP_CONFIG = 0x0e,
1284 MCU_UNI_CMD_POWER_CTRL = 0x0f,
1285 MCU_UNI_CMD_RX_HDR_TRANS = 0x12,
1286 MCU_UNI_CMD_SER = 0x13,
1287 MCU_UNI_CMD_TWT = 0x14,
1288 MCU_UNI_CMD_SET_DOMAIN_INFO = 0x15,
1289 MCU_UNI_CMD_SCAN_REQ = 0x16,
1290 MCU_UNI_CMD_RDD_CTRL = 0x19,
1291 MCU_UNI_CMD_GET_MIB_INFO = 0x22,
1292 MCU_UNI_CMD_GET_STAT_INFO = 0x23,
1293 MCU_UNI_CMD_SNIFFER = 0x24,
1294 MCU_UNI_CMD_SR = 0x25,
1295 MCU_UNI_CMD_ROC = 0x27,
1296 MCU_UNI_CMD_SET_DBDC_PARMS = 0x28,
1297 MCU_UNI_CMD_TXPOWER = 0x2b,
1298 MCU_UNI_CMD_SET_POWER_LIMIT = 0x2c,
1299 MCU_UNI_CMD_EFUSE_CTRL = 0x2d,
1300 MCU_UNI_CMD_RA = 0x2f,
1301 MCU_UNI_CMD_MURU = 0x31,
1302 MCU_UNI_CMD_TESTMODE_RX_STAT = 0x32,
1303 MCU_UNI_CMD_BF = 0x33,
1304 MCU_UNI_CMD_CHANNEL_SWITCH = 0x34,
1305 MCU_UNI_CMD_THERMAL = 0x35,
1306 MCU_UNI_CMD_VOW = 0x37,
1307 MCU_UNI_CMD_FIXED_RATE_TABLE = 0x40,
1308 MCU_UNI_CMD_RSSI_MONITOR = 0x41,
1309 MCU_UNI_CMD_TESTMODE_CTRL = 0x46,
1310 MCU_UNI_CMD_RRO = 0x57,
1311 MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58,
1312 MCU_UNI_CMD_PER_STA_INFO = 0x6d,
1313 MCU_UNI_CMD_ALL_STA_INFO = 0x6e,
1314 MCU_UNI_CMD_ASSERT_DUMP = 0x6f,
1315 MCU_UNI_CMD_RADIO_STATUS = 0x80,
1316 MCU_UNI_CMD_SDO = 0x88,
1317 };
1318
1319 enum {
1320 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
1321 MCU_CMD_FW_START_REQ = 0x02,
1322 MCU_CMD_INIT_ACCESS_REG = 0x3,
1323 MCU_CMD_NIC_POWER_CTRL = 0x4,
1324 MCU_CMD_PATCH_START_REQ = 0x05,
1325 MCU_CMD_PATCH_FINISH_REQ = 0x07,
1326 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
1327 MCU_CMD_WA_PARAM = 0xc4,
1328 MCU_CMD_EXT_CID = 0xed,
1329 MCU_CMD_FW_SCATTER = 0xee,
1330 MCU_CMD_RESTART_DL_REQ = 0xef,
1331 };
1332
1333 /* offload mcu commands */
1334 enum {
1335 MCU_CE_CMD_TEST_CTRL = 0x01,
1336 MCU_CE_CMD_START_HW_SCAN = 0x03,
1337 MCU_CE_CMD_SET_PS_PROFILE = 0x05,
1338 MCU_CE_CMD_SET_RX_FILTER = 0x0a,
1339 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f,
1340 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16,
1341 MCU_CE_CMD_SET_BSS_ABORT = 0x17,
1342 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b,
1343 MCU_CE_CMD_SET_ROC = 0x1c,
1344 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d,
1345 MCU_CE_CMD_SET_P2P_OPPPS = 0x33,
1346 MCU_CE_CMD_SET_CLC = 0x5c,
1347 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d,
1348 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61,
1349 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62,
1350 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a,
1351 MCU_CE_CMD_RSSI_MONITOR = 0xa1,
1352 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0,
1353 MCU_CE_CMD_REG_WRITE = 0xc0,
1354 MCU_CE_CMD_REG_READ = 0xc0,
1355 MCU_CE_CMD_CHIP_CONFIG = 0xca,
1356 MCU_CE_CMD_FWLOG_2_HOST = 0xc5,
1357 MCU_CE_CMD_GET_WTBL = 0xcd,
1358 MCU_CE_CMD_GET_TXPWR = 0xd0,
1359 };
1360
1361 enum {
1362 PATCH_SEM_RELEASE,
1363 PATCH_SEM_GET
1364 };
1365
1366 enum {
1367 UNI_BSS_INFO_BASIC = 0,
1368 UNI_BSS_INFO_RA = 1,
1369 UNI_BSS_INFO_RLM = 2,
1370 UNI_BSS_INFO_BSS_COLOR = 4,
1371 UNI_BSS_INFO_HE_BASIC = 5,
1372 UNI_BSS_INFO_11V_MBSSID = 6,
1373 UNI_BSS_INFO_BCN_CONTENT = 7,
1374 UNI_BSS_INFO_BCN_CSA = 8,
1375 UNI_BSS_INFO_BCN_BCC = 9,
1376 UNI_BSS_INFO_BCN_MBSSID = 10,
1377 UNI_BSS_INFO_RATE = 11,
1378 UNI_BSS_INFO_QBSS = 15,
1379 UNI_BSS_INFO_SEC = 16,
1380 UNI_BSS_INFO_BCN_PROT = 17,
1381 UNI_BSS_INFO_TXCMD = 18,
1382 UNI_BSS_INFO_UAPSD = 19,
1383 UNI_BSS_INFO_PS = 21,
1384 UNI_BSS_INFO_BCNFT = 22,
1385 UNI_BSS_INFO_IFS_TIME = 23,
1386 UNI_BSS_INFO_OFFLOAD = 25,
1387 UNI_BSS_INFO_MLD = 26,
1388 UNI_BSS_INFO_PM_DISABLE = 27,
1389 UNI_BSS_INFO_EHT = 30,
1390 };
1391
1392 enum {
1393 UNI_OFFLOAD_OFFLOAD_ARP,
1394 UNI_OFFLOAD_OFFLOAD_ND,
1395 UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
1396 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
1397 };
1398
1399 enum UNI_ALL_STA_INFO_TAG {
1400 UNI_ALL_STA_TXRX_RATE,
1401 UNI_ALL_STA_TX_STAT,
1402 UNI_ALL_STA_TXRX_ADM_STAT,
1403 UNI_ALL_STA_TXRX_AIR_TIME,
1404 UNI_ALL_STA_DATA_TX_RETRY_COUNT,
1405 UNI_ALL_STA_GI_MODE,
1406 UNI_ALL_STA_TXRX_MSDU_COUNT,
1407 UNI_ALL_STA_MAX_NUM
1408 };
1409
1410 enum {
1411 MT_NIC_CAP_TX_RESOURCE,
1412 MT_NIC_CAP_TX_EFUSE_ADDR,
1413 MT_NIC_CAP_COEX,
1414 MT_NIC_CAP_SINGLE_SKU,
1415 MT_NIC_CAP_CSUM_OFFLOAD,
1416 MT_NIC_CAP_HW_VER,
1417 MT_NIC_CAP_SW_VER,
1418 MT_NIC_CAP_MAC_ADDR,
1419 MT_NIC_CAP_PHY,
1420 MT_NIC_CAP_MAC,
1421 MT_NIC_CAP_FRAME_BUF,
1422 MT_NIC_CAP_BEAM_FORM,
1423 MT_NIC_CAP_LOCATION,
1424 MT_NIC_CAP_MUMIMO,
1425 MT_NIC_CAP_BUFFER_MODE_INFO,
1426 MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
1427 MT_NIC_CAP_ANTSWP = 0x16,
1428 MT_NIC_CAP_WFDMA_REALLOC,
1429 MT_NIC_CAP_6G,
1430 MT_NIC_CAP_CHIP_CAP = 0x20,
1431 MT_NIC_CAP_EML_CAP = 0x22,
1432 };
1433
1434 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0)
1435 #define UNI_WOW_DETECT_TYPE_ANY BIT(1)
1436 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2)
1437 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3)
1438 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4)
1439 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5)
1440 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6)
1441
1442 enum {
1443 UNI_SUSPEND_MODE_SETTING,
1444 UNI_SUSPEND_WOW_CTRL,
1445 UNI_SUSPEND_WOW_GPIO_PARAM,
1446 UNI_SUSPEND_WOW_WAKEUP_PORT,
1447 UNI_SUSPEND_WOW_PATTERN,
1448 };
1449
1450 enum {
1451 WOW_USB = 1,
1452 WOW_PCIE = 2,
1453 WOW_GPIO = 3,
1454 };
1455
1456 struct mt76_connac_bss_basic_tlv {
1457 __le16 tag;
1458 __le16 len;
1459 u8 active;
1460 u8 omac_idx;
1461 u8 hw_bss_idx;
1462 u8 band_idx;
1463 __le32 conn_type;
1464 u8 conn_state;
1465 u8 wmm_idx;
1466 u8 bssid[ETH_ALEN];
1467 __le16 bmc_tx_wlan_idx;
1468 __le16 bcn_interval;
1469 u8 dtim_period;
1470 u8 phymode; /* bit(0): A
1471 * bit(1): B
1472 * bit(2): G
1473 * bit(3): GN
1474 * bit(4): AN
1475 * bit(5): AC
1476 * bit(6): AX2
1477 * bit(7): AX5
1478 * bit(8): AX6
1479 */
1480 __le16 sta_idx;
1481 __le16 nonht_basic_phy;
1482 u8 phymode_ext; /* bit(0) AX_6G */
1483 u8 link_idx;
1484 } __packed;
1485
1486 struct mt76_connac_bss_qos_tlv {
1487 __le16 tag;
1488 __le16 len;
1489 u8 qos;
1490 u8 pad[3];
1491 } __packed;
1492
1493 struct mt76_connac_beacon_loss_event {
1494 u8 bss_idx;
1495 u8 reason;
1496 u8 pad[2];
1497 } __packed;
1498
1499 struct mt76_connac_rssi_notify_event {
1500 __le32 rssi[4];
1501 } __packed;
1502
1503 struct mt76_connac_mcu_bss_event {
1504 u8 bss_idx;
1505 u8 is_absent;
1506 u8 free_quota;
1507 u8 pad;
1508 } __packed;
1509
1510 struct mt76_connac_mcu_scan_ssid {
1511 __le32 ssid_len;
1512 u8 ssid[IEEE80211_MAX_SSID_LEN];
1513 } __packed;
1514
1515 struct mt76_connac_mcu_scan_channel {
1516 u8 band; /* 1: 2.4GHz
1517 * 2: 5.0GHz
1518 * Others: Reserved
1519 */
1520 u8 channel_num;
1521 } __packed;
1522
1523 struct mt76_connac_mcu_scan_match {
1524 __le32 rssi_th;
1525 u8 ssid[IEEE80211_MAX_SSID_LEN];
1526 u8 ssid_len;
1527 u8 rsv[3];
1528 } __packed;
1529
1530 struct mt76_connac_hw_scan_req {
1531 u8 seq_num;
1532 u8 bss_idx;
1533 u8 scan_type; /* 0: PASSIVE SCAN
1534 * 1: ACTIVE SCAN
1535 */
1536 u8 ssid_type; /* BIT(0) wildcard SSID
1537 * BIT(1) P2P wildcard SSID
1538 * BIT(2) specified SSID + wildcard SSID
1539 * BIT(2) + ssid_type_ext BIT(0) specified SSID only
1540 */
1541 u8 ssids_num;
1542 u8 probe_req_num; /* Number of probe request for each SSID */
1543 u8 scan_func; /* BIT(0) Enable random MAC scan
1544 * BIT(1) Disable DBDC scan type 1~3.
1545 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
1546 */
1547 u8 version; /* 0: Not support fields after ies.
1548 * 1: Support fields after ies.
1549 */
1550 struct mt76_connac_mcu_scan_ssid ssids[4];
1551 __le16 probe_delay_time;
1552 __le16 channel_dwell_time; /* channel Dwell interval */
1553 __le16 timeout_value;
1554 u8 channel_type; /* 0: Full channels
1555 * 1: Only 2.4GHz channels
1556 * 2: Only 5GHz channels
1557 * 3: P2P social channel only (channel #1, #6 and #11)
1558 * 4: Specified channels
1559 * Others: Reserved
1560 */
1561 u8 channels_num; /* valid when channel_type is 4 */
1562 /* valid when channels_num is set */
1563 struct mt76_connac_mcu_scan_channel channels[32];
1564 __le16 ies_len;
1565 u8 ies[MT76_CONNAC_SCAN_IE_LEN];
1566 /* following fields are valid if version > 0 */
1567 u8 ext_channels_num;
1568 u8 ext_ssids_num;
1569 __le16 channel_min_dwell_time;
1570 struct mt76_connac_mcu_scan_channel ext_channels[32];
1571 struct mt76_connac_mcu_scan_ssid ext_ssids[6];
1572 u8 bssid[ETH_ALEN];
1573 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
1574 u8 pad[63];
1575 u8 ssid_type_ext;
1576 } __packed;
1577
1578 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64
1579
1580 struct mt76_connac_hw_scan_done {
1581 u8 seq_num;
1582 u8 sparse_channel_num;
1583 struct mt76_connac_mcu_scan_channel sparse_channel;
1584 u8 complete_channel_num;
1585 u8 current_state;
1586 u8 version;
1587 u8 pad;
1588 __le32 beacon_scan_num;
1589 u8 pno_enabled;
1590 u8 pad2[3];
1591 u8 sparse_channel_valid_num;
1592 u8 pad3[3];
1593 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1594 /* idle format for channel_idle_time
1595 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
1596 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
1597 * 2: dwell time (16us)
1598 */
1599 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1600 /* beacon and probe response count */
1601 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1602 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1603 __le32 beacon_2g_num;
1604 __le32 beacon_5g_num;
1605 } __packed;
1606
1607 struct mt76_connac_sched_scan_req {
1608 u8 version;
1609 u8 seq_num;
1610 u8 stop_on_match;
1611 u8 ssids_num;
1612 u8 match_num;
1613 u8 pad;
1614 __le16 ie_len;
1615 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
1616 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
1617 u8 channel_type;
1618 u8 channels_num;
1619 u8 intervals_num;
1620 u8 scan_func; /* MT7663: BIT(0) eable random mac address */
1621 struct mt76_connac_mcu_scan_channel channels[64];
1622 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
1623 union {
1624 struct {
1625 u8 random_mac[ETH_ALEN];
1626 u8 pad2[58];
1627 } mt7663;
1628 struct {
1629 u8 bss_idx;
1630 u8 pad1[3];
1631 __le32 delay;
1632 u8 pad2[12];
1633 u8 random_mac[ETH_ALEN];
1634 u8 pad3[38];
1635 } mt7921;
1636 };
1637 } __packed;
1638
1639 struct mt76_connac_sched_scan_done {
1640 u8 seq_num;
1641 u8 status; /* 0: ssid found */
1642 __le16 pad;
1643 } __packed;
1644
1645 struct bss_info_uni_bss_color {
1646 __le16 tag;
1647 __le16 len;
1648 u8 enable;
1649 u8 bss_color;
1650 u8 rsv[2];
1651 } __packed;
1652
1653 struct bss_info_uni_he {
1654 __le16 tag;
1655 __le16 len;
1656 __le16 he_rts_thres;
1657 u8 he_pe_duration;
1658 u8 su_disable;
1659 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
1660 u8 rsv[2];
1661 } __packed;
1662
1663 struct bss_info_uni_mbssid {
1664 __le16 tag;
1665 __le16 len;
1666 u8 max_indicator;
1667 u8 mbss_idx;
1668 u8 tx_bss_omac_idx;
1669 u8 rsv;
1670 } __packed;
1671
1672 struct mt76_connac_gtk_rekey_tlv {
1673 __le16 tag;
1674 __le16 len;
1675 u8 kek[NL80211_KEK_LEN];
1676 u8 kck[NL80211_KCK_LEN];
1677 u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
1678 u8 rekey_mode; /* 0: rekey offload enable
1679 * 1: rekey offload disable
1680 * 2: rekey update
1681 */
1682 u8 keyid;
1683 u8 option; /* 1: rekey data update without enabling offload */
1684 u8 pad[1];
1685 __le32 proto; /* WPA-RSN-WAPI-OPSN */
1686 __le32 pairwise_cipher;
1687 __le32 group_cipher;
1688 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
1689 __le32 mgmt_group_cipher;
1690 u8 reserverd[4];
1691 } __packed;
1692
1693 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16
1694 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128
1695
1696 struct mt76_connac_wow_pattern_tlv {
1697 __le16 tag;
1698 __le16 len;
1699 u8 index; /* pattern index */
1700 u8 enable; /* 0: disable
1701 * 1: enable
1702 */
1703 u8 data_len; /* pattern length */
1704 u8 pad;
1705 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
1706 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
1707 u8 rsv[4];
1708 } __packed;
1709
1710 struct mt76_connac_wow_ctrl_tlv {
1711 __le16 tag;
1712 __le16 len;
1713 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
1714 * 0x2: PM_WOWLAN_REQ_STOP
1715 * 0x3: PM_WOWLAN_PARAM_CLEAR
1716 */
1717 u8 trigger; /* 0: NONE
1718 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
1719 * BIT(1): NL80211_WOWLAN_TRIG_ANY
1720 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
1721 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
1722 * BIT(4): BEACON_LOST
1723 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
1724 */
1725 u8 wakeup_hif; /* 0x0: HIF_SDIO
1726 * 0x1: HIF_USB
1727 * 0x2: HIF_PCIE
1728 * 0x3: HIF_GPIO
1729 */
1730 u8 pad;
1731 u8 rsv[4];
1732 } __packed;
1733
1734 struct mt76_connac_wow_gpio_param_tlv {
1735 __le16 tag;
1736 __le16 len;
1737 u8 gpio_pin;
1738 u8 trigger_lvl;
1739 u8 pad[2];
1740 __le32 gpio_interval;
1741 u8 rsv[4];
1742 } __packed;
1743
1744 struct mt76_connac_arpns_tlv {
1745 __le16 tag;
1746 __le16 len;
1747 u8 mode;
1748 u8 ips_num;
1749 u8 option;
1750 u8 pad[1];
1751 } __packed;
1752
1753 struct mt76_connac_suspend_tlv {
1754 __le16 tag;
1755 __le16 len;
1756 u8 enable; /* 0: suspend mode disabled
1757 * 1: suspend mode enabled
1758 */
1759 u8 mdtim; /* LP parameter */
1760 u8 wow_suspend; /* 0: update by origin policy
1761 * 1: update by wow dtim
1762 */
1763 u8 pad[5];
1764 } __packed;
1765
1766 enum mt76_sta_info_state {
1767 MT76_STA_INFO_STATE_NONE,
1768 MT76_STA_INFO_STATE_AUTH,
1769 MT76_STA_INFO_STATE_ASSOC
1770 };
1771
1772 struct mt76_sta_cmd_info {
1773 union {
1774 struct ieee80211_sta *sta;
1775 struct ieee80211_link_sta *link_sta;
1776 };
1777 struct mt76_wcid *wcid;
1778
1779 struct ieee80211_vif *vif;
1780 struct ieee80211_bss_conf *link_conf;
1781
1782 bool offload_fw;
1783 bool enable;
1784 bool newly;
1785 int cmd;
1786 u8 rcpi;
1787 u8 state;
1788 };
1789
1790 #define MT_SKU_POWER_LIMIT 161
1791
1792 struct mt76_connac_sku_tlv {
1793 u8 channel;
1794 s8 pwr_limit[MT_SKU_POWER_LIMIT];
1795 } __packed;
1796
1797 struct mt76_connac_tx_power_limit_tlv {
1798 /* DW0 - common info*/
1799 u8 ver;
1800 u8 pad0;
1801 __le16 len;
1802 /* DW1 - cmd hint */
1803 u8 n_chan; /* # channel */
1804 u8 band; /* 2.4GHz - 5GHz - 6GHz */
1805 u8 last_msg;
1806 u8 pad1;
1807 /* DW3 */
1808 u8 alpha2[4]; /* regulatory_request.alpha2 */
1809 u8 pad2[32];
1810 } __packed;
1811
1812 struct mt76_connac_config {
1813 __le16 id;
1814 u8 type;
1815 u8 resp_type;
1816 __le16 data_size;
1817 __le16 resv;
1818 u8 data[320];
1819 } __packed;
1820
1821 struct mt76_connac_mcu_uni_event {
1822 u8 cid;
1823 u8 pad[3];
1824 __le32 status; /* 0: success, others: fail */
1825 } __packed;
1826
1827 struct mt76_connac_mcu_reg_event {
1828 __le32 reg;
1829 __le32 val;
1830 } __packed;
1831
1832 static inline enum mcu_cipher_type
mt76_connac_mcu_get_cipher(int cipher)1833 mt76_connac_mcu_get_cipher(int cipher)
1834 {
1835 switch (cipher) {
1836 case WLAN_CIPHER_SUITE_WEP40:
1837 return MCU_CIPHER_WEP40;
1838 case WLAN_CIPHER_SUITE_WEP104:
1839 return MCU_CIPHER_WEP104;
1840 case WLAN_CIPHER_SUITE_TKIP:
1841 return MCU_CIPHER_TKIP;
1842 case WLAN_CIPHER_SUITE_AES_CMAC:
1843 return MCU_CIPHER_BIP_CMAC_128;
1844 case WLAN_CIPHER_SUITE_CCMP:
1845 return MCU_CIPHER_AES_CCMP;
1846 case WLAN_CIPHER_SUITE_CCMP_256:
1847 return MCU_CIPHER_CCMP_256;
1848 case WLAN_CIPHER_SUITE_GCMP:
1849 return MCU_CIPHER_GCMP;
1850 case WLAN_CIPHER_SUITE_GCMP_256:
1851 return MCU_CIPHER_GCMP_256;
1852 case WLAN_CIPHER_SUITE_BIP_GMAC_128:
1853 return MCU_CIPHER_BIP_GMAC_128;
1854 case WLAN_CIPHER_SUITE_BIP_GMAC_256:
1855 return MCU_CIPHER_BIP_GMAC_256;
1856 case WLAN_CIPHER_SUITE_BIP_CMAC_256:
1857 return MCU_CIPHER_BIP_CMAC_256;
1858 case WLAN_CIPHER_SUITE_SMS4:
1859 return MCU_CIPHER_WAPI;
1860 default:
1861 return MCU_CIPHER_NONE;
1862 }
1863 }
1864
1865 static inline u32
mt76_connac_mcu_gen_dl_mode(struct mt76_dev * dev,u8 feature_set,bool is_wa)1866 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa)
1867 {
1868 u32 ret = 0;
1869
1870 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ?
1871 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0;
1872 if (is_mt7921(dev) || is_mt7925(dev))
1873 ret |= feature_set & FW_FEATURE_ENCRY_MODE ?
1874 DL_CONFIG_ENCRY_MODE_SEL : 0;
1875 ret |= FIELD_PREP(DL_MODE_KEY_IDX,
1876 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set));
1877 ret |= DL_MODE_NEED_RSP;
1878 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0;
1879
1880 return ret;
1881 }
1882
1883 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1884 #define to_wcid_hi(id) FIELD_GET(GENMASK(10, 8), (u16)id)
1885
1886 static inline void
mt76_connac_mcu_get_wlan_idx(struct mt76_dev * dev,struct mt76_wcid * wcid,u8 * wlan_idx_lo,u8 * wlan_idx_hi)1887 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1888 u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1889 {
1890 *wlan_idx_hi = 0;
1891
1892 if (!is_connac_v1(dev)) {
1893 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1894 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1895 } else {
1896 *wlan_idx_lo = wcid ? wcid->idx : 0;
1897 }
1898 }
1899
1900 struct sk_buff *
1901 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif_link *mvif,
1902 struct mt76_wcid *wcid, int len);
1903 static inline struct sk_buff *
mt76_connac_mcu_alloc_sta_req(struct mt76_dev * dev,struct mt76_vif_link * mvif,struct mt76_wcid * wcid)1904 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif_link *mvif,
1905 struct mt76_wcid *wcid)
1906 {
1907 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid,
1908 MT76_CONNAC_STA_UPDATE_MAX_SIZE);
1909 }
1910
1911 struct wtbl_req_hdr *
1912 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1913 int cmd, void *sta_wtbl, struct sk_buff **skb);
1914 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1915 int len, void *sta_ntlv,
1916 void *sta_wtbl);
1917 static inline struct tlv *
mt76_connac_mcu_add_tlv(struct sk_buff * skb,int tag,int len)1918 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1919 {
1920 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1921 }
1922
1923 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
1924 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
1925 void mt76_connac_mcu_sta_basic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1926 struct ieee80211_bss_conf *link_conf,
1927 struct ieee80211_link_sta *link_sta,
1928 int state, bool newly);
1929 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1930 struct ieee80211_vif *vif,
1931 struct ieee80211_sta *sta, void *sta_wtbl,
1932 void *wtbl_tlv);
1933 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
1934 struct ieee80211_vif *vif,
1935 struct mt76_wcid *wcid,
1936 void *sta_wtbl, void *wtbl_tlv);
1937 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
1938 struct ieee80211_vif *vif,
1939 struct mt76_wcid *wcid, int cmd);
1940 void mt76_connac_mcu_sta_he_tlv_v2(struct sk_buff *skb, struct ieee80211_sta *sta);
1941 u8 mt76_connac_get_phy_mode_v2(struct mt76_phy *mphy, struct ieee80211_vif *vif,
1942 enum nl80211_band band,
1943 struct ieee80211_link_sta *link_sta);
1944 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev,
1945 struct ieee80211_vif *vif,
1946 struct ieee80211_sta *sta);
1947 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
1948 struct ieee80211_sta *sta,
1949 struct ieee80211_vif *vif,
1950 u8 rcpi, u8 state);
1951 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1952 struct ieee80211_sta *sta, void *sta_wtbl,
1953 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc);
1954 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1955 struct ieee80211_ampdu_params *params,
1956 bool enable, bool tx, void *sta_wtbl,
1957 void *wtbl_tlv);
1958 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
1959 struct ieee80211_ampdu_params *params,
1960 bool enable, bool tx);
1961 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
1962 struct ieee80211_bss_conf *bss_conf,
1963 struct mt76_vif_link *mvif,
1964 struct mt76_wcid *wcid,
1965 bool enable);
1966 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif_link *mvif,
1967 struct ieee80211_ampdu_params *params,
1968 int cmd, bool enable, bool tx);
1969 int mt76_connac_mcu_uni_set_chctx(struct mt76_phy *phy,
1970 struct mt76_vif_link *vif,
1971 struct ieee80211_chanctx_conf *ctx);
1972 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
1973 struct ieee80211_vif *vif,
1974 struct mt76_wcid *wcid,
1975 bool enable,
1976 struct ieee80211_chanctx_conf *ctx);
1977 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
1978 struct mt76_sta_cmd_info *info);
1979 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
1980 struct ieee80211_vif *vif);
1981 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
1982 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
1983 bool hdr_trans);
1984 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
1985 u32 mode);
1986 int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
1987 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
1988 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
1989
1990 void mt76_connac_mcu_build_rnr_scan_param(struct mt76_dev *mdev,
1991 struct cfg80211_scan_request *sreq);
1992 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
1993 struct ieee80211_scan_request *scan_req);
1994 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
1995 struct ieee80211_vif *vif);
1996 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
1997 struct ieee80211_vif *vif,
1998 struct cfg80211_sched_scan_request *sreq);
1999 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
2000 struct ieee80211_vif *vif,
2001 bool enable);
2002 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
2003 struct mt76_vif_link *vif,
2004 struct ieee80211_bss_conf *info);
2005 int mt76_connac_mcu_set_gtk_rekey(struct mt76_dev *dev, struct ieee80211_vif *vif,
2006 bool suspend);
2007 int mt76_connac_mcu_set_wow_ctrl(struct mt76_phy *phy, struct ieee80211_vif *vif,
2008 bool suspend, struct cfg80211_wowlan *wowlan);
2009 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
2010 struct ieee80211_vif *vif,
2011 struct cfg80211_gtk_rekey_data *key);
2012 int mt76_connac_mcu_set_suspend_mode(struct mt76_dev *dev,
2013 struct ieee80211_vif *vif,
2014 bool enable, u8 mdtim,
2015 bool wow_suspend);
2016 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend, bool wait_resp);
2017 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
2018 struct ieee80211_vif *vif);
2019 int mt76_connac_sta_state_dp(struct mt76_dev *dev,
2020 enum ieee80211_sta_state old_state,
2021 enum ieee80211_sta_state new_state);
2022 int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
2023 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
2024 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
2025 struct mt76_connac_coredump *coredump);
2026 s8 mt76_connac_get_ch_power(struct mt76_phy *phy,
2027 struct ieee80211_channel *chan,
2028 s8 target_power);
2029 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
2030 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
2031 struct ieee80211_vif *vif);
2032 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
2033 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
2034
2035 const struct ieee80211_sta_he_cap *
2036 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
2037 const struct ieee80211_sta_eht_cap *
2038 mt76_connac_get_eht_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
2039 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif,
2040 enum nl80211_band band,
2041 struct ieee80211_link_sta *sta);
2042 u8 mt76_connac_get_phy_mode_ext(struct mt76_phy *phy, struct ieee80211_bss_conf *conf,
2043 enum nl80211_band band);
2044
2045 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
2046 struct mt76_connac_sta_key_conf *sta_key_conf,
2047 struct ieee80211_key_conf *key, int mcu_cmd,
2048 struct mt76_wcid *wcid, enum set_key_cmd cmd);
2049
2050 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif_link *mvif);
2051 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb,
2052 struct ieee80211_vif *vif);
2053 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
2054 struct ieee80211_vif *vif,
2055 struct ieee80211_sta *sta,
2056 struct mt76_phy *phy, u16 wlan_idx,
2057 bool enable);
2058 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif,
2059 struct ieee80211_sta *sta);
2060 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb,
2061 struct ieee80211_sta *sta,
2062 void *sta_wtbl, void *wtbl_tlv);
2063 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter);
2064 int mt76_connac_mcu_restart(struct mt76_dev *dev);
2065 int mt76_connac_mcu_del_wtbl_all(struct mt76_dev *dev);
2066 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index,
2067 u8 rx_sel, u8 val);
2068 int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb);
2069 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm,
2070 const char *fw_wa);
2071 int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name);
2072 int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
2073 int cmd, int *wait_seq);
2074 #endif /* __MT76_CONNAC_MCU_H */
2075