1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ADIS16550 IMU driver
4 *
5 * Copyright 2024 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/crc32.h>
11 #include <linux/debugfs.h>
12 #include <linux/iio/buffer.h>
13 #include <linux/iio/iio.h>
14 #include <linux/iio/imu/adis.h>
15 #include <linux/iio/trigger_consumer.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/lcm.h>
19 #include <linux/math.h>
20 #include <linux/module.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/spi/spi.h>
23 #include <linux/swab.h>
24 #include <linux/unaligned.h>
25
26 #define ADIS16550_REG_BURST_GYRO_ACCEL 0x0a
27 #define ADIS16550_REG_BURST_DELTA_ANG_VEL 0x0b
28 #define ADIS16550_BURST_DATA_GYRO_ACCEL_MASK GENMASK(6, 1)
29 #define ADIS16550_BURST_DATA_DELTA_ANG_VEL_MASK GENMASK(12, 7)
30
31 #define ADIS16550_REG_STATUS 0x0e
32 #define ADIS16550_REG_TEMP 0x10
33 #define ADIS16550_REG_X_GYRO 0x12
34 #define ADIS16550_REG_Y_GYRO 0x14
35 #define ADIS16550_REG_Z_GYRO 0x16
36 #define ADIS16550_REG_X_ACCEL 0x18
37 #define ADIS16550_REG_Y_ACCEL 0x1a
38 #define ADIS16550_REG_Z_ACCEL 0x1c
39 #define ADIS16550_REG_X_DELTANG_L 0x1E
40 #define ADIS16550_REG_Y_DELTANG_L 0x20
41 #define ADIS16550_REG_Z_DELTANG_L 0x22
42 #define ADIS16550_REG_X_DELTVEL_L 0x24
43 #define ADIS16550_REG_Y_DELTVEL_L 0x26
44 #define ADIS16550_REG_Z_DELTVEL_L 0x28
45 #define ADIS16550_REG_X_GYRO_SCALE 0x30
46 #define ADIS16550_REG_Y_GYRO_SCALE 0x32
47 #define ADIS16550_REG_Z_GYRO_SCALE 0x34
48 #define ADIS16550_REG_X_ACCEL_SCALE 0x36
49 #define ADIS16550_REG_Y_ACCEL_SCALE 0x38
50 #define ADIS16550_REG_Z_ACCEL_SCALE 0x3a
51 #define ADIS16550_REG_X_GYRO_BIAS 0x40
52 #define ADIS16550_REG_Y_GYRO_BIAS 0x42
53 #define ADIS16550_REG_Z_GYRO_BIAS 0x44
54 #define ADIS16550_REG_X_ACCEL_BIAS 0x46
55 #define ADIS16550_REG_Y_ACCEL_BIAS 0x48
56 #define ADIS16550_REG_Z_ACCEL_BIAS 0x4a
57 #define ADIS16550_REG_COMMAND 0x50
58 #define ADIS16550_REG_CONFIG 0x52
59 #define ADIS16550_GYRO_FIR_EN_MASK BIT(3)
60 #define ADIS16550_ACCL_FIR_EN_MASK BIT(2)
61 #define ADIS16550_SYNC_MASK \
62 (ADIS16550_SYNC_EN_MASK | ADIS16550_SYNC_MODE_MASK)
63 #define ADIS16550_SYNC_MODE_MASK BIT(1)
64 #define ADIS16550_SYNC_EN_MASK BIT(0)
65 /* max of 4000 SPS in scale sync */
66 #define ADIS16550_SYNC_SCALE_MAX_RATE (4000 * 1000)
67 #define ADIS16550_REG_DEC_RATE 0x54
68 #define ADIS16550_REG_SYNC_SCALE 0x56
69 #define ADIS16550_REG_SERIAL_NUM 0x76
70 #define ADIS16550_REG_FW_REV 0x7A
71 #define ADIS16550_REG_FW_DATE 0x7C
72 #define ADIS16550_REG_PROD_ID 0x7E
73 #define ADIS16550_REG_FLASH_CNT 0x72
74 /* SPI protocol*/
75 #define ADIS16550_SPI_DATA_MASK GENMASK(31, 16)
76 #define ADIS16550_SPI_REG_MASK GENMASK(14, 8)
77 #define ADIS16550_SPI_R_W_MASK BIT(7)
78 #define ADIS16550_SPI_CRC_MASK GENMASK(3, 0)
79 #define ADIS16550_SPI_SV_MASK GENMASK(7, 6)
80 /* burst read */
81 #define ADIS16550_BURST_N_ELEM 12
82 #define ADIS16550_BURST_DATA_LEN (ADIS16550_BURST_N_ELEM * 4)
83 #define ADIS16550_MAX_SCAN_DATA 12
84
85 struct adis16550_sync {
86 u16 sync_mode;
87 u16 min_rate;
88 u16 max_rate;
89 };
90
91 struct adis16550 {
92 struct adis adis;
93 unsigned long clk_freq_hz;
94 u32 sync_mode;
95 struct spi_transfer xfer[2];
96 u8 buffer[ADIS16550_BURST_DATA_LEN + sizeof(u32)] __aligned(IIO_DMA_MINALIGN);
97 __be32 din[2];
98 __be32 dout[2];
99 };
100
101 enum {
102 ADIS16550_SV_INIT,
103 ADIS16550_SV_OK,
104 ADIS16550_SV_NOK,
105 ADIS16550_SV_SPI_ERROR,
106 };
107
108 /*
109 * This is a simplified implementation of lib/crc4.c. It could not be used
110 * directly since the polynomial used is different from the one used by the
111 * 16550 which is 0b10001
112 */
spi_crc4(const u32 val)113 static u8 spi_crc4(const u32 val)
114 {
115 int i;
116 const int bits = 28;
117 u8 crc = 0xa;
118 /* ignore 4lsb */
119 const u32 __val = val >> 4;
120
121 /* Calculate crc4 over four-bit nibbles, starting at the MSbit */
122 for (i = bits - 4; i >= 0; i -= 4)
123 crc = crc ^ ((__val >> i) & 0xf);
124
125 return crc;
126 }
127
adis16550_spi_validate(const struct adis * adis,__be32 dout,u16 * data)128 static int adis16550_spi_validate(const struct adis *adis, __be32 dout,
129 u16 *data)
130 {
131 u32 __dout;
132 u8 crc, crc_rcv, sv;
133
134 __dout = be32_to_cpu(dout);
135
136 /* validate received message */
137 crc_rcv = FIELD_GET(ADIS16550_SPI_CRC_MASK, __dout);
138 crc = spi_crc4(__dout);
139 if (crc_rcv != crc) {
140 dev_err(&adis->spi->dev,
141 "Invalid crc, rcv: 0x%02x, calc: 0x%02x!\n",
142 crc_rcv, crc);
143 return -EIO;
144 }
145 sv = FIELD_GET(ADIS16550_SPI_SV_MASK, __dout);
146 if (sv >= ADIS16550_SV_NOK) {
147 dev_err(&adis->spi->dev,
148 "State vector error detected: %02X", sv);
149 return -EIO;
150 }
151 *data = FIELD_GET(ADIS16550_SPI_DATA_MASK, __dout);
152
153 return 0;
154 }
155
adis16550_spi_msg_prepare(const u32 reg,const bool write,const u16 data,__be32 * din)156 static void adis16550_spi_msg_prepare(const u32 reg, const bool write,
157 const u16 data, __be32 *din)
158 {
159 u8 crc;
160 u32 __din;
161
162 __din = FIELD_PREP(ADIS16550_SPI_REG_MASK, reg);
163
164 if (write) {
165 __din |= FIELD_PREP(ADIS16550_SPI_R_W_MASK, 1);
166 __din |= FIELD_PREP(ADIS16550_SPI_DATA_MASK, data);
167 }
168
169 crc = spi_crc4(__din);
170 __din |= FIELD_PREP(ADIS16550_SPI_CRC_MASK, crc);
171
172 *din = cpu_to_be32(__din);
173 }
174
adis16550_spi_xfer(const struct adis * adis,u32 reg,u32 len,u32 * readval,u32 writeval)175 static int adis16550_spi_xfer(const struct adis *adis, u32 reg, u32 len,
176 u32 *readval, u32 writeval)
177 {
178 int ret;
179 u16 data = 0;
180 struct spi_message msg;
181 bool wr = readval ? false : true;
182 struct spi_device *spi = adis->spi;
183 struct adis16550 *st = container_of(adis, struct adis16550, adis);
184 struct spi_transfer xfers[] = {
185 {
186 .tx_buf = &st->din[0],
187 .len = 4,
188 .cs_change = 1,
189 }, {
190 .tx_buf = &st->din[1],
191 .len = 4,
192 .cs_change = 1,
193 .rx_buf = st->dout,
194 }, {
195 .tx_buf = &st->din[1],
196 .rx_buf = &st->dout[1],
197 .len = 4,
198 },
199 };
200
201 spi_message_init(&msg);
202
203 switch (len) {
204 case 4:
205 adis16550_spi_msg_prepare(reg + 1, wr, writeval >> 16,
206 &st->din[0]);
207 spi_message_add_tail(&xfers[0], &msg);
208 fallthrough;
209 case 2:
210 adis16550_spi_msg_prepare(reg, wr, writeval, &st->din[1]);
211 spi_message_add_tail(&xfers[1], &msg);
212 spi_message_add_tail(&xfers[2], &msg);
213 break;
214 default:
215 return -EINVAL;
216 }
217
218 ret = spi_sync(spi, &msg);
219 if (ret) {
220 dev_err(&spi->dev, "Spi failure %d\n", ret);
221 return ret;
222 }
223 /*
224 * When writing a register, the device will reply with a readback on the
225 * transfer so that we can validate if our data was actually written..
226 */
227 switch (len) {
228 case 4:
229 ret = adis16550_spi_validate(adis, st->dout[0], &data);
230 if (ret)
231 return ret;
232
233 if (readval) {
234 *readval = data << 16;
235 } else if ((writeval >> 16) != data && reg != ADIS16550_REG_COMMAND) {
236 dev_err(&spi->dev,
237 "Data not written: wr: 0x%04X, rcv: 0x%04X\n",
238 writeval >> 16, data);
239 return -EIO;
240 }
241
242 fallthrough;
243 case 2:
244 ret = adis16550_spi_validate(adis, st->dout[1], &data);
245 if (ret)
246 return ret;
247
248 if (readval) {
249 *readval = (*readval & GENMASK(31, 16)) | data;
250 } else if ((writeval & GENMASK(15, 0)) != data && reg != ADIS16550_REG_COMMAND) {
251 dev_err(&spi->dev,
252 "Data not written: wr: 0x%04X, rcv: 0x%04X\n",
253 (u16)writeval, data);
254 return -EIO;
255 }
256 }
257
258 return 0;
259 }
260
adis16550_spi_read(struct adis * adis,const u32 reg,u32 * value,const u32 len)261 static int adis16550_spi_read(struct adis *adis, const u32 reg,
262 u32 *value, const u32 len)
263 {
264 return adis16550_spi_xfer(adis, reg, len, value, 0);
265 }
266
adis16550_spi_write(struct adis * adis,const u32 reg,const u32 value,const u32 len)267 static int adis16550_spi_write(struct adis *adis, const u32 reg,
268 const u32 value, const u32 len)
269 {
270 return adis16550_spi_xfer(adis, reg, len, NULL, value);
271 }
272
adis16550_show_firmware_revision(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)273 static ssize_t adis16550_show_firmware_revision(struct file *file,
274 char __user *userbuf,
275 size_t count, loff_t *ppos)
276 {
277 struct adis16550 *st = file->private_data;
278 char buf[7];
279 size_t len;
280 u16 rev;
281 int ret;
282
283 ret = adis_read_reg_16(&st->adis, ADIS16550_REG_FW_REV, &rev);
284 if (ret)
285 return ret;
286
287 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
288
289 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
290 }
291
292 static const struct file_operations adis16550_firmware_revision_fops = {
293 .open = simple_open,
294 .read = adis16550_show_firmware_revision,
295 .llseek = default_llseek,
296 .owner = THIS_MODULE,
297 };
298
adis16550_show_firmware_date(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)299 static ssize_t adis16550_show_firmware_date(struct file *file,
300 char __user *userbuf,
301 size_t count, loff_t *ppos)
302 {
303 struct adis16550 *st = file->private_data;
304 char buf[12];
305 size_t len;
306 u32 date;
307 int ret;
308
309 ret = adis_read_reg_32(&st->adis, ADIS16550_REG_FW_DATE, &date);
310 if (ret)
311 return ret;
312
313 len = scnprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", date & 0xff,
314 (date >> 8) & 0xff, date >> 16);
315
316 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
317 }
318
319 static const struct file_operations adis16550_firmware_date_fops = {
320 .open = simple_open,
321 .read = adis16550_show_firmware_date,
322 .llseek = default_llseek,
323 .owner = THIS_MODULE,
324 };
325
adis16550_show_serial_number(void * arg,u64 * val)326 static int adis16550_show_serial_number(void *arg, u64 *val)
327 {
328 struct adis16550 *st = arg;
329 u32 serial;
330 int ret;
331
332 ret = adis_read_reg_32(&st->adis, ADIS16550_REG_SERIAL_NUM, &serial);
333 if (ret)
334 return ret;
335
336 *val = serial;
337
338 return 0;
339 }
340 DEFINE_DEBUGFS_ATTRIBUTE(adis16550_serial_number_fops,
341 adis16550_show_serial_number, NULL, "0x%.8llx\n");
342
adis16550_show_product_id(void * arg,u64 * val)343 static int adis16550_show_product_id(void *arg, u64 *val)
344 {
345 struct adis16550 *st = arg;
346 u16 prod_id;
347 int ret;
348
349 ret = adis_read_reg_16(&st->adis, ADIS16550_REG_PROD_ID, &prod_id);
350 if (ret)
351 return ret;
352
353 *val = prod_id;
354
355 return 0;
356 }
357 DEFINE_DEBUGFS_ATTRIBUTE(adis16550_product_id_fops,
358 adis16550_show_product_id, NULL, "%llu\n");
359
adis16550_show_flash_count(void * arg,u64 * val)360 static int adis16550_show_flash_count(void *arg, u64 *val)
361 {
362 struct adis16550 *st = arg;
363 u16 flash_count;
364 int ret;
365
366 ret = adis_read_reg_16(&st->adis, ADIS16550_REG_FLASH_CNT, &flash_count);
367 if (ret)
368 return ret;
369
370 *val = flash_count;
371
372 return 0;
373 }
374 DEFINE_DEBUGFS_ATTRIBUTE(adis16550_flash_count_fops,
375 adis16550_show_flash_count, NULL, "%lld\n");
376
adis16550_debugfs_init(struct iio_dev * indio_dev)377 static void adis16550_debugfs_init(struct iio_dev *indio_dev)
378 {
379 struct adis16550 *st = iio_priv(indio_dev);
380 struct dentry *d = iio_get_debugfs_dentry(indio_dev);
381
382 debugfs_create_file_unsafe("serial_number", 0400, d, st,
383 &adis16550_serial_number_fops);
384 debugfs_create_file_unsafe("product_id", 0400, d, st,
385 &adis16550_product_id_fops);
386 debugfs_create_file("firmware_revision", 0400, d, st,
387 &adis16550_firmware_revision_fops);
388 debugfs_create_file("firmware_date", 0400, d, st,
389 &adis16550_firmware_date_fops);
390 debugfs_create_file_unsafe("flash_count", 0400, d, st,
391 &adis16550_flash_count_fops);
392 }
393
394 enum {
395 ADIS16550_SYNC_MODE_DIRECT,
396 ADIS16550_SYNC_MODE_SCALED,
397 };
398
adis16550_get_freq(struct adis16550 * st,u32 * freq)399 static int adis16550_get_freq(struct adis16550 *st, u32 *freq)
400 {
401 int ret;
402 u16 dec = 0;
403 u32 sample_rate = st->clk_freq_hz;
404
405 adis_dev_auto_lock(&st->adis);
406
407 if (st->sync_mode == ADIS16550_SYNC_MODE_SCALED) {
408 u16 sync_scale;
409
410 ret = __adis_read_reg_16(&st->adis, ADIS16550_REG_SYNC_SCALE, &sync_scale);
411 if (ret)
412 return ret;
413
414 sample_rate = st->clk_freq_hz * sync_scale;
415 }
416
417 ret = __adis_read_reg_16(&st->adis, ADIS16550_REG_DEC_RATE, &dec);
418 if (ret)
419 return -EINVAL;
420 *freq = DIV_ROUND_CLOSEST(sample_rate, dec + 1);
421
422 return 0;
423 }
424
adis16550_set_freq_hz(struct adis16550 * st,u32 freq_hz)425 static int adis16550_set_freq_hz(struct adis16550 *st, u32 freq_hz)
426 {
427 u16 dec;
428 int ret;
429 u32 sample_rate = st->clk_freq_hz;
430 /*
431 * The optimal sample rate for the supported IMUs is between
432 * int_clk - 1000 and int_clk + 500.
433 */
434 u32 max_sample_rate = 4000 * 1000 + 500000;
435 u32 min_sample_rate = 4000 * 1000 - 1000000;
436
437 if (!freq_hz)
438 return -EINVAL;
439
440 adis_dev_auto_lock(&st->adis);
441
442 if (st->sync_mode == ADIS16550_SYNC_MODE_SCALED) {
443 unsigned long scaled_rate = lcm(st->clk_freq_hz, freq_hz);
444 int sync_scale;
445
446 if (scaled_rate > max_sample_rate)
447 scaled_rate = max_sample_rate / st->clk_freq_hz * st->clk_freq_hz;
448 else
449 scaled_rate = max_sample_rate / scaled_rate * scaled_rate;
450
451 if (scaled_rate < min_sample_rate)
452 scaled_rate = roundup(min_sample_rate, st->clk_freq_hz);
453
454 sync_scale = scaled_rate / st->clk_freq_hz;
455 ret = __adis_write_reg_16(&st->adis, ADIS16550_REG_SYNC_SCALE,
456 sync_scale);
457 if (ret)
458 return ret;
459
460 sample_rate = scaled_rate;
461 }
462
463 dec = DIV_ROUND_CLOSEST(sample_rate, freq_hz);
464
465 if (dec)
466 dec--;
467
468 dec = min(dec, 4095);
469
470 return __adis_write_reg_16(&st->adis, ADIS16550_REG_DEC_RATE, dec);
471 }
472
adis16550_get_accl_filter_freq(struct adis16550 * st,int * freq_hz)473 static int adis16550_get_accl_filter_freq(struct adis16550 *st, int *freq_hz)
474 {
475 int ret;
476 u16 config = 0;
477
478 ret = adis_read_reg_16(&st->adis, ADIS16550_REG_CONFIG, &config);
479 if (ret)
480 return -EINVAL;
481
482 if (FIELD_GET(ADIS16550_ACCL_FIR_EN_MASK, config))
483 *freq_hz = 100;
484 else
485 *freq_hz = 0;
486
487 return 0;
488 }
489
adis16550_set_accl_filter_freq(struct adis16550 * st,int freq_hz)490 static int adis16550_set_accl_filter_freq(struct adis16550 *st, int freq_hz)
491 {
492 u8 en = freq_hz ? 1 : 0;
493 u16 val = FIELD_PREP(ADIS16550_ACCL_FIR_EN_MASK, en);
494
495 return __adis_update_bits(&st->adis, ADIS16550_REG_CONFIG,
496 ADIS16550_ACCL_FIR_EN_MASK, val);
497 }
498
adis16550_get_gyro_filter_freq(struct adis16550 * st,int * freq_hz)499 static int adis16550_get_gyro_filter_freq(struct adis16550 *st, int *freq_hz)
500 {
501 int ret;
502 u16 config = 0;
503
504 ret = adis_read_reg_16(&st->adis, ADIS16550_REG_CONFIG, &config);
505 if (ret)
506 return -EINVAL;
507
508 if (FIELD_GET(ADIS16550_GYRO_FIR_EN_MASK, config))
509 *freq_hz = 100;
510 else
511 *freq_hz = 0;
512
513 return 0;
514 }
515
adis16550_set_gyro_filter_freq(struct adis16550 * st,int freq_hz)516 static int adis16550_set_gyro_filter_freq(struct adis16550 *st, int freq_hz)
517 {
518 u8 en = freq_hz ? 1 : 0;
519 u16 val = FIELD_PREP(ADIS16550_GYRO_FIR_EN_MASK, en);
520
521 return __adis_update_bits(&st->adis, ADIS16550_REG_CONFIG,
522 ADIS16550_GYRO_FIR_EN_MASK, val);
523 }
524
525 enum {
526 ADIS16550_SCAN_TEMP,
527 ADIS16550_SCAN_GYRO_X,
528 ADIS16550_SCAN_GYRO_Y,
529 ADIS16550_SCAN_GYRO_Z,
530 ADIS16550_SCAN_ACCEL_X,
531 ADIS16550_SCAN_ACCEL_Y,
532 ADIS16550_SCAN_ACCEL_Z,
533 ADIS16550_SCAN_DELTANG_X,
534 ADIS16550_SCAN_DELTANG_Y,
535 ADIS16550_SCAN_DELTANG_Z,
536 ADIS16550_SCAN_DELTVEL_X,
537 ADIS16550_SCAN_DELTVEL_Y,
538 ADIS16550_SCAN_DELTVEL_Z,
539 };
540
541 static const u32 adis16550_calib_bias[] = {
542 [ADIS16550_SCAN_GYRO_X] = ADIS16550_REG_X_GYRO_BIAS,
543 [ADIS16550_SCAN_GYRO_Y] = ADIS16550_REG_Y_GYRO_BIAS,
544 [ADIS16550_SCAN_GYRO_Z] = ADIS16550_REG_Z_GYRO_BIAS,
545 [ADIS16550_SCAN_ACCEL_X] = ADIS16550_REG_X_ACCEL_BIAS,
546 [ADIS16550_SCAN_ACCEL_Y] = ADIS16550_REG_Y_ACCEL_BIAS,
547 [ADIS16550_SCAN_ACCEL_Z] = ADIS16550_REG_Z_ACCEL_BIAS,
548
549 };
550
551 static const u32 adis16550_calib_scale[] = {
552 [ADIS16550_SCAN_GYRO_X] = ADIS16550_REG_X_GYRO_SCALE,
553 [ADIS16550_SCAN_GYRO_Y] = ADIS16550_REG_Y_GYRO_SCALE,
554 [ADIS16550_SCAN_GYRO_Z] = ADIS16550_REG_Z_GYRO_SCALE,
555 [ADIS16550_SCAN_ACCEL_X] = ADIS16550_REG_X_ACCEL_SCALE,
556 [ADIS16550_SCAN_ACCEL_Y] = ADIS16550_REG_Y_ACCEL_SCALE,
557 [ADIS16550_SCAN_ACCEL_Z] = ADIS16550_REG_Z_ACCEL_SCALE,
558 };
559
adis16550_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)560 static int adis16550_read_raw(struct iio_dev *indio_dev,
561 const struct iio_chan_spec *chan,
562 int *val, int *val2, long info)
563 {
564 struct adis16550 *st = iio_priv(indio_dev);
565 const int idx = chan->scan_index;
566 u16 scale;
567 int ret;
568 u32 tmp;
569
570 switch (info) {
571 case IIO_CHAN_INFO_RAW:
572 return adis_single_conversion(indio_dev, chan, 0, val);
573 case IIO_CHAN_INFO_SCALE:
574 switch (chan->type) {
575 case IIO_ANGL_VEL:
576 *val = 1;
577 *val2 = IIO_RAD_TO_DEGREE(80 << 16);
578 return IIO_VAL_FRACTIONAL;
579 case IIO_ACCEL:
580 *val = 1;
581 *val2 = IIO_M_S_2_TO_G(102400000);
582 return IIO_VAL_FRACTIONAL;
583 case IIO_TEMP:
584 *val = 4;
585 return IIO_VAL_INT;
586 case IIO_DELTA_ANGL:
587 *val = IIO_DEGREE_TO_RAD(720);
588 *val2 = 31;
589 return IIO_VAL_FRACTIONAL_LOG2;
590 case IIO_DELTA_VELOCITY:
591 *val = 125;
592 *val2 = 31;
593 return IIO_VAL_FRACTIONAL_LOG2;
594 default:
595 return -EINVAL;
596 }
597 case IIO_CHAN_INFO_OFFSET:
598 /* temperature centered at 25°C divided by temp scale */
599 *val = 25000 / 4;
600 return IIO_VAL_INT;
601 case IIO_CHAN_INFO_CALIBBIAS:
602 ret = adis_read_reg_32(&st->adis,
603 adis16550_calib_bias[idx], val);
604 if (ret)
605 return ret;
606
607 return IIO_VAL_INT;
608 case IIO_CHAN_INFO_CALIBSCALE:
609 ret = adis_read_reg_16(&st->adis,
610 adis16550_calib_scale[idx], &scale);
611 if (ret)
612 return ret;
613
614 *val = scale;
615 return IIO_VAL_INT;
616 case IIO_CHAN_INFO_SAMP_FREQ:
617 ret = adis16550_get_freq(st, &tmp);
618 if (ret)
619 return ret;
620
621 *val = tmp / 1000;
622 *val2 = (tmp % 1000) * 1000;
623 return IIO_VAL_INT_PLUS_MICRO;
624 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
625 switch (chan->type) {
626 case IIO_ANGL_VEL:
627 ret = adis16550_get_gyro_filter_freq(st, val);
628 if (ret)
629 return ret;
630 return IIO_VAL_INT;
631 case IIO_ACCEL:
632 ret = adis16550_get_accl_filter_freq(st, val);
633 if (ret)
634 return ret;
635 return IIO_VAL_INT;
636 default:
637 return -EINVAL;
638 }
639 default:
640 return -EINVAL;
641 }
642 }
643
adis16550_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long info)644 static int adis16550_write_raw(struct iio_dev *indio_dev,
645 const struct iio_chan_spec *chan,
646 int val, int val2, long info)
647 {
648 struct adis16550 *st = iio_priv(indio_dev);
649 const int idx = chan->scan_index;
650 u32 tmp;
651
652 switch (info) {
653 case IIO_CHAN_INFO_SAMP_FREQ:
654 tmp = val * 1000 + val2 / 1000;
655 return adis16550_set_freq_hz(st, tmp);
656 case IIO_CHAN_INFO_CALIBBIAS:
657 return adis_write_reg_32(&st->adis, adis16550_calib_bias[idx],
658 val);
659 case IIO_CHAN_INFO_CALIBSCALE:
660 return adis_write_reg_16(&st->adis, adis16550_calib_scale[idx],
661 val);
662 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
663 switch (chan->type) {
664 case IIO_ANGL_VEL:
665 return adis16550_set_gyro_filter_freq(st, val);
666 case IIO_ACCEL:
667 return adis16550_set_accl_filter_freq(st, val);
668 default:
669 return -EINVAL;
670 }
671 default:
672 return -EINVAL;
673 }
674 }
675
676 #define ADIS16550_MOD_CHAN(_type, _mod, _address, _si) \
677 { \
678 .type = (_type), \
679 .modified = 1, \
680 .channel2 = (_mod), \
681 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
682 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
683 BIT(IIO_CHAN_INFO_CALIBSCALE), \
684 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
685 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
686 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
687 .address = (_address), \
688 .scan_index = (_si), \
689 .scan_type = { \
690 .sign = 's', \
691 .realbits = 32, \
692 .storagebits = 32, \
693 .endianness = IIO_BE, \
694 }, \
695 }
696
697 #define ADIS16550_GYRO_CHANNEL(_mod) \
698 ADIS16550_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
699 ADIS16550_REG_ ## _mod ## _GYRO, ADIS16550_SCAN_GYRO_ ## _mod)
700
701 #define ADIS16550_ACCEL_CHANNEL(_mod) \
702 ADIS16550_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \
703 ADIS16550_REG_ ## _mod ## _ACCEL, ADIS16550_SCAN_ACCEL_ ## _mod)
704
705 #define ADIS16550_TEMP_CHANNEL() { \
706 .type = IIO_TEMP, \
707 .indexed = 1, \
708 .channel = 0, \
709 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
710 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), \
711 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
712 .address = ADIS16550_REG_TEMP, \
713 .scan_index = ADIS16550_SCAN_TEMP, \
714 .scan_type = { \
715 .sign = 's', \
716 .realbits = 16, \
717 .storagebits = 32, \
718 .endianness = IIO_BE, \
719 }, \
720 }
721
722 #define ADIS16550_MOD_CHAN_DELTA(_type, _mod, _address, _si) { \
723 .type = (_type), \
724 .modified = 1, \
725 .channel2 = (_mod), \
726 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
727 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
728 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
729 .address = (_address), \
730 .scan_index = _si, \
731 .scan_type = { \
732 .sign = 's', \
733 .realbits = 32, \
734 .storagebits = 32, \
735 .endianness = IIO_BE, \
736 }, \
737 }
738
739 #define ADIS16550_DELTANG_CHAN(_mod) \
740 ADIS16550_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \
741 ADIS16550_REG_ ## _mod ## _DELTANG_L, ADIS16550_SCAN_DELTANG_ ## _mod)
742
743 #define ADIS16550_DELTVEL_CHAN(_mod) \
744 ADIS16550_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \
745 ADIS16550_REG_ ## _mod ## _DELTVEL_L, ADIS16550_SCAN_DELTVEL_ ## _mod)
746
747 #define ADIS16550_DELTANG_CHAN_NO_SCAN(_mod) \
748 ADIS16550_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \
749 ADIS16550_REG_ ## _mod ## _DELTANG_L, -1)
750
751 #define ADIS16550_DELTVEL_CHAN_NO_SCAN(_mod) \
752 ADIS16550_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \
753 ADIS16550_REG_ ## _mod ## _DELTVEL_L, -1)
754
755 static const struct iio_chan_spec adis16550_channels[] = {
756 ADIS16550_TEMP_CHANNEL(),
757 ADIS16550_GYRO_CHANNEL(X),
758 ADIS16550_GYRO_CHANNEL(Y),
759 ADIS16550_GYRO_CHANNEL(Z),
760 ADIS16550_ACCEL_CHANNEL(X),
761 ADIS16550_ACCEL_CHANNEL(Y),
762 ADIS16550_ACCEL_CHANNEL(Z),
763 ADIS16550_DELTANG_CHAN(X),
764 ADIS16550_DELTANG_CHAN(Y),
765 ADIS16550_DELTANG_CHAN(Z),
766 ADIS16550_DELTVEL_CHAN(X),
767 ADIS16550_DELTVEL_CHAN(Y),
768 ADIS16550_DELTVEL_CHAN(Z),
769 IIO_CHAN_SOFT_TIMESTAMP(13),
770 };
771
772 static const struct adis16550_sync adis16550_sync_modes[] = {
773 { ADIS16550_SYNC_MODE_DIRECT, 3000, 4500 },
774 { ADIS16550_SYNC_MODE_SCALED, 1, 128 },
775 };
776
adis16550_validate_crc(__be32 * buffer,const u8 n_elem)777 static u32 adis16550_validate_crc(__be32 *buffer, const u8 n_elem)
778 {
779 int i;
780 u32 crc_calc;
781 u32 crc_buf[ADIS16550_BURST_N_ELEM - 2];
782 u32 crc = be32_to_cpu(buffer[ADIS16550_BURST_N_ELEM - 1]);
783 /*
784 * The crc calculation of the data is done in little endian. Hence, we
785 * always swap the 32bit elements making sure that the data LSB is
786 * always on address 0...
787 */
788 for (i = 0; i < n_elem; i++)
789 crc_buf[i] = be32_to_cpu(buffer[i]);
790
791 crc_calc = crc32(~0, crc_buf, n_elem * 4);
792 crc_calc ^= ~0;
793
794 return (crc_calc == crc);
795 }
796
adis16550_trigger_handler(int irq,void * p)797 static irqreturn_t adis16550_trigger_handler(int irq, void *p)
798 {
799 int ret;
800 u16 dummy;
801 bool valid;
802 struct iio_poll_func *pf = p;
803 __be32 data[ADIS16550_MAX_SCAN_DATA] __aligned(8) = { };
804 struct iio_dev *indio_dev = pf->indio_dev;
805 struct adis16550 *st = iio_priv(indio_dev);
806 struct adis *adis = iio_device_get_drvdata(indio_dev);
807 __be32 *buffer = (__be32 *)st->buffer;
808
809 ret = spi_sync(adis->spi, &adis->msg);
810 if (ret)
811 goto done;
812 /*
813 * Validate the header. The header is a normal spi reply with state
814 * vector and crc4.
815 */
816 ret = adis16550_spi_validate(&st->adis, buffer[0], &dummy);
817 if (ret)
818 goto done;
819
820 /* the header is not included in the crc */
821 valid = adis16550_validate_crc(buffer, ADIS16550_BURST_N_ELEM - 2);
822 if (!valid) {
823 dev_err(&adis->spi->dev, "Burst Invalid crc!\n");
824 goto done;
825 }
826
827 /* copy the temperature together with sensor data */
828 memcpy(data, &buffer[3],
829 (ADIS16550_SCAN_ACCEL_Z - ADIS16550_SCAN_GYRO_X + 2) *
830 sizeof(__be32));
831 iio_push_to_buffers_with_timestamp(indio_dev, data, pf->timestamp);
832 done:
833 iio_trigger_notify_done(indio_dev->trig);
834 return IRQ_HANDLED;
835 }
836
837 static const unsigned long adis16550_channel_masks[] = {
838 ADIS16550_BURST_DATA_GYRO_ACCEL_MASK | BIT(ADIS16550_SCAN_TEMP),
839 ADIS16550_BURST_DATA_DELTA_ANG_VEL_MASK | BIT(ADIS16550_SCAN_TEMP),
840 0
841 };
842
adis16550_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)843 static int adis16550_update_scan_mode(struct iio_dev *indio_dev,
844 const unsigned long *scan_mask)
845 {
846 u16 burst_length = ADIS16550_BURST_DATA_LEN;
847 struct adis16550 *st = iio_priv(indio_dev);
848 u8 burst_cmd;
849 u8 *tx;
850
851 memset(st->buffer, 0, burst_length + sizeof(u32));
852
853 if (*scan_mask & ADIS16550_BURST_DATA_GYRO_ACCEL_MASK)
854 burst_cmd = ADIS16550_REG_BURST_GYRO_ACCEL;
855 else
856 burst_cmd = ADIS16550_REG_BURST_DELTA_ANG_VEL;
857
858 tx = st->buffer + burst_length;
859 tx[0] = 0x00;
860 tx[1] = 0x00;
861 tx[2] = burst_cmd;
862 /* crc4 is 0 on burst command */
863 tx[3] = spi_crc4(get_unaligned_le32(tx));
864
865 return 0;
866 }
867
adis16550_reset(struct adis * adis)868 static int adis16550_reset(struct adis *adis)
869 {
870 return __adis_write_reg_16(adis, ADIS16550_REG_COMMAND, BIT(15));
871 }
872
adis16550_config_sync(struct adis16550 * st)873 static int adis16550_config_sync(struct adis16550 *st)
874 {
875 struct device *dev = &st->adis.spi->dev;
876 const struct adis16550_sync *sync_mode_data;
877 struct clk *clk;
878 int ret, i;
879 u16 mode;
880
881 clk = devm_clk_get_optional_enabled(dev, NULL);
882 if (IS_ERR(clk))
883 return PTR_ERR(clk);
884 if (!clk) {
885 st->clk_freq_hz = 4000000;
886 return 0;
887 }
888
889 st->clk_freq_hz = clk_get_rate(clk);
890
891 for (i = 0; i < ARRAY_SIZE(adis16550_sync_modes); i++) {
892 if (st->clk_freq_hz >= adis16550_sync_modes[i].min_rate &&
893 st->clk_freq_hz <= adis16550_sync_modes[i].max_rate) {
894 sync_mode_data = &adis16550_sync_modes[i];
895 break;
896 }
897 }
898
899 if (i == ARRAY_SIZE(adis16550_sync_modes))
900 return dev_err_probe(dev, -EINVAL, "Clk rate: %lu not in a valid range",
901 st->clk_freq_hz);
902
903 if (sync_mode_data->sync_mode == ADIS16550_SYNC_MODE_SCALED) {
904 u16 sync_scale;
905 /*
906 * In sps scaled sync we must scale the input clock to a range
907 * of [3000 4500].
908 */
909
910 sync_scale = DIV_ROUND_CLOSEST(4000, st->clk_freq_hz);
911
912 if (3000 > sync_scale || 4500 < sync_scale)
913 return dev_err_probe(dev, -EINVAL,
914 "Invalid value:%u for sync_scale",
915 sync_scale);
916
917 ret = adis_write_reg_16(&st->adis, ADIS16550_REG_SYNC_SCALE,
918 sync_scale);
919 if (ret)
920 return ret;
921
922 st->clk_freq_hz = 4000;
923 }
924
925 st->clk_freq_hz *= 1000;
926
927 mode = FIELD_PREP(ADIS16550_SYNC_MODE_MASK, sync_mode_data->sync_mode) |
928 FIELD_PREP(ADIS16550_SYNC_EN_MASK, true);
929
930 return __adis_update_bits(&st->adis, ADIS16550_REG_CONFIG,
931 ADIS16550_SYNC_MASK, mode);
932 }
933
934 static const struct iio_info adis16550_info = {
935 .read_raw = &adis16550_read_raw,
936 .write_raw = &adis16550_write_raw,
937 .update_scan_mode = adis16550_update_scan_mode,
938 .debugfs_reg_access = adis_debugfs_reg_access,
939 };
940
941 enum {
942 ADIS16550_STATUS_CRC_CODE,
943 ADIS16550_STATUS_CRC_CONFIG,
944 ADIS16550_STATUS_FLASH_UPDATE,
945 ADIS16550_STATUS_INERIAL,
946 ADIS16550_STATUS_SENSOR,
947 ADIS16550_STATUS_TEMPERATURE,
948 ADIS16550_STATUS_SPI,
949 ADIS16550_STATUS_PROCESSING,
950 ADIS16550_STATUS_POWER,
951 ADIS16550_STATUS_BOOT,
952 ADIS16550_STATUS_WATCHDOG = 15,
953 ADIS16550_STATUS_REGULATOR = 28,
954 ADIS16550_STATUS_SENSOR_SUPPLY,
955 ADIS16550_STATUS_CPU_SUPPLY,
956 ADIS16550_STATUS_5V_SUPPLY,
957 };
958
959 static const char * const adis16550_status_error_msgs[] = {
960 [ADIS16550_STATUS_CRC_CODE] = "Code CRC Error",
961 [ADIS16550_STATUS_CRC_CONFIG] = "Configuration/Calibration CRC Error",
962 [ADIS16550_STATUS_FLASH_UPDATE] = "Flash Update Error",
963 [ADIS16550_STATUS_INERIAL] = "Overrange for Inertial Signals",
964 [ADIS16550_STATUS_SENSOR] = "Sensor failure",
965 [ADIS16550_STATUS_TEMPERATURE] = "Temperature Error",
966 [ADIS16550_STATUS_SPI] = "SPI Communication Error",
967 [ADIS16550_STATUS_PROCESSING] = "Processing Overrun Error",
968 [ADIS16550_STATUS_POWER] = "Power Supply Failure",
969 [ADIS16550_STATUS_BOOT] = "Boot Memory Failure",
970 [ADIS16550_STATUS_WATCHDOG] = "Watchdog timer flag",
971 [ADIS16550_STATUS_REGULATOR] = "Internal Regulator Error",
972 [ADIS16550_STATUS_SENSOR_SUPPLY] = "Internal Sensor Supply Error.",
973 [ADIS16550_STATUS_CPU_SUPPLY] = "Internal Processor Supply Error.",
974 [ADIS16550_STATUS_5V_SUPPLY] = "External 5V Supply Error",
975 };
976
977 static const struct adis_timeout adis16550_timeouts = {
978 .reset_ms = 1000,
979 .sw_reset_ms = 1000,
980 .self_test_ms = 1000,
981 };
982
983 static const struct adis_data adis16550_data = {
984 .diag_stat_reg = ADIS16550_REG_STATUS,
985 .diag_stat_size = 4,
986 .prod_id_reg = ADIS16550_REG_PROD_ID,
987 .prod_id = 16550,
988 .self_test_mask = BIT(1),
989 .self_test_reg = ADIS16550_REG_COMMAND,
990 .cs_change_delay = 5,
991 .unmasked_drdy = true,
992 .status_error_msgs = adis16550_status_error_msgs,
993 .status_error_mask = BIT(ADIS16550_STATUS_CRC_CODE) |
994 BIT(ADIS16550_STATUS_CRC_CONFIG) |
995 BIT(ADIS16550_STATUS_FLASH_UPDATE) |
996 BIT(ADIS16550_STATUS_INERIAL) |
997 BIT(ADIS16550_STATUS_SENSOR) |
998 BIT(ADIS16550_STATUS_TEMPERATURE) |
999 BIT(ADIS16550_STATUS_SPI) |
1000 BIT(ADIS16550_STATUS_PROCESSING) |
1001 BIT(ADIS16550_STATUS_POWER) |
1002 BIT(ADIS16550_STATUS_BOOT) |
1003 BIT(ADIS16550_STATUS_WATCHDOG) |
1004 BIT(ADIS16550_STATUS_REGULATOR) |
1005 BIT(ADIS16550_STATUS_SENSOR_SUPPLY) |
1006 BIT(ADIS16550_STATUS_CPU_SUPPLY) |
1007 BIT(ADIS16550_STATUS_5V_SUPPLY),
1008 .timeouts = &adis16550_timeouts,
1009 };
1010
1011 static const struct adis_ops adis16550_ops = {
1012 .write = adis16550_spi_write,
1013 .read = adis16550_spi_read,
1014 .reset = adis16550_reset,
1015 };
1016
adis16550_probe(struct spi_device * spi)1017 static int adis16550_probe(struct spi_device *spi)
1018 {
1019 u16 burst_length = ADIS16550_BURST_DATA_LEN;
1020 struct device *dev = &spi->dev;
1021 struct iio_dev *indio_dev;
1022 struct adis16550 *st;
1023 struct adis *adis;
1024 int ret;
1025
1026 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1027 if (!indio_dev)
1028 return -ENOMEM;
1029
1030 st = iio_priv(indio_dev);
1031
1032 adis = &st->adis;
1033 indio_dev->name = "adis16550";
1034 indio_dev->channels = adis16550_channels;
1035 indio_dev->num_channels = ARRAY_SIZE(adis16550_channels);
1036 indio_dev->available_scan_masks = adis16550_channel_masks;
1037 indio_dev->info = &adis16550_info;
1038 indio_dev->modes = INDIO_DIRECT_MODE;
1039
1040 st->adis.ops = &adis16550_ops;
1041 st->xfer[0].tx_buf = st->buffer + burst_length;
1042 st->xfer[0].len = 4;
1043 st->xfer[0].cs_change = 1;
1044 st->xfer[0].delay.value = 8;
1045 st->xfer[0].delay.unit = SPI_DELAY_UNIT_USECS;
1046 st->xfer[1].rx_buf = st->buffer;
1047 st->xfer[1].len = burst_length;
1048
1049 spi_message_init_with_transfers(&adis->msg, st->xfer, 2);
1050
1051 ret = devm_regulator_get_enable(dev, "vdd");
1052 if (ret)
1053 return dev_err_probe(dev, ret, "Failed to get vdd regulator\n");
1054
1055 ret = adis_init(&st->adis, indio_dev, spi, &adis16550_data);
1056 if (ret)
1057 return ret;
1058
1059 ret = __adis_initial_startup(&st->adis);
1060 if (ret)
1061 return ret;
1062
1063 ret = adis16550_config_sync(st);
1064 if (ret)
1065 return ret;
1066
1067 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
1068 adis16550_trigger_handler);
1069 if (ret)
1070 return ret;
1071
1072 ret = devm_iio_device_register(dev, indio_dev);
1073 if (ret)
1074 return ret;
1075
1076 adis16550_debugfs_init(indio_dev);
1077
1078 return 0;
1079 }
1080
1081 static const struct spi_device_id adis16550_id[] = {
1082 { .name = "adis16550" },
1083 { }
1084 };
1085 MODULE_DEVICE_TABLE(spi, adis16550_id);
1086
1087 static const struct of_device_id adis16550_of_match[] = {
1088 { .compatible = "adi,adis16550" },
1089 { }
1090 };
1091 MODULE_DEVICE_TABLE(of, adis16550_of_match);
1092
1093 static struct spi_driver adis16550_driver = {
1094 .driver = {
1095 .name = "adis16550",
1096 .of_match_table = adis16550_of_match,
1097 },
1098 .probe = adis16550_probe,
1099 .id_table = adis16550_id,
1100 };
1101 module_spi_driver(adis16550_driver);
1102
1103 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
1104 MODULE_AUTHOR("Ramona Gradinariu <ramona.gradinariu@analog.com>");
1105 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>");
1106 MODULE_AUTHOR("Robert Budai <robert.budai@analog.com>");
1107 MODULE_DESCRIPTION("Analog Devices ADIS16550 IMU driver");
1108 MODULE_IMPORT_NS("IIO_ADISLIB");
1109 MODULE_LICENSE("GPL");
1110