1 /*-
2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr>
3 * Copyright (c) 2008 Benjamin Close <benjsc@FreeBSD.org>
4 * Copyright (c) 2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2011 Intel Corporation
6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr>
7 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 */
21
22 /*
23 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network
24 * adapters.
25 */
26
27 #include <sys/cdefs.h>
28 #include "opt_wlan.h"
29 #include "opt_iwn.h"
30
31 #include <sys/param.h>
32 #include <sys/sockio.h>
33 #include <sys/sysctl.h>
34 #include <sys/mbuf.h>
35 #include <sys/kernel.h>
36 #include <sys/socket.h>
37 #include <sys/systm.h>
38 #include <sys/malloc.h>
39 #include <sys/bus.h>
40 #include <sys/conf.h>
41 #include <sys/rman.h>
42 #include <sys/endian.h>
43 #include <sys/firmware.h>
44 #include <sys/limits.h>
45 #include <sys/module.h>
46 #include <sys/priv.h>
47 #include <sys/queue.h>
48 #include <sys/taskqueue.h>
49
50 #include <machine/bus.h>
51 #include <machine/resource.h>
52 #include <machine/clock.h>
53
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
56
57 #include <net/if.h>
58 #include <net/if_var.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61
62 #include <netinet/in.h>
63 #include <netinet/if_ether.h>
64
65 #include <net80211/ieee80211_var.h>
66 #include <net80211/ieee80211_radiotap.h>
67 #include <net80211/ieee80211_regdomain.h>
68 #include <net80211/ieee80211_ratectl.h>
69
70 #include <dev/iwn/if_iwnreg.h>
71 #include <dev/iwn/if_iwnvar.h>
72 #include <dev/iwn/if_iwn_devid.h>
73 #include <dev/iwn/if_iwn_chip_cfg.h>
74 #include <dev/iwn/if_iwn_debug.h>
75 #include <dev/iwn/if_iwn_ioctl.h>
76
77 struct iwn_ident {
78 uint16_t vendor;
79 uint16_t device;
80 const char *name;
81 };
82
83 static const struct iwn_ident iwn_ident_table[] = {
84 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" },
85 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" },
86 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" },
87 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" },
88 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" },
89 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" },
90 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" },
91 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" },
92 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" },
93 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" },
94 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" },
95 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" },
96 { 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN" },
97 { 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN" },
98 /* XXX 2200D is IWN_SDID_2x00_4; there's no way to express this here! */
99 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" },
100 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" },
101 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" },
102 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" },
103 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" },
104 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" },
105 { 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105" },
106 { 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105" },
107 { 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135" },
108 { 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135" },
109 { 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965" },
110 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" },
111 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" },
112 { 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965" },
113 { 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965" },
114 { 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100" },
115 { 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965" },
116 { 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300" },
117 { 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300" },
118 { 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100" },
119 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" },
120 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" },
121 { 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350" },
122 { 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350" },
123 { 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150" },
124 { 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150" },
125 { 0x8086, IWN_DID_6035_1, "Intel Centrino Advanced 6235" },
126 { 0x8086, IWN_DID_6035_2, "Intel Centrino Advanced 6235" },
127 { 0, 0, NULL }
128 };
129
130 static int iwn_probe(device_t);
131 static int iwn_attach(device_t);
132 static void iwn4965_attach(struct iwn_softc *, uint16_t);
133 static void iwn5000_attach(struct iwn_softc *, uint16_t);
134 static int iwn_config_specific(struct iwn_softc *, uint16_t);
135 static void iwn_radiotap_attach(struct iwn_softc *);
136 static void iwn_sysctlattach(struct iwn_softc *);
137 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *,
138 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
139 const uint8_t [IEEE80211_ADDR_LEN],
140 const uint8_t [IEEE80211_ADDR_LEN]);
141 static void iwn_vap_delete(struct ieee80211vap *);
142 static int iwn_detach(device_t);
143 static int iwn_shutdown(device_t);
144 static int iwn_suspend(device_t);
145 static int iwn_resume(device_t);
146 static int iwn_nic_lock(struct iwn_softc *);
147 static int iwn_eeprom_lock(struct iwn_softc *);
148 static int iwn_init_otprom(struct iwn_softc *);
149 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int);
150 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int);
151 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *,
152 void **, bus_size_t, bus_size_t);
153 static void iwn_dma_contig_free(struct iwn_dma_info *);
154 static int iwn_alloc_sched(struct iwn_softc *);
155 static void iwn_free_sched(struct iwn_softc *);
156 static int iwn_alloc_kw(struct iwn_softc *);
157 static void iwn_free_kw(struct iwn_softc *);
158 static int iwn_alloc_ict(struct iwn_softc *);
159 static void iwn_free_ict(struct iwn_softc *);
160 static int iwn_alloc_fwmem(struct iwn_softc *);
161 static void iwn_free_fwmem(struct iwn_softc *);
162 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
163 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
164 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
165 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *,
166 int);
167 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
168 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
169 static void iwn_check_tx_ring(struct iwn_softc *, int);
170 static void iwn5000_ict_reset(struct iwn_softc *);
171 static int iwn_read_eeprom(struct iwn_softc *,
172 uint8_t macaddr[IEEE80211_ADDR_LEN]);
173 static void iwn4965_read_eeprom(struct iwn_softc *);
174 #ifdef IWN_DEBUG
175 static void iwn4965_print_power_group(struct iwn_softc *, int);
176 #endif
177 static void iwn5000_read_eeprom(struct iwn_softc *);
178 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *);
179 static void iwn_read_eeprom_band(struct iwn_softc *, int, int, int *,
180 struct ieee80211_channel[]);
181 static void iwn_read_eeprom_ht40(struct iwn_softc *, int, int, int *,
182 struct ieee80211_channel[]);
183 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t);
184 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *,
185 struct ieee80211_channel *);
186 static void iwn_getradiocaps(struct ieee80211com *, int, int *,
187 struct ieee80211_channel[]);
188 static int iwn_setregdomain(struct ieee80211com *,
189 struct ieee80211_regdomain *, int,
190 struct ieee80211_channel[]);
191 static void iwn_read_eeprom_enhinfo(struct iwn_softc *);
192 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *,
193 const uint8_t mac[IEEE80211_ADDR_LEN]);
194 static void iwn_newassoc(struct ieee80211_node *, int);
195 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
196 static void iwn_calib_timeout(void *);
197 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *);
198 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *,
199 struct iwn_rx_data *);
200 static void iwn_agg_tx_complete(struct iwn_softc *, struct iwn_tx_ring *,
201 int, int, int);
202 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *);
203 static void iwn5000_rx_calib_results(struct iwn_softc *,
204 struct iwn_rx_desc *);
205 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *);
206 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
207 struct iwn_rx_data *);
208 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
209 struct iwn_rx_data *);
210 static void iwn_adj_ampdu_ptr(struct iwn_softc *, struct iwn_tx_ring *);
211 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, int,
212 uint8_t);
213 static int iwn_ampdu_check_bitmap(uint64_t, int, int);
214 static int iwn_ampdu_index_check(struct iwn_softc *, struct iwn_tx_ring *,
215 uint64_t, int, int);
216 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *);
217 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *);
218 static void iwn_notif_intr(struct iwn_softc *);
219 static void iwn_wakeup_intr(struct iwn_softc *);
220 static void iwn_rftoggle_task(void *, int);
221 static void iwn_fatal_intr(struct iwn_softc *);
222 static void iwn_intr(void *);
223 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t,
224 uint16_t);
225 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t,
226 uint16_t);
227 #ifdef notyet
228 static void iwn5000_reset_sched(struct iwn_softc *, int, int);
229 #endif
230 static int iwn_tx_data(struct iwn_softc *, struct mbuf *,
231 struct ieee80211_node *);
232 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *,
233 struct ieee80211_node *,
234 const struct ieee80211_bpf_params *params);
235 static int iwn_tx_cmd(struct iwn_softc *, struct mbuf *,
236 struct ieee80211_node *, struct iwn_tx_ring *);
237 static void iwn_xmit_task(void *arg0, int pending);
238 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
239 const struct ieee80211_bpf_params *);
240 static int iwn_transmit(struct ieee80211com *, struct mbuf *);
241 static void iwn_scan_timeout(void *);
242 static void iwn_watchdog(void *);
243 static int iwn_ioctl(struct ieee80211com *, u_long , void *);
244 static void iwn_parent(struct ieee80211com *);
245 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int);
246 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *,
247 int);
248 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *,
249 int);
250 static int iwn_set_link_quality(struct iwn_softc *,
251 struct ieee80211_node *);
252 static int iwn_add_broadcast_node(struct iwn_softc *, int);
253 static int iwn_updateedca(struct ieee80211com *);
254 static void iwn_set_promisc(struct iwn_softc *);
255 static void iwn_update_promisc(struct ieee80211com *);
256 static void iwn_update_mcast(struct ieee80211com *);
257 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t);
258 static int iwn_set_critical_temp(struct iwn_softc *);
259 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *);
260 static void iwn4965_power_calibration(struct iwn_softc *, int);
261 static int iwn4965_set_txpower(struct iwn_softc *, int);
262 static int iwn5000_set_txpower(struct iwn_softc *, int);
263 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
264 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
265 static int iwn_get_noise(const struct iwn_rx_general_stats *);
266 static int iwn4965_get_temperature(struct iwn_softc *);
267 static int iwn5000_get_temperature(struct iwn_softc *);
268 static int iwn_init_sensitivity(struct iwn_softc *);
269 static void iwn_collect_noise(struct iwn_softc *,
270 const struct iwn_rx_general_stats *);
271 static int iwn4965_init_gains(struct iwn_softc *);
272 static int iwn5000_init_gains(struct iwn_softc *);
273 static int iwn4965_set_gains(struct iwn_softc *);
274 static int iwn5000_set_gains(struct iwn_softc *);
275 static void iwn_tune_sensitivity(struct iwn_softc *,
276 const struct iwn_rx_stats *);
277 static void iwn_save_stats_counters(struct iwn_softc *,
278 const struct iwn_stats *);
279 static int iwn_send_sensitivity(struct iwn_softc *);
280 static void iwn_check_rx_recovery(struct iwn_softc *, struct iwn_stats *);
281 static int iwn_set_pslevel(struct iwn_softc *, int, int, int);
282 static int iwn_send_btcoex(struct iwn_softc *);
283 static int iwn_send_advanced_btcoex(struct iwn_softc *);
284 static int iwn5000_runtime_calib(struct iwn_softc *);
285 static int iwn_check_bss_filter(struct iwn_softc *);
286 static int iwn4965_rxon_assoc(struct iwn_softc *, int);
287 static int iwn5000_rxon_assoc(struct iwn_softc *, int);
288 static int iwn_send_rxon(struct iwn_softc *, int, int);
289 static int iwn_config(struct iwn_softc *);
290 static int iwn_scan(struct iwn_softc *, struct ieee80211vap *,
291 struct ieee80211_scan_state *, struct ieee80211_channel *);
292 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap);
293 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap);
294 static int iwn_ampdu_rx_start(struct ieee80211_node *,
295 struct ieee80211_rx_ampdu *, int, int, int);
296 static void iwn_ampdu_rx_stop(struct ieee80211_node *,
297 struct ieee80211_rx_ampdu *);
298 static int iwn_addba_request(struct ieee80211_node *,
299 struct ieee80211_tx_ampdu *, int, int, int);
300 static int iwn_addba_response(struct ieee80211_node *,
301 struct ieee80211_tx_ampdu *, int, int, int);
302 static int iwn_ampdu_tx_start(struct ieee80211com *,
303 struct ieee80211_node *, uint8_t);
304 static void iwn_ampdu_tx_stop(struct ieee80211_node *,
305 struct ieee80211_tx_ampdu *);
306 static void iwn4965_ampdu_tx_start(struct iwn_softc *,
307 struct ieee80211_node *, int, uint8_t, uint16_t);
308 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int,
309 uint8_t, uint16_t);
310 static void iwn5000_ampdu_tx_start(struct iwn_softc *,
311 struct ieee80211_node *, int, uint8_t, uint16_t);
312 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int,
313 uint8_t, uint16_t);
314 static int iwn5000_query_calibration(struct iwn_softc *);
315 static int iwn5000_send_calibration(struct iwn_softc *);
316 static int iwn5000_send_wimax_coex(struct iwn_softc *);
317 static int iwn5000_crystal_calib(struct iwn_softc *);
318 static int iwn5000_temp_offset_calib(struct iwn_softc *);
319 static int iwn5000_temp_offset_calibv2(struct iwn_softc *);
320 static int iwn4965_post_alive(struct iwn_softc *);
321 static int iwn5000_post_alive(struct iwn_softc *);
322 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *,
323 int);
324 static int iwn4965_load_firmware(struct iwn_softc *);
325 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t,
326 const uint8_t *, int);
327 static int iwn5000_load_firmware(struct iwn_softc *);
328 static int iwn_read_firmware_leg(struct iwn_softc *,
329 struct iwn_fw_info *);
330 static int iwn_read_firmware_tlv(struct iwn_softc *,
331 struct iwn_fw_info *, uint16_t);
332 static int iwn_read_firmware(struct iwn_softc *);
333 static void iwn_unload_firmware(struct iwn_softc *);
334 static int iwn_clock_wait(struct iwn_softc *);
335 static int iwn_apm_init(struct iwn_softc *);
336 static void iwn_apm_stop_master(struct iwn_softc *);
337 static void iwn_apm_stop(struct iwn_softc *);
338 static int iwn4965_nic_config(struct iwn_softc *);
339 static int iwn5000_nic_config(struct iwn_softc *);
340 static int iwn_hw_prepare(struct iwn_softc *);
341 static int iwn_hw_init(struct iwn_softc *);
342 static void iwn_hw_stop(struct iwn_softc *);
343 static void iwn_panicked(void *, int);
344 static int iwn_init_locked(struct iwn_softc *);
345 static int iwn_init(struct iwn_softc *);
346 static void iwn_stop_locked(struct iwn_softc *);
347 static void iwn_stop(struct iwn_softc *);
348 static void iwn_scan_start(struct ieee80211com *);
349 static void iwn_scan_end(struct ieee80211com *);
350 static void iwn_set_channel(struct ieee80211com *);
351 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long);
352 static void iwn_scan_mindwell(struct ieee80211_scan_state *);
353 #ifdef IWN_DEBUG
354 static char *iwn_get_csr_string(int);
355 static void iwn_debug_register(struct iwn_softc *);
356 #endif
357
358 static device_method_t iwn_methods[] = {
359 /* Device interface */
360 DEVMETHOD(device_probe, iwn_probe),
361 DEVMETHOD(device_attach, iwn_attach),
362 DEVMETHOD(device_detach, iwn_detach),
363 DEVMETHOD(device_shutdown, iwn_shutdown),
364 DEVMETHOD(device_suspend, iwn_suspend),
365 DEVMETHOD(device_resume, iwn_resume),
366
367 DEVMETHOD_END
368 };
369
370 static driver_t iwn_driver = {
371 "iwn",
372 iwn_methods,
373 sizeof(struct iwn_softc)
374 };
375
376 DRIVER_MODULE(iwn, pci, iwn_driver, NULL, NULL);
377 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, iwn, iwn_ident_table,
378 nitems(iwn_ident_table) - 1);
379 MODULE_VERSION(iwn, 1);
380
381 MODULE_DEPEND(iwn, firmware, 1, 1, 1);
382 MODULE_DEPEND(iwn, pci, 1, 1, 1);
383 MODULE_DEPEND(iwn, wlan, 1, 1, 1);
384
385 static d_ioctl_t iwn_cdev_ioctl;
386 static d_open_t iwn_cdev_open;
387 static d_close_t iwn_cdev_close;
388
389 static struct cdevsw iwn_cdevsw = {
390 .d_version = D_VERSION,
391 .d_flags = 0,
392 .d_open = iwn_cdev_open,
393 .d_close = iwn_cdev_close,
394 .d_ioctl = iwn_cdev_ioctl,
395 .d_name = "iwn",
396 };
397
398 static int
iwn_probe(device_t dev)399 iwn_probe(device_t dev)
400 {
401 const struct iwn_ident *ident;
402
403 for (ident = iwn_ident_table; ident->name != NULL; ident++) {
404 if (pci_get_vendor(dev) == ident->vendor &&
405 pci_get_device(dev) == ident->device) {
406 device_set_desc(dev, ident->name);
407 return (BUS_PROBE_DEFAULT);
408 }
409 }
410 return ENXIO;
411 }
412
413 static int
iwn_is_3stream_device(struct iwn_softc * sc)414 iwn_is_3stream_device(struct iwn_softc *sc)
415 {
416 /* XXX for now only 5300, until the 5350 can be tested */
417 if (sc->hw_type == IWN_HW_REV_TYPE_5300)
418 return (1);
419 return (0);
420 }
421
422 static int
iwn_attach(device_t dev)423 iwn_attach(device_t dev)
424 {
425 struct iwn_softc *sc = device_get_softc(dev);
426 struct ieee80211com *ic;
427 int i, error, rid;
428
429 sc->sc_dev = dev;
430
431 #ifdef IWN_DEBUG
432 error = resource_int_value(device_get_name(sc->sc_dev),
433 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug));
434 if (error != 0)
435 sc->sc_debug = 0;
436 #else
437 sc->sc_debug = 0;
438 #endif
439
440 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__);
441
442 /*
443 * Get the offset of the PCI Express Capability Structure in PCI
444 * Configuration Space.
445 */
446 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
447 if (error != 0) {
448 device_printf(dev, "PCIe capability structure not found!\n");
449 return error;
450 }
451
452 /* Clear device-specific "PCI retry timeout" register (41h). */
453 pci_write_config(dev, 0x41, 0, 1);
454
455 /* Enable bus-mastering. */
456 pci_enable_busmaster(dev);
457
458 rid = PCIR_BAR(0);
459 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
460 RF_ACTIVE);
461 if (sc->mem == NULL) {
462 device_printf(dev, "can't map mem space\n");
463 error = ENOMEM;
464 return error;
465 }
466 sc->sc_st = rman_get_bustag(sc->mem);
467 sc->sc_sh = rman_get_bushandle(sc->mem);
468
469 i = 1;
470 rid = 0;
471 if (pci_alloc_msi(dev, &i) == 0)
472 rid = 1;
473 /* Install interrupt handler. */
474 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE |
475 (rid != 0 ? 0 : RF_SHAREABLE));
476 if (sc->irq == NULL) {
477 device_printf(dev, "can't map interrupt\n");
478 error = ENOMEM;
479 goto fail;
480 }
481
482 IWN_LOCK_INIT(sc);
483
484 /* Read hardware revision and attach. */
485 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT)
486 & IWN_HW_REV_TYPE_MASK;
487 sc->subdevice_id = pci_get_subdevice(dev);
488
489 /*
490 * 4965 versus 5000 and later have different methods.
491 * Let's set those up first.
492 */
493 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
494 iwn4965_attach(sc, pci_get_device(dev));
495 else
496 iwn5000_attach(sc, pci_get_device(dev));
497
498 /*
499 * Next, let's setup the various parameters of each NIC.
500 */
501 error = iwn_config_specific(sc, pci_get_device(dev));
502 if (error != 0) {
503 device_printf(dev, "could not attach device, error %d\n",
504 error);
505 goto fail;
506 }
507
508 if ((error = iwn_hw_prepare(sc)) != 0) {
509 device_printf(dev, "hardware not ready, error %d\n", error);
510 goto fail;
511 }
512
513 /* Allocate DMA memory for firmware transfers. */
514 if ((error = iwn_alloc_fwmem(sc)) != 0) {
515 device_printf(dev,
516 "could not allocate memory for firmware, error %d\n",
517 error);
518 goto fail;
519 }
520
521 /* Allocate "Keep Warm" page. */
522 if ((error = iwn_alloc_kw(sc)) != 0) {
523 device_printf(dev,
524 "could not allocate keep warm page, error %d\n", error);
525 goto fail;
526 }
527
528 /* Allocate ICT table for 5000 Series. */
529 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
530 (error = iwn_alloc_ict(sc)) != 0) {
531 device_printf(dev, "could not allocate ICT table, error %d\n",
532 error);
533 goto fail;
534 }
535
536 /* Allocate TX scheduler "rings". */
537 if ((error = iwn_alloc_sched(sc)) != 0) {
538 device_printf(dev,
539 "could not allocate TX scheduler rings, error %d\n", error);
540 goto fail;
541 }
542
543 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */
544 for (i = 0; i < sc->ntxqs; i++) {
545 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) {
546 device_printf(dev,
547 "could not allocate TX ring %d, error %d\n", i,
548 error);
549 goto fail;
550 }
551 }
552
553 /* Allocate RX ring. */
554 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) {
555 device_printf(dev, "could not allocate RX ring, error %d\n",
556 error);
557 goto fail;
558 }
559
560 /* Clear pending interrupts. */
561 IWN_WRITE(sc, IWN_INT, 0xffffffff);
562
563 ic = &sc->sc_ic;
564 ic->ic_softc = sc;
565 ic->ic_name = device_get_nameunit(dev);
566 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
567 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
568
569 /* Set device capabilities. */
570 ic->ic_caps =
571 IEEE80211_C_STA /* station mode supported */
572 | IEEE80211_C_MONITOR /* monitor mode supported */
573 #if 0
574 | IEEE80211_C_BGSCAN /* background scanning */
575 #endif
576 | IEEE80211_C_TXPMGT /* tx power management */
577 | IEEE80211_C_SHSLOT /* short slot time supported */
578 | IEEE80211_C_WPA
579 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
580 #if 0
581 | IEEE80211_C_IBSS /* ibss/adhoc mode */
582 #endif
583 | IEEE80211_C_WME /* WME */
584 | IEEE80211_C_PMGT /* Station-side power mgmt */
585 ;
586
587 /* Driver / firmware assigned sequence numbers */
588 ic->ic_flags_ext |= IEEE80211_FEXT_SEQNO_OFFLOAD;
589 /* Don't originate null data frames in net80211 */
590 ic->ic_flags_ext |= IEEE80211_FEXT_NO_NULLDATA;
591
592 /* Read MAC address, channels, etc from EEPROM. */
593 if ((error = iwn_read_eeprom(sc, ic->ic_macaddr)) != 0) {
594 device_printf(dev, "could not read EEPROM, error %d\n",
595 error);
596 goto fail;
597 }
598
599 /* Count the number of available chains. */
600 sc->ntxchains =
601 ((sc->txchainmask >> 2) & 1) +
602 ((sc->txchainmask >> 1) & 1) +
603 ((sc->txchainmask >> 0) & 1);
604 sc->nrxchains =
605 ((sc->rxchainmask >> 2) & 1) +
606 ((sc->rxchainmask >> 1) & 1) +
607 ((sc->rxchainmask >> 0) & 1);
608 if (bootverbose) {
609 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n",
610 sc->ntxchains, sc->nrxchains, sc->eeprom_domain,
611 ic->ic_macaddr, ":");
612 }
613
614 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
615 ic->ic_rxstream = sc->nrxchains;
616 ic->ic_txstream = sc->ntxchains;
617
618 /*
619 * Some of the 3 antenna devices (ie, the 4965) only supports
620 * 2x2 operation. So correct the number of streams if
621 * it's not a 3-stream device.
622 */
623 if (! iwn_is_3stream_device(sc)) {
624 if (ic->ic_rxstream > 2)
625 ic->ic_rxstream = 2;
626 if (ic->ic_txstream > 2)
627 ic->ic_txstream = 2;
628 }
629
630 ic->ic_htcaps =
631 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */
632 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */
633 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/
634 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */
635 #ifdef notyet
636 | IEEE80211_HTCAP_GREENFIELD
637 #if IWN_RBUF_SIZE == 8192
638 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */
639 #else
640 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */
641 #endif
642 #endif
643 /* s/w capabilities */
644 | IEEE80211_HTC_HT /* HT operation */
645 | IEEE80211_HTC_AMPDU /* tx A-MPDU */
646 #ifdef notyet
647 | IEEE80211_HTC_AMSDU /* tx A-MSDU */
648 #endif
649 ;
650 }
651
652 ieee80211_ifattach(ic);
653 ic->ic_vap_create = iwn_vap_create;
654 ic->ic_ioctl = iwn_ioctl;
655 ic->ic_parent = iwn_parent;
656 ic->ic_vap_delete = iwn_vap_delete;
657 ic->ic_transmit = iwn_transmit;
658 ic->ic_raw_xmit = iwn_raw_xmit;
659 ic->ic_node_alloc = iwn_node_alloc;
660 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start;
661 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start;
662 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop;
663 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop;
664 sc->sc_addba_request = ic->ic_addba_request;
665 ic->ic_addba_request = iwn_addba_request;
666 sc->sc_addba_response = ic->ic_addba_response;
667 ic->ic_addba_response = iwn_addba_response;
668 sc->sc_addba_stop = ic->ic_addba_stop;
669 ic->ic_addba_stop = iwn_ampdu_tx_stop;
670 ic->ic_newassoc = iwn_newassoc;
671 ic->ic_wme.wme_update = iwn_updateedca;
672 ic->ic_update_promisc = iwn_update_promisc;
673 ic->ic_update_mcast = iwn_update_mcast;
674 ic->ic_scan_start = iwn_scan_start;
675 ic->ic_scan_end = iwn_scan_end;
676 ic->ic_set_channel = iwn_set_channel;
677 ic->ic_scan_curchan = iwn_scan_curchan;
678 ic->ic_scan_mindwell = iwn_scan_mindwell;
679 ic->ic_getradiocaps = iwn_getradiocaps;
680 ic->ic_setregdomain = iwn_setregdomain;
681
682 iwn_radiotap_attach(sc);
683
684 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0);
685 callout_init_mtx(&sc->scan_timeout, &sc->sc_mtx, 0);
686 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0);
687 TASK_INIT(&sc->sc_rftoggle_task, 0, iwn_rftoggle_task, sc);
688 TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked, sc);
689 TASK_INIT(&sc->sc_xmit_task, 0, iwn_xmit_task, sc);
690
691 mbufq_init(&sc->sc_xmit_queue, 1024);
692
693 sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK,
694 taskqueue_thread_enqueue, &sc->sc_tq);
695 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwn_taskq");
696 if (error != 0) {
697 device_printf(dev, "can't start threads, error %d\n", error);
698 goto fail;
699 }
700
701 iwn_sysctlattach(sc);
702
703 /*
704 * Hook our interrupt after all initialization is complete.
705 */
706 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
707 NULL, iwn_intr, sc, &sc->sc_ih);
708 if (error != 0) {
709 device_printf(dev, "can't establish interrupt, error %d\n",
710 error);
711 goto fail;
712 }
713
714 #if 0
715 device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n",
716 __func__,
717 sizeof(struct iwn_stats),
718 sizeof(struct iwn_stats_bt));
719 #endif
720
721 if (bootverbose)
722 ieee80211_announce(ic);
723 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
724
725 /* Add debug ioctl right at the end */
726 sc->sc_cdev = make_dev(&iwn_cdevsw, device_get_unit(dev),
727 UID_ROOT, GID_WHEEL, 0600, "%s", device_get_nameunit(dev));
728 if (sc->sc_cdev == NULL) {
729 device_printf(dev, "failed to create debug character device\n");
730 } else {
731 sc->sc_cdev->si_drv1 = sc;
732 }
733 return 0;
734 fail:
735 iwn_detach(dev);
736 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__);
737 return error;
738 }
739
740 /*
741 * Define specific configuration based on device id and subdevice id
742 * pid : PCI device id
743 */
744 static int
iwn_config_specific(struct iwn_softc * sc,uint16_t pid)745 iwn_config_specific(struct iwn_softc *sc, uint16_t pid)
746 {
747
748 switch (pid) {
749 /* 4965 series */
750 case IWN_DID_4965_1:
751 case IWN_DID_4965_2:
752 case IWN_DID_4965_3:
753 case IWN_DID_4965_4:
754 sc->base_params = &iwn4965_base_params;
755 sc->limits = &iwn4965_sensitivity_limits;
756 sc->fwname = "iwn4965fw";
757 /* Override chains masks, ROM is known to be broken. */
758 sc->txchainmask = IWN_ANT_AB;
759 sc->rxchainmask = IWN_ANT_ABC;
760 /* Enable normal btcoex */
761 sc->sc_flags |= IWN_FLAG_BTCOEX;
762 break;
763 /* 1000 Series */
764 case IWN_DID_1000_1:
765 case IWN_DID_1000_2:
766 switch(sc->subdevice_id) {
767 case IWN_SDID_1000_1:
768 case IWN_SDID_1000_2:
769 case IWN_SDID_1000_3:
770 case IWN_SDID_1000_4:
771 case IWN_SDID_1000_5:
772 case IWN_SDID_1000_6:
773 case IWN_SDID_1000_7:
774 case IWN_SDID_1000_8:
775 case IWN_SDID_1000_9:
776 case IWN_SDID_1000_10:
777 case IWN_SDID_1000_11:
778 case IWN_SDID_1000_12:
779 sc->limits = &iwn1000_sensitivity_limits;
780 sc->base_params = &iwn1000_base_params;
781 sc->fwname = "iwn1000fw";
782 break;
783 default:
784 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
785 "0x%04x rev %d not supported (subdevice)\n", pid,
786 sc->subdevice_id,sc->hw_type);
787 return ENOTSUP;
788 }
789 break;
790 /* 6x00 Series */
791 case IWN_DID_6x00_2:
792 case IWN_DID_6x00_4:
793 case IWN_DID_6x00_1:
794 case IWN_DID_6x00_3:
795 sc->fwname = "iwn6000fw";
796 sc->limits = &iwn6000_sensitivity_limits;
797 switch(sc->subdevice_id) {
798 case IWN_SDID_6x00_1:
799 case IWN_SDID_6x00_2:
800 case IWN_SDID_6x00_8:
801 //iwl6000_3agn_cfg
802 sc->base_params = &iwn_6000_base_params;
803 break;
804 case IWN_SDID_6x00_3:
805 case IWN_SDID_6x00_6:
806 case IWN_SDID_6x00_9:
807 ////iwl6000i_2agn
808 case IWN_SDID_6x00_4:
809 case IWN_SDID_6x00_7:
810 case IWN_SDID_6x00_10:
811 //iwl6000i_2abg_cfg
812 case IWN_SDID_6x00_5:
813 //iwl6000i_2bg_cfg
814 sc->base_params = &iwn_6000i_base_params;
815 sc->sc_flags |= IWN_FLAG_INTERNAL_PA;
816 sc->txchainmask = IWN_ANT_BC;
817 sc->rxchainmask = IWN_ANT_BC;
818 break;
819 default:
820 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
821 "0x%04x rev %d not supported (subdevice)\n", pid,
822 sc->subdevice_id,sc->hw_type);
823 return ENOTSUP;
824 }
825 break;
826 /* 6x05 Series */
827 case IWN_DID_6x05_1:
828 case IWN_DID_6x05_2:
829 switch(sc->subdevice_id) {
830 case IWN_SDID_6x05_1:
831 case IWN_SDID_6x05_4:
832 case IWN_SDID_6x05_6:
833 //iwl6005_2agn_cfg
834 case IWN_SDID_6x05_2:
835 case IWN_SDID_6x05_5:
836 case IWN_SDID_6x05_7:
837 //iwl6005_2abg_cfg
838 case IWN_SDID_6x05_3:
839 //iwl6005_2bg_cfg
840 case IWN_SDID_6x05_8:
841 case IWN_SDID_6x05_9:
842 //iwl6005_2agn_sff_cfg
843 case IWN_SDID_6x05_10:
844 //iwl6005_2agn_d_cfg
845 case IWN_SDID_6x05_11:
846 //iwl6005_2agn_mow1_cfg
847 case IWN_SDID_6x05_12:
848 //iwl6005_2agn_mow2_cfg
849 sc->fwname = "iwn6000g2afw";
850 sc->limits = &iwn6000_sensitivity_limits;
851 sc->base_params = &iwn_6000g2_base_params;
852 break;
853 default:
854 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
855 "0x%04x rev %d not supported (subdevice)\n", pid,
856 sc->subdevice_id,sc->hw_type);
857 return ENOTSUP;
858 }
859 break;
860 /* 6x35 Series */
861 case IWN_DID_6035_1:
862 case IWN_DID_6035_2:
863 switch(sc->subdevice_id) {
864 case IWN_SDID_6035_1:
865 case IWN_SDID_6035_2:
866 case IWN_SDID_6035_3:
867 case IWN_SDID_6035_4:
868 case IWN_SDID_6035_5:
869 sc->fwname = "iwn6000g2bfw";
870 sc->limits = &iwn6235_sensitivity_limits;
871 sc->base_params = &iwn_6235_base_params;
872 break;
873 default:
874 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
875 "0x%04x rev %d not supported (subdevice)\n", pid,
876 sc->subdevice_id,sc->hw_type);
877 return ENOTSUP;
878 }
879 break;
880 /* 6x50 WiFi/WiMax Series */
881 case IWN_DID_6050_1:
882 case IWN_DID_6050_2:
883 switch(sc->subdevice_id) {
884 case IWN_SDID_6050_1:
885 case IWN_SDID_6050_3:
886 case IWN_SDID_6050_5:
887 //iwl6050_2agn_cfg
888 case IWN_SDID_6050_2:
889 case IWN_SDID_6050_4:
890 case IWN_SDID_6050_6:
891 //iwl6050_2abg_cfg
892 sc->fwname = "iwn6050fw";
893 sc->txchainmask = IWN_ANT_AB;
894 sc->rxchainmask = IWN_ANT_AB;
895 sc->limits = &iwn6000_sensitivity_limits;
896 sc->base_params = &iwn_6050_base_params;
897 break;
898 default:
899 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
900 "0x%04x rev %d not supported (subdevice)\n", pid,
901 sc->subdevice_id,sc->hw_type);
902 return ENOTSUP;
903 }
904 break;
905 /* 6150 WiFi/WiMax Series */
906 case IWN_DID_6150_1:
907 case IWN_DID_6150_2:
908 switch(sc->subdevice_id) {
909 case IWN_SDID_6150_1:
910 case IWN_SDID_6150_3:
911 case IWN_SDID_6150_5:
912 // iwl6150_bgn_cfg
913 case IWN_SDID_6150_2:
914 case IWN_SDID_6150_4:
915 case IWN_SDID_6150_6:
916 //iwl6150_bg_cfg
917 sc->fwname = "iwn6050fw";
918 sc->limits = &iwn6000_sensitivity_limits;
919 sc->base_params = &iwn_6150_base_params;
920 break;
921 default:
922 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
923 "0x%04x rev %d not supported (subdevice)\n", pid,
924 sc->subdevice_id,sc->hw_type);
925 return ENOTSUP;
926 }
927 break;
928 /* 6030 Series and 1030 Series */
929 case IWN_DID_x030_1:
930 case IWN_DID_x030_2:
931 case IWN_DID_x030_3:
932 case IWN_DID_x030_4:
933 switch(sc->subdevice_id) {
934 case IWN_SDID_x030_1:
935 case IWN_SDID_x030_3:
936 case IWN_SDID_x030_5:
937 // iwl1030_bgn_cfg
938 case IWN_SDID_x030_2:
939 case IWN_SDID_x030_4:
940 case IWN_SDID_x030_6:
941 //iwl1030_bg_cfg
942 case IWN_SDID_x030_7:
943 case IWN_SDID_x030_10:
944 case IWN_SDID_x030_14:
945 //iwl6030_2agn_cfg
946 case IWN_SDID_x030_8:
947 case IWN_SDID_x030_11:
948 case IWN_SDID_x030_15:
949 // iwl6030_2bgn_cfg
950 case IWN_SDID_x030_9:
951 case IWN_SDID_x030_12:
952 case IWN_SDID_x030_16:
953 // iwl6030_2abg_cfg
954 case IWN_SDID_x030_13:
955 //iwl6030_2bg_cfg
956 sc->fwname = "iwn6000g2bfw";
957 sc->limits = &iwn6000_sensitivity_limits;
958 sc->base_params = &iwn_6000g2b_base_params;
959 break;
960 default:
961 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
962 "0x%04x rev %d not supported (subdevice)\n", pid,
963 sc->subdevice_id,sc->hw_type);
964 return ENOTSUP;
965 }
966 break;
967 /* 130 Series WiFi */
968 /* XXX: This series will need adjustment for rate.
969 * see rx_with_siso_diversity in linux kernel
970 */
971 case IWN_DID_130_1:
972 case IWN_DID_130_2:
973 switch(sc->subdevice_id) {
974 case IWN_SDID_130_1:
975 case IWN_SDID_130_3:
976 case IWN_SDID_130_5:
977 //iwl130_bgn_cfg
978 case IWN_SDID_130_2:
979 case IWN_SDID_130_4:
980 case IWN_SDID_130_6:
981 //iwl130_bg_cfg
982 sc->fwname = "iwn6000g2bfw";
983 sc->limits = &iwn6000_sensitivity_limits;
984 sc->base_params = &iwn_6000g2b_base_params;
985 break;
986 default:
987 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
988 "0x%04x rev %d not supported (subdevice)\n", pid,
989 sc->subdevice_id,sc->hw_type);
990 return ENOTSUP;
991 }
992 break;
993 /* 100 Series WiFi */
994 case IWN_DID_100_1:
995 case IWN_DID_100_2:
996 switch(sc->subdevice_id) {
997 case IWN_SDID_100_1:
998 case IWN_SDID_100_2:
999 case IWN_SDID_100_3:
1000 case IWN_SDID_100_4:
1001 case IWN_SDID_100_5:
1002 case IWN_SDID_100_6:
1003 sc->limits = &iwn1000_sensitivity_limits;
1004 sc->base_params = &iwn1000_base_params;
1005 sc->fwname = "iwn100fw";
1006 break;
1007 default:
1008 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1009 "0x%04x rev %d not supported (subdevice)\n", pid,
1010 sc->subdevice_id,sc->hw_type);
1011 return ENOTSUP;
1012 }
1013 break;
1014
1015 /* 105 Series */
1016 /* XXX: This series will need adjustment for rate.
1017 * see rx_with_siso_diversity in linux kernel
1018 */
1019 case IWN_DID_105_1:
1020 case IWN_DID_105_2:
1021 switch(sc->subdevice_id) {
1022 case IWN_SDID_105_1:
1023 case IWN_SDID_105_2:
1024 case IWN_SDID_105_3:
1025 //iwl105_bgn_cfg
1026 case IWN_SDID_105_4:
1027 //iwl105_bgn_d_cfg
1028 sc->limits = &iwn2030_sensitivity_limits;
1029 sc->base_params = &iwn2000_base_params;
1030 sc->fwname = "iwn105fw";
1031 break;
1032 default:
1033 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1034 "0x%04x rev %d not supported (subdevice)\n", pid,
1035 sc->subdevice_id,sc->hw_type);
1036 return ENOTSUP;
1037 }
1038 break;
1039
1040 /* 135 Series */
1041 /* XXX: This series will need adjustment for rate.
1042 * see rx_with_siso_diversity in linux kernel
1043 */
1044 case IWN_DID_135_1:
1045 case IWN_DID_135_2:
1046 switch(sc->subdevice_id) {
1047 case IWN_SDID_135_1:
1048 case IWN_SDID_135_2:
1049 case IWN_SDID_135_3:
1050 sc->limits = &iwn2030_sensitivity_limits;
1051 sc->base_params = &iwn2030_base_params;
1052 sc->fwname = "iwn135fw";
1053 break;
1054 default:
1055 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1056 "0x%04x rev %d not supported (subdevice)\n", pid,
1057 sc->subdevice_id,sc->hw_type);
1058 return ENOTSUP;
1059 }
1060 break;
1061
1062 /* 2x00 Series */
1063 case IWN_DID_2x00_1:
1064 case IWN_DID_2x00_2:
1065 switch(sc->subdevice_id) {
1066 case IWN_SDID_2x00_1:
1067 case IWN_SDID_2x00_2:
1068 case IWN_SDID_2x00_3:
1069 //iwl2000_2bgn_cfg
1070 case IWN_SDID_2x00_4:
1071 //iwl2000_2bgn_d_cfg
1072 sc->limits = &iwn2030_sensitivity_limits;
1073 sc->base_params = &iwn2000_base_params;
1074 sc->fwname = "iwn2000fw";
1075 break;
1076 default:
1077 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1078 "0x%04x rev %d not supported (subdevice) \n",
1079 pid, sc->subdevice_id, sc->hw_type);
1080 return ENOTSUP;
1081 }
1082 break;
1083 /* 2x30 Series */
1084 case IWN_DID_2x30_1:
1085 case IWN_DID_2x30_2:
1086 switch(sc->subdevice_id) {
1087 case IWN_SDID_2x30_1:
1088 case IWN_SDID_2x30_3:
1089 case IWN_SDID_2x30_5:
1090 //iwl100_bgn_cfg
1091 case IWN_SDID_2x30_2:
1092 case IWN_SDID_2x30_4:
1093 case IWN_SDID_2x30_6:
1094 //iwl100_bg_cfg
1095 sc->limits = &iwn2030_sensitivity_limits;
1096 sc->base_params = &iwn2030_base_params;
1097 sc->fwname = "iwn2030fw";
1098 break;
1099 default:
1100 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1101 "0x%04x rev %d not supported (subdevice)\n", pid,
1102 sc->subdevice_id,sc->hw_type);
1103 return ENOTSUP;
1104 }
1105 break;
1106 /* 5x00 Series */
1107 case IWN_DID_5x00_1:
1108 case IWN_DID_5x00_2:
1109 case IWN_DID_5x00_3:
1110 case IWN_DID_5x00_4:
1111 sc->limits = &iwn5000_sensitivity_limits;
1112 sc->base_params = &iwn5000_base_params;
1113 sc->fwname = "iwn5000fw";
1114 switch(sc->subdevice_id) {
1115 case IWN_SDID_5x00_1:
1116 case IWN_SDID_5x00_2:
1117 case IWN_SDID_5x00_3:
1118 case IWN_SDID_5x00_4:
1119 case IWN_SDID_5x00_9:
1120 case IWN_SDID_5x00_10:
1121 case IWN_SDID_5x00_11:
1122 case IWN_SDID_5x00_12:
1123 case IWN_SDID_5x00_17:
1124 case IWN_SDID_5x00_18:
1125 case IWN_SDID_5x00_19:
1126 case IWN_SDID_5x00_20:
1127 //iwl5100_agn_cfg
1128 sc->txchainmask = IWN_ANT_B;
1129 sc->rxchainmask = IWN_ANT_AB;
1130 break;
1131 case IWN_SDID_5x00_5:
1132 case IWN_SDID_5x00_6:
1133 case IWN_SDID_5x00_13:
1134 case IWN_SDID_5x00_14:
1135 case IWN_SDID_5x00_21:
1136 case IWN_SDID_5x00_22:
1137 //iwl5100_bgn_cfg
1138 sc->txchainmask = IWN_ANT_B;
1139 sc->rxchainmask = IWN_ANT_AB;
1140 break;
1141 case IWN_SDID_5x00_7:
1142 case IWN_SDID_5x00_8:
1143 case IWN_SDID_5x00_15:
1144 case IWN_SDID_5x00_16:
1145 case IWN_SDID_5x00_23:
1146 case IWN_SDID_5x00_24:
1147 //iwl5100_abg_cfg
1148 sc->txchainmask = IWN_ANT_B;
1149 sc->rxchainmask = IWN_ANT_AB;
1150 break;
1151 case IWN_SDID_5x00_25:
1152 case IWN_SDID_5x00_26:
1153 case IWN_SDID_5x00_27:
1154 case IWN_SDID_5x00_28:
1155 case IWN_SDID_5x00_29:
1156 case IWN_SDID_5x00_30:
1157 case IWN_SDID_5x00_31:
1158 case IWN_SDID_5x00_32:
1159 case IWN_SDID_5x00_33:
1160 case IWN_SDID_5x00_34:
1161 case IWN_SDID_5x00_35:
1162 case IWN_SDID_5x00_36:
1163 //iwl5300_agn_cfg
1164 sc->txchainmask = IWN_ANT_ABC;
1165 sc->rxchainmask = IWN_ANT_ABC;
1166 break;
1167 default:
1168 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1169 "0x%04x rev %d not supported (subdevice)\n", pid,
1170 sc->subdevice_id,sc->hw_type);
1171 return ENOTSUP;
1172 }
1173 break;
1174 /* 5x50 Series */
1175 case IWN_DID_5x50_1:
1176 case IWN_DID_5x50_2:
1177 case IWN_DID_5x50_3:
1178 case IWN_DID_5x50_4:
1179 sc->limits = &iwn5000_sensitivity_limits;
1180 sc->base_params = &iwn5000_base_params;
1181 sc->fwname = "iwn5000fw";
1182 switch(sc->subdevice_id) {
1183 case IWN_SDID_5x50_1:
1184 case IWN_SDID_5x50_2:
1185 case IWN_SDID_5x50_3:
1186 //iwl5350_agn_cfg
1187 sc->limits = &iwn5000_sensitivity_limits;
1188 sc->base_params = &iwn5000_base_params;
1189 sc->fwname = "iwn5000fw";
1190 break;
1191 case IWN_SDID_5x50_4:
1192 case IWN_SDID_5x50_5:
1193 case IWN_SDID_5x50_8:
1194 case IWN_SDID_5x50_9:
1195 case IWN_SDID_5x50_10:
1196 case IWN_SDID_5x50_11:
1197 //iwl5150_agn_cfg
1198 case IWN_SDID_5x50_6:
1199 case IWN_SDID_5x50_7:
1200 case IWN_SDID_5x50_12:
1201 case IWN_SDID_5x50_13:
1202 //iwl5150_abg_cfg
1203 sc->limits = &iwn5000_sensitivity_limits;
1204 sc->fwname = "iwn5150fw";
1205 sc->base_params = &iwn_5x50_base_params;
1206 break;
1207 default:
1208 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1209 "0x%04x rev %d not supported (subdevice)\n", pid,
1210 sc->subdevice_id,sc->hw_type);
1211 return ENOTSUP;
1212 }
1213 break;
1214 default:
1215 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x"
1216 "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id,
1217 sc->hw_type);
1218 return ENOTSUP;
1219 }
1220 return 0;
1221 }
1222
1223 static void
iwn4965_attach(struct iwn_softc * sc,uint16_t pid)1224 iwn4965_attach(struct iwn_softc *sc, uint16_t pid)
1225 {
1226 struct iwn_ops *ops = &sc->ops;
1227
1228 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1229
1230 ops->load_firmware = iwn4965_load_firmware;
1231 ops->read_eeprom = iwn4965_read_eeprom;
1232 ops->post_alive = iwn4965_post_alive;
1233 ops->nic_config = iwn4965_nic_config;
1234 ops->update_sched = iwn4965_update_sched;
1235 ops->get_temperature = iwn4965_get_temperature;
1236 ops->get_rssi = iwn4965_get_rssi;
1237 ops->set_txpower = iwn4965_set_txpower;
1238 ops->init_gains = iwn4965_init_gains;
1239 ops->set_gains = iwn4965_set_gains;
1240 ops->rxon_assoc = iwn4965_rxon_assoc;
1241 ops->add_node = iwn4965_add_node;
1242 ops->tx_done = iwn4965_tx_done;
1243 ops->ampdu_tx_start = iwn4965_ampdu_tx_start;
1244 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop;
1245 sc->ntxqs = IWN4965_NTXQUEUES;
1246 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE;
1247 sc->ndmachnls = IWN4965_NDMACHNLS;
1248 sc->broadcast_id = IWN4965_ID_BROADCAST;
1249 sc->rxonsz = IWN4965_RXONSZ;
1250 sc->schedsz = IWN4965_SCHEDSZ;
1251 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ;
1252 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ;
1253 sc->fwsz = IWN4965_FWSZ;
1254 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT;
1255 sc->limits = &iwn4965_sensitivity_limits;
1256 sc->fwname = "iwn4965fw";
1257 /* Override chains masks, ROM is known to be broken. */
1258 sc->txchainmask = IWN_ANT_AB;
1259 sc->rxchainmask = IWN_ANT_ABC;
1260 /* Enable normal btcoex */
1261 sc->sc_flags |= IWN_FLAG_BTCOEX;
1262
1263 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__);
1264 }
1265
1266 static void
iwn5000_attach(struct iwn_softc * sc,uint16_t pid)1267 iwn5000_attach(struct iwn_softc *sc, uint16_t pid)
1268 {
1269 struct iwn_ops *ops = &sc->ops;
1270
1271 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1272
1273 ops->load_firmware = iwn5000_load_firmware;
1274 ops->read_eeprom = iwn5000_read_eeprom;
1275 ops->post_alive = iwn5000_post_alive;
1276 ops->nic_config = iwn5000_nic_config;
1277 ops->update_sched = iwn5000_update_sched;
1278 ops->get_temperature = iwn5000_get_temperature;
1279 ops->get_rssi = iwn5000_get_rssi;
1280 ops->set_txpower = iwn5000_set_txpower;
1281 ops->init_gains = iwn5000_init_gains;
1282 ops->set_gains = iwn5000_set_gains;
1283 ops->rxon_assoc = iwn5000_rxon_assoc;
1284 ops->add_node = iwn5000_add_node;
1285 ops->tx_done = iwn5000_tx_done;
1286 ops->ampdu_tx_start = iwn5000_ampdu_tx_start;
1287 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop;
1288 sc->ntxqs = IWN5000_NTXQUEUES;
1289 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE;
1290 sc->ndmachnls = IWN5000_NDMACHNLS;
1291 sc->broadcast_id = IWN5000_ID_BROADCAST;
1292 sc->rxonsz = IWN5000_RXONSZ;
1293 sc->schedsz = IWN5000_SCHEDSZ;
1294 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ;
1295 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ;
1296 sc->fwsz = IWN5000_FWSZ;
1297 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT;
1298 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN;
1299 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN;
1300
1301 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__);
1302 }
1303
1304 /*
1305 * Attach the interface to 802.11 radiotap.
1306 */
1307 static void
iwn_radiotap_attach(struct iwn_softc * sc)1308 iwn_radiotap_attach(struct iwn_softc *sc)
1309 {
1310
1311 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1312 ieee80211_radiotap_attach(&sc->sc_ic,
1313 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
1314 IWN_TX_RADIOTAP_PRESENT,
1315 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
1316 IWN_RX_RADIOTAP_PRESENT);
1317 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
1318 }
1319
1320 static void
iwn_sysctlattach(struct iwn_softc * sc)1321 iwn_sysctlattach(struct iwn_softc *sc)
1322 {
1323 #ifdef IWN_DEBUG
1324 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
1325 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
1326
1327 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
1328 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug,
1329 "control debugging printfs");
1330 #endif
1331 }
1332
1333 static struct ieee80211vap *
iwn_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])1334 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1335 enum ieee80211_opmode opmode, int flags,
1336 const uint8_t bssid[IEEE80211_ADDR_LEN],
1337 const uint8_t mac[IEEE80211_ADDR_LEN])
1338 {
1339 struct iwn_softc *sc = ic->ic_softc;
1340 struct iwn_vap *ivp;
1341 struct ieee80211vap *vap;
1342
1343 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
1344 return NULL;
1345
1346 ivp = malloc(sizeof(struct iwn_vap), M_80211_VAP, M_WAITOK | M_ZERO);
1347 vap = &ivp->iv_vap;
1348 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
1349 ivp->ctx = IWN_RXON_BSS_CTX;
1350 vap->iv_bmissthreshold = 10; /* override default */
1351 /* Override with driver methods. */
1352 ivp->iv_newstate = vap->iv_newstate;
1353 vap->iv_newstate = iwn_newstate;
1354 sc->ivap[IWN_RXON_BSS_CTX] = vap;
1355 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1356 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_4; /* 4uS */
1357
1358 ieee80211_ratectl_init(vap);
1359 /* Complete setup. */
1360 ieee80211_vap_attach(vap, ieee80211_media_change,
1361 ieee80211_media_status, mac);
1362 ic->ic_opmode = opmode;
1363 return vap;
1364 }
1365
1366 static void
iwn_vap_delete(struct ieee80211vap * vap)1367 iwn_vap_delete(struct ieee80211vap *vap)
1368 {
1369 struct iwn_vap *ivp = IWN_VAP(vap);
1370
1371 ieee80211_ratectl_deinit(vap);
1372 ieee80211_vap_detach(vap);
1373 free(ivp, M_80211_VAP);
1374 }
1375
1376 static void
iwn_xmit_queue_drain(struct iwn_softc * sc)1377 iwn_xmit_queue_drain(struct iwn_softc *sc)
1378 {
1379 struct mbuf *m;
1380 struct ieee80211_node *ni;
1381
1382 IWN_LOCK_ASSERT(sc);
1383 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) {
1384 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1385 ieee80211_free_node(ni);
1386 m_freem(m);
1387 }
1388 }
1389
1390 static int
iwn_xmit_queue_enqueue(struct iwn_softc * sc,struct mbuf * m)1391 iwn_xmit_queue_enqueue(struct iwn_softc *sc, struct mbuf *m)
1392 {
1393
1394 IWN_LOCK_ASSERT(sc);
1395 return (mbufq_enqueue(&sc->sc_xmit_queue, m));
1396 }
1397
1398 static int
iwn_detach(device_t dev)1399 iwn_detach(device_t dev)
1400 {
1401 struct iwn_softc *sc = device_get_softc(dev);
1402 int qid;
1403
1404 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1405
1406 if (sc->sc_ic.ic_softc != NULL) {
1407 /* Free the mbuf queue and node references */
1408 IWN_LOCK(sc);
1409 iwn_xmit_queue_drain(sc);
1410 IWN_UNLOCK(sc);
1411
1412 iwn_stop(sc);
1413
1414 taskqueue_drain_all(sc->sc_tq);
1415 taskqueue_free(sc->sc_tq);
1416
1417 callout_drain(&sc->watchdog_to);
1418 callout_drain(&sc->scan_timeout);
1419 callout_drain(&sc->calib_to);
1420 ieee80211_ifdetach(&sc->sc_ic);
1421 }
1422
1423 /* Uninstall interrupt handler. */
1424 if (sc->irq != NULL) {
1425 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
1426 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq),
1427 sc->irq);
1428 pci_release_msi(dev);
1429 }
1430
1431 /* Free DMA resources. */
1432 iwn_free_rx_ring(sc, &sc->rxq);
1433 for (qid = 0; qid < sc->ntxqs; qid++)
1434 iwn_free_tx_ring(sc, &sc->txq[qid]);
1435 iwn_free_sched(sc);
1436 iwn_free_kw(sc);
1437 if (sc->ict != NULL)
1438 iwn_free_ict(sc);
1439 iwn_free_fwmem(sc);
1440
1441 if (sc->mem != NULL)
1442 bus_release_resource(dev, SYS_RES_MEMORY,
1443 rman_get_rid(sc->mem), sc->mem);
1444
1445 if (sc->sc_cdev) {
1446 destroy_dev(sc->sc_cdev);
1447 sc->sc_cdev = NULL;
1448 }
1449
1450 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__);
1451 IWN_LOCK_DESTROY(sc);
1452 return 0;
1453 }
1454
1455 static int
iwn_shutdown(device_t dev)1456 iwn_shutdown(device_t dev)
1457 {
1458 struct iwn_softc *sc = device_get_softc(dev);
1459
1460 iwn_stop(sc);
1461 return 0;
1462 }
1463
1464 static int
iwn_suspend(device_t dev)1465 iwn_suspend(device_t dev)
1466 {
1467 struct iwn_softc *sc = device_get_softc(dev);
1468
1469 ieee80211_suspend_all(&sc->sc_ic);
1470 return 0;
1471 }
1472
1473 static int
iwn_resume(device_t dev)1474 iwn_resume(device_t dev)
1475 {
1476 struct iwn_softc *sc = device_get_softc(dev);
1477
1478 /* Clear device-specific "PCI retry timeout" register (41h). */
1479 pci_write_config(dev, 0x41, 0, 1);
1480
1481 ieee80211_resume_all(&sc->sc_ic);
1482 return 0;
1483 }
1484
1485 static int
iwn_nic_lock(struct iwn_softc * sc)1486 iwn_nic_lock(struct iwn_softc *sc)
1487 {
1488 int ntries;
1489
1490 /* Request exclusive access to NIC. */
1491 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
1492
1493 /* Spin until we actually get the lock. */
1494 for (ntries = 0; ntries < 1000; ntries++) {
1495 if ((IWN_READ(sc, IWN_GP_CNTRL) &
1496 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) ==
1497 IWN_GP_CNTRL_MAC_ACCESS_ENA)
1498 return 0;
1499 DELAY(10);
1500 }
1501 return ETIMEDOUT;
1502 }
1503
1504 static __inline void
iwn_nic_unlock(struct iwn_softc * sc)1505 iwn_nic_unlock(struct iwn_softc *sc)
1506 {
1507 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
1508 }
1509
1510 static __inline uint32_t
iwn_prph_read(struct iwn_softc * sc,uint32_t addr)1511 iwn_prph_read(struct iwn_softc *sc, uint32_t addr)
1512 {
1513 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr);
1514 IWN_BARRIER_READ_WRITE(sc);
1515 return IWN_READ(sc, IWN_PRPH_RDATA);
1516 }
1517
1518 static __inline void
iwn_prph_write(struct iwn_softc * sc,uint32_t addr,uint32_t data)1519 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
1520 {
1521 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr);
1522 IWN_BARRIER_WRITE(sc);
1523 IWN_WRITE(sc, IWN_PRPH_WDATA, data);
1524 }
1525
1526 static __inline void
iwn_prph_setbits(struct iwn_softc * sc,uint32_t addr,uint32_t mask)1527 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
1528 {
1529 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask);
1530 }
1531
1532 static __inline void
iwn_prph_clrbits(struct iwn_softc * sc,uint32_t addr,uint32_t mask)1533 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
1534 {
1535 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask);
1536 }
1537
1538 static __inline void
iwn_prph_write_region_4(struct iwn_softc * sc,uint32_t addr,const uint32_t * data,int count)1539 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr,
1540 const uint32_t *data, int count)
1541 {
1542 for (; count > 0; count--, data++, addr += 4)
1543 iwn_prph_write(sc, addr, *data);
1544 }
1545
1546 static __inline uint32_t
iwn_mem_read(struct iwn_softc * sc,uint32_t addr)1547 iwn_mem_read(struct iwn_softc *sc, uint32_t addr)
1548 {
1549 IWN_WRITE(sc, IWN_MEM_RADDR, addr);
1550 IWN_BARRIER_READ_WRITE(sc);
1551 return IWN_READ(sc, IWN_MEM_RDATA);
1552 }
1553
1554 static __inline void
iwn_mem_write(struct iwn_softc * sc,uint32_t addr,uint32_t data)1555 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
1556 {
1557 IWN_WRITE(sc, IWN_MEM_WADDR, addr);
1558 IWN_BARRIER_WRITE(sc);
1559 IWN_WRITE(sc, IWN_MEM_WDATA, data);
1560 }
1561
1562 static __inline void
iwn_mem_write_2(struct iwn_softc * sc,uint32_t addr,uint16_t data)1563 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data)
1564 {
1565 uint32_t tmp;
1566
1567 tmp = iwn_mem_read(sc, addr & ~3);
1568 if (addr & 3)
1569 tmp = (tmp & 0x0000ffff) | data << 16;
1570 else
1571 tmp = (tmp & 0xffff0000) | data;
1572 iwn_mem_write(sc, addr & ~3, tmp);
1573 }
1574
1575 static __inline void
iwn_mem_read_region_4(struct iwn_softc * sc,uint32_t addr,uint32_t * data,int count)1576 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data,
1577 int count)
1578 {
1579 for (; count > 0; count--, addr += 4)
1580 *data++ = iwn_mem_read(sc, addr);
1581 }
1582
1583 static __inline void
iwn_mem_set_region_4(struct iwn_softc * sc,uint32_t addr,uint32_t val,int count)1584 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,
1585 int count)
1586 {
1587 for (; count > 0; count--, addr += 4)
1588 iwn_mem_write(sc, addr, val);
1589 }
1590
1591 static int
iwn_eeprom_lock(struct iwn_softc * sc)1592 iwn_eeprom_lock(struct iwn_softc *sc)
1593 {
1594 int i, ntries;
1595
1596 for (i = 0; i < 100; i++) {
1597 /* Request exclusive access to EEPROM. */
1598 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
1599 IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1600
1601 /* Spin until we actually get the lock. */
1602 for (ntries = 0; ntries < 100; ntries++) {
1603 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
1604 IWN_HW_IF_CONFIG_EEPROM_LOCKED)
1605 return 0;
1606 DELAY(10);
1607 }
1608 }
1609 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__);
1610 return ETIMEDOUT;
1611 }
1612
1613 static __inline void
iwn_eeprom_unlock(struct iwn_softc * sc)1614 iwn_eeprom_unlock(struct iwn_softc *sc)
1615 {
1616 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1617 }
1618
1619 /*
1620 * Initialize access by host to One Time Programmable ROM.
1621 * NB: This kind of ROM can be found on 1000 or 6000 Series only.
1622 */
1623 static int
iwn_init_otprom(struct iwn_softc * sc)1624 iwn_init_otprom(struct iwn_softc *sc)
1625 {
1626 uint16_t prev, base, next;
1627 int count, error;
1628
1629 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1630
1631 /* Wait for clock stabilization before accessing prph. */
1632 if ((error = iwn_clock_wait(sc)) != 0)
1633 return error;
1634
1635 if ((error = iwn_nic_lock(sc)) != 0)
1636 return error;
1637 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1638 DELAY(5);
1639 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1640 iwn_nic_unlock(sc);
1641
1642 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
1643 if (sc->base_params->shadow_ram_support) {
1644 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT,
1645 IWN_RESET_LINK_PWR_MGMT_DIS);
1646 }
1647 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER);
1648 /* Clear ECC status. */
1649 IWN_SETBITS(sc, IWN_OTP_GP,
1650 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS);
1651
1652 /*
1653 * Find the block before last block (contains the EEPROM image)
1654 * for HW without OTP shadow RAM.
1655 */
1656 if (! sc->base_params->shadow_ram_support) {
1657 /* Switch to absolute addressing mode. */
1658 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS);
1659 base = prev = 0;
1660 for (count = 0; count < sc->base_params->max_ll_items;
1661 count++) {
1662 error = iwn_read_prom_data(sc, base, &next, 2);
1663 if (error != 0)
1664 return error;
1665 if (next == 0) /* End of linked-list. */
1666 break;
1667 prev = base;
1668 base = le16toh(next);
1669 }
1670 if (count == 0 || count == sc->base_params->max_ll_items)
1671 return EIO;
1672 /* Skip "next" word. */
1673 sc->prom_base = prev + 1;
1674 }
1675
1676 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
1677
1678 return 0;
1679 }
1680
1681 static int
iwn_read_prom_data(struct iwn_softc * sc,uint32_t addr,void * data,int count)1682 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count)
1683 {
1684 uint8_t *out = data;
1685 uint32_t val, tmp;
1686 int ntries;
1687
1688 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1689
1690 addr += sc->prom_base;
1691 for (; count > 0; count -= 2, addr++) {
1692 IWN_WRITE(sc, IWN_EEPROM, addr << 2);
1693 for (ntries = 0; ntries < 20; ntries++) {
1694 val = IWN_READ(sc, IWN_EEPROM);
1695 if (val & IWN_EEPROM_READ_VALID)
1696 break;
1697 DELAY(5);
1698 }
1699 if (ntries == 20) {
1700 device_printf(sc->sc_dev,
1701 "timeout reading ROM at 0x%x\n", addr);
1702 return ETIMEDOUT;
1703 }
1704 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1705 /* OTPROM, check for ECC errors. */
1706 tmp = IWN_READ(sc, IWN_OTP_GP);
1707 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
1708 device_printf(sc->sc_dev,
1709 "OTPROM ECC error at 0x%x\n", addr);
1710 return EIO;
1711 }
1712 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
1713 /* Correctable ECC error, clear bit. */
1714 IWN_SETBITS(sc, IWN_OTP_GP,
1715 IWN_OTP_GP_ECC_CORR_STTS);
1716 }
1717 }
1718 *out++ = val >> 16;
1719 if (count > 1)
1720 *out++ = val >> 24;
1721 }
1722
1723 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
1724
1725 return 0;
1726 }
1727
1728 static void
iwn_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nsegs,int error)1729 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1730 {
1731 if (error != 0)
1732 return;
1733 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs));
1734 *(bus_addr_t *)arg = segs[0].ds_addr;
1735 }
1736
1737 static int
iwn_dma_contig_alloc(struct iwn_softc * sc,struct iwn_dma_info * dma,void ** kvap,bus_size_t size,bus_size_t alignment)1738 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma,
1739 void **kvap, bus_size_t size, bus_size_t alignment)
1740 {
1741 int error;
1742
1743 dma->tag = NULL;
1744 dma->size = size;
1745
1746 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment,
1747 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size,
1748 1, size, 0, NULL, NULL, &dma->tag);
1749 if (error != 0)
1750 goto fail;
1751
1752 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr,
1753 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map);
1754 if (error != 0)
1755 goto fail;
1756
1757 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size,
1758 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT);
1759 if (error != 0)
1760 goto fail;
1761
1762 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
1763
1764 if (kvap != NULL)
1765 *kvap = dma->vaddr;
1766
1767 return 0;
1768
1769 fail: iwn_dma_contig_free(dma);
1770 return error;
1771 }
1772
1773 static void
iwn_dma_contig_free(struct iwn_dma_info * dma)1774 iwn_dma_contig_free(struct iwn_dma_info *dma)
1775 {
1776 if (dma->vaddr != NULL) {
1777 bus_dmamap_sync(dma->tag, dma->map,
1778 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1779 bus_dmamap_unload(dma->tag, dma->map);
1780 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
1781 dma->vaddr = NULL;
1782 }
1783 if (dma->tag != NULL) {
1784 bus_dma_tag_destroy(dma->tag);
1785 dma->tag = NULL;
1786 }
1787 }
1788
1789 static int
iwn_alloc_sched(struct iwn_softc * sc)1790 iwn_alloc_sched(struct iwn_softc *sc)
1791 {
1792 /* TX scheduler rings must be aligned on a 1KB boundary. */
1793 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched,
1794 sc->schedsz, 1024);
1795 }
1796
1797 static void
iwn_free_sched(struct iwn_softc * sc)1798 iwn_free_sched(struct iwn_softc *sc)
1799 {
1800 iwn_dma_contig_free(&sc->sched_dma);
1801 }
1802
1803 static int
iwn_alloc_kw(struct iwn_softc * sc)1804 iwn_alloc_kw(struct iwn_softc *sc)
1805 {
1806 /* "Keep Warm" page must be aligned on a 4KB boundary. */
1807 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096);
1808 }
1809
1810 static void
iwn_free_kw(struct iwn_softc * sc)1811 iwn_free_kw(struct iwn_softc *sc)
1812 {
1813 iwn_dma_contig_free(&sc->kw_dma);
1814 }
1815
1816 static int
iwn_alloc_ict(struct iwn_softc * sc)1817 iwn_alloc_ict(struct iwn_softc *sc)
1818 {
1819 /* ICT table must be aligned on a 4KB boundary. */
1820 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict,
1821 IWN_ICT_SIZE, 4096);
1822 }
1823
1824 static void
iwn_free_ict(struct iwn_softc * sc)1825 iwn_free_ict(struct iwn_softc *sc)
1826 {
1827 iwn_dma_contig_free(&sc->ict_dma);
1828 }
1829
1830 static int
iwn_alloc_fwmem(struct iwn_softc * sc)1831 iwn_alloc_fwmem(struct iwn_softc *sc)
1832 {
1833 /* Must be aligned on a 16-byte boundary. */
1834 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16);
1835 }
1836
1837 static void
iwn_free_fwmem(struct iwn_softc * sc)1838 iwn_free_fwmem(struct iwn_softc *sc)
1839 {
1840 iwn_dma_contig_free(&sc->fw_dma);
1841 }
1842
1843 static int
iwn_alloc_rx_ring(struct iwn_softc * sc,struct iwn_rx_ring * ring)1844 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1845 {
1846 bus_size_t size;
1847 int i, error;
1848
1849 ring->cur = 0;
1850
1851 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1852
1853 /* Allocate RX descriptors (256-byte aligned). */
1854 size = IWN_RX_RING_COUNT * sizeof (uint32_t);
1855 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
1856 size, 256);
1857 if (error != 0) {
1858 device_printf(sc->sc_dev,
1859 "%s: could not allocate RX ring DMA memory, error %d\n",
1860 __func__, error);
1861 goto fail;
1862 }
1863
1864 /* Allocate RX status area (16-byte aligned). */
1865 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat,
1866 sizeof (struct iwn_rx_status), 16);
1867 if (error != 0) {
1868 device_printf(sc->sc_dev,
1869 "%s: could not allocate RX status DMA memory, error %d\n",
1870 __func__, error);
1871 goto fail;
1872 }
1873
1874 /* Create RX buffer DMA tag. */
1875 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
1876 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1877 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, 0, NULL, NULL, &ring->data_dmat);
1878 if (error != 0) {
1879 device_printf(sc->sc_dev,
1880 "%s: could not create RX buf DMA tag, error %d\n",
1881 __func__, error);
1882 goto fail;
1883 }
1884
1885 /*
1886 * Allocate and map RX buffers.
1887 */
1888 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1889 struct iwn_rx_data *data = &ring->data[i];
1890 bus_addr_t paddr;
1891
1892 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1893 if (error != 0) {
1894 device_printf(sc->sc_dev,
1895 "%s: could not create RX buf DMA map, error %d\n",
1896 __func__, error);
1897 goto fail;
1898 }
1899
1900 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1901 IWN_RBUF_SIZE);
1902 if (data->m == NULL) {
1903 device_printf(sc->sc_dev,
1904 "%s: could not allocate RX mbuf\n", __func__);
1905 error = ENOBUFS;
1906 goto fail;
1907 }
1908
1909 error = bus_dmamap_load(ring->data_dmat, data->map,
1910 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
1911 &paddr, BUS_DMA_NOWAIT);
1912 if (error != 0 && error != EFBIG) {
1913 device_printf(sc->sc_dev,
1914 "%s: can't map mbuf, error %d\n", __func__,
1915 error);
1916 goto fail;
1917 }
1918
1919 bus_dmamap_sync(ring->data_dmat, data->map,
1920 BUS_DMASYNC_PREREAD);
1921
1922 /* Set physical address of RX buffer (256-byte aligned). */
1923 ring->desc[i] = htole32(paddr >> 8);
1924 }
1925
1926 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1927 BUS_DMASYNC_PREWRITE);
1928
1929 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
1930
1931 return 0;
1932
1933 fail: iwn_free_rx_ring(sc, ring);
1934
1935 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__);
1936
1937 return error;
1938 }
1939
1940 static void
iwn_reset_rx_ring(struct iwn_softc * sc,struct iwn_rx_ring * ring)1941 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1942 {
1943 int ntries;
1944
1945 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
1946
1947 if (iwn_nic_lock(sc) == 0) {
1948 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
1949 for (ntries = 0; ntries < 1000; ntries++) {
1950 if (IWN_READ(sc, IWN_FH_RX_STATUS) &
1951 IWN_FH_RX_STATUS_IDLE)
1952 break;
1953 DELAY(10);
1954 }
1955 iwn_nic_unlock(sc);
1956 }
1957 ring->cur = 0;
1958 sc->last_rx_valid = 0;
1959 }
1960
1961 static void
iwn_free_rx_ring(struct iwn_softc * sc,struct iwn_rx_ring * ring)1962 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1963 {
1964 int i;
1965
1966 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__);
1967
1968 iwn_dma_contig_free(&ring->desc_dma);
1969 iwn_dma_contig_free(&ring->stat_dma);
1970
1971 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1972 struct iwn_rx_data *data = &ring->data[i];
1973
1974 if (data->m != NULL) {
1975 bus_dmamap_sync(ring->data_dmat, data->map,
1976 BUS_DMASYNC_POSTREAD);
1977 bus_dmamap_unload(ring->data_dmat, data->map);
1978 m_freem(data->m);
1979 data->m = NULL;
1980 }
1981 if (data->map != NULL)
1982 bus_dmamap_destroy(ring->data_dmat, data->map);
1983 }
1984 if (ring->data_dmat != NULL) {
1985 bus_dma_tag_destroy(ring->data_dmat);
1986 ring->data_dmat = NULL;
1987 }
1988 }
1989
1990 static int
iwn_alloc_tx_ring(struct iwn_softc * sc,struct iwn_tx_ring * ring,int qid)1991 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
1992 {
1993 bus_addr_t paddr;
1994 bus_size_t size;
1995 int i, error;
1996
1997 ring->qid = qid;
1998 ring->queued = 0;
1999 ring->cur = 0;
2000
2001 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2002
2003 /* Allocate TX descriptors (256-byte aligned). */
2004 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc);
2005 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
2006 size, 256);
2007 if (error != 0) {
2008 device_printf(sc->sc_dev,
2009 "%s: could not allocate TX ring DMA memory, error %d\n",
2010 __func__, error);
2011 goto fail;
2012 }
2013
2014 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd);
2015 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd,
2016 size, 4);
2017 if (error != 0) {
2018 device_printf(sc->sc_dev,
2019 "%s: could not allocate TX cmd DMA memory, error %d\n",
2020 __func__, error);
2021 goto fail;
2022 }
2023
2024 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
2025 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
2026 IWN_MAX_SCATTER - 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
2027 if (error != 0) {
2028 device_printf(sc->sc_dev,
2029 "%s: could not create TX buf DMA tag, error %d\n",
2030 __func__, error);
2031 goto fail;
2032 }
2033
2034 paddr = ring->cmd_dma.paddr;
2035 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
2036 struct iwn_tx_data *data = &ring->data[i];
2037
2038 data->cmd_paddr = paddr;
2039 data->scratch_paddr = paddr + 12;
2040 paddr += sizeof (struct iwn_tx_cmd);
2041
2042 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
2043 if (error != 0) {
2044 device_printf(sc->sc_dev,
2045 "%s: could not create TX buf DMA map, error %d\n",
2046 __func__, error);
2047 goto fail;
2048 }
2049 }
2050
2051 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2052
2053 return 0;
2054
2055 fail: iwn_free_tx_ring(sc, ring);
2056 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__);
2057 return error;
2058 }
2059
2060 static void
iwn_reset_tx_ring(struct iwn_softc * sc,struct iwn_tx_ring * ring)2061 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
2062 {
2063 int i;
2064
2065 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__);
2066
2067 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
2068 struct iwn_tx_data *data = &ring->data[i];
2069
2070 if (data->m != NULL) {
2071 bus_dmamap_sync(ring->data_dmat, data->map,
2072 BUS_DMASYNC_POSTWRITE);
2073 bus_dmamap_unload(ring->data_dmat, data->map);
2074 m_freem(data->m);
2075 data->m = NULL;
2076 }
2077 if (data->ni != NULL) {
2078 ieee80211_free_node(data->ni);
2079 data->ni = NULL;
2080 }
2081 data->remapped = 0;
2082 data->long_retries = 0;
2083 }
2084 /* Clear TX descriptors. */
2085 memset(ring->desc, 0, ring->desc_dma.size);
2086 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
2087 BUS_DMASYNC_PREWRITE);
2088 sc->qfullmsk &= ~(1 << ring->qid);
2089 ring->queued = 0;
2090 ring->cur = 0;
2091 }
2092
2093 static void
iwn_free_tx_ring(struct iwn_softc * sc,struct iwn_tx_ring * ring)2094 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
2095 {
2096 int i;
2097
2098 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__);
2099
2100 iwn_dma_contig_free(&ring->desc_dma);
2101 iwn_dma_contig_free(&ring->cmd_dma);
2102
2103 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
2104 struct iwn_tx_data *data = &ring->data[i];
2105
2106 if (data->m != NULL) {
2107 bus_dmamap_sync(ring->data_dmat, data->map,
2108 BUS_DMASYNC_POSTWRITE);
2109 bus_dmamap_unload(ring->data_dmat, data->map);
2110 m_freem(data->m);
2111 }
2112 if (data->map != NULL)
2113 bus_dmamap_destroy(ring->data_dmat, data->map);
2114 }
2115 if (ring->data_dmat != NULL) {
2116 bus_dma_tag_destroy(ring->data_dmat);
2117 ring->data_dmat = NULL;
2118 }
2119 }
2120
2121 static void
iwn_check_tx_ring(struct iwn_softc * sc,int qid)2122 iwn_check_tx_ring(struct iwn_softc *sc, int qid)
2123 {
2124 struct iwn_tx_ring *ring = &sc->txq[qid];
2125
2126 KASSERT(ring->queued >= 0, ("%s: ring->queued (%d) for queue %d < 0!",
2127 __func__, ring->queued, qid));
2128
2129 if (qid >= sc->firstaggqueue) {
2130 struct iwn_ops *ops = &sc->ops;
2131 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid];
2132
2133 if (ring->queued == 0 && !IEEE80211_AMPDU_RUNNING(tap)) {
2134 uint16_t ssn = tap->txa_start & 0xfff;
2135 uint8_t tid = tap->txa_tid;
2136 int *res = tap->txa_private;
2137
2138 iwn_nic_lock(sc);
2139 ops->ampdu_tx_stop(sc, qid, tid, ssn);
2140 iwn_nic_unlock(sc);
2141
2142 sc->qid2tap[qid] = NULL;
2143 free(res, M_DEVBUF);
2144 }
2145 }
2146
2147 if (ring->queued < IWN_TX_RING_LOMARK) {
2148 sc->qfullmsk &= ~(1 << qid);
2149
2150 if (ring->queued == 0)
2151 sc->sc_tx_timer = 0;
2152 else
2153 sc->sc_tx_timer = 5;
2154 }
2155 }
2156
2157 static void
iwn5000_ict_reset(struct iwn_softc * sc)2158 iwn5000_ict_reset(struct iwn_softc *sc)
2159 {
2160 /* Disable interrupts. */
2161 IWN_WRITE(sc, IWN_INT_MASK, 0);
2162
2163 /* Reset ICT table. */
2164 memset(sc->ict, 0, IWN_ICT_SIZE);
2165 sc->ict_cur = 0;
2166
2167 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map,
2168 BUS_DMASYNC_PREWRITE);
2169
2170 /* Set physical address of ICT table (4KB aligned). */
2171 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__);
2172 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE |
2173 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
2174
2175 /* Enable periodic RX interrupt. */
2176 sc->int_mask |= IWN_INT_RX_PERIODIC;
2177 /* Switch to ICT interrupt mode in driver. */
2178 sc->sc_flags |= IWN_FLAG_USE_ICT;
2179
2180 /* Re-enable interrupts. */
2181 IWN_WRITE(sc, IWN_INT, 0xffffffff);
2182 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
2183 }
2184
2185 static int
iwn_read_eeprom(struct iwn_softc * sc,uint8_t macaddr[IEEE80211_ADDR_LEN])2186 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
2187 {
2188 struct iwn_ops *ops = &sc->ops;
2189 uint16_t val;
2190 int error;
2191
2192 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2193
2194 /* Check whether adapter has an EEPROM or an OTPROM. */
2195 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 &&
2196 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP))
2197 sc->sc_flags |= IWN_FLAG_HAS_OTPROM;
2198 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n",
2199 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM");
2200
2201 /* Adapter has to be powered on for EEPROM access to work. */
2202 if ((error = iwn_apm_init(sc)) != 0) {
2203 device_printf(sc->sc_dev,
2204 "%s: could not power ON adapter, error %d\n", __func__,
2205 error);
2206 return error;
2207 }
2208
2209 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) {
2210 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__);
2211 return EIO;
2212 }
2213 if ((error = iwn_eeprom_lock(sc)) != 0) {
2214 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n",
2215 __func__, error);
2216 return error;
2217 }
2218 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
2219 if ((error = iwn_init_otprom(sc)) != 0) {
2220 device_printf(sc->sc_dev,
2221 "%s: could not initialize OTPROM, error %d\n",
2222 __func__, error);
2223 return error;
2224 }
2225 }
2226
2227 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2);
2228 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val));
2229 /* Check if HT support is bonded out. */
2230 if (val & htole16(IWN_EEPROM_SKU_CAP_11N))
2231 sc->sc_flags |= IWN_FLAG_HAS_11N;
2232
2233 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2);
2234 sc->rfcfg = le16toh(val);
2235 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg);
2236 /* Read Tx/Rx chains from ROM unless it's known to be broken. */
2237 if (sc->txchainmask == 0)
2238 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg);
2239 if (sc->rxchainmask == 0)
2240 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg);
2241
2242 /* Read MAC address. */
2243 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6);
2244
2245 /* Read adapter-specific information from EEPROM. */
2246 ops->read_eeprom(sc);
2247
2248 iwn_apm_stop(sc); /* Power OFF adapter. */
2249
2250 iwn_eeprom_unlock(sc);
2251
2252 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2253
2254 return 0;
2255 }
2256
2257 static void
iwn4965_read_eeprom(struct iwn_softc * sc)2258 iwn4965_read_eeprom(struct iwn_softc *sc)
2259 {
2260 uint32_t addr;
2261 uint16_t val;
2262 int i;
2263
2264 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2265
2266 /* Read regulatory domain (4 ASCII characters). */
2267 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4);
2268
2269 /* Read the list of authorized channels (20MHz & 40MHz). */
2270 for (i = 0; i < IWN_NBANDS - 1; i++) {
2271 addr = iwn4965_regulatory_bands[i];
2272 iwn_read_eeprom_channels(sc, i, addr);
2273 }
2274
2275 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */
2276 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2);
2277 sc->maxpwr2GHz = val & 0xff;
2278 sc->maxpwr5GHz = val >> 8;
2279 /* Check that EEPROM values are within valid range. */
2280 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50)
2281 sc->maxpwr5GHz = 38;
2282 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50)
2283 sc->maxpwr2GHz = 38;
2284 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n",
2285 sc->maxpwr2GHz, sc->maxpwr5GHz);
2286
2287 /* Read samples for each TX power group. */
2288 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands,
2289 sizeof sc->bands);
2290
2291 /* Read voltage at which samples were taken. */
2292 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2);
2293 sc->eeprom_voltage = (int16_t)le16toh(val);
2294 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n",
2295 sc->eeprom_voltage);
2296
2297 #ifdef IWN_DEBUG
2298 /* Print samples. */
2299 if (sc->sc_debug & IWN_DEBUG_ANY) {
2300 for (i = 0; i < IWN_NBANDS - 1; i++)
2301 iwn4965_print_power_group(sc, i);
2302 }
2303 #endif
2304
2305 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2306 }
2307
2308 #ifdef IWN_DEBUG
2309 static void
iwn4965_print_power_group(struct iwn_softc * sc,int i)2310 iwn4965_print_power_group(struct iwn_softc *sc, int i)
2311 {
2312 struct iwn4965_eeprom_band *band = &sc->bands[i];
2313 struct iwn4965_eeprom_chan_samples *chans = band->chans;
2314 int j, c;
2315
2316 printf("===band %d===\n", i);
2317 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi);
2318 printf("chan1 num=%d\n", chans[0].num);
2319 for (c = 0; c < 2; c++) {
2320 for (j = 0; j < IWN_NSAMPLES; j++) {
2321 printf("chain %d, sample %d: temp=%d gain=%d "
2322 "power=%d pa_det=%d\n", c, j,
2323 chans[0].samples[c][j].temp,
2324 chans[0].samples[c][j].gain,
2325 chans[0].samples[c][j].power,
2326 chans[0].samples[c][j].pa_det);
2327 }
2328 }
2329 printf("chan2 num=%d\n", chans[1].num);
2330 for (c = 0; c < 2; c++) {
2331 for (j = 0; j < IWN_NSAMPLES; j++) {
2332 printf("chain %d, sample %d: temp=%d gain=%d "
2333 "power=%d pa_det=%d\n", c, j,
2334 chans[1].samples[c][j].temp,
2335 chans[1].samples[c][j].gain,
2336 chans[1].samples[c][j].power,
2337 chans[1].samples[c][j].pa_det);
2338 }
2339 }
2340 }
2341 #endif
2342
2343 static void
iwn5000_read_eeprom(struct iwn_softc * sc)2344 iwn5000_read_eeprom(struct iwn_softc *sc)
2345 {
2346 struct iwn5000_eeprom_calib_hdr hdr;
2347 int32_t volt;
2348 uint32_t base, addr;
2349 uint16_t val;
2350 int i;
2351
2352 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2353
2354 /* Read regulatory domain (4 ASCII characters). */
2355 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
2356 base = le16toh(val);
2357 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN,
2358 sc->eeprom_domain, 4);
2359
2360 /* Read the list of authorized channels (20MHz & 40MHz). */
2361 for (i = 0; i < IWN_NBANDS - 1; i++) {
2362 addr = base + sc->base_params->regulatory_bands[i];
2363 iwn_read_eeprom_channels(sc, i, addr);
2364 }
2365
2366 /* Read enhanced TX power information for 6000 Series. */
2367 if (sc->base_params->enhanced_TX_power)
2368 iwn_read_eeprom_enhinfo(sc);
2369
2370 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2);
2371 base = le16toh(val);
2372 iwn_read_prom_data(sc, base, &hdr, sizeof hdr);
2373 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2374 "%s: calib version=%u pa type=%u voltage=%u\n", __func__,
2375 hdr.version, hdr.pa_type, le16toh(hdr.volt));
2376 sc->calib_ver = hdr.version;
2377
2378 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) {
2379 sc->eeprom_voltage = le16toh(hdr.volt);
2380 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
2381 sc->eeprom_temp_high=le16toh(val);
2382 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
2383 sc->eeprom_temp = le16toh(val);
2384 }
2385
2386 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
2387 /* Compute temperature offset. */
2388 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
2389 sc->eeprom_temp = le16toh(val);
2390 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
2391 volt = le16toh(val);
2392 sc->temp_off = sc->eeprom_temp - (volt / -5);
2393 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n",
2394 sc->eeprom_temp, volt, sc->temp_off);
2395 } else {
2396 /* Read crystal calibration. */
2397 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL,
2398 &sc->eeprom_crystal, sizeof (uint32_t));
2399 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n",
2400 le32toh(sc->eeprom_crystal));
2401 }
2402
2403 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2404
2405 }
2406
2407 /*
2408 * Translate EEPROM flags to net80211.
2409 */
2410 static uint32_t
iwn_eeprom_channel_flags(struct iwn_eeprom_chan * channel)2411 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel)
2412 {
2413 uint32_t nflags;
2414
2415 nflags = 0;
2416 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0)
2417 nflags |= IEEE80211_CHAN_PASSIVE;
2418 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0)
2419 nflags |= IEEE80211_CHAN_NOADHOC;
2420 if (channel->flags & IWN_EEPROM_CHAN_RADAR) {
2421 nflags |= IEEE80211_CHAN_DFS;
2422 /* XXX apparently IBSS may still be marked */
2423 nflags |= IEEE80211_CHAN_NOADHOC;
2424 }
2425
2426 return nflags;
2427 }
2428
2429 static void
iwn_read_eeprom_band(struct iwn_softc * sc,int n,int maxchans,int * nchans,struct ieee80211_channel chans[])2430 iwn_read_eeprom_band(struct iwn_softc *sc, int n, int maxchans, int *nchans,
2431 struct ieee80211_channel chans[])
2432 {
2433 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
2434 const struct iwn_chan_band *band = &iwn_bands[n];
2435 uint8_t bands[IEEE80211_MODE_BYTES];
2436 uint8_t chan;
2437 int i, error, nflags;
2438
2439 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2440
2441 memset(bands, 0, sizeof(bands));
2442 if (n == 0) {
2443 setbit(bands, IEEE80211_MODE_11B);
2444 setbit(bands, IEEE80211_MODE_11G);
2445 if (sc->sc_flags & IWN_FLAG_HAS_11N)
2446 setbit(bands, IEEE80211_MODE_11NG);
2447 } else {
2448 setbit(bands, IEEE80211_MODE_11A);
2449 if (sc->sc_flags & IWN_FLAG_HAS_11N)
2450 setbit(bands, IEEE80211_MODE_11NA);
2451 }
2452
2453 for (i = 0; i < band->nchan; i++) {
2454 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
2455 DPRINTF(sc, IWN_DEBUG_RESET,
2456 "skip chan %d flags 0x%x maxpwr %d\n",
2457 band->chan[i], channels[i].flags,
2458 channels[i].maxpwr);
2459 continue;
2460 }
2461
2462 chan = band->chan[i];
2463 nflags = iwn_eeprom_channel_flags(&channels[i]);
2464 error = ieee80211_add_channel(chans, maxchans, nchans,
2465 chan, 0, channels[i].maxpwr, nflags, bands);
2466 if (error != 0)
2467 break;
2468
2469 /* Save maximum allowed TX power for this channel. */
2470 /* XXX wrong */
2471 sc->maxpwr[chan] = channels[i].maxpwr;
2472
2473 DPRINTF(sc, IWN_DEBUG_RESET,
2474 "add chan %d flags 0x%x maxpwr %d\n", chan,
2475 channels[i].flags, channels[i].maxpwr);
2476 }
2477
2478 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2479
2480 }
2481
2482 static void
iwn_read_eeprom_ht40(struct iwn_softc * sc,int n,int maxchans,int * nchans,struct ieee80211_channel chans[])2483 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n, int maxchans, int *nchans,
2484 struct ieee80211_channel chans[])
2485 {
2486 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
2487 const struct iwn_chan_band *band = &iwn_bands[n];
2488 uint8_t chan;
2489 int i, error, nflags;
2490
2491 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__);
2492
2493 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) {
2494 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__);
2495 return;
2496 }
2497
2498 for (i = 0; i < band->nchan; i++) {
2499 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
2500 DPRINTF(sc, IWN_DEBUG_RESET,
2501 "skip chan %d flags 0x%x maxpwr %d\n",
2502 band->chan[i], channels[i].flags,
2503 channels[i].maxpwr);
2504 continue;
2505 }
2506
2507 chan = band->chan[i];
2508 nflags = iwn_eeprom_channel_flags(&channels[i]);
2509 nflags |= (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A);
2510 error = ieee80211_add_channel_ht40(chans, maxchans, nchans,
2511 chan, channels[i].maxpwr, nflags);
2512 switch (error) {
2513 case EINVAL:
2514 device_printf(sc->sc_dev,
2515 "%s: no entry for channel %d\n", __func__, chan);
2516 continue;
2517 case ENOENT:
2518 DPRINTF(sc, IWN_DEBUG_RESET,
2519 "%s: skip chan %d, extension channel not found\n",
2520 __func__, chan);
2521 continue;
2522 case ENOBUFS:
2523 device_printf(sc->sc_dev,
2524 "%s: channel table is full!\n", __func__);
2525 break;
2526 case 0:
2527 DPRINTF(sc, IWN_DEBUG_RESET,
2528 "add ht40 chan %d flags 0x%x maxpwr %d\n",
2529 chan, channels[i].flags, channels[i].maxpwr);
2530 /* FALLTHROUGH */
2531 default:
2532 break;
2533 }
2534 }
2535
2536 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2537
2538 }
2539
2540 static void
iwn_read_eeprom_channels(struct iwn_softc * sc,int n,uint32_t addr)2541 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr)
2542 {
2543 struct ieee80211com *ic = &sc->sc_ic;
2544
2545 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n],
2546 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan));
2547
2548 if (n < 5) {
2549 iwn_read_eeprom_band(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans,
2550 ic->ic_channels);
2551 } else {
2552 iwn_read_eeprom_ht40(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans,
2553 ic->ic_channels);
2554 }
2555 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans);
2556 }
2557
2558 static struct iwn_eeprom_chan *
iwn_find_eeprom_channel(struct iwn_softc * sc,struct ieee80211_channel * c)2559 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c)
2560 {
2561 int band, chan, i, j;
2562
2563 if (IEEE80211_IS_CHAN_HT40(c)) {
2564 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5;
2565 if (IEEE80211_IS_CHAN_HT40D(c))
2566 chan = c->ic_extieee;
2567 else
2568 chan = c->ic_ieee;
2569 for (i = 0; i < iwn_bands[band].nchan; i++) {
2570 if (iwn_bands[band].chan[i] == chan)
2571 return &sc->eeprom_channels[band][i];
2572 }
2573 } else {
2574 for (j = 0; j < 5; j++) {
2575 for (i = 0; i < iwn_bands[j].nchan; i++) {
2576 if (iwn_bands[j].chan[i] == c->ic_ieee &&
2577 ((j == 0) ^ IEEE80211_IS_CHAN_A(c)) == 1)
2578 return &sc->eeprom_channels[j][i];
2579 }
2580 }
2581 }
2582 return NULL;
2583 }
2584
2585 static void
iwn_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])2586 iwn_getradiocaps(struct ieee80211com *ic,
2587 int maxchans, int *nchans, struct ieee80211_channel chans[])
2588 {
2589 struct iwn_softc *sc = ic->ic_softc;
2590 int i;
2591
2592 /* Parse the list of authorized channels. */
2593 for (i = 0; i < 5 && *nchans < maxchans; i++)
2594 iwn_read_eeprom_band(sc, i, maxchans, nchans, chans);
2595 for (i = 5; i < IWN_NBANDS - 1 && *nchans < maxchans; i++)
2596 iwn_read_eeprom_ht40(sc, i, maxchans, nchans, chans);
2597 }
2598
2599 /*
2600 * Enforce flags read from EEPROM.
2601 */
2602 static int
iwn_setregdomain(struct ieee80211com * ic,struct ieee80211_regdomain * rd,int nchan,struct ieee80211_channel chans[])2603 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd,
2604 int nchan, struct ieee80211_channel chans[])
2605 {
2606 struct iwn_softc *sc = ic->ic_softc;
2607 int i;
2608
2609 for (i = 0; i < nchan; i++) {
2610 struct ieee80211_channel *c = &chans[i];
2611 struct iwn_eeprom_chan *channel;
2612
2613 channel = iwn_find_eeprom_channel(sc, c);
2614 if (channel == NULL) {
2615 ic_printf(ic, "%s: invalid channel %u freq %u/0x%x\n",
2616 __func__, c->ic_ieee, c->ic_freq, c->ic_flags);
2617 return EINVAL;
2618 }
2619 c->ic_flags |= iwn_eeprom_channel_flags(channel);
2620 }
2621
2622 return 0;
2623 }
2624
2625 static void
iwn_read_eeprom_enhinfo(struct iwn_softc * sc)2626 iwn_read_eeprom_enhinfo(struct iwn_softc *sc)
2627 {
2628 struct iwn_eeprom_enhinfo enhinfo[35];
2629 struct ieee80211com *ic = &sc->sc_ic;
2630 struct ieee80211_channel *c;
2631 uint16_t val, base;
2632 int8_t maxpwr;
2633 uint8_t flags;
2634 int i, j;
2635
2636 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2637
2638 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
2639 base = le16toh(val);
2640 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO,
2641 enhinfo, sizeof enhinfo);
2642
2643 for (i = 0; i < nitems(enhinfo); i++) {
2644 flags = enhinfo[i].flags;
2645 if (!(flags & IWN_ENHINFO_VALID))
2646 continue; /* Skip invalid entries. */
2647
2648 maxpwr = 0;
2649 if (sc->txchainmask & IWN_ANT_A)
2650 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]);
2651 if (sc->txchainmask & IWN_ANT_B)
2652 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]);
2653 if (sc->txchainmask & IWN_ANT_C)
2654 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]);
2655 if (sc->ntxchains == 2)
2656 maxpwr = MAX(maxpwr, enhinfo[i].mimo2);
2657 else if (sc->ntxchains == 3)
2658 maxpwr = MAX(maxpwr, enhinfo[i].mimo3);
2659
2660 for (j = 0; j < ic->ic_nchans; j++) {
2661 c = &ic->ic_channels[j];
2662 if ((flags & IWN_ENHINFO_5GHZ)) {
2663 if (!IEEE80211_IS_CHAN_A(c))
2664 continue;
2665 } else if ((flags & IWN_ENHINFO_OFDM)) {
2666 if (!IEEE80211_IS_CHAN_G(c))
2667 continue;
2668 } else if (!IEEE80211_IS_CHAN_B(c))
2669 continue;
2670 if ((flags & IWN_ENHINFO_HT40)) {
2671 if (!IEEE80211_IS_CHAN_HT40(c))
2672 continue;
2673 } else {
2674 if (IEEE80211_IS_CHAN_HT40(c))
2675 continue;
2676 }
2677 if (enhinfo[i].chan != 0 &&
2678 enhinfo[i].chan != c->ic_ieee)
2679 continue;
2680
2681 DPRINTF(sc, IWN_DEBUG_RESET,
2682 "channel %d(%x), maxpwr %d\n", c->ic_ieee,
2683 c->ic_flags, maxpwr / 2);
2684 c->ic_maxregpower = maxpwr / 2;
2685 c->ic_maxpower = maxpwr;
2686 }
2687 }
2688
2689 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2690
2691 }
2692
2693 static struct ieee80211_node *
iwn_node_alloc(struct ieee80211vap * vap,const uint8_t mac[IEEE80211_ADDR_LEN])2694 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
2695 {
2696 struct iwn_node *wn;
2697
2698 wn = malloc(sizeof (struct iwn_node), M_80211_NODE, M_NOWAIT | M_ZERO);
2699 if (wn == NULL)
2700 return (NULL);
2701
2702 wn->id = IWN_ID_UNDEFINED;
2703
2704 return (&wn->ni);
2705 }
2706
2707 static __inline int
rate2plcp(int rate)2708 rate2plcp(int rate)
2709 {
2710 switch (rate & 0xff) {
2711 case 12: return 0xd;
2712 case 18: return 0xf;
2713 case 24: return 0x5;
2714 case 36: return 0x7;
2715 case 48: return 0x9;
2716 case 72: return 0xb;
2717 case 96: return 0x1;
2718 case 108: return 0x3;
2719 case 2: return 10;
2720 case 4: return 20;
2721 case 11: return 55;
2722 case 22: return 110;
2723 }
2724 return 0;
2725 }
2726
2727 static __inline uint8_t
plcp2rate(const uint8_t rate_plcp)2728 plcp2rate(const uint8_t rate_plcp)
2729 {
2730 switch (rate_plcp) {
2731 case 0xd: return 12;
2732 case 0xf: return 18;
2733 case 0x5: return 24;
2734 case 0x7: return 36;
2735 case 0x9: return 48;
2736 case 0xb: return 72;
2737 case 0x1: return 96;
2738 case 0x3: return 108;
2739 case 10: return 2;
2740 case 20: return 4;
2741 case 55: return 11;
2742 case 110: return 22;
2743 default: return 0;
2744 }
2745 }
2746
2747 static int
iwn_get_1stream_tx_antmask(struct iwn_softc * sc)2748 iwn_get_1stream_tx_antmask(struct iwn_softc *sc)
2749 {
2750
2751 return IWN_LSB(sc->txchainmask);
2752 }
2753
2754 static int
iwn_get_2stream_tx_antmask(struct iwn_softc * sc)2755 iwn_get_2stream_tx_antmask(struct iwn_softc *sc)
2756 {
2757 int tx;
2758
2759 /*
2760 * The '2 stream' setup is a bit .. odd.
2761 *
2762 * For NICs that support only 1 antenna, default to IWN_ANT_AB or
2763 * the firmware panics (eg Intel 5100.)
2764 *
2765 * For NICs that support two antennas, we use ANT_AB.
2766 *
2767 * For NICs that support three antennas, we use the two that
2768 * wasn't the default one.
2769 *
2770 * XXX TODO: if bluetooth (full concurrent) is enabled, restrict
2771 * this to only one antenna.
2772 */
2773
2774 /* Default - transmit on the other antennas */
2775 tx = (sc->txchainmask & ~IWN_LSB(sc->txchainmask));
2776
2777 /* Now, if it's zero, set it to IWN_ANT_AB, so to not panic firmware */
2778 if (tx == 0)
2779 tx = IWN_ANT_AB;
2780
2781 /*
2782 * If the NIC is a two-stream TX NIC, configure the TX mask to
2783 * the default chainmask
2784 */
2785 else if (sc->ntxchains == 2)
2786 tx = sc->txchainmask;
2787
2788 return (tx);
2789 }
2790
2791
2792
2793 /*
2794 * Calculate the required PLCP value from the given rate,
2795 * to the given node.
2796 *
2797 * This will take the node configuration (eg 11n, rate table
2798 * setup, etc) into consideration.
2799 */
2800 static uint32_t
iwn_rate_to_plcp(struct iwn_softc * sc,struct ieee80211_node * ni,uint8_t rate)2801 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni,
2802 uint8_t rate)
2803 {
2804 struct ieee80211com *ic = ni->ni_ic;
2805 uint32_t plcp = 0;
2806 int ridx;
2807
2808 /*
2809 * If it's an MCS rate, let's set the plcp correctly
2810 * and set the relevant flags based on the node config.
2811 */
2812 if (rate & IEEE80211_RATE_MCS) {
2813 /*
2814 * Set the initial PLCP value to be between 0->31 for
2815 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!"
2816 * flag.
2817 */
2818 plcp = IEEE80211_RV(rate) | IWN_RFLAG_MCS;
2819
2820 /*
2821 * Set the channel width and guard interval.
2822 *
2823 * Take into account the local configuration and
2824 * the node/peer advertised abilities.
2825 */
2826 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) {
2827 plcp |= IWN_RFLAG_HT40;
2828 if (ieee80211_ht_check_tx_shortgi_40(ni))
2829 plcp |= IWN_RFLAG_SGI;
2830 } else if (ieee80211_ht_check_tx_shortgi_20(ni))
2831 plcp |= IWN_RFLAG_SGI;
2832
2833 /*
2834 * Ensure the selected rate matches the link quality
2835 * table entries being used.
2836 */
2837 if (rate > 0x8f)
2838 plcp |= IWN_RFLAG_ANT(sc->txchainmask);
2839 else if (rate > 0x87)
2840 plcp |= IWN_RFLAG_ANT(iwn_get_2stream_tx_antmask(sc));
2841 else
2842 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc));
2843 } else {
2844 /*
2845 * Set the initial PLCP - fine for both
2846 * OFDM and CCK rates.
2847 */
2848 plcp = rate2plcp(rate);
2849
2850 /* Set CCK flag if it's CCK */
2851
2852 /* XXX It would be nice to have a method
2853 * to map the ridx -> phy table entry
2854 * so we could just query that, rather than
2855 * this hack to check against IWN_RIDX_OFDM6.
2856 */
2857 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt,
2858 rate & IEEE80211_RATE_VAL);
2859 if (ridx < IWN_RIDX_OFDM6 &&
2860 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
2861 plcp |= IWN_RFLAG_CCK;
2862
2863 /* Set antenna configuration */
2864 /* XXX TODO: is this the right antenna to use for legacy? */
2865 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc));
2866 }
2867
2868 DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n",
2869 __func__,
2870 rate,
2871 plcp);
2872
2873 return (htole32(plcp));
2874 }
2875
2876 static void
iwn_newassoc(struct ieee80211_node * ni,int isnew)2877 iwn_newassoc(struct ieee80211_node *ni, int isnew)
2878 {
2879 /* Doesn't do anything at the moment */
2880 }
2881
2882 static int
iwn_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)2883 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
2884 {
2885 struct iwn_vap *ivp = IWN_VAP(vap);
2886 struct ieee80211com *ic = vap->iv_ic;
2887 struct iwn_softc *sc = ic->ic_softc;
2888 int error = 0;
2889
2890 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2891
2892 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
2893 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]);
2894
2895 IEEE80211_UNLOCK(ic);
2896 IWN_LOCK(sc);
2897 callout_stop(&sc->calib_to);
2898
2899 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
2900
2901 switch (nstate) {
2902 case IEEE80211_S_ASSOC:
2903 if (vap->iv_state != IEEE80211_S_RUN)
2904 break;
2905 /* FALLTHROUGH */
2906 case IEEE80211_S_AUTH:
2907 if (vap->iv_state == IEEE80211_S_AUTH)
2908 break;
2909
2910 /*
2911 * !AUTH -> AUTH transition requires state reset to handle
2912 * reassociations correctly.
2913 */
2914 sc->rxon->associd = 0;
2915 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS);
2916 sc->calib.state = IWN_CALIB_STATE_INIT;
2917
2918 /* Wait until we hear a beacon before we transmit */
2919 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan))
2920 sc->sc_beacon_wait = 1;
2921
2922 if ((error = iwn_auth(sc, vap)) != 0) {
2923 device_printf(sc->sc_dev,
2924 "%s: could not move to auth state\n", __func__);
2925 }
2926 break;
2927
2928 case IEEE80211_S_RUN:
2929 /*
2930 * RUN -> RUN transition; Just restart the timers.
2931 */
2932 if (vap->iv_state == IEEE80211_S_RUN) {
2933 sc->calib_cnt = 0;
2934 break;
2935 }
2936
2937 /* Wait until we hear a beacon before we transmit */
2938 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan))
2939 sc->sc_beacon_wait = 1;
2940
2941 /*
2942 * !RUN -> RUN requires setting the association id
2943 * which is done with a firmware cmd. We also defer
2944 * starting the timers until that work is done.
2945 */
2946 if ((error = iwn_run(sc, vap)) != 0) {
2947 device_printf(sc->sc_dev,
2948 "%s: could not move to run state\n", __func__);
2949 }
2950 break;
2951
2952 case IEEE80211_S_INIT:
2953 sc->calib.state = IWN_CALIB_STATE_INIT;
2954 /*
2955 * Purge the xmit queue so we don't have old frames
2956 * during a new association attempt.
2957 */
2958 sc->sc_beacon_wait = 0;
2959 iwn_xmit_queue_drain(sc);
2960 break;
2961
2962 default:
2963 break;
2964 }
2965 IWN_UNLOCK(sc);
2966 IEEE80211_LOCK(ic);
2967 if (error != 0){
2968 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__);
2969 return error;
2970 }
2971
2972 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
2973
2974 return ivp->iv_newstate(vap, nstate, arg);
2975 }
2976
2977 static void
iwn_calib_timeout(void * arg)2978 iwn_calib_timeout(void *arg)
2979 {
2980 struct iwn_softc *sc = arg;
2981
2982 IWN_LOCK_ASSERT(sc);
2983
2984 /* Force automatic TX power calibration every 60 secs. */
2985 if (++sc->calib_cnt >= 120) {
2986 uint32_t flags = 0;
2987
2988 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n",
2989 "sending request for statistics");
2990 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags,
2991 sizeof flags, 1);
2992 sc->calib_cnt = 0;
2993 }
2994 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
2995 sc);
2996 }
2997
2998 /*
2999 * Process an RX_PHY firmware notification. This is usually immediately
3000 * followed by an MPDU_RX_DONE notification.
3001 */
3002 static void
iwn_rx_phy(struct iwn_softc * sc,struct iwn_rx_desc * desc)3003 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc)
3004 {
3005 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1);
3006
3007 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__);
3008
3009 /* Save RX statistics, they will be used on MPDU_RX_DONE. */
3010 memcpy(&sc->last_rx_stat, stat, sizeof (*stat));
3011 sc->last_rx_valid = 1;
3012 }
3013
3014 /*
3015 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification.
3016 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one.
3017 */
3018 static void
iwn_rx_done(struct iwn_softc * sc,struct iwn_rx_desc * desc,struct iwn_rx_data * data)3019 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
3020 struct iwn_rx_data *data)
3021 {
3022 struct iwn_ops *ops = &sc->ops;
3023 struct ieee80211com *ic = &sc->sc_ic;
3024 struct iwn_rx_ring *ring = &sc->rxq;
3025 struct ieee80211_frame_min *wh;
3026 struct ieee80211_node *ni;
3027 struct mbuf *m, *m1;
3028 struct iwn_rx_stat *stat;
3029 caddr_t head;
3030 bus_addr_t paddr;
3031 uint32_t flags;
3032 int error, len, rssi, nf;
3033
3034 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3035
3036 if (desc->type == IWN_MPDU_RX_DONE) {
3037 /* Check for prior RX_PHY notification. */
3038 if (!sc->last_rx_valid) {
3039 DPRINTF(sc, IWN_DEBUG_ANY,
3040 "%s: missing RX_PHY\n", __func__);
3041 return;
3042 }
3043 stat = &sc->last_rx_stat;
3044 } else
3045 stat = (struct iwn_rx_stat *)(desc + 1);
3046
3047 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) {
3048 device_printf(sc->sc_dev,
3049 "%s: invalid RX statistic header, len %d\n", __func__,
3050 stat->cfg_phy_len);
3051 return;
3052 }
3053 if (desc->type == IWN_MPDU_RX_DONE) {
3054 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1);
3055 head = (caddr_t)(mpdu + 1);
3056 len = le16toh(mpdu->len);
3057 } else {
3058 head = (caddr_t)(stat + 1) + stat->cfg_phy_len;
3059 len = le16toh(stat->len);
3060 }
3061
3062 flags = le32toh(*(uint32_t *)(head + len));
3063
3064 /* Discard frames with a bad FCS early. */
3065 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) {
3066 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n",
3067 __func__, flags);
3068 counter_u64_add(ic->ic_ierrors, 1);
3069 return;
3070 }
3071 /* Discard frames that are too short. */
3072 if (len < sizeof (struct ieee80211_frame_ack)) {
3073 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n",
3074 __func__, len);
3075 counter_u64_add(ic->ic_ierrors, 1);
3076 return;
3077 }
3078
3079 m1 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE);
3080 if (m1 == NULL) {
3081 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n",
3082 __func__);
3083 counter_u64_add(ic->ic_ierrors, 1);
3084 return;
3085 }
3086 bus_dmamap_unload(ring->data_dmat, data->map);
3087
3088 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *),
3089 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
3090 if (error != 0 && error != EFBIG) {
3091 device_printf(sc->sc_dev,
3092 "%s: bus_dmamap_load failed, error %d\n", __func__, error);
3093 m_freem(m1);
3094
3095 /* Try to reload the old mbuf. */
3096 error = bus_dmamap_load(ring->data_dmat, data->map,
3097 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
3098 &paddr, BUS_DMA_NOWAIT);
3099 if (error != 0 && error != EFBIG) {
3100 panic("%s: could not load old RX mbuf", __func__);
3101 }
3102 bus_dmamap_sync(ring->data_dmat, data->map,
3103 BUS_DMASYNC_PREREAD);
3104 /* Physical address may have changed. */
3105 ring->desc[ring->cur] = htole32(paddr >> 8);
3106 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3107 BUS_DMASYNC_PREWRITE);
3108 counter_u64_add(ic->ic_ierrors, 1);
3109 return;
3110 }
3111
3112 bus_dmamap_sync(ring->data_dmat, data->map,
3113 BUS_DMASYNC_PREREAD);
3114
3115 m = data->m;
3116 data->m = m1;
3117 /* Update RX descriptor. */
3118 ring->desc[ring->cur] = htole32(paddr >> 8);
3119 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3120 BUS_DMASYNC_PREWRITE);
3121
3122 /* Finalize mbuf. */
3123 m->m_data = head;
3124 m->m_pkthdr.len = m->m_len = len;
3125
3126 /* Grab a reference to the source node. */
3127 wh = mtod(m, struct ieee80211_frame_min *);
3128 if (len >= sizeof(struct ieee80211_frame_min))
3129 ni = ieee80211_find_rxnode(ic, wh);
3130 else
3131 ni = NULL;
3132 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN &&
3133 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95;
3134
3135 rssi = ops->get_rssi(sc, stat);
3136
3137 if (ieee80211_radiotap_active(ic)) {
3138 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap;
3139 uint32_t rate = le32toh(stat->rate);
3140
3141 tap->wr_flags = 0;
3142 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE))
3143 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3144 tap->wr_dbm_antsignal = (int8_t)rssi;
3145 tap->wr_dbm_antnoise = (int8_t)nf;
3146 tap->wr_tsft = stat->tstamp;
3147 if (rate & IWN_RFLAG_MCS) {
3148 tap->wr_rate = rate & IWN_RFLAG_RATE_MCS;
3149 tap->wr_rate |= IEEE80211_RATE_MCS;
3150 } else
3151 tap->wr_rate = plcp2rate(rate & IWN_RFLAG_RATE);
3152 }
3153
3154 /*
3155 * If it's a beacon and we're waiting, then do the
3156 * wakeup. This should unblock raw_xmit/start.
3157 */
3158 if (sc->sc_beacon_wait) {
3159 uint8_t type, subtype;
3160 /* NB: Re-assign wh */
3161 wh = mtod(m, struct ieee80211_frame_min *);
3162 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3163 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3164 /*
3165 * This assumes at this point we've received our own
3166 * beacon.
3167 */
3168 DPRINTF(sc, IWN_DEBUG_TRACE,
3169 "%s: beacon_wait, type=%d, subtype=%d\n",
3170 __func__, type, subtype);
3171 if (type == IEEE80211_FC0_TYPE_MGT &&
3172 subtype == IEEE80211_FC0_SUBTYPE_BEACON) {
3173 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT,
3174 "%s: waking things up\n", __func__);
3175 /* queue taskqueue to transmit! */
3176 taskqueue_enqueue(sc->sc_tq, &sc->sc_xmit_task);
3177 }
3178 }
3179
3180 IWN_UNLOCK(sc);
3181
3182 /* Send the frame to the 802.11 layer. */
3183 if (ni != NULL) {
3184 if (ni->ni_flags & IEEE80211_NODE_HT)
3185 m->m_flags |= M_AMPDU;
3186 (void)ieee80211_input(ni, m, rssi - nf, nf);
3187 /* Node is no longer needed. */
3188 ieee80211_free_node(ni);
3189 } else
3190 (void)ieee80211_input_all(ic, m, rssi - nf, nf);
3191
3192 IWN_LOCK(sc);
3193
3194 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3195
3196 }
3197
3198 static void
iwn_agg_tx_complete(struct iwn_softc * sc,struct iwn_tx_ring * ring,int tid,int idx,int success)3199 iwn_agg_tx_complete(struct iwn_softc *sc, struct iwn_tx_ring *ring, int tid,
3200 int idx, int success)
3201 {
3202 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs;
3203 struct iwn_tx_data *data = &ring->data[idx];
3204 struct iwn_node *wn;
3205 struct mbuf *m;
3206 struct ieee80211_node *ni;
3207
3208 KASSERT(data->ni != NULL, ("idx %d: no node", idx));
3209 KASSERT(data->m != NULL, ("idx %d: no mbuf", idx));
3210
3211 /* Unmap and free mbuf. */
3212 bus_dmamap_sync(ring->data_dmat, data->map,
3213 BUS_DMASYNC_POSTWRITE);
3214 bus_dmamap_unload(ring->data_dmat, data->map);
3215 m = data->m, data->m = NULL;
3216 ni = data->ni, data->ni = NULL;
3217 wn = (void *)ni;
3218
3219 #if 0
3220 /* XXX causes significant performance degradation. */
3221 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY |
3222 IEEE80211_RATECTL_STATUS_LONG_RETRY;
3223 txs->long_retries = data->long_retries - 1;
3224 #else
3225 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY;
3226 #endif
3227 txs->short_retries = wn->agg[tid].short_retries;
3228 if (success)
3229 txs->status = IEEE80211_RATECTL_TX_SUCCESS;
3230 else
3231 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
3232
3233 wn->agg[tid].short_retries = 0;
3234 data->long_retries = 0;
3235
3236 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: freeing m %p ni %p idx %d qid %d\n",
3237 __func__, m, ni, idx, ring->qid);
3238 ieee80211_ratectl_tx_complete(ni, txs);
3239 ieee80211_tx_complete(ni, m, !success);
3240 }
3241
3242 /* Process an incoming Compressed BlockAck. */
3243 static void
iwn_rx_compressed_ba(struct iwn_softc * sc,struct iwn_rx_desc * desc)3244 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc)
3245 {
3246 struct iwn_tx_ring *ring;
3247 struct iwn_tx_data *data;
3248 struct iwn_node *wn;
3249 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1);
3250 struct ieee80211_tx_ampdu *tap;
3251 uint64_t bitmap;
3252 uint8_t tid;
3253 int i, qid, shift;
3254 int tx_ok = 0;
3255
3256 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3257
3258 qid = le16toh(ba->qid);
3259 tap = sc->qid2tap[qid];
3260 ring = &sc->txq[qid];
3261 tid = tap->txa_tid;
3262 wn = (void *)tap->txa_ni;
3263
3264 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: qid %d tid %d seq %04X ssn %04X\n"
3265 "bitmap: ba %016jX wn %016jX, start %d\n",
3266 __func__, qid, tid, le16toh(ba->seq), le16toh(ba->ssn),
3267 (uintmax_t)le64toh(ba->bitmap), (uintmax_t)wn->agg[tid].bitmap,
3268 wn->agg[tid].startidx);
3269
3270 if (wn->agg[tid].bitmap == 0)
3271 return;
3272
3273 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff);
3274 if (shift <= -64)
3275 shift += 0x100;
3276
3277 /*
3278 * Walk the bitmap and calculate how many successful attempts
3279 * are made.
3280 *
3281 * Yes, the rate control code doesn't know these are A-MPDU
3282 * subframes; due to that long_retries stats are not used here.
3283 */
3284 bitmap = le64toh(ba->bitmap);
3285 if (shift >= 0)
3286 bitmap >>= shift;
3287 else
3288 bitmap <<= -shift;
3289 bitmap &= wn->agg[tid].bitmap;
3290 wn->agg[tid].bitmap = 0;
3291
3292 for (i = wn->agg[tid].startidx;
3293 bitmap;
3294 bitmap >>= 1, i = (i + 1) % IWN_TX_RING_COUNT) {
3295 if ((bitmap & 1) == 0)
3296 continue;
3297
3298 data = &ring->data[i];
3299 if (__predict_false(data->m == NULL)) {
3300 /*
3301 * There is no frame; skip this entry.
3302 *
3303 * NB: it is "ok" to have both
3304 * 'tx done' + 'compressed BA' replies for frame
3305 * with STATE_SCD_QUERY status.
3306 */
3307 DPRINTF(sc, IWN_DEBUG_AMPDU,
3308 "%s: ring %d: no entry %d\n", __func__, qid, i);
3309 continue;
3310 }
3311
3312 tx_ok++;
3313 iwn_agg_tx_complete(sc, ring, tid, i, 1);
3314 }
3315
3316 ring->queued -= tx_ok;
3317 iwn_check_tx_ring(sc, qid);
3318
3319 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_AMPDU,
3320 "->%s: end; %d ok\n",__func__, tx_ok);
3321 }
3322
3323 /*
3324 * Process a CALIBRATION_RESULT notification sent by the initialization
3325 * firmware on response to a CMD_CALIB_CONFIG command (5000 only).
3326 */
3327 static void
iwn5000_rx_calib_results(struct iwn_softc * sc,struct iwn_rx_desc * desc)3328 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc)
3329 {
3330 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1);
3331 int len, idx = -1;
3332
3333 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3334
3335 /* Runtime firmware should not send such a notification. */
3336 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){
3337 DPRINTF(sc, IWN_DEBUG_TRACE,
3338 "->%s received after calib done\n", __func__);
3339 return;
3340 }
3341 len = (le32toh(desc->len) & 0x3fff) - 4;
3342
3343 switch (calib->code) {
3344 case IWN5000_PHY_CALIB_DC:
3345 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC)
3346 idx = 0;
3347 break;
3348 case IWN5000_PHY_CALIB_LO:
3349 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO)
3350 idx = 1;
3351 break;
3352 case IWN5000_PHY_CALIB_TX_IQ:
3353 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ)
3354 idx = 2;
3355 break;
3356 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC:
3357 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC)
3358 idx = 3;
3359 break;
3360 case IWN5000_PHY_CALIB_BASE_BAND:
3361 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND)
3362 idx = 4;
3363 break;
3364 }
3365 if (idx == -1) /* Ignore other results. */
3366 return;
3367
3368 /* Save calibration result. */
3369 if (sc->calibcmd[idx].buf != NULL)
3370 free(sc->calibcmd[idx].buf, M_DEVBUF);
3371 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT);
3372 if (sc->calibcmd[idx].buf == NULL) {
3373 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
3374 "not enough memory for calibration result %d\n",
3375 calib->code);
3376 return;
3377 }
3378 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
3379 "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len);
3380 sc->calibcmd[idx].len = len;
3381 memcpy(sc->calibcmd[idx].buf, calib, len);
3382 }
3383
3384 static void
iwn_stats_update(struct iwn_softc * sc,struct iwn_calib_state * calib,struct iwn_stats * stats,int len)3385 iwn_stats_update(struct iwn_softc *sc, struct iwn_calib_state *calib,
3386 struct iwn_stats *stats, int len)
3387 {
3388 struct iwn_stats_bt *stats_bt;
3389 struct iwn_stats *lstats;
3390
3391 /*
3392 * First - check whether the length is the bluetooth or normal.
3393 *
3394 * If it's normal - just copy it and bump out.
3395 * Otherwise we have to convert things.
3396 */
3397
3398 if (len == sizeof(struct iwn_stats) + 4) {
3399 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats));
3400 sc->last_stat_valid = 1;
3401 return;
3402 }
3403
3404 /*
3405 * If it's not the bluetooth size - log, then just copy.
3406 */
3407 if (len != sizeof(struct iwn_stats_bt) + 4) {
3408 DPRINTF(sc, IWN_DEBUG_STATS,
3409 "%s: size of rx statistics (%d) not an expected size!\n",
3410 __func__,
3411 len);
3412 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats));
3413 sc->last_stat_valid = 1;
3414 return;
3415 }
3416
3417 /*
3418 * Ok. Time to copy.
3419 */
3420 stats_bt = (struct iwn_stats_bt *) stats;
3421 lstats = &sc->last_stat;
3422
3423 /* flags */
3424 lstats->flags = stats_bt->flags;
3425 /* rx_bt */
3426 memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm,
3427 sizeof(struct iwn_rx_phy_stats));
3428 memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck,
3429 sizeof(struct iwn_rx_phy_stats));
3430 memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common,
3431 sizeof(struct iwn_rx_general_stats));
3432 memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht,
3433 sizeof(struct iwn_rx_ht_phy_stats));
3434 /* tx */
3435 memcpy(&lstats->tx, &stats_bt->tx,
3436 sizeof(struct iwn_tx_stats));
3437 /* general */
3438 memcpy(&lstats->general, &stats_bt->general,
3439 sizeof(struct iwn_general_stats));
3440
3441 /* XXX TODO: Squirrel away the extra bluetooth stats somewhere */
3442 sc->last_stat_valid = 1;
3443 }
3444
3445 /*
3446 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification.
3447 * The latter is sent by the firmware after each received beacon.
3448 */
3449 static void
iwn_rx_statistics(struct iwn_softc * sc,struct iwn_rx_desc * desc)3450 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc)
3451 {
3452 struct iwn_ops *ops = &sc->ops;
3453 struct ieee80211com *ic = &sc->sc_ic;
3454 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3455 struct iwn_calib_state *calib = &sc->calib;
3456 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1);
3457 struct iwn_stats *lstats;
3458 int temp;
3459
3460 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3461
3462 /* Ignore statistics received during a scan. */
3463 if (vap->iv_state != IEEE80211_S_RUN ||
3464 (ic->ic_flags & IEEE80211_F_SCAN)){
3465 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n",
3466 __func__);
3467 return;
3468 }
3469
3470 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_STATS,
3471 "%s: received statistics, cmd %d, len %d\n",
3472 __func__, desc->type, le16toh(desc->len));
3473 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */
3474
3475 /*
3476 * Collect/track general statistics for reporting.
3477 *
3478 * This takes care of ensuring that the bluetooth sized message
3479 * will be correctly converted to the legacy sized message.
3480 */
3481 iwn_stats_update(sc, calib, stats, le16toh(desc->len));
3482
3483 /*
3484 * And now, let's take a reference of it to use!
3485 */
3486 lstats = &sc->last_stat;
3487
3488 /* Test if temperature has changed. */
3489 if (lstats->general.temp != sc->rawtemp) {
3490 /* Convert "raw" temperature to degC. */
3491 sc->rawtemp = stats->general.temp;
3492 temp = ops->get_temperature(sc);
3493 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n",
3494 __func__, temp);
3495
3496 /* Update TX power if need be (4965AGN only). */
3497 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
3498 iwn4965_power_calibration(sc, temp);
3499 }
3500
3501 if (desc->type != IWN_BEACON_STATISTICS)
3502 return; /* Reply to a statistics request. */
3503
3504 sc->noise = iwn_get_noise(&lstats->rx.general);
3505 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise);
3506
3507 /* Test that RSSI and noise are present in stats report. */
3508 if (le32toh(lstats->rx.general.flags) != 1) {
3509 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n",
3510 "received statistics without RSSI");
3511 return;
3512 }
3513
3514 if (calib->state == IWN_CALIB_STATE_ASSOC)
3515 iwn_collect_noise(sc, &lstats->rx.general);
3516 else if (calib->state == IWN_CALIB_STATE_RUN) {
3517 iwn_tune_sensitivity(sc, &lstats->rx);
3518 /*
3519 * XXX TODO: Only run the RX recovery if we're associated!
3520 */
3521 iwn_check_rx_recovery(sc, lstats);
3522 iwn_save_stats_counters(sc, lstats);
3523 }
3524
3525 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3526 }
3527
3528 /*
3529 * Save the relevant statistic counters for the next calibration
3530 * pass.
3531 */
3532 static void
iwn_save_stats_counters(struct iwn_softc * sc,const struct iwn_stats * rs)3533 iwn_save_stats_counters(struct iwn_softc *sc, const struct iwn_stats *rs)
3534 {
3535 struct iwn_calib_state *calib = &sc->calib;
3536
3537 /* Save counters values for next call. */
3538 calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp);
3539 calib->fa_cck = le32toh(rs->rx.cck.fa);
3540 calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp);
3541 calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp);
3542 calib->fa_ofdm = le32toh(rs->rx.ofdm.fa);
3543
3544 /* Last time we received these tick values */
3545 sc->last_calib_ticks = ticks;
3546 }
3547
3548 /*
3549 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN
3550 * and 5000 adapters have different incompatible TX status formats.
3551 */
3552 static void
iwn4965_tx_done(struct iwn_softc * sc,struct iwn_rx_desc * desc,struct iwn_rx_data * data)3553 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
3554 struct iwn_rx_data *data)
3555 {
3556 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1);
3557 int qid = desc->qid & IWN_RX_DESC_QID_MSK;
3558
3559 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
3560 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n",
3561 __func__, desc->qid, desc->idx,
3562 stat->rtsfailcnt,
3563 stat->ackfailcnt,
3564 stat->btkillcnt,
3565 stat->rate, le16toh(stat->duration),
3566 le32toh(stat->status));
3567
3568 if (qid >= sc->firstaggqueue && stat->nframes != 1) {
3569 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt,
3570 &stat->status);
3571 } else {
3572 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt,
3573 le32toh(stat->status) & 0xff);
3574 }
3575 }
3576
3577 static void
iwn5000_tx_done(struct iwn_softc * sc,struct iwn_rx_desc * desc,struct iwn_rx_data * data)3578 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
3579 struct iwn_rx_data *data)
3580 {
3581 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1);
3582 int qid = desc->qid & IWN_RX_DESC_QID_MSK;
3583
3584 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
3585 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n",
3586 __func__, desc->qid, desc->idx,
3587 stat->rtsfailcnt,
3588 stat->ackfailcnt,
3589 stat->btkillcnt,
3590 stat->rate, le16toh(stat->duration),
3591 le32toh(stat->status));
3592
3593 #ifdef notyet
3594 /* Reset TX scheduler slot. */
3595 iwn5000_reset_sched(sc, qid, desc->idx);
3596 #endif
3597
3598 if (qid >= sc->firstaggqueue && stat->nframes != 1) {
3599 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt,
3600 &stat->status);
3601 } else {
3602 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt,
3603 le16toh(stat->status) & 0xff);
3604 }
3605 }
3606
3607 static void
iwn_adj_ampdu_ptr(struct iwn_softc * sc,struct iwn_tx_ring * ring)3608 iwn_adj_ampdu_ptr(struct iwn_softc *sc, struct iwn_tx_ring *ring)
3609 {
3610 int i;
3611
3612 for (i = ring->read; i != ring->cur; i = (i + 1) % IWN_TX_RING_COUNT) {
3613 struct iwn_tx_data *data = &ring->data[i];
3614
3615 if (data->m != NULL)
3616 break;
3617
3618 data->remapped = 0;
3619 }
3620
3621 ring->read = i;
3622 }
3623
3624 /*
3625 * Adapter-independent backend for TX_DONE firmware notifications.
3626 */
3627 static void
iwn_tx_done(struct iwn_softc * sc,struct iwn_rx_desc * desc,int rtsfailcnt,int ackfailcnt,uint8_t status)3628 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int rtsfailcnt,
3629 int ackfailcnt, uint8_t status)
3630 {
3631 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs;
3632 struct iwn_tx_ring *ring = &sc->txq[desc->qid & IWN_RX_DESC_QID_MSK];
3633 struct iwn_tx_data *data = &ring->data[desc->idx];
3634 struct mbuf *m;
3635 struct ieee80211_node *ni;
3636
3637 if (__predict_false(data->m == NULL &&
3638 ring->qid >= sc->firstaggqueue)) {
3639 /*
3640 * There is no frame; skip this entry.
3641 */
3642 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: ring %d: no entry %d\n",
3643 __func__, ring->qid, desc->idx);
3644 return;
3645 }
3646
3647 KASSERT(data->ni != NULL, ("no node"));
3648 KASSERT(data->m != NULL, ("no mbuf"));
3649
3650 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3651
3652 /* Unmap and free mbuf. */
3653 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE);
3654 bus_dmamap_unload(ring->data_dmat, data->map);
3655 m = data->m, data->m = NULL;
3656 ni = data->ni, data->ni = NULL;
3657
3658 data->long_retries = 0;
3659
3660 if (ring->qid >= sc->firstaggqueue)
3661 iwn_adj_ampdu_ptr(sc, ring);
3662
3663 /*
3664 * XXX f/w may hang (device timeout) when desc->idx - ring->read == 64
3665 * (aggregation queues only).
3666 */
3667
3668 ring->queued--;
3669 iwn_check_tx_ring(sc, ring->qid);
3670
3671 /*
3672 * Update rate control statistics for the node.
3673 */
3674 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY |
3675 IEEE80211_RATECTL_STATUS_LONG_RETRY;
3676 txs->short_retries = rtsfailcnt;
3677 txs->long_retries = ackfailcnt;
3678 if (!(status & IWN_TX_FAIL))
3679 txs->status = IEEE80211_RATECTL_TX_SUCCESS;
3680 else {
3681 switch (status) {
3682 case IWN_TX_FAIL_SHORT_LIMIT:
3683 txs->status = IEEE80211_RATECTL_TX_FAIL_SHORT;
3684 break;
3685 case IWN_TX_FAIL_LONG_LIMIT:
3686 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG;
3687 break;
3688 case IWN_TX_STATUS_FAIL_LIFE_EXPIRE:
3689 txs->status = IEEE80211_RATECTL_TX_FAIL_EXPIRED;
3690 break;
3691 default:
3692 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
3693 break;
3694 }
3695 }
3696 ieee80211_ratectl_tx_complete(ni, txs);
3697
3698 /*
3699 * Channels marked for "radar" require traffic to be received
3700 * to unlock before we can transmit. Until traffic is seen
3701 * any attempt to transmit is returned immediately with status
3702 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily
3703 * happen on first authenticate after scanning. To workaround
3704 * this we ignore a failure of this sort in AUTH state so the
3705 * 802.11 layer will fall back to using a timeout to wait for
3706 * the AUTH reply. This allows the firmware time to see
3707 * traffic so a subsequent retry of AUTH succeeds. It's
3708 * unclear why the firmware does not maintain state for
3709 * channels recently visited as this would allow immediate
3710 * use of the channel after a scan (where we see traffic).
3711 */
3712 if (status == IWN_TX_FAIL_TX_LOCKED &&
3713 ni->ni_vap->iv_state == IEEE80211_S_AUTH)
3714 ieee80211_tx_complete(ni, m, 0);
3715 else
3716 ieee80211_tx_complete(ni, m,
3717 (status & IWN_TX_FAIL) != 0);
3718
3719 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3720 }
3721
3722 /*
3723 * Process a "command done" firmware notification. This is where we wakeup
3724 * processes waiting for a synchronous command completion.
3725 */
3726 static void
iwn_cmd_done(struct iwn_softc * sc,struct iwn_rx_desc * desc)3727 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc)
3728 {
3729 struct iwn_tx_ring *ring;
3730 struct iwn_tx_data *data;
3731 int cmd_queue_num;
3732
3733 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT)
3734 cmd_queue_num = IWN_PAN_CMD_QUEUE;
3735 else
3736 cmd_queue_num = IWN_CMD_QUEUE_NUM;
3737
3738 if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num)
3739 return; /* Not a command ack. */
3740
3741 ring = &sc->txq[cmd_queue_num];
3742 data = &ring->data[desc->idx];
3743
3744 /* If the command was mapped in an mbuf, free it. */
3745 if (data->m != NULL) {
3746 bus_dmamap_sync(ring->data_dmat, data->map,
3747 BUS_DMASYNC_POSTWRITE);
3748 bus_dmamap_unload(ring->data_dmat, data->map);
3749 m_freem(data->m);
3750 data->m = NULL;
3751 }
3752 wakeup(&ring->desc[desc->idx]);
3753 }
3754
3755 static int
iwn_ampdu_check_bitmap(uint64_t bitmap,int start,int idx)3756 iwn_ampdu_check_bitmap(uint64_t bitmap, int start, int idx)
3757 {
3758 int bit, shift;
3759
3760 bit = idx - start;
3761 shift = 0;
3762 if (bit >= 64) {
3763 shift = 0x100 - bit;
3764 bit = 0;
3765 } else if (bit <= -64)
3766 bit = 0x100 + bit;
3767 else if (bit < 0) {
3768 shift = -bit;
3769 bit = 0;
3770 }
3771
3772 if (bit - shift >= 64)
3773 return (0);
3774
3775 return ((bitmap & (1ULL << (bit - shift))) != 0);
3776 }
3777
3778 /*
3779 * Firmware bug workaround: in case if 'retries' counter
3780 * overflows 'seqno' field will be incremented:
3781 * status|sequence|status|sequence|status|sequence
3782 * 0000 0A48 0001 0A49 0000 0A6A
3783 * 1000 0A48 1000 0A49 1000 0A6A
3784 * 2000 0A48 2000 0A49 2000 0A6A
3785 * ...
3786 * E000 0A48 E000 0A49 E000 0A6A
3787 * F000 0A48 F000 0A49 F000 0A6A
3788 * 0000 0A49 0000 0A49 0000 0A6B
3789 * 1000 0A49 1000 0A49 1000 0A6B
3790 * ...
3791 * D000 0A49 D000 0A49 D000 0A6B
3792 * E000 0A49 E001 0A49 E000 0A6B
3793 * F000 0A49 F001 0A49 F000 0A6B
3794 * 0000 0A4A 0000 0A4B 0000 0A6A
3795 * 1000 0A4A 1000 0A4B 1000 0A6A
3796 * ...
3797 *
3798 * Odd 'seqno' numbers are incremened by 2 every 2 overflows.
3799 * For even 'seqno' % 4 != 0 overflow is cyclic (0 -> +1 -> 0).
3800 * Not checked with nretries >= 64.
3801 *
3802 */
3803 static int
iwn_ampdu_index_check(struct iwn_softc * sc,struct iwn_tx_ring * ring,uint64_t bitmap,int start,int idx)3804 iwn_ampdu_index_check(struct iwn_softc *sc, struct iwn_tx_ring *ring,
3805 uint64_t bitmap, int start, int idx)
3806 {
3807 struct ieee80211com *ic = &sc->sc_ic;
3808 struct iwn_tx_data *data;
3809 int diff, min_retries, max_retries, new_idx, loop_end;
3810
3811 new_idx = idx - IWN_LONG_RETRY_LIMIT_LOG;
3812 if (new_idx < 0)
3813 new_idx += IWN_TX_RING_COUNT;
3814
3815 /*
3816 * Corner case: check if retry count is not too big;
3817 * reset device otherwise.
3818 */
3819 if (!iwn_ampdu_check_bitmap(bitmap, start, new_idx)) {
3820 data = &ring->data[new_idx];
3821 if (data->long_retries > IWN_LONG_RETRY_LIMIT) {
3822 device_printf(sc->sc_dev,
3823 "%s: retry count (%d) for idx %d/%d overflow, "
3824 "resetting...\n", __func__, data->long_retries,
3825 ring->qid, new_idx);
3826 ieee80211_restart_all(ic);
3827 return (-1);
3828 }
3829 }
3830
3831 /* Correct index if needed. */
3832 loop_end = idx;
3833 do {
3834 data = &ring->data[new_idx];
3835 diff = idx - new_idx;
3836 if (diff < 0)
3837 diff += IWN_TX_RING_COUNT;
3838
3839 min_retries = IWN_LONG_RETRY_FW_OVERFLOW * diff;
3840 if ((new_idx % 2) == 0)
3841 max_retries = IWN_LONG_RETRY_FW_OVERFLOW * (diff + 1);
3842 else
3843 max_retries = IWN_LONG_RETRY_FW_OVERFLOW * (diff + 2);
3844
3845 if (!iwn_ampdu_check_bitmap(bitmap, start, new_idx) &&
3846 ((data->long_retries >= min_retries &&
3847 data->long_retries < max_retries) ||
3848 (diff == 1 &&
3849 (new_idx & 0x03) == 0x02 &&
3850 data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW))) {
3851 DPRINTF(sc, IWN_DEBUG_AMPDU,
3852 "%s: correcting index %d -> %d in queue %d"
3853 " (retries %d)\n", __func__, idx, new_idx,
3854 ring->qid, data->long_retries);
3855 return (new_idx);
3856 }
3857
3858 new_idx = (new_idx + 1) % IWN_TX_RING_COUNT;
3859 } while (new_idx != loop_end);
3860
3861 return (idx);
3862 }
3863
3864 static void
iwn_ampdu_tx_done(struct iwn_softc * sc,int qid,int nframes,int rtsfailcnt,void * stat)3865 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int nframes, int rtsfailcnt,
3866 void *stat)
3867 {
3868 struct iwn_tx_ring *ring = &sc->txq[qid];
3869 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid];
3870 struct iwn_node *wn = (void *)tap->txa_ni;
3871 struct iwn_tx_data *data;
3872 uint64_t bitmap = 0;
3873 uint16_t *aggstatus = stat;
3874 uint8_t tid = tap->txa_tid;
3875 int bit, i, idx, shift, start, tx_err;
3876
3877 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3878
3879 start = le16toh(*(aggstatus + nframes * 2)) & 0xff;
3880
3881 for (i = 0; i < nframes; i++) {
3882 uint16_t status = le16toh(aggstatus[i * 2]);
3883
3884 if (status & IWN_AGG_TX_STATE_IGNORE_MASK)
3885 continue;
3886
3887 idx = le16toh(aggstatus[i * 2 + 1]) & 0xff;
3888 data = &ring->data[idx];
3889 if (data->remapped) {
3890 idx = iwn_ampdu_index_check(sc, ring, bitmap, start, idx);
3891 if (idx == -1) {
3892 /* skip error (device will be restarted anyway). */
3893 continue;
3894 }
3895
3896 /* Index may have changed. */
3897 data = &ring->data[idx];
3898 }
3899
3900 /*
3901 * XXX Sometimes (rarely) some frames are excluded from events.
3902 * XXX Due to that long_retries counter may be wrong.
3903 */
3904 data->long_retries &= ~0x0f;
3905 data->long_retries += IWN_AGG_TX_TRY_COUNT(status) + 1;
3906
3907 if (data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW) {
3908 int diff, wrong_idx;
3909
3910 diff = data->long_retries / IWN_LONG_RETRY_FW_OVERFLOW;
3911 wrong_idx = (idx + diff) % IWN_TX_RING_COUNT;
3912
3913 /*
3914 * Mark the entry so the above code will check it
3915 * next time.
3916 */
3917 ring->data[wrong_idx].remapped = 1;
3918 }
3919
3920 if (status & IWN_AGG_TX_STATE_UNDERRUN_MSK) {
3921 /*
3922 * NB: count retries but postpone - it was not
3923 * transmitted.
3924 */
3925 continue;
3926 }
3927
3928 bit = idx - start;
3929 shift = 0;
3930 if (bit >= 64) {
3931 shift = 0x100 - bit;
3932 bit = 0;
3933 } else if (bit <= -64)
3934 bit = 0x100 + bit;
3935 else if (bit < 0) {
3936 shift = -bit;
3937 bit = 0;
3938 }
3939 bitmap = bitmap << shift;
3940 bitmap |= 1ULL << bit;
3941 }
3942 wn->agg[tid].startidx = start;
3943 wn->agg[tid].bitmap = bitmap;
3944 wn->agg[tid].short_retries = rtsfailcnt;
3945
3946 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: nframes %d start %d bitmap %016jX\n",
3947 __func__, nframes, start, (uintmax_t)bitmap);
3948
3949 i = ring->read;
3950
3951 for (tx_err = 0;
3952 i != wn->agg[tid].startidx;
3953 i = (i + 1) % IWN_TX_RING_COUNT) {
3954 data = &ring->data[i];
3955 data->remapped = 0;
3956 if (data->m == NULL)
3957 continue;
3958
3959 tx_err++;
3960 iwn_agg_tx_complete(sc, ring, tid, i, 0);
3961 }
3962
3963 ring->read = wn->agg[tid].startidx;
3964 ring->queued -= tx_err;
3965
3966 iwn_check_tx_ring(sc, qid);
3967
3968 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3969 }
3970
3971 /*
3972 * Process an INT_FH_RX or INT_SW_RX interrupt.
3973 */
3974 static void
iwn_notif_intr(struct iwn_softc * sc)3975 iwn_notif_intr(struct iwn_softc *sc)
3976 {
3977 struct iwn_ops *ops = &sc->ops;
3978 struct ieee80211com *ic = &sc->sc_ic;
3979 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3980 uint16_t hw;
3981 int is_stopped;
3982
3983 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map,
3984 BUS_DMASYNC_POSTREAD);
3985
3986 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff;
3987 while (sc->rxq.cur != hw) {
3988 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur];
3989 struct iwn_rx_desc *desc;
3990
3991 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3992 BUS_DMASYNC_POSTREAD);
3993 desc = mtod(data->m, struct iwn_rx_desc *);
3994
3995 DPRINTF(sc, IWN_DEBUG_RECV,
3996 "%s: cur=%d; qid %x idx %d flags %x type %d(%s) len %d\n",
3997 __func__, sc->rxq.cur, desc->qid & IWN_RX_DESC_QID_MSK,
3998 desc->idx, desc->flags, desc->type,
3999 iwn_intr_str(desc->type), le16toh(desc->len));
4000
4001 if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF)) /* Reply to a command. */
4002 iwn_cmd_done(sc, desc);
4003
4004 switch (desc->type) {
4005 case IWN_RX_PHY:
4006 iwn_rx_phy(sc, desc);
4007 break;
4008
4009 case IWN_RX_DONE: /* 4965AGN only. */
4010 case IWN_MPDU_RX_DONE:
4011 /* An 802.11 frame has been received. */
4012 iwn_rx_done(sc, desc, data);
4013
4014 is_stopped = (sc->sc_flags & IWN_FLAG_RUNNING) == 0;
4015 if (__predict_false(is_stopped))
4016 return;
4017
4018 break;
4019
4020 case IWN_RX_COMPRESSED_BA:
4021 /* A Compressed BlockAck has been received. */
4022 iwn_rx_compressed_ba(sc, desc);
4023 break;
4024
4025 case IWN_TX_DONE:
4026 /* An 802.11 frame has been transmitted. */
4027 ops->tx_done(sc, desc, data);
4028 break;
4029
4030 case IWN_RX_STATISTICS:
4031 case IWN_BEACON_STATISTICS:
4032 iwn_rx_statistics(sc, desc);
4033 break;
4034
4035 case IWN_BEACON_MISSED:
4036 {
4037 struct iwn_beacon_missed *miss =
4038 (struct iwn_beacon_missed *)(desc + 1);
4039 int misses;
4040
4041 misses = le32toh(miss->consecutive);
4042
4043 DPRINTF(sc, IWN_DEBUG_STATE,
4044 "%s: beacons missed %d/%d\n", __func__,
4045 misses, le32toh(miss->total));
4046 /*
4047 * If more than 5 consecutive beacons are missed,
4048 * reinitialize the sensitivity state machine.
4049 */
4050 if (vap->iv_state == IEEE80211_S_RUN &&
4051 (ic->ic_flags & IEEE80211_F_SCAN) == 0) {
4052 if (misses > 5)
4053 (void)iwn_init_sensitivity(sc);
4054 if (misses >= vap->iv_bmissthreshold) {
4055 IWN_UNLOCK(sc);
4056 ieee80211_beacon_miss(ic);
4057 IWN_LOCK(sc);
4058
4059 is_stopped = (sc->sc_flags &
4060 IWN_FLAG_RUNNING) == 0;
4061 if (__predict_false(is_stopped))
4062 return;
4063 }
4064 }
4065 break;
4066 }
4067 case IWN_UC_READY:
4068 {
4069 struct iwn_ucode_info *uc =
4070 (struct iwn_ucode_info *)(desc + 1);
4071
4072 /* The microcontroller is ready. */
4073 DPRINTF(sc, IWN_DEBUG_RESET,
4074 "microcode alive notification version=%d.%d "
4075 "subtype=%x alive=%x\n", uc->major, uc->minor,
4076 uc->subtype, le32toh(uc->valid));
4077
4078 if (le32toh(uc->valid) != 1) {
4079 device_printf(sc->sc_dev,
4080 "microcontroller initialization failed");
4081 break;
4082 }
4083 if (uc->subtype == IWN_UCODE_INIT) {
4084 /* Save microcontroller report. */
4085 memcpy(&sc->ucode_info, uc, sizeof (*uc));
4086 }
4087 /* Save the address of the error log in SRAM. */
4088 sc->errptr = le32toh(uc->errptr);
4089 break;
4090 }
4091 #ifdef IWN_DEBUG
4092 case IWN_STATE_CHANGED:
4093 {
4094 /*
4095 * State change allows hardware switch change to be
4096 * noted. However, we handle this in iwn_intr as we
4097 * get both the enable/disble intr.
4098 */
4099 uint32_t *status = (uint32_t *)(desc + 1);
4100 DPRINTF(sc, IWN_DEBUG_INTR | IWN_DEBUG_STATE,
4101 "state changed to %x\n",
4102 le32toh(*status));
4103 break;
4104 }
4105 case IWN_START_SCAN:
4106 {
4107 struct iwn_start_scan *scan =
4108 (struct iwn_start_scan *)(desc + 1);
4109 DPRINTF(sc, IWN_DEBUG_ANY,
4110 "%s: scanning channel %d status %x\n",
4111 __func__, scan->chan, le32toh(scan->status));
4112 break;
4113 }
4114 #endif
4115 case IWN_STOP_SCAN:
4116 {
4117 #ifdef IWN_DEBUG
4118 struct iwn_stop_scan *scan =
4119 (struct iwn_stop_scan *)(desc + 1);
4120 DPRINTF(sc, IWN_DEBUG_STATE | IWN_DEBUG_SCAN,
4121 "scan finished nchan=%d status=%d chan=%d\n",
4122 scan->nchan, scan->status, scan->chan);
4123 #endif
4124 sc->sc_is_scanning = 0;
4125 callout_stop(&sc->scan_timeout);
4126 IWN_UNLOCK(sc);
4127 ieee80211_scan_next(vap);
4128 IWN_LOCK(sc);
4129
4130 is_stopped = (sc->sc_flags & IWN_FLAG_RUNNING) == 0;
4131 if (__predict_false(is_stopped))
4132 return;
4133
4134 break;
4135 }
4136 case IWN5000_CALIBRATION_RESULT:
4137 iwn5000_rx_calib_results(sc, desc);
4138 break;
4139
4140 case IWN5000_CALIBRATION_DONE:
4141 sc->sc_flags |= IWN_FLAG_CALIB_DONE;
4142 wakeup(sc);
4143 break;
4144 }
4145
4146 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT;
4147 }
4148
4149 /* Tell the firmware what we have processed. */
4150 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1;
4151 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7);
4152 }
4153
4154 /*
4155 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up
4156 * from power-down sleep mode.
4157 */
4158 static void
iwn_wakeup_intr(struct iwn_softc * sc)4159 iwn_wakeup_intr(struct iwn_softc *sc)
4160 {
4161 int qid;
4162
4163 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n",
4164 __func__);
4165
4166 /* Wakeup RX and TX rings. */
4167 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7);
4168 for (qid = 0; qid < sc->ntxqs; qid++) {
4169 struct iwn_tx_ring *ring = &sc->txq[qid];
4170 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur);
4171 }
4172 }
4173
4174 static void
iwn_rftoggle_task(void * arg,int npending)4175 iwn_rftoggle_task(void *arg, int npending)
4176 {
4177 struct iwn_softc *sc = arg;
4178 struct ieee80211com *ic = &sc->sc_ic;
4179 uint32_t tmp;
4180
4181 IWN_LOCK(sc);
4182 tmp = IWN_READ(sc, IWN_GP_CNTRL);
4183 IWN_UNLOCK(sc);
4184
4185 device_printf(sc->sc_dev, "RF switch: radio %s\n",
4186 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled");
4187 if (!(tmp & IWN_GP_CNTRL_RFKILL)) {
4188 ieee80211_suspend_all(ic);
4189
4190 /* Enable interrupts to get RF toggle notification. */
4191 IWN_LOCK(sc);
4192 IWN_WRITE(sc, IWN_INT, 0xffffffff);
4193 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
4194 IWN_UNLOCK(sc);
4195 } else
4196 ieee80211_resume_all(ic);
4197 }
4198
4199 /*
4200 * Dump the error log of the firmware when a firmware panic occurs. Although
4201 * we can't debug the firmware because it is neither open source nor free, it
4202 * can help us to identify certain classes of problems.
4203 */
4204 static void
iwn_fatal_intr(struct iwn_softc * sc)4205 iwn_fatal_intr(struct iwn_softc *sc)
4206 {
4207 struct iwn_fw_dump dump;
4208 int i;
4209
4210 IWN_LOCK_ASSERT(sc);
4211
4212 /* Force a complete recalibration on next init. */
4213 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE;
4214
4215 /* Check that the error log address is valid. */
4216 if (sc->errptr < IWN_FW_DATA_BASE ||
4217 sc->errptr + sizeof (dump) >
4218 IWN_FW_DATA_BASE + sc->fw_data_maxsz) {
4219 printf("%s: bad firmware error log address 0x%08x\n", __func__,
4220 sc->errptr);
4221 return;
4222 }
4223 if (iwn_nic_lock(sc) != 0) {
4224 printf("%s: could not read firmware error log\n", __func__);
4225 return;
4226 }
4227 /* Read firmware error log from SRAM. */
4228 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump,
4229 sizeof (dump) / sizeof (uint32_t));
4230 iwn_nic_unlock(sc);
4231
4232 if (dump.valid == 0) {
4233 printf("%s: firmware error log is empty\n", __func__);
4234 return;
4235 }
4236 printf("firmware error log:\n");
4237 printf(" error type = \"%s\" (0x%08X)\n",
4238 (dump.id < nitems(iwn_fw_errmsg)) ?
4239 iwn_fw_errmsg[dump.id] : "UNKNOWN",
4240 dump.id);
4241 printf(" program counter = 0x%08X\n", dump.pc);
4242 printf(" source line = 0x%08X\n", dump.src_line);
4243 printf(" error data = 0x%08X%08X\n",
4244 dump.error_data[0], dump.error_data[1]);
4245 printf(" branch link = 0x%08X%08X\n",
4246 dump.branch_link[0], dump.branch_link[1]);
4247 printf(" interrupt link = 0x%08X%08X\n",
4248 dump.interrupt_link[0], dump.interrupt_link[1]);
4249 printf(" time = %u\n", dump.time[0]);
4250
4251 /* Dump driver status (TX and RX rings) while we're here. */
4252 printf("driver status:\n");
4253 for (i = 0; i < sc->ntxqs; i++) {
4254 struct iwn_tx_ring *ring = &sc->txq[i];
4255 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n",
4256 i, ring->qid, ring->cur, ring->queued);
4257 }
4258 printf(" rx ring: cur=%d\n", sc->rxq.cur);
4259 }
4260
4261 static void
iwn_intr(void * arg)4262 iwn_intr(void *arg)
4263 {
4264 struct iwn_softc *sc = arg;
4265 uint32_t r1, r2, tmp;
4266
4267 IWN_LOCK(sc);
4268
4269 /* Disable interrupts. */
4270 IWN_WRITE(sc, IWN_INT_MASK, 0);
4271
4272 /* Read interrupts from ICT (fast) or from registers (slow). */
4273 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
4274 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map,
4275 BUS_DMASYNC_POSTREAD);
4276 tmp = 0;
4277 while (sc->ict[sc->ict_cur] != 0) {
4278 tmp |= sc->ict[sc->ict_cur];
4279 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */
4280 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT;
4281 }
4282 tmp = le32toh(tmp);
4283 if (tmp == 0xffffffff) /* Shouldn't happen. */
4284 tmp = 0;
4285 else if (tmp & 0xc0000) /* Workaround a HW bug. */
4286 tmp |= 0x8000;
4287 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff);
4288 r2 = 0; /* Unused. */
4289 } else {
4290 r1 = IWN_READ(sc, IWN_INT);
4291 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) {
4292 IWN_UNLOCK(sc);
4293 return; /* Hardware gone! */
4294 }
4295 r2 = IWN_READ(sc, IWN_FH_INT);
4296 }
4297
4298 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n"
4299 , r1, r2);
4300
4301 if (r1 == 0 && r2 == 0)
4302 goto done; /* Interrupt not for us. */
4303
4304 /* Acknowledge interrupts. */
4305 IWN_WRITE(sc, IWN_INT, r1);
4306 if (!(sc->sc_flags & IWN_FLAG_USE_ICT))
4307 IWN_WRITE(sc, IWN_FH_INT, r2);
4308
4309 if (r1 & IWN_INT_RF_TOGGLED) {
4310 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task);
4311 goto done;
4312 }
4313 if (r1 & IWN_INT_CT_REACHED) {
4314 device_printf(sc->sc_dev, "%s: critical temperature reached!\n",
4315 __func__);
4316 }
4317 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) {
4318 device_printf(sc->sc_dev, "%s: fatal firmware error\n",
4319 __func__);
4320 #ifdef IWN_DEBUG
4321 iwn_debug_register(sc);
4322 #endif
4323 /* Dump firmware error log and stop. */
4324 iwn_fatal_intr(sc);
4325
4326 taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task);
4327 goto done;
4328 }
4329 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) ||
4330 (r2 & IWN_FH_INT_RX)) {
4331 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
4332 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX))
4333 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX);
4334 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
4335 IWN_INT_PERIODIC_DIS);
4336 iwn_notif_intr(sc);
4337 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) {
4338 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
4339 IWN_INT_PERIODIC_ENA);
4340 }
4341 } else
4342 iwn_notif_intr(sc);
4343 }
4344
4345 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) {
4346 if (sc->sc_flags & IWN_FLAG_USE_ICT)
4347 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX);
4348 wakeup(sc); /* FH DMA transfer completed. */
4349 }
4350
4351 if (r1 & IWN_INT_ALIVE)
4352 wakeup(sc); /* Firmware is alive. */
4353
4354 if (r1 & IWN_INT_WAKEUP)
4355 iwn_wakeup_intr(sc);
4356
4357 done:
4358 /* Re-enable interrupts. */
4359 if (sc->sc_flags & IWN_FLAG_RUNNING)
4360 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
4361
4362 IWN_UNLOCK(sc);
4363 }
4364
4365 /*
4366 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and
4367 * 5000 adapters use a slightly different format).
4368 */
4369 static void
iwn4965_update_sched(struct iwn_softc * sc,int qid,int idx,uint8_t id,uint16_t len)4370 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
4371 uint16_t len)
4372 {
4373 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx];
4374
4375 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
4376
4377 *w = htole16(len + 8);
4378 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4379 BUS_DMASYNC_PREWRITE);
4380 if (idx < IWN_SCHED_WINSZ) {
4381 *(w + IWN_TX_RING_COUNT) = *w;
4382 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4383 BUS_DMASYNC_PREWRITE);
4384 }
4385 }
4386
4387 static void
iwn5000_update_sched(struct iwn_softc * sc,int qid,int idx,uint8_t id,uint16_t len)4388 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
4389 uint16_t len)
4390 {
4391 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
4392
4393 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
4394
4395 *w = htole16(id << 12 | (len + 8));
4396 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4397 BUS_DMASYNC_PREWRITE);
4398 if (idx < IWN_SCHED_WINSZ) {
4399 *(w + IWN_TX_RING_COUNT) = *w;
4400 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4401 BUS_DMASYNC_PREWRITE);
4402 }
4403 }
4404
4405 #ifdef notyet
4406 static void
iwn5000_reset_sched(struct iwn_softc * sc,int qid,int idx)4407 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx)
4408 {
4409 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
4410
4411 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
4412
4413 *w = (*w & htole16(0xf000)) | htole16(1);
4414 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4415 BUS_DMASYNC_PREWRITE);
4416 if (idx < IWN_SCHED_WINSZ) {
4417 *(w + IWN_TX_RING_COUNT) = *w;
4418 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4419 BUS_DMASYNC_PREWRITE);
4420 }
4421 }
4422 #endif
4423
4424 /*
4425 * Check whether OFDM 11g protection will be enabled for the given rate.
4426 *
4427 * The original driver code only enabled protection for OFDM rates.
4428 * It didn't check to see whether it was operating in 11a or 11bg mode.
4429 */
4430 static int
iwn_check_rate_needs_protection(struct iwn_softc * sc,struct ieee80211vap * vap,uint8_t rate)4431 iwn_check_rate_needs_protection(struct iwn_softc *sc,
4432 struct ieee80211vap *vap, uint8_t rate)
4433 {
4434 struct ieee80211com *ic = vap->iv_ic;
4435
4436 /*
4437 * Not in 2GHz mode? Then there's no need to enable OFDM
4438 * 11bg protection.
4439 */
4440 if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
4441 return (0);
4442 }
4443
4444 /*
4445 * 11bg protection not enabled? Then don't use it.
4446 */
4447 if ((vap->iv_flags & IEEE80211_F_USEPROT) == 0)
4448 return (0);
4449
4450 /*
4451 * If it's an 11n rate - no protection.
4452 * We'll do it via a specific 11n check.
4453 */
4454 if (rate & IEEE80211_RATE_MCS) {
4455 return (0);
4456 }
4457
4458 /*
4459 * Do a rate table lookup. If the PHY is CCK,
4460 * don't do protection.
4461 */
4462 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK)
4463 return (0);
4464
4465 /*
4466 * Yup, enable protection.
4467 */
4468 return (1);
4469 }
4470
4471 /*
4472 * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into
4473 * the link quality table that reflects this particular entry.
4474 */
4475 static int
iwn_tx_rate_to_linkq_offset(struct iwn_softc * sc,struct ieee80211_node * ni,uint8_t rate)4476 iwn_tx_rate_to_linkq_offset(struct iwn_softc *sc, struct ieee80211_node *ni,
4477 uint8_t rate)
4478 {
4479 struct ieee80211_rateset *rs;
4480 int is_11n;
4481 int nr;
4482 int i;
4483 uint8_t cmp_rate;
4484
4485 /*
4486 * Figure out if we're using 11n or not here.
4487 */
4488 if (ieee80211_ht_check_tx_ht(ni))
4489 is_11n = 1;
4490 else
4491 is_11n = 0;
4492
4493 /*
4494 * Use the correct rate table.
4495 */
4496 if (is_11n) {
4497 rs = (struct ieee80211_rateset *) &ni->ni_htrates;
4498 nr = ni->ni_htrates.rs_nrates;
4499 } else {
4500 rs = &ni->ni_rates;
4501 nr = rs->rs_nrates;
4502 }
4503
4504 /*
4505 * Find the relevant link quality entry in the table.
4506 */
4507 for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) {
4508 /*
4509 * The link quality table index starts at 0 == highest
4510 * rate, so we walk the rate table backwards.
4511 */
4512 cmp_rate = rs->rs_rates[(nr - 1) - i];
4513 if (rate & IEEE80211_RATE_MCS)
4514 cmp_rate |= IEEE80211_RATE_MCS;
4515
4516 #if 0
4517 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: idx %d: nr=%d, rate=0x%02x, rateentry=0x%02x\n",
4518 __func__,
4519 i,
4520 nr,
4521 rate,
4522 cmp_rate);
4523 #endif
4524
4525 if (cmp_rate == rate)
4526 return (i);
4527 }
4528
4529 /* Failed? Start at the end */
4530 return (IWN_MAX_TX_RETRIES - 1);
4531 }
4532
4533 static int
iwn_tx_data(struct iwn_softc * sc,struct mbuf * m,struct ieee80211_node * ni)4534 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
4535 {
4536 const struct ieee80211_txparam *tp = ni->ni_txparms;
4537 struct ieee80211vap *vap = ni->ni_vap;
4538 struct ieee80211com *ic = ni->ni_ic;
4539 struct iwn_node *wn = (void *)ni;
4540 struct iwn_tx_ring *ring;
4541 struct iwn_tx_cmd *cmd;
4542 struct iwn_cmd_data *tx;
4543 struct ieee80211_frame *wh;
4544 struct ieee80211_key *k = NULL;
4545 uint32_t flags;
4546 uint16_t qos;
4547 uint8_t tid, type;
4548 int ac, totlen, rate;
4549
4550 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
4551
4552 IWN_LOCK_ASSERT(sc);
4553
4554 wh = mtod(m, struct ieee80211_frame *);
4555 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
4556
4557 /* Select EDCA Access Category and TX ring for this frame. */
4558 if (IEEE80211_QOS_HAS_SEQ(wh)) {
4559 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
4560 tid = qos & IEEE80211_QOS_TID;
4561 } else {
4562 qos = 0;
4563 tid = 0;
4564 }
4565
4566 /* Choose a TX rate index. */
4567 if (type == IEEE80211_FC0_TYPE_MGT ||
4568 type == IEEE80211_FC0_TYPE_CTL ||
4569 (m->m_flags & M_EAPOL) != 0)
4570 rate = tp->mgmtrate;
4571 else if (IEEE80211_IS_MULTICAST(wh->i_addr1))
4572 rate = tp->mcastrate;
4573 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
4574 rate = tp->ucastrate;
4575 else {
4576 /* XXX pass pktlen */
4577 (void) ieee80211_ratectl_rate(ni, NULL, 0);
4578 rate = ieee80211_node_get_txrate_dot11rate(ni);
4579 }
4580
4581 /*
4582 * XXX TODO: Group addressed frames aren't aggregated and must
4583 * go to the normal non-aggregation queue, and have a NONQOS TID
4584 * assigned from net80211.
4585 *
4586 * TODO: same with NULL QOS frames, which we shouldn't be sending
4587 * anyway ourselves (and should stub out / warn / etc.)
4588 */
4589
4590 ac = M_WME_GETAC(m);
4591 if (m->m_flags & M_AMPDU_MPDU) {
4592 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac];
4593
4594 if (!IEEE80211_AMPDU_RUNNING(tap))
4595 return (EINVAL);
4596
4597 ac = *(int *)tap->txa_private;
4598 }
4599
4600 /* Only assign if not A-MPDU; the A-MPDU TX path will do its own */
4601 if ((m->m_flags & M_AMPDU_MPDU) == 0)
4602 ieee80211_output_seqno_assign(ni, -1, m);
4603
4604 /* Encrypt the frame if need be. */
4605 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
4606 /* Retrieve key for TX. */
4607 k = ieee80211_crypto_encap(ni, m);
4608 if (k == NULL) {
4609 return ENOBUFS;
4610 }
4611 /* 802.11 header may have moved. */
4612 wh = mtod(m, struct ieee80211_frame *);
4613 }
4614 totlen = m->m_pkthdr.len;
4615
4616 if (ieee80211_radiotap_active_vap(vap)) {
4617 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
4618
4619 tap->wt_flags = 0;
4620 tap->wt_rate = rate;
4621 if (k != NULL)
4622 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
4623
4624 ieee80211_radiotap_tx(vap, m);
4625 }
4626
4627 flags = 0;
4628 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
4629 /* Unicast frame, check if an ACK is expected. */
4630 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
4631 IEEE80211_QOS_ACKPOLICY_NOACK)
4632 flags |= IWN_TX_NEED_ACK;
4633 }
4634 if (IEEE80211_IS_CTL_BAR(wh))
4635 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */
4636
4637 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
4638 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */
4639
4640 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */
4641 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
4642 /* NB: Group frames are sent using CCK in 802.11b/g. */
4643 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) {
4644 flags |= IWN_TX_NEED_RTS;
4645 } else if (iwn_check_rate_needs_protection(sc, vap, rate)) {
4646 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
4647 flags |= IWN_TX_NEED_CTS;
4648 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
4649 flags |= IWN_TX_NEED_RTS;
4650 } else if ((rate & IEEE80211_RATE_MCS) &&
4651 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) {
4652 flags |= IWN_TX_NEED_RTS;
4653 }
4654
4655 /* XXX HT protection? */
4656
4657 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) {
4658 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4659 /* 5000 autoselects RTS/CTS or CTS-to-self. */
4660 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS);
4661 flags |= IWN_TX_NEED_PROTECTION;
4662 } else
4663 flags |= IWN_TX_FULL_TXOP;
4664 }
4665 }
4666
4667 ring = &sc->txq[ac];
4668 if (m->m_flags & M_AMPDU_MPDU) {
4669 uint16_t seqno = ni->ni_txseqs[tid];
4670
4671 if (ring->queued > IWN_TX_RING_COUNT / 2 &&
4672 (ring->cur + 1) % IWN_TX_RING_COUNT == ring->read) {
4673 DPRINTF(sc, IWN_DEBUG_AMPDU, "%s: no more space "
4674 "(queued %d) left in %d queue!\n",
4675 __func__, ring->queued, ac);
4676 return (ENOBUFS);
4677 }
4678
4679 /*
4680 * Queue this frame to the hardware ring that we've
4681 * negotiated AMPDU TX on.
4682 *
4683 * Note that the sequence number must match the TX slot
4684 * being used!
4685 */
4686 if ((seqno % 256) != ring->cur) {
4687 device_printf(sc->sc_dev,
4688 "%s: m=%p: seqno (%d) (%d) != ring index (%d) !\n",
4689 __func__,
4690 m,
4691 seqno,
4692 seqno % 256,
4693 ring->cur);
4694
4695 /* XXX until D9195 will not be committed */
4696 ni->ni_txseqs[tid] &= ~0xff;
4697 ni->ni_txseqs[tid] += ring->cur;
4698 seqno = ni->ni_txseqs[tid];
4699 }
4700
4701 *(uint16_t *)wh->i_seq =
4702 htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
4703 ni->ni_txseqs[tid]++;
4704 }
4705
4706 /* Prepare TX firmware command. */
4707 cmd = &ring->cmd[ring->cur];
4708 tx = (struct iwn_cmd_data *)cmd->data;
4709
4710 /* NB: No need to clear tx, all fields are reinitialized here. */
4711 tx->scratch = 0; /* clear "scratch" area */
4712
4713 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
4714 type != IEEE80211_FC0_TYPE_DATA)
4715 tx->id = sc->broadcast_id;
4716 else
4717 tx->id = wn->id;
4718
4719 if (type == IEEE80211_FC0_TYPE_MGT) {
4720 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
4721
4722 /* Tell HW to set timestamp in probe responses. */
4723 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
4724 flags |= IWN_TX_INSERT_TSTAMP;
4725 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
4726 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
4727 tx->timeout = htole16(3);
4728 else
4729 tx->timeout = htole16(2);
4730 } else
4731 tx->timeout = htole16(0);
4732
4733 if (tx->id == sc->broadcast_id) {
4734 /* Group or management frame. */
4735 tx->linkq = 0;
4736 } else {
4737 tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate);
4738 flags |= IWN_TX_LINKQ; /* enable MRR */
4739 }
4740
4741 tx->tid = tid;
4742 tx->rts_ntries = 60;
4743 tx->data_ntries = 15;
4744 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
4745 tx->rate = iwn_rate_to_plcp(sc, ni, rate);
4746 tx->security = 0;
4747 tx->flags = htole32(flags);
4748
4749 return (iwn_tx_cmd(sc, m, ni, ring));
4750 }
4751
4752 static int
iwn_tx_data_raw(struct iwn_softc * sc,struct mbuf * m,struct ieee80211_node * ni,const struct ieee80211_bpf_params * params)4753 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m,
4754 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
4755 {
4756 struct ieee80211vap *vap = ni->ni_vap;
4757 struct iwn_tx_cmd *cmd;
4758 struct iwn_cmd_data *tx;
4759 struct ieee80211_frame *wh;
4760 struct iwn_tx_ring *ring;
4761 uint32_t flags;
4762 int ac, rate;
4763 uint8_t type;
4764
4765 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
4766
4767 IWN_LOCK_ASSERT(sc);
4768
4769 wh = mtod(m, struct ieee80211_frame *);
4770 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
4771
4772 ac = params->ibp_pri & 3;
4773
4774 /* Assign sequence number. */
4775 if ((m->m_flags & M_AMPDU_MPDU) == 0)
4776 ieee80211_output_seqno_assign(ni, -1, m);
4777
4778 /* Choose a TX rate. */
4779 rate = params->ibp_rate0;
4780
4781 flags = 0;
4782 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
4783 flags |= IWN_TX_NEED_ACK;
4784 if (params->ibp_flags & IEEE80211_BPF_RTS) {
4785 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4786 /* 5000 autoselects RTS/CTS or CTS-to-self. */
4787 flags &= ~IWN_TX_NEED_RTS;
4788 flags |= IWN_TX_NEED_PROTECTION;
4789 } else
4790 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP;
4791 }
4792 if (params->ibp_flags & IEEE80211_BPF_CTS) {
4793 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4794 /* 5000 autoselects RTS/CTS or CTS-to-self. */
4795 flags &= ~IWN_TX_NEED_CTS;
4796 flags |= IWN_TX_NEED_PROTECTION;
4797 } else
4798 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP;
4799 }
4800
4801 if (ieee80211_radiotap_active_vap(vap)) {
4802 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
4803
4804 tap->wt_flags = 0;
4805 tap->wt_rate = rate;
4806
4807 ieee80211_radiotap_tx(vap, m);
4808 }
4809
4810 ring = &sc->txq[ac];
4811 cmd = &ring->cmd[ring->cur];
4812
4813 tx = (struct iwn_cmd_data *)cmd->data;
4814 /* NB: No need to clear tx, all fields are reinitialized here. */
4815 tx->scratch = 0; /* clear "scratch" area */
4816
4817 if (type == IEEE80211_FC0_TYPE_MGT) {
4818 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
4819
4820 /* Tell HW to set timestamp in probe responses. */
4821 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
4822 flags |= IWN_TX_INSERT_TSTAMP;
4823
4824 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
4825 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
4826 tx->timeout = htole16(3);
4827 else
4828 tx->timeout = htole16(2);
4829 } else
4830 tx->timeout = htole16(0);
4831
4832 tx->tid = 0;
4833 tx->id = sc->broadcast_id;
4834 tx->rts_ntries = params->ibp_try1;
4835 tx->data_ntries = params->ibp_try0;
4836 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
4837 tx->rate = iwn_rate_to_plcp(sc, ni, rate);
4838 tx->security = 0;
4839 tx->flags = htole32(flags);
4840
4841 /* Group or management frame. */
4842 tx->linkq = 0;
4843
4844 return (iwn_tx_cmd(sc, m, ni, ring));
4845 }
4846
4847 static int
iwn_tx_cmd(struct iwn_softc * sc,struct mbuf * m,struct ieee80211_node * ni,struct iwn_tx_ring * ring)4848 iwn_tx_cmd(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
4849 struct iwn_tx_ring *ring)
4850 {
4851 struct iwn_ops *ops = &sc->ops;
4852 struct iwn_tx_cmd *cmd;
4853 struct iwn_cmd_data *tx;
4854 struct ieee80211_frame *wh;
4855 struct iwn_tx_desc *desc;
4856 struct iwn_tx_data *data;
4857 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER];
4858 struct mbuf *m1;
4859 u_int hdrlen;
4860 int totlen, error, pad, nsegs = 0, i;
4861
4862 wh = mtod(m, struct ieee80211_frame *);
4863 hdrlen = ieee80211_anyhdrsize(wh);
4864 totlen = m->m_pkthdr.len;
4865
4866 desc = &ring->desc[ring->cur];
4867 data = &ring->data[ring->cur];
4868
4869 if (__predict_false(data->m != NULL || data->ni != NULL)) {
4870 device_printf(sc->sc_dev, "%s: ni (%p) or m (%p) for idx %d "
4871 "in queue %d is not NULL!\n", __func__, data->ni, data->m,
4872 ring->cur, ring->qid);
4873 return EIO;
4874 }
4875
4876 /* Prepare TX firmware command. */
4877 cmd = &ring->cmd[ring->cur];
4878 cmd->code = IWN_CMD_TX_DATA;
4879 cmd->flags = 0;
4880 cmd->qid = ring->qid;
4881 cmd->idx = ring->cur;
4882
4883 tx = (struct iwn_cmd_data *)cmd->data;
4884 tx->len = htole16(totlen);
4885
4886 /* Set physical address of "scratch area". */
4887 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
4888 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
4889 if (hdrlen & 3) {
4890 /* First segment length must be a multiple of 4. */
4891 tx->flags |= htole32(IWN_TX_NEED_PADDING);
4892 pad = 4 - (hdrlen & 3);
4893 } else
4894 pad = 0;
4895
4896 /* Copy 802.11 header in TX command. */
4897 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
4898
4899 /* Trim 802.11 header. */
4900 m_adj(m, hdrlen);
4901
4902 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs,
4903 &nsegs, BUS_DMA_NOWAIT);
4904 if (error != 0) {
4905 if (error != EFBIG) {
4906 device_printf(sc->sc_dev,
4907 "%s: can't map mbuf (error %d)\n", __func__, error);
4908 return error;
4909 }
4910 /* Too many DMA segments, linearize mbuf. */
4911 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1);
4912 if (m1 == NULL) {
4913 device_printf(sc->sc_dev,
4914 "%s: could not defrag mbuf\n", __func__);
4915 return ENOBUFS;
4916 }
4917 m = m1;
4918
4919 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m,
4920 segs, &nsegs, BUS_DMA_NOWAIT);
4921 if (error != 0) {
4922 /* XXX fix this */
4923 /*
4924 * NB: Do not return error;
4925 * original mbuf does not exist anymore.
4926 */
4927 device_printf(sc->sc_dev,
4928 "%s: can't map mbuf (error %d)\n",
4929 __func__, error);
4930 if_inc_counter(ni->ni_vap->iv_ifp,
4931 IFCOUNTER_OERRORS, 1);
4932 ieee80211_free_node(ni);
4933 m_freem(m);
4934 return 0;
4935 }
4936 }
4937
4938 data->m = m;
4939 data->ni = ni;
4940
4941 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d "
4942 "plcp 0x%x\n",
4943 __func__, ring->qid, ring->cur, totlen, nsegs, tx->rate);
4944
4945 /* Fill TX descriptor. */
4946 desc->nsegs = 1;
4947 if (m->m_len != 0)
4948 desc->nsegs += nsegs;
4949 /* First DMA segment is used by the TX command. */
4950 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
4951 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
4952 (4 + sizeof (*tx) + hdrlen + pad) << 4);
4953 /* Other DMA segments are for data payload. */
4954 seg = &segs[0];
4955 for (i = 1; i <= nsegs; i++) {
4956 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
4957 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) |
4958 seg->ds_len << 4);
4959 seg++;
4960 }
4961
4962 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
4963 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map,
4964 BUS_DMASYNC_PREWRITE);
4965 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
4966 BUS_DMASYNC_PREWRITE);
4967
4968 /* Update TX scheduler. */
4969 if (ring->qid >= sc->firstaggqueue)
4970 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
4971
4972 /* Kick TX ring. */
4973 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
4974 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
4975
4976 /* Mark TX ring as full if we reach a certain threshold. */
4977 if (++ring->queued > IWN_TX_RING_HIMARK)
4978 sc->qfullmsk |= 1 << ring->qid;
4979
4980 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
4981
4982 return 0;
4983 }
4984
4985 static void
iwn_xmit_task(void * arg0,int pending)4986 iwn_xmit_task(void *arg0, int pending)
4987 {
4988 struct iwn_softc *sc = arg0;
4989 struct ieee80211_node *ni;
4990 struct mbuf *m;
4991 int error;
4992 struct ieee80211_bpf_params p;
4993 int have_p;
4994
4995 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: called\n", __func__);
4996
4997 IWN_LOCK(sc);
4998 /*
4999 * Dequeue frames, attempt to transmit,
5000 * then disable beaconwait when we're done.
5001 */
5002 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) {
5003 have_p = 0;
5004 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
5005
5006 /* Get xmit params if appropriate */
5007 if (ieee80211_get_xmit_params(m, &p) == 0)
5008 have_p = 1;
5009
5010 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: m=%p, have_p=%d\n",
5011 __func__, m, have_p);
5012
5013 /* If we have xmit params, use them */
5014 if (have_p)
5015 error = iwn_tx_data_raw(sc, m, ni, &p);
5016 else
5017 error = iwn_tx_data(sc, m, ni);
5018
5019 if (error != 0) {
5020 if_inc_counter(ni->ni_vap->iv_ifp,
5021 IFCOUNTER_OERRORS, 1);
5022 ieee80211_free_node(ni);
5023 m_freem(m);
5024 }
5025 }
5026
5027 sc->sc_beacon_wait = 0;
5028 IWN_UNLOCK(sc);
5029 }
5030
5031 /*
5032 * raw frame xmit - free node/reference if failed.
5033 */
5034 static int
iwn_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)5035 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
5036 const struct ieee80211_bpf_params *params)
5037 {
5038 struct ieee80211com *ic = ni->ni_ic;
5039 struct iwn_softc *sc = ic->ic_softc;
5040 int error = 0;
5041
5042 DPRINTF(sc, IWN_DEBUG_XMIT | IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5043
5044 IWN_LOCK(sc);
5045 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0) {
5046 m_freem(m);
5047 IWN_UNLOCK(sc);
5048 return (ENETDOWN);
5049 }
5050
5051 /* queue frame if we have to */
5052 if (sc->sc_beacon_wait) {
5053 if (iwn_xmit_queue_enqueue(sc, m) != 0) {
5054 m_freem(m);
5055 IWN_UNLOCK(sc);
5056 return (ENOBUFS);
5057 }
5058 /* Queued, so just return OK */
5059 IWN_UNLOCK(sc);
5060 return (0);
5061 }
5062
5063 if (params == NULL) {
5064 /*
5065 * Legacy path; interpret frame contents to decide
5066 * precisely how to send the frame.
5067 */
5068 error = iwn_tx_data(sc, m, ni);
5069 } else {
5070 /*
5071 * Caller supplied explicit parameters to use in
5072 * sending the frame.
5073 */
5074 error = iwn_tx_data_raw(sc, m, ni, params);
5075 }
5076 if (error == 0)
5077 sc->sc_tx_timer = 5;
5078 else
5079 m_freem(m);
5080
5081 IWN_UNLOCK(sc);
5082
5083 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s: end\n",__func__);
5084
5085 return (error);
5086 }
5087
5088 /*
5089 * transmit - don't free mbuf if failed; don't free node ref if failed.
5090 */
5091 static int
iwn_transmit(struct ieee80211com * ic,struct mbuf * m)5092 iwn_transmit(struct ieee80211com *ic, struct mbuf *m)
5093 {
5094 struct iwn_softc *sc = ic->ic_softc;
5095 struct ieee80211_node *ni;
5096 int error;
5097
5098 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
5099
5100 IWN_LOCK(sc);
5101 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0 || sc->sc_beacon_wait) {
5102 IWN_UNLOCK(sc);
5103 return (ENXIO);
5104 }
5105
5106 if (sc->qfullmsk) {
5107 IWN_UNLOCK(sc);
5108 return (ENOBUFS);
5109 }
5110
5111 error = iwn_tx_data(sc, m, ni);
5112 if (!error)
5113 sc->sc_tx_timer = 5;
5114 IWN_UNLOCK(sc);
5115 return (error);
5116 }
5117
5118 static void
iwn_scan_timeout(void * arg)5119 iwn_scan_timeout(void *arg)
5120 {
5121 struct iwn_softc *sc = arg;
5122 struct ieee80211com *ic = &sc->sc_ic;
5123
5124 ic_printf(ic, "scan timeout\n");
5125 ieee80211_restart_all(ic);
5126 }
5127
5128 static void
iwn_watchdog(void * arg)5129 iwn_watchdog(void *arg)
5130 {
5131 struct iwn_softc *sc = arg;
5132 struct ieee80211com *ic = &sc->sc_ic;
5133
5134 IWN_LOCK_ASSERT(sc);
5135
5136 KASSERT(sc->sc_flags & IWN_FLAG_RUNNING, ("not running"));
5137
5138 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5139
5140 if (sc->sc_tx_timer > 0) {
5141 if (--sc->sc_tx_timer == 0) {
5142 ic_printf(ic, "device timeout\n");
5143 ieee80211_restart_all(ic);
5144 return;
5145 }
5146 }
5147 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
5148 }
5149
5150 static int
iwn_cdev_open(struct cdev * dev,int flags,int type,struct thread * td)5151 iwn_cdev_open(struct cdev *dev, int flags, int type, struct thread *td)
5152 {
5153
5154 return (0);
5155 }
5156
5157 static int
iwn_cdev_close(struct cdev * dev,int flags,int type,struct thread * td)5158 iwn_cdev_close(struct cdev *dev, int flags, int type, struct thread *td)
5159 {
5160
5161 return (0);
5162 }
5163
5164 static int
iwn_cdev_ioctl(struct cdev * dev,unsigned long cmd,caddr_t data,int fflag,struct thread * td)5165 iwn_cdev_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
5166 struct thread *td)
5167 {
5168 int rc;
5169 struct iwn_softc *sc = dev->si_drv1;
5170 struct iwn_ioctl_data *d;
5171
5172 rc = priv_check(td, PRIV_DRIVER);
5173 if (rc != 0)
5174 return (0);
5175
5176 switch (cmd) {
5177 case SIOCGIWNSTATS:
5178 d = (struct iwn_ioctl_data *) data;
5179 IWN_LOCK(sc);
5180 /* XXX validate permissions/memory/etc? */
5181 rc = copyout(&sc->last_stat, d->dst_addr, sizeof(struct iwn_stats));
5182 IWN_UNLOCK(sc);
5183 break;
5184 case SIOCZIWNSTATS:
5185 IWN_LOCK(sc);
5186 memset(&sc->last_stat, 0, sizeof(struct iwn_stats));
5187 IWN_UNLOCK(sc);
5188 break;
5189 default:
5190 rc = EINVAL;
5191 break;
5192 }
5193 return (rc);
5194 }
5195
5196 static int
iwn_ioctl(struct ieee80211com * ic,u_long cmd,void * data)5197 iwn_ioctl(struct ieee80211com *ic, u_long cmd, void *data)
5198 {
5199
5200 return (ENOTTY);
5201 }
5202
5203 static void
iwn_parent(struct ieee80211com * ic)5204 iwn_parent(struct ieee80211com *ic)
5205 {
5206 struct iwn_softc *sc = ic->ic_softc;
5207 struct ieee80211vap *vap;
5208 int error;
5209
5210 if (ic->ic_nrunning > 0) {
5211 error = iwn_init(sc);
5212
5213 switch (error) {
5214 case 0:
5215 ieee80211_start_all(ic);
5216 break;
5217 case 1:
5218 /* radio is disabled via RFkill switch */
5219 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task);
5220 break;
5221 default:
5222 vap = TAILQ_FIRST(&ic->ic_vaps);
5223 if (vap != NULL)
5224 ieee80211_stop(vap);
5225 break;
5226 }
5227 } else
5228 iwn_stop(sc);
5229 }
5230
5231 /*
5232 * Send a command to the firmware.
5233 */
5234 static int
iwn_cmd(struct iwn_softc * sc,int code,const void * buf,int size,int async)5235 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async)
5236 {
5237 struct iwn_tx_ring *ring;
5238 struct iwn_tx_desc *desc;
5239 struct iwn_tx_data *data;
5240 struct iwn_tx_cmd *cmd;
5241 struct mbuf *m;
5242 bus_addr_t paddr;
5243 int totlen, error;
5244 int cmd_queue_num;
5245
5246 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5247
5248 if (async == 0)
5249 IWN_LOCK_ASSERT(sc);
5250
5251 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT)
5252 cmd_queue_num = IWN_PAN_CMD_QUEUE;
5253 else
5254 cmd_queue_num = IWN_CMD_QUEUE_NUM;
5255
5256 ring = &sc->txq[cmd_queue_num];
5257 desc = &ring->desc[ring->cur];
5258 data = &ring->data[ring->cur];
5259 totlen = 4 + size;
5260
5261 if (size > sizeof cmd->data) {
5262 /* Command is too large to fit in a descriptor. */
5263 if (totlen > MCLBYTES)
5264 return EINVAL;
5265 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE);
5266 if (m == NULL)
5267 return ENOMEM;
5268 cmd = mtod(m, struct iwn_tx_cmd *);
5269 error = bus_dmamap_load(ring->data_dmat, data->map, cmd,
5270 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
5271 if (error != 0) {
5272 m_freem(m);
5273 return error;
5274 }
5275 data->m = m;
5276 } else {
5277 cmd = &ring->cmd[ring->cur];
5278 paddr = data->cmd_paddr;
5279 }
5280
5281 cmd->code = code;
5282 cmd->flags = 0;
5283 cmd->qid = ring->qid;
5284 cmd->idx = ring->cur;
5285 memcpy(cmd->data, buf, size);
5286
5287 desc->nsegs = 1;
5288 desc->segs[0].addr = htole32(IWN_LOADDR(paddr));
5289 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4);
5290
5291 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n",
5292 __func__, iwn_intr_str(cmd->code), cmd->code,
5293 cmd->flags, cmd->qid, cmd->idx);
5294
5295 if (size > sizeof cmd->data) {
5296 bus_dmamap_sync(ring->data_dmat, data->map,
5297 BUS_DMASYNC_PREWRITE);
5298 } else {
5299 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map,
5300 BUS_DMASYNC_PREWRITE);
5301 }
5302 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
5303 BUS_DMASYNC_PREWRITE);
5304
5305 /* Kick command ring. */
5306 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
5307 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
5308
5309 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5310
5311 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz);
5312 }
5313
5314 static int
iwn4965_add_node(struct iwn_softc * sc,struct iwn_node_info * node,int async)5315 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
5316 {
5317 struct iwn4965_node_info hnode;
5318 caddr_t src, dst;
5319
5320 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5321
5322 /*
5323 * We use the node structure for 5000 Series internally (it is
5324 * a superset of the one for 4965AGN). We thus copy the common
5325 * fields before sending the command.
5326 */
5327 src = (caddr_t)node;
5328 dst = (caddr_t)&hnode;
5329 memcpy(dst, src, 48);
5330 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */
5331 memcpy(dst + 48, src + 72, 20);
5332 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async);
5333 }
5334
5335 static int
iwn5000_add_node(struct iwn_softc * sc,struct iwn_node_info * node,int async)5336 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
5337 {
5338
5339 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5340
5341 /* Direct mapping. */
5342 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async);
5343 }
5344
5345 static int
iwn_set_link_quality(struct iwn_softc * sc,struct ieee80211_node * ni)5346 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni)
5347 {
5348 struct iwn_node *wn = (void *)ni;
5349 struct ieee80211_rateset *rs;
5350 struct iwn_cmd_link_quality linkq;
5351 int i, rate, txrate;
5352 int is_11n;
5353
5354 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5355
5356 memset(&linkq, 0, sizeof linkq);
5357 linkq.id = wn->id;
5358 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc);
5359 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc);
5360
5361 linkq.ampdu_max = 32; /* XXX negotiated? */
5362 linkq.ampdu_threshold = 3;
5363 linkq.ampdu_limit = htole16(4000); /* 4ms */
5364
5365 DPRINTF(sc, IWN_DEBUG_XMIT,
5366 "%s: 1stream antenna=0x%02x, 2stream antenna=0x%02x, ntxstreams=%d\n",
5367 __func__,
5368 linkq.antmsk_1stream,
5369 linkq.antmsk_2stream,
5370 sc->ntxchains);
5371
5372 /*
5373 * Are we using 11n rates? Ensure the channel is
5374 * 11n _and_ we have some 11n rates, or don't
5375 * try.
5376 */
5377 if (ieee80211_ht_check_tx_ht(ni)) {
5378 rs = (struct ieee80211_rateset *) &ni->ni_htrates;
5379 is_11n = 1;
5380 } else {
5381 rs = &ni->ni_rates;
5382 is_11n = 0;
5383 }
5384
5385 /* Start at highest available bit-rate. */
5386 /*
5387 * XXX this is all very dirty!
5388 */
5389 if (is_11n)
5390 txrate = ni->ni_htrates.rs_nrates - 1;
5391 else
5392 txrate = rs->rs_nrates - 1;
5393 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) {
5394 uint32_t plcp;
5395
5396 /*
5397 * XXX TODO: ensure the last two slots are the two lowest
5398 * rate entries, just for now.
5399 */
5400 if (i == 14 || i == 15)
5401 txrate = 0;
5402
5403 if (is_11n)
5404 rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate];
5405 else
5406 rate = IEEE80211_RV(rs->rs_rates[txrate]);
5407
5408 /* Do rate -> PLCP config mapping */
5409 plcp = iwn_rate_to_plcp(sc, ni, rate);
5410 linkq.retry[i] = plcp;
5411 DPRINTF(sc, IWN_DEBUG_XMIT,
5412 "%s: i=%d, txrate=%d, rate=0x%02x, plcp=0x%08x\n",
5413 __func__,
5414 i,
5415 txrate,
5416 rate,
5417 le32toh(plcp));
5418
5419 /*
5420 * The mimo field is an index into the table which
5421 * indicates the first index where it and subsequent entries
5422 * will not be using MIMO.
5423 *
5424 * Since we're filling linkq from 0..15 and we're filling
5425 * from the highest MCS rates to the lowest rates, if we
5426 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie,
5427 * the next entry.) That way if the next entry is a non-MIMO
5428 * entry, we're already pointing at it.
5429 */
5430 if ((le32toh(plcp) & IWN_RFLAG_MCS) &&
5431 IEEE80211_RV(le32toh(plcp)) > 7)
5432 linkq.mimo = i + 1;
5433
5434 /* Next retry at immediate lower bit-rate. */
5435 if (txrate > 0)
5436 txrate--;
5437 }
5438 /*
5439 * If we reached the end of the list and indeed we hit
5440 * all MIMO rates (eg 5300 doing MCS23-15) then yes,
5441 * set mimo to 15. Setting it to 16 panics the firmware.
5442 */
5443 if (linkq.mimo > 15)
5444 linkq.mimo = 15;
5445
5446 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: mimo = %d\n", __func__, linkq.mimo);
5447
5448 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5449
5450 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1);
5451 }
5452
5453 /*
5454 * Broadcast node is used to send group-addressed and management frames.
5455 */
5456 static int
iwn_add_broadcast_node(struct iwn_softc * sc,int async)5457 iwn_add_broadcast_node(struct iwn_softc *sc, int async)
5458 {
5459 struct iwn_ops *ops = &sc->ops;
5460 struct ieee80211com *ic = &sc->sc_ic;
5461 struct iwn_node_info node;
5462 struct iwn_cmd_link_quality linkq;
5463 uint8_t txant;
5464 int i, error;
5465
5466 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5467
5468 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
5469
5470 memset(&node, 0, sizeof node);
5471 IEEE80211_ADDR_COPY(node.macaddr, ieee80211broadcastaddr);
5472 node.id = sc->broadcast_id;
5473 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__);
5474 if ((error = ops->add_node(sc, &node, async)) != 0)
5475 return error;
5476
5477 /* Use the first valid TX antenna. */
5478 txant = IWN_LSB(sc->txchainmask);
5479
5480 memset(&linkq, 0, sizeof linkq);
5481 linkq.id = sc->broadcast_id;
5482 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc);
5483 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc);
5484 linkq.ampdu_max = 64;
5485 linkq.ampdu_threshold = 3;
5486 linkq.ampdu_limit = htole16(4000); /* 4ms */
5487
5488 /* Use lowest mandatory bit-rate. */
5489 /* XXX rate table lookup? */
5490 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
5491 linkq.retry[0] = htole32(0xd);
5492 else
5493 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK);
5494 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant));
5495 /* Use same bit-rate for all TX retries. */
5496 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) {
5497 linkq.retry[i] = linkq.retry[0];
5498 }
5499
5500 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5501
5502 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async);
5503 }
5504
5505 static int
iwn_updateedca(struct ieee80211com * ic)5506 iwn_updateedca(struct ieee80211com *ic)
5507 {
5508 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */
5509 struct iwn_softc *sc = ic->ic_softc;
5510 struct iwn_edca_params cmd;
5511 struct chanAccParams chp;
5512 int aci;
5513
5514 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5515
5516 ieee80211_wme_ic_getparams(ic, &chp);
5517
5518 memset(&cmd, 0, sizeof cmd);
5519 cmd.flags = htole32(IWN_EDCA_UPDATE);
5520
5521 IEEE80211_LOCK(ic);
5522 for (aci = 0; aci < WME_NUM_AC; aci++) {
5523 const struct wmeParams *ac = &chp.cap_wmeParams[aci];
5524 cmd.ac[aci].aifsn = ac->wmep_aifsn;
5525 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin));
5526 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax));
5527 cmd.ac[aci].txoplimit =
5528 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit));
5529 }
5530 IEEE80211_UNLOCK(ic);
5531
5532 IWN_LOCK(sc);
5533 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1);
5534 IWN_UNLOCK(sc);
5535
5536 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5537
5538 return 0;
5539 #undef IWN_EXP2
5540 }
5541
5542 static void
iwn_set_promisc(struct iwn_softc * sc)5543 iwn_set_promisc(struct iwn_softc *sc)
5544 {
5545 struct ieee80211com *ic = &sc->sc_ic;
5546 uint32_t promisc_filter;
5547
5548 promisc_filter = IWN_FILTER_CTL | IWN_FILTER_PROMISC;
5549 if (ic->ic_promisc > 0 || ic->ic_opmode == IEEE80211_M_MONITOR)
5550 sc->rxon->filter |= htole32(promisc_filter);
5551 else
5552 sc->rxon->filter &= ~htole32(promisc_filter);
5553 }
5554
5555 static void
iwn_update_promisc(struct ieee80211com * ic)5556 iwn_update_promisc(struct ieee80211com *ic)
5557 {
5558 struct iwn_softc *sc = ic->ic_softc;
5559 int error;
5560
5561 if (ic->ic_opmode == IEEE80211_M_MONITOR)
5562 return; /* nothing to do */
5563
5564 IWN_LOCK(sc);
5565 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) {
5566 IWN_UNLOCK(sc);
5567 return;
5568 }
5569
5570 iwn_set_promisc(sc);
5571 if ((error = iwn_send_rxon(sc, 1, 1)) != 0) {
5572 device_printf(sc->sc_dev,
5573 "%s: could not send RXON, error %d\n",
5574 __func__, error);
5575 }
5576 IWN_UNLOCK(sc);
5577 }
5578
5579 static void
iwn_update_mcast(struct ieee80211com * ic)5580 iwn_update_mcast(struct ieee80211com *ic)
5581 {
5582 /* Ignore */
5583 }
5584
5585 static void
iwn_set_led(struct iwn_softc * sc,uint8_t which,uint8_t off,uint8_t on)5586 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on)
5587 {
5588 struct iwn_cmd_led led;
5589
5590 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5591
5592 #if 0
5593 /* XXX don't set LEDs during scan? */
5594 if (sc->sc_is_scanning)
5595 return;
5596 #endif
5597
5598 /* Clear microcode LED ownership. */
5599 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL);
5600
5601 led.which = which;
5602 led.unit = htole32(10000); /* on/off in unit of 100ms */
5603 led.off = off;
5604 led.on = on;
5605 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1);
5606 }
5607
5608 /*
5609 * Set the critical temperature at which the firmware will stop the radio
5610 * and notify us.
5611 */
5612 static int
iwn_set_critical_temp(struct iwn_softc * sc)5613 iwn_set_critical_temp(struct iwn_softc *sc)
5614 {
5615 struct iwn_critical_temp crit;
5616 int32_t temp;
5617
5618 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5619
5620 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF);
5621
5622 if (sc->hw_type == IWN_HW_REV_TYPE_5150)
5623 temp = (IWN_CTOK(110) - sc->temp_off) * -5;
5624 else if (sc->hw_type == IWN_HW_REV_TYPE_4965)
5625 temp = IWN_CTOK(110);
5626 else
5627 temp = 110;
5628 memset(&crit, 0, sizeof crit);
5629 crit.tempR = htole32(temp);
5630 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp);
5631 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0);
5632 }
5633
5634 static int
iwn_set_timing(struct iwn_softc * sc,struct ieee80211_node * ni)5635 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni)
5636 {
5637 struct iwn_cmd_timing cmd;
5638 uint64_t val, mod;
5639
5640 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5641
5642 memset(&cmd, 0, sizeof cmd);
5643 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t));
5644 cmd.bintval = htole16(ni->ni_intval);
5645 cmd.lintval = htole16(10);
5646
5647 /* Compute remaining time until next beacon. */
5648 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU;
5649 mod = le64toh(cmd.tstamp) % val;
5650 cmd.binitval = htole32((uint32_t)(val - mod));
5651
5652 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n",
5653 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod));
5654
5655 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1);
5656 }
5657
5658 static void
iwn4965_power_calibration(struct iwn_softc * sc,int temp)5659 iwn4965_power_calibration(struct iwn_softc *sc, int temp)
5660 {
5661
5662 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5663
5664 /* Adjust TX power if need be (delta >= 3 degC). */
5665 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
5666 __func__, sc->temp, temp);
5667 if (abs(temp - sc->temp) >= 3) {
5668 /* Record temperature of last calibration. */
5669 sc->temp = temp;
5670 (void)iwn4965_set_txpower(sc, 1);
5671 }
5672 }
5673
5674 /*
5675 * Set TX power for current channel (each rate has its own power settings).
5676 * This function takes into account the regulatory information from EEPROM,
5677 * the current temperature and the current voltage.
5678 */
5679 static int
iwn4965_set_txpower(struct iwn_softc * sc,int async)5680 iwn4965_set_txpower(struct iwn_softc *sc, int async)
5681 {
5682 /* Fixed-point arithmetic division using a n-bit fractional part. */
5683 #define fdivround(a, b, n) \
5684 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n))
5685 /* Linear interpolation. */
5686 #define interpolate(x, x1, y1, x2, y2, n) \
5687 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n))
5688
5689 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 };
5690 struct iwn_ucode_info *uc = &sc->ucode_info;
5691 struct iwn4965_cmd_txpower cmd;
5692 struct iwn4965_eeprom_chan_samples *chans;
5693 const uint8_t *rf_gain, *dsp_gain;
5694 int32_t vdiff, tdiff;
5695 int i, is_chan_5ghz, c, grp, maxpwr;
5696 uint8_t chan;
5697
5698 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
5699 /* Retrieve current channel from last RXON. */
5700 chan = sc->rxon->chan;
5701 is_chan_5ghz = (sc->rxon->flags & htole32(IWN_RXON_24GHZ)) == 0;
5702 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n",
5703 chan);
5704
5705 memset(&cmd, 0, sizeof cmd);
5706 cmd.band = is_chan_5ghz ? 0 : 1;
5707 cmd.chan = chan;
5708
5709 if (is_chan_5ghz) {
5710 maxpwr = sc->maxpwr5GHz;
5711 rf_gain = iwn4965_rf_gain_5ghz;
5712 dsp_gain = iwn4965_dsp_gain_5ghz;
5713 } else {
5714 maxpwr = sc->maxpwr2GHz;
5715 rf_gain = iwn4965_rf_gain_2ghz;
5716 dsp_gain = iwn4965_dsp_gain_2ghz;
5717 }
5718
5719 /* Compute voltage compensation. */
5720 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7;
5721 if (vdiff > 0)
5722 vdiff *= 2;
5723 if (abs(vdiff) > 2)
5724 vdiff = 0;
5725 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5726 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n",
5727 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage);
5728
5729 /* Get channel attenuation group. */
5730 if (chan <= 20) /* 1-20 */
5731 grp = 4;
5732 else if (chan <= 43) /* 34-43 */
5733 grp = 0;
5734 else if (chan <= 70) /* 44-70 */
5735 grp = 1;
5736 else if (chan <= 124) /* 71-124 */
5737 grp = 2;
5738 else /* 125-200 */
5739 grp = 3;
5740 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5741 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp);
5742
5743 /* Get channel sub-band. */
5744 for (i = 0; i < IWN_NBANDS; i++)
5745 if (sc->bands[i].lo != 0 &&
5746 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi)
5747 break;
5748 if (i == IWN_NBANDS) /* Can't happen in real-life. */
5749 return EINVAL;
5750 chans = sc->bands[i].chans;
5751 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5752 "%s: chan %d sub-band=%d\n", __func__, chan, i);
5753
5754 for (c = 0; c < 2; c++) {
5755 uint8_t power, gain, temp;
5756 int maxchpwr, pwr, ridx, idx;
5757
5758 power = interpolate(chan,
5759 chans[0].num, chans[0].samples[c][1].power,
5760 chans[1].num, chans[1].samples[c][1].power, 1);
5761 gain = interpolate(chan,
5762 chans[0].num, chans[0].samples[c][1].gain,
5763 chans[1].num, chans[1].samples[c][1].gain, 1);
5764 temp = interpolate(chan,
5765 chans[0].num, chans[0].samples[c][1].temp,
5766 chans[1].num, chans[1].samples[c][1].temp, 1);
5767 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5768 "%s: Tx chain %d: power=%d gain=%d temp=%d\n",
5769 __func__, c, power, gain, temp);
5770
5771 /* Compute temperature compensation. */
5772 tdiff = ((sc->temp - temp) * 2) / tdiv[grp];
5773 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5774 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n",
5775 __func__, tdiff, sc->temp, temp);
5776
5777 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) {
5778 /* Convert dBm to half-dBm. */
5779 maxchpwr = sc->maxpwr[chan] * 2;
5780 if ((ridx / 8) & 1)
5781 maxchpwr -= 6; /* MIMO 2T: -3dB */
5782
5783 pwr = maxpwr;
5784
5785 /* Adjust TX power based on rate. */
5786 if ((ridx % 8) == 5)
5787 pwr -= 15; /* OFDM48: -7.5dB */
5788 else if ((ridx % 8) == 6)
5789 pwr -= 17; /* OFDM54: -8.5dB */
5790 else if ((ridx % 8) == 7)
5791 pwr -= 20; /* OFDM60: -10dB */
5792 else
5793 pwr -= 10; /* Others: -5dB */
5794
5795 /* Do not exceed channel max TX power. */
5796 if (pwr > maxchpwr)
5797 pwr = maxchpwr;
5798
5799 idx = gain - (pwr - power) - tdiff - vdiff;
5800 if ((ridx / 8) & 1) /* MIMO */
5801 idx += (int32_t)le32toh(uc->atten[grp][c]);
5802
5803 if (cmd.band == 0)
5804 idx += 9; /* 5GHz */
5805 if (ridx == IWN_RIDX_MAX)
5806 idx += 5; /* CCK */
5807
5808 /* Make sure idx stays in a valid range. */
5809 if (idx < 0)
5810 idx = 0;
5811 else if (idx > IWN4965_MAX_PWR_INDEX)
5812 idx = IWN4965_MAX_PWR_INDEX;
5813
5814 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5815 "%s: Tx chain %d, rate idx %d: power=%d\n",
5816 __func__, c, ridx, idx);
5817 cmd.power[ridx].rf_gain[c] = rf_gain[idx];
5818 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx];
5819 }
5820 }
5821
5822 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
5823 "%s: set tx power for chan %d\n", __func__, chan);
5824 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async);
5825
5826 #undef interpolate
5827 #undef fdivround
5828 }
5829
5830 static int
iwn5000_set_txpower(struct iwn_softc * sc,int async)5831 iwn5000_set_txpower(struct iwn_softc *sc, int async)
5832 {
5833 struct iwn5000_cmd_txpower cmd;
5834 int cmdid;
5835
5836 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5837
5838 /*
5839 * TX power calibration is handled automatically by the firmware
5840 * for 5000 Series.
5841 */
5842 memset(&cmd, 0, sizeof cmd);
5843 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */
5844 cmd.flags = IWN5000_TXPOWER_NO_CLOSED;
5845 cmd.srv_limit = IWN5000_TXPOWER_AUTO;
5846 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT,
5847 "%s: setting TX power; rev=%d\n",
5848 __func__,
5849 IWN_UCODE_API(sc->ucode_rev));
5850 if (IWN_UCODE_API(sc->ucode_rev) == 1)
5851 cmdid = IWN_CMD_TXPOWER_DBM_V1;
5852 else
5853 cmdid = IWN_CMD_TXPOWER_DBM;
5854 return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async);
5855 }
5856
5857 /*
5858 * Retrieve the maximum RSSI (in dBm) among receivers.
5859 */
5860 static int
iwn4965_get_rssi(struct iwn_softc * sc,struct iwn_rx_stat * stat)5861 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
5862 {
5863 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf;
5864 uint8_t mask, agc;
5865 int rssi;
5866
5867 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5868
5869 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC;
5870 agc = (le16toh(phy->agc) >> 7) & 0x7f;
5871
5872 rssi = 0;
5873 if (mask & IWN_ANT_A)
5874 rssi = MAX(rssi, phy->rssi[0]);
5875 if (mask & IWN_ANT_B)
5876 rssi = MAX(rssi, phy->rssi[2]);
5877 if (mask & IWN_ANT_C)
5878 rssi = MAX(rssi, phy->rssi[4]);
5879
5880 DPRINTF(sc, IWN_DEBUG_RECV,
5881 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc,
5882 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4],
5883 rssi - agc - IWN_RSSI_TO_DBM);
5884 return rssi - agc - IWN_RSSI_TO_DBM;
5885 }
5886
5887 static int
iwn5000_get_rssi(struct iwn_softc * sc,struct iwn_rx_stat * stat)5888 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
5889 {
5890 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf;
5891 uint8_t agc;
5892 int rssi;
5893
5894 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5895
5896 agc = (le32toh(phy->agc) >> 9) & 0x7f;
5897
5898 rssi = MAX(le16toh(phy->rssi[0]) & 0xff,
5899 le16toh(phy->rssi[1]) & 0xff);
5900 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi);
5901
5902 DPRINTF(sc, IWN_DEBUG_RECV,
5903 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc,
5904 phy->rssi[0], phy->rssi[1], phy->rssi[2],
5905 rssi - agc - IWN_RSSI_TO_DBM);
5906 return rssi - agc - IWN_RSSI_TO_DBM;
5907 }
5908
5909 /*
5910 * Retrieve the average noise (in dBm) among receivers.
5911 */
5912 static int
iwn_get_noise(const struct iwn_rx_general_stats * stats)5913 iwn_get_noise(const struct iwn_rx_general_stats *stats)
5914 {
5915 int i, total, nbant, noise;
5916
5917 total = nbant = 0;
5918 for (i = 0; i < 3; i++) {
5919 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0)
5920 continue;
5921 total += noise;
5922 nbant++;
5923 }
5924 /* There should be at least one antenna but check anyway. */
5925 return (nbant == 0) ? -127 : (total / nbant) - 107;
5926 }
5927
5928 /*
5929 * Compute temperature (in degC) from last received statistics.
5930 */
5931 static int
iwn4965_get_temperature(struct iwn_softc * sc)5932 iwn4965_get_temperature(struct iwn_softc *sc)
5933 {
5934 struct iwn_ucode_info *uc = &sc->ucode_info;
5935 int32_t r1, r2, r3, r4, temp;
5936
5937 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5938
5939 r1 = le32toh(uc->temp[0].chan20MHz);
5940 r2 = le32toh(uc->temp[1].chan20MHz);
5941 r3 = le32toh(uc->temp[2].chan20MHz);
5942 r4 = le32toh(sc->rawtemp);
5943
5944 if (r1 == r3) /* Prevents division by 0 (should not happen). */
5945 return 0;
5946
5947 /* Sign-extend 23-bit R4 value to 32-bit. */
5948 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000;
5949 /* Compute temperature in Kelvin. */
5950 temp = (259 * (r4 - r2)) / (r3 - r1);
5951 temp = (temp * 97) / 100 + 8;
5952
5953 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp,
5954 IWN_KTOC(temp));
5955 return IWN_KTOC(temp);
5956 }
5957
5958 static int
iwn5000_get_temperature(struct iwn_softc * sc)5959 iwn5000_get_temperature(struct iwn_softc *sc)
5960 {
5961 int32_t temp;
5962
5963 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5964
5965 /*
5966 * Temperature is not used by the driver for 5000 Series because
5967 * TX power calibration is handled by firmware.
5968 */
5969 temp = le32toh(sc->rawtemp);
5970 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
5971 temp = (temp / -5) + sc->temp_off;
5972 temp = IWN_KTOC(temp);
5973 }
5974 return temp;
5975 }
5976
5977 /*
5978 * Initialize sensitivity calibration state machine.
5979 */
5980 static int
iwn_init_sensitivity(struct iwn_softc * sc)5981 iwn_init_sensitivity(struct iwn_softc *sc)
5982 {
5983 struct iwn_ops *ops = &sc->ops;
5984 struct iwn_calib_state *calib = &sc->calib;
5985 uint32_t flags;
5986 int error;
5987
5988 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5989
5990 /* Reset calibration state machine. */
5991 memset(calib, 0, sizeof (*calib));
5992 calib->state = IWN_CALIB_STATE_INIT;
5993 calib->cck_state = IWN_CCK_STATE_HIFA;
5994 /* Set initial correlation values. */
5995 calib->ofdm_x1 = sc->limits->min_ofdm_x1;
5996 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1;
5997 calib->ofdm_x4 = sc->limits->min_ofdm_x4;
5998 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4;
5999 calib->cck_x4 = 125;
6000 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4;
6001 calib->energy_cck = sc->limits->energy_cck;
6002
6003 /* Write initial sensitivity. */
6004 if ((error = iwn_send_sensitivity(sc)) != 0)
6005 return error;
6006
6007 /* Write initial gains. */
6008 if ((error = ops->init_gains(sc)) != 0)
6009 return error;
6010
6011 /* Request statistics at each beacon interval. */
6012 flags = 0;
6013 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n",
6014 __func__);
6015 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1);
6016 }
6017
6018 /*
6019 * Collect noise and RSSI statistics for the first 20 beacons received
6020 * after association and use them to determine connected antennas and
6021 * to set differential gains.
6022 */
6023 static void
iwn_collect_noise(struct iwn_softc * sc,const struct iwn_rx_general_stats * stats)6024 iwn_collect_noise(struct iwn_softc *sc,
6025 const struct iwn_rx_general_stats *stats)
6026 {
6027 struct iwn_ops *ops = &sc->ops;
6028 struct iwn_calib_state *calib = &sc->calib;
6029 struct ieee80211com *ic = &sc->sc_ic;
6030 uint32_t val;
6031 int i;
6032
6033 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
6034
6035 /* Accumulate RSSI and noise for all 3 antennas. */
6036 for (i = 0; i < 3; i++) {
6037 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff;
6038 calib->noise[i] += le32toh(stats->noise[i]) & 0xff;
6039 }
6040 /* NB: We update differential gains only once after 20 beacons. */
6041 if (++calib->nbeacons < 20)
6042 return;
6043
6044 /* Determine highest average RSSI. */
6045 val = MAX(calib->rssi[0], calib->rssi[1]);
6046 val = MAX(calib->rssi[2], val);
6047
6048 /* Determine which antennas are connected. */
6049 sc->chainmask = sc->rxchainmask;
6050 for (i = 0; i < 3; i++)
6051 if (val - calib->rssi[i] > 15 * 20)
6052 sc->chainmask &= ~(1 << i);
6053 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT,
6054 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n",
6055 __func__, sc->rxchainmask, sc->chainmask);
6056
6057 /* If none of the TX antennas are connected, keep at least one. */
6058 if ((sc->chainmask & sc->txchainmask) == 0)
6059 sc->chainmask |= IWN_LSB(sc->txchainmask);
6060
6061 (void)ops->set_gains(sc);
6062 calib->state = IWN_CALIB_STATE_RUN;
6063
6064 #ifdef notyet
6065 /* XXX Disable RX chains with no antennas connected. */
6066 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask));
6067 if (sc->sc_is_scanning)
6068 device_printf(sc->sc_dev,
6069 "%s: is_scanning set, before RXON\n",
6070 __func__);
6071 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1);
6072 #endif
6073
6074 /* Enable power-saving mode if requested by user. */
6075 if (ic->ic_flags & IEEE80211_F_PMGTON)
6076 (void)iwn_set_pslevel(sc, 0, 3, 1);
6077
6078 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
6079
6080 }
6081
6082 static int
iwn4965_init_gains(struct iwn_softc * sc)6083 iwn4965_init_gains(struct iwn_softc *sc)
6084 {
6085 struct iwn_phy_calib_gain cmd;
6086
6087 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
6088
6089 memset(&cmd, 0, sizeof cmd);
6090 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
6091 /* Differential gains initially set to 0 for all 3 antennas. */
6092 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6093 "%s: setting initial differential gains\n", __func__);
6094 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
6095 }
6096
6097 static int
iwn5000_init_gains(struct iwn_softc * sc)6098 iwn5000_init_gains(struct iwn_softc *sc)
6099 {
6100 struct iwn_phy_calib cmd;
6101
6102 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
6103
6104 memset(&cmd, 0, sizeof cmd);
6105 cmd.code = sc->reset_noise_gain;
6106 cmd.ngroups = 1;
6107 cmd.isvalid = 1;
6108 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6109 "%s: setting initial differential gains\n", __func__);
6110 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
6111 }
6112
6113 static int
iwn4965_set_gains(struct iwn_softc * sc)6114 iwn4965_set_gains(struct iwn_softc *sc)
6115 {
6116 struct iwn_calib_state *calib = &sc->calib;
6117 struct iwn_phy_calib_gain cmd;
6118 int i, delta, noise;
6119
6120 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
6121
6122 /* Get minimal noise among connected antennas. */
6123 noise = INT_MAX; /* NB: There's at least one antenna. */
6124 for (i = 0; i < 3; i++)
6125 if (sc->chainmask & (1 << i))
6126 noise = MIN(calib->noise[i], noise);
6127
6128 memset(&cmd, 0, sizeof cmd);
6129 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
6130 /* Set differential gains for connected antennas. */
6131 for (i = 0; i < 3; i++) {
6132 if (sc->chainmask & (1 << i)) {
6133 /* Compute attenuation (in unit of 1.5dB). */
6134 delta = (noise - (int32_t)calib->noise[i]) / 30;
6135 /* NB: delta <= 0 */
6136 /* Limit to [-4.5dB,0]. */
6137 cmd.gain[i] = MIN(abs(delta), 3);
6138 if (delta < 0)
6139 cmd.gain[i] |= 1 << 2; /* sign bit */
6140 }
6141 }
6142 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6143 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n",
6144 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask);
6145 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
6146 }
6147
6148 static int
iwn5000_set_gains(struct iwn_softc * sc)6149 iwn5000_set_gains(struct iwn_softc *sc)
6150 {
6151 struct iwn_calib_state *calib = &sc->calib;
6152 struct iwn_phy_calib_gain cmd;
6153 int i, ant, div, delta;
6154
6155 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
6156
6157 /* We collected 20 beacons and !=6050 need a 1.5 factor. */
6158 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;
6159
6160 memset(&cmd, 0, sizeof cmd);
6161 cmd.code = sc->noise_gain;
6162 cmd.ngroups = 1;
6163 cmd.isvalid = 1;
6164 /* Get first available RX antenna as referential. */
6165 ant = IWN_LSB(sc->rxchainmask);
6166 /* Set differential gains for other antennas. */
6167 for (i = ant + 1; i < 3; i++) {
6168 if (sc->chainmask & (1 << i)) {
6169 /* The delta is relative to antenna "ant". */
6170 delta = ((int32_t)calib->noise[ant] -
6171 (int32_t)calib->noise[i]) / div;
6172 /* Limit to [-4.5dB,+4.5dB]. */
6173 cmd.gain[i - 1] = MIN(abs(delta), 3);
6174 if (delta < 0)
6175 cmd.gain[i - 1] |= 1 << 2; /* sign bit */
6176 }
6177 }
6178 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT,
6179 "setting differential gains Ant B/C: %x/%x (%x)\n",
6180 cmd.gain[0], cmd.gain[1], sc->chainmask);
6181 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
6182 }
6183
6184 /*
6185 * Tune RF RX sensitivity based on the number of false alarms detected
6186 * during the last beacon period.
6187 */
6188 static void
iwn_tune_sensitivity(struct iwn_softc * sc,const struct iwn_rx_stats * stats)6189 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats)
6190 {
6191 #define inc(val, inc, max) \
6192 if ((val) < (max)) { \
6193 if ((val) < (max) - (inc)) \
6194 (val) += (inc); \
6195 else \
6196 (val) = (max); \
6197 needs_update = 1; \
6198 }
6199 #define dec(val, dec, min) \
6200 if ((val) > (min)) { \
6201 if ((val) > (min) + (dec)) \
6202 (val) -= (dec); \
6203 else \
6204 (val) = (min); \
6205 needs_update = 1; \
6206 }
6207
6208 const struct iwn_sensitivity_limits *limits = sc->limits;
6209 struct iwn_calib_state *calib = &sc->calib;
6210 uint32_t val, rxena, fa;
6211 uint32_t energy[3], energy_min;
6212 uint8_t noise[3], noise_ref;
6213 int i, needs_update = 0;
6214
6215 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
6216
6217 /* Check that we've been enabled long enough. */
6218 if ((rxena = le32toh(stats->general.load)) == 0){
6219 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__);
6220 return;
6221 }
6222
6223 /* Compute number of false alarms since last call for OFDM. */
6224 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm;
6225 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm;
6226 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */
6227
6228 if (fa > 50 * rxena) {
6229 /* High false alarm count, decrease sensitivity. */
6230 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6231 "%s: OFDM high false alarm count: %u\n", __func__, fa);
6232 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1);
6233 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1);
6234 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4);
6235 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4);
6236
6237 } else if (fa < 5 * rxena) {
6238 /* Low false alarm count, increase sensitivity. */
6239 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6240 "%s: OFDM low false alarm count: %u\n", __func__, fa);
6241 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1);
6242 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1);
6243 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4);
6244 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4);
6245 }
6246
6247 /* Compute maximum noise among 3 receivers. */
6248 for (i = 0; i < 3; i++)
6249 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff;
6250 val = MAX(noise[0], noise[1]);
6251 val = MAX(noise[2], val);
6252 /* Insert it into our samples table. */
6253 calib->noise_samples[calib->cur_noise_sample] = val;
6254 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20;
6255
6256 /* Compute maximum noise among last 20 samples. */
6257 noise_ref = calib->noise_samples[0];
6258 for (i = 1; i < 20; i++)
6259 noise_ref = MAX(noise_ref, calib->noise_samples[i]);
6260
6261 /* Compute maximum energy among 3 receivers. */
6262 for (i = 0; i < 3; i++)
6263 energy[i] = le32toh(stats->general.energy[i]);
6264 val = MIN(energy[0], energy[1]);
6265 val = MIN(energy[2], val);
6266 /* Insert it into our samples table. */
6267 calib->energy_samples[calib->cur_energy_sample] = val;
6268 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10;
6269
6270 /* Compute minimum energy among last 10 samples. */
6271 energy_min = calib->energy_samples[0];
6272 for (i = 1; i < 10; i++)
6273 energy_min = MAX(energy_min, calib->energy_samples[i]);
6274 energy_min += 6;
6275
6276 /* Compute number of false alarms since last call for CCK. */
6277 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck;
6278 fa += le32toh(stats->cck.fa) - calib->fa_cck;
6279 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */
6280
6281 if (fa > 50 * rxena) {
6282 /* High false alarm count, decrease sensitivity. */
6283 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6284 "%s: CCK high false alarm count: %u\n", __func__, fa);
6285 calib->cck_state = IWN_CCK_STATE_HIFA;
6286 calib->low_fa = 0;
6287
6288 if (calib->cck_x4 > 160) {
6289 calib->noise_ref = noise_ref;
6290 if (calib->energy_cck > 2)
6291 dec(calib->energy_cck, 2, energy_min);
6292 }
6293 if (calib->cck_x4 < 160) {
6294 calib->cck_x4 = 161;
6295 needs_update = 1;
6296 } else
6297 inc(calib->cck_x4, 3, limits->max_cck_x4);
6298
6299 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4);
6300
6301 } else if (fa < 5 * rxena) {
6302 /* Low false alarm count, increase sensitivity. */
6303 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6304 "%s: CCK low false alarm count: %u\n", __func__, fa);
6305 calib->cck_state = IWN_CCK_STATE_LOFA;
6306 calib->low_fa++;
6307
6308 if (calib->cck_state != IWN_CCK_STATE_INIT &&
6309 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 ||
6310 calib->low_fa > 100)) {
6311 inc(calib->energy_cck, 2, limits->min_energy_cck);
6312 dec(calib->cck_x4, 3, limits->min_cck_x4);
6313 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4);
6314 }
6315 } else {
6316 /* Not worth to increase or decrease sensitivity. */
6317 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6318 "%s: CCK normal false alarm count: %u\n", __func__, fa);
6319 calib->low_fa = 0;
6320 calib->noise_ref = noise_ref;
6321
6322 if (calib->cck_state == IWN_CCK_STATE_HIFA) {
6323 /* Previous interval had many false alarms. */
6324 dec(calib->energy_cck, 8, energy_min);
6325 }
6326 calib->cck_state = IWN_CCK_STATE_INIT;
6327 }
6328
6329 if (needs_update)
6330 (void)iwn_send_sensitivity(sc);
6331
6332 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
6333
6334 #undef dec
6335 #undef inc
6336 }
6337
6338 static int
iwn_send_sensitivity(struct iwn_softc * sc)6339 iwn_send_sensitivity(struct iwn_softc *sc)
6340 {
6341 struct iwn_calib_state *calib = &sc->calib;
6342 struct iwn_enhanced_sensitivity_cmd cmd;
6343 int len;
6344
6345 memset(&cmd, 0, sizeof cmd);
6346 len = sizeof (struct iwn_sensitivity_cmd);
6347 cmd.which = IWN_SENSITIVITY_WORKTBL;
6348 /* OFDM modulation. */
6349 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1);
6350 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1);
6351 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4);
6352 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4);
6353 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm);
6354 cmd.energy_ofdm_th = htole16(62);
6355 /* CCK modulation. */
6356 cmd.corr_cck_x4 = htole16(calib->cck_x4);
6357 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4);
6358 cmd.energy_cck = htole16(calib->energy_cck);
6359 /* Barker modulation: use default values. */
6360 cmd.corr_barker = htole16(190);
6361 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc);
6362
6363 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6364 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__,
6365 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4,
6366 calib->ofdm_mrc_x4, calib->cck_x4,
6367 calib->cck_mrc_x4, calib->energy_cck);
6368
6369 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS))
6370 goto send;
6371 /* Enhanced sensitivity settings. */
6372 len = sizeof (struct iwn_enhanced_sensitivity_cmd);
6373 cmd.ofdm_det_slope_mrc = htole16(668);
6374 cmd.ofdm_det_icept_mrc = htole16(4);
6375 cmd.ofdm_det_slope = htole16(486);
6376 cmd.ofdm_det_icept = htole16(37);
6377 cmd.cck_det_slope_mrc = htole16(853);
6378 cmd.cck_det_icept_mrc = htole16(4);
6379 cmd.cck_det_slope = htole16(476);
6380 cmd.cck_det_icept = htole16(99);
6381 send:
6382 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1);
6383 }
6384
6385 /*
6386 * Look at the increase of PLCP errors over time; if it exceeds
6387 * a programmed threshold then trigger an RF retune.
6388 */
6389 static void
iwn_check_rx_recovery(struct iwn_softc * sc,struct iwn_stats * rs)6390 iwn_check_rx_recovery(struct iwn_softc *sc, struct iwn_stats *rs)
6391 {
6392 int32_t delta_ofdm, delta_ht, delta_cck;
6393 struct iwn_calib_state *calib = &sc->calib;
6394 int delta_ticks, cur_ticks;
6395 int delta_msec;
6396 int thresh;
6397
6398 /*
6399 * Calculate the difference between the current and
6400 * previous statistics.
6401 */
6402 delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck;
6403 delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm;
6404 delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht;
6405
6406 /*
6407 * Calculate the delta in time between successive statistics
6408 * messages. Yes, it can roll over; so we make sure that
6409 * this doesn't happen.
6410 *
6411 * XXX go figure out what to do about rollover
6412 * XXX go figure out what to do if ticks rolls over to -ve instead!
6413 * XXX go stab signed integer overflow undefined-ness in the face.
6414 */
6415 cur_ticks = ticks;
6416 delta_ticks = cur_ticks - sc->last_calib_ticks;
6417
6418 /*
6419 * If any are negative, then the firmware likely reset; so just
6420 * bail. We'll pick this up next time.
6421 */
6422 if (delta_cck < 0 || delta_ofdm < 0 || delta_ht < 0 || delta_ticks < 0)
6423 return;
6424
6425 /*
6426 * delta_ticks is in ticks; we need to convert it up to milliseconds
6427 * so we can do some useful math with it.
6428 */
6429 delta_msec = ticks_to_msecs(delta_ticks);
6430
6431 /*
6432 * Calculate what our threshold is given the current delta_msec.
6433 */
6434 thresh = sc->base_params->plcp_err_threshold * delta_msec;
6435
6436 DPRINTF(sc, IWN_DEBUG_STATE,
6437 "%s: time delta: %d; cck=%d, ofdm=%d, ht=%d, total=%d, thresh=%d\n",
6438 __func__,
6439 delta_msec,
6440 delta_cck,
6441 delta_ofdm,
6442 delta_ht,
6443 (delta_msec + delta_cck + delta_ofdm + delta_ht),
6444 thresh);
6445
6446 /*
6447 * If we need a retune, then schedule a single channel scan
6448 * to a channel that isn't the currently active one!
6449 *
6450 * The math from linux iwlwifi:
6451 *
6452 * if ((delta * 100 / msecs) > threshold)
6453 */
6454 if (thresh > 0 && (delta_cck + delta_ofdm + delta_ht) * 100 > thresh) {
6455 DPRINTF(sc, IWN_DEBUG_ANY,
6456 "%s: PLCP error threshold raw (%d) comparison (%d) "
6457 "over limit (%d); retune!\n",
6458 __func__,
6459 (delta_cck + delta_ofdm + delta_ht),
6460 (delta_cck + delta_ofdm + delta_ht) * 100,
6461 thresh);
6462 }
6463 }
6464
6465 /*
6466 * Set STA mode power saving level (between 0 and 5).
6467 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving.
6468 */
6469 static int
iwn_set_pslevel(struct iwn_softc * sc,int dtim,int level,int async)6470 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async)
6471 {
6472 struct iwn_pmgt_cmd cmd;
6473 const struct iwn_pmgt *pmgt;
6474 uint32_t max, skip_dtim;
6475 uint32_t reg;
6476 int i;
6477
6478 DPRINTF(sc, IWN_DEBUG_PWRSAVE,
6479 "%s: dtim=%d, level=%d, async=%d\n",
6480 __func__,
6481 dtim,
6482 level,
6483 async);
6484
6485 /* Select which PS parameters to use. */
6486 if (dtim <= 2)
6487 pmgt = &iwn_pmgt[0][level];
6488 else if (dtim <= 10)
6489 pmgt = &iwn_pmgt[1][level];
6490 else
6491 pmgt = &iwn_pmgt[2][level];
6492
6493 memset(&cmd, 0, sizeof cmd);
6494 if (level != 0) /* not CAM */
6495 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP);
6496 if (level == 5)
6497 cmd.flags |= htole16(IWN_PS_FAST_PD);
6498 /* Retrieve PCIe Active State Power Management (ASPM). */
6499 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);
6500 if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */
6501 cmd.flags |= htole16(IWN_PS_PCI_PMGT);
6502 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024);
6503 cmd.txtimeout = htole32(pmgt->txtimeout * 1024);
6504
6505 if (dtim == 0) {
6506 dtim = 1;
6507 skip_dtim = 0;
6508 } else
6509 skip_dtim = pmgt->skip_dtim;
6510 if (skip_dtim != 0) {
6511 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM);
6512 max = pmgt->intval[4];
6513 if (max == (uint32_t)-1)
6514 max = dtim * (skip_dtim + 1);
6515 else if (max > dtim)
6516 max = rounddown(max, dtim);
6517 } else
6518 max = dtim;
6519 for (i = 0; i < 5; i++)
6520 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i]));
6521
6522 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n",
6523 level);
6524 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async);
6525 }
6526
6527 static int
iwn_send_btcoex(struct iwn_softc * sc)6528 iwn_send_btcoex(struct iwn_softc *sc)
6529 {
6530 struct iwn_bluetooth cmd;
6531
6532 memset(&cmd, 0, sizeof cmd);
6533 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO;
6534 cmd.lead_time = IWN_BT_LEAD_TIME_DEF;
6535 cmd.max_kill = IWN_BT_MAX_KILL_DEF;
6536 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n",
6537 __func__);
6538 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0);
6539 }
6540
6541 static int
iwn_send_advanced_btcoex(struct iwn_softc * sc)6542 iwn_send_advanced_btcoex(struct iwn_softc *sc)
6543 {
6544 static const uint32_t btcoex_3wire[12] = {
6545 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa,
6546 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa,
6547 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000,
6548 };
6549 struct iwn6000_btcoex_config btconfig;
6550 struct iwn2000_btcoex_config btconfig2k;
6551 struct iwn_btcoex_priotable btprio;
6552 struct iwn_btcoex_prot btprot;
6553 int error, i;
6554 uint8_t flags;
6555
6556 memset(&btconfig, 0, sizeof btconfig);
6557 memset(&btconfig2k, 0, sizeof btconfig2k);
6558
6559 flags = IWN_BT_FLAG_COEX6000_MODE_3W <<
6560 IWN_BT_FLAG_COEX6000_MODE_SHIFT; // Done as is in linux kernel 3.2
6561
6562 if (sc->base_params->bt_sco_disable)
6563 flags &= ~IWN_BT_FLAG_SYNC_2_BT_DISABLE;
6564 else
6565 flags |= IWN_BT_FLAG_SYNC_2_BT_DISABLE;
6566
6567 flags |= IWN_BT_FLAG_COEX6000_CHAN_INHIBITION;
6568
6569 /* Default flags result is 145 as old value */
6570
6571 /*
6572 * Flags value has to be review. Values must change if we
6573 * which to disable it
6574 */
6575 if (sc->base_params->bt_session_2) {
6576 btconfig2k.flags = flags;
6577 btconfig2k.max_kill = 5;
6578 btconfig2k.bt3_t7_timer = 1;
6579 btconfig2k.kill_ack = htole32(0xffff0000);
6580 btconfig2k.kill_cts = htole32(0xffff0000);
6581 btconfig2k.sample_time = 2;
6582 btconfig2k.bt3_t2_timer = 0xc;
6583
6584 for (i = 0; i < 12; i++)
6585 btconfig2k.lookup_table[i] = htole32(btcoex_3wire[i]);
6586 btconfig2k.valid = htole16(0xff);
6587 btconfig2k.prio_boost = htole32(0xf0);
6588 DPRINTF(sc, IWN_DEBUG_RESET,
6589 "%s: configuring advanced bluetooth coexistence"
6590 " session 2, flags : 0x%x\n",
6591 __func__,
6592 flags);
6593 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig2k,
6594 sizeof(btconfig2k), 1);
6595 } else {
6596 btconfig.flags = flags;
6597 btconfig.max_kill = 5;
6598 btconfig.bt3_t7_timer = 1;
6599 btconfig.kill_ack = htole32(0xffff0000);
6600 btconfig.kill_cts = htole32(0xffff0000);
6601 btconfig.sample_time = 2;
6602 btconfig.bt3_t2_timer = 0xc;
6603
6604 for (i = 0; i < 12; i++)
6605 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]);
6606 btconfig.valid = htole16(0xff);
6607 btconfig.prio_boost = 0xf0;
6608 DPRINTF(sc, IWN_DEBUG_RESET,
6609 "%s: configuring advanced bluetooth coexistence,"
6610 " flags : 0x%x\n",
6611 __func__,
6612 flags);
6613 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig,
6614 sizeof(btconfig), 1);
6615 }
6616
6617 if (error != 0)
6618 return error;
6619
6620 memset(&btprio, 0, sizeof btprio);
6621 btprio.calib_init1 = 0x6;
6622 btprio.calib_init2 = 0x7;
6623 btprio.calib_periodic_low1 = 0x2;
6624 btprio.calib_periodic_low2 = 0x3;
6625 btprio.calib_periodic_high1 = 0x4;
6626 btprio.calib_periodic_high2 = 0x5;
6627 btprio.dtim = 0x6;
6628 btprio.scan52 = 0x8;
6629 btprio.scan24 = 0xa;
6630 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio),
6631 1);
6632 if (error != 0)
6633 return error;
6634
6635 /* Force BT state machine change. */
6636 memset(&btprot, 0, sizeof btprot);
6637 btprot.open = 1;
6638 btprot.type = 1;
6639 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1);
6640 if (error != 0)
6641 return error;
6642 btprot.open = 0;
6643 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1);
6644 }
6645
6646 static int
iwn5000_runtime_calib(struct iwn_softc * sc)6647 iwn5000_runtime_calib(struct iwn_softc *sc)
6648 {
6649 struct iwn5000_calib_config cmd;
6650
6651 memset(&cmd, 0, sizeof cmd);
6652 cmd.ucode.once.enable = 0xffffffff;
6653 cmd.ucode.once.start = IWN5000_CALIB_DC;
6654 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
6655 "%s: configuring runtime calibration\n", __func__);
6656 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0);
6657 }
6658
6659 static uint32_t
iwn_get_rxon_ht_flags(struct iwn_softc * sc,struct ieee80211vap * vap,struct ieee80211_channel * c)6660 iwn_get_rxon_ht_flags(struct iwn_softc *sc, struct ieee80211vap *vap,
6661 struct ieee80211_channel *c)
6662 {
6663 uint32_t htflags = 0;
6664
6665 if (! IEEE80211_IS_CHAN_HT(c))
6666 return (0);
6667
6668 htflags |= IWN_RXON_HT_PROTMODE(vap->iv_curhtprotmode);
6669
6670 if (IEEE80211_IS_CHAN_HT40(c)) {
6671 switch (vap->iv_curhtprotmode) {
6672 case IEEE80211_HTINFO_OPMODE_HT20PR:
6673 htflags |= IWN_RXON_HT_MODEPURE40;
6674 break;
6675 default:
6676 htflags |= IWN_RXON_HT_MODEMIXED;
6677 break;
6678 }
6679 }
6680 if (IEEE80211_IS_CHAN_HT40D(c))
6681 htflags |= IWN_RXON_HT_HT40MINUS;
6682
6683 return (htflags);
6684 }
6685
6686 static int
iwn_check_bss_filter(struct iwn_softc * sc)6687 iwn_check_bss_filter(struct iwn_softc *sc)
6688 {
6689 return ((sc->rxon->filter & htole32(IWN_FILTER_BSS)) != 0);
6690 }
6691
6692 static int
iwn4965_rxon_assoc(struct iwn_softc * sc,int async)6693 iwn4965_rxon_assoc(struct iwn_softc *sc, int async)
6694 {
6695 struct iwn4965_rxon_assoc cmd;
6696 struct iwn_rxon *rxon = sc->rxon;
6697
6698 cmd.flags = rxon->flags;
6699 cmd.filter = rxon->filter;
6700 cmd.ofdm_mask = rxon->ofdm_mask;
6701 cmd.cck_mask = rxon->cck_mask;
6702 cmd.ht_single_mask = rxon->ht_single_mask;
6703 cmd.ht_dual_mask = rxon->ht_dual_mask;
6704 cmd.rxchain = rxon->rxchain;
6705 cmd.reserved = 0;
6706
6707 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async));
6708 }
6709
6710 static int
iwn5000_rxon_assoc(struct iwn_softc * sc,int async)6711 iwn5000_rxon_assoc(struct iwn_softc *sc, int async)
6712 {
6713 struct iwn5000_rxon_assoc cmd;
6714 struct iwn_rxon *rxon = sc->rxon;
6715
6716 cmd.flags = rxon->flags;
6717 cmd.filter = rxon->filter;
6718 cmd.ofdm_mask = rxon->ofdm_mask;
6719 cmd.cck_mask = rxon->cck_mask;
6720 cmd.reserved1 = 0;
6721 cmd.ht_single_mask = rxon->ht_single_mask;
6722 cmd.ht_dual_mask = rxon->ht_dual_mask;
6723 cmd.ht_triple_mask = rxon->ht_triple_mask;
6724 cmd.reserved2 = 0;
6725 cmd.rxchain = rxon->rxchain;
6726 cmd.acquisition = rxon->acquisition;
6727 cmd.reserved3 = 0;
6728
6729 return (iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &cmd, sizeof(cmd), async));
6730 }
6731
6732 static int
iwn_send_rxon(struct iwn_softc * sc,int assoc,int async)6733 iwn_send_rxon(struct iwn_softc *sc, int assoc, int async)
6734 {
6735 struct iwn_ops *ops = &sc->ops;
6736 int error;
6737
6738 IWN_LOCK_ASSERT(sc);
6739
6740 if (assoc && iwn_check_bss_filter(sc) != 0) {
6741 error = ops->rxon_assoc(sc, async);
6742 if (error != 0) {
6743 device_printf(sc->sc_dev,
6744 "%s: RXON_ASSOC command failed, error %d\n",
6745 __func__, error);
6746 return (error);
6747 }
6748 } else {
6749 if (sc->sc_is_scanning)
6750 device_printf(sc->sc_dev,
6751 "%s: is_scanning set, before RXON\n",
6752 __func__);
6753
6754 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, async);
6755 if (error != 0) {
6756 device_printf(sc->sc_dev,
6757 "%s: RXON command failed, error %d\n",
6758 __func__, error);
6759 return (error);
6760 }
6761
6762 /*
6763 * Reconfiguring RXON clears the firmware nodes table so
6764 * we must add the broadcast node again.
6765 */
6766 if (iwn_check_bss_filter(sc) == 0 &&
6767 (error = iwn_add_broadcast_node(sc, async)) != 0) {
6768 device_printf(sc->sc_dev,
6769 "%s: could not add broadcast node, error %d\n",
6770 __func__, error);
6771 return (error);
6772 }
6773 }
6774
6775 /* Configuration has changed, set TX power accordingly. */
6776 if ((error = ops->set_txpower(sc, async)) != 0) {
6777 device_printf(sc->sc_dev,
6778 "%s: could not set TX power, error %d\n",
6779 __func__, error);
6780 return (error);
6781 }
6782
6783 return (0);
6784 }
6785
6786 static int
iwn_config(struct iwn_softc * sc)6787 iwn_config(struct iwn_softc *sc)
6788 {
6789 struct ieee80211com *ic = &sc->sc_ic;
6790 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6791 const uint8_t *macaddr;
6792 uint32_t txmask;
6793 uint16_t rxchain;
6794 int error;
6795
6796 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
6797
6798 if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET)
6799 && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) {
6800 device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are"
6801 " exclusive each together. Review NIC config file. Conf"
6802 " : 0x%08x Flags : 0x%08x \n", __func__,
6803 sc->base_params->calib_need,
6804 (IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET |
6805 IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2));
6806 return (EINVAL);
6807 }
6808
6809 /* Compute temperature calib if needed. Will be send by send calib */
6810 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) {
6811 error = iwn5000_temp_offset_calib(sc);
6812 if (error != 0) {
6813 device_printf(sc->sc_dev,
6814 "%s: could not set temperature offset\n", __func__);
6815 return (error);
6816 }
6817 } else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) {
6818 error = iwn5000_temp_offset_calibv2(sc);
6819 if (error != 0) {
6820 device_printf(sc->sc_dev,
6821 "%s: could not compute temperature offset v2\n",
6822 __func__);
6823 return (error);
6824 }
6825 }
6826
6827 if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
6828 /* Configure runtime DC calibration. */
6829 error = iwn5000_runtime_calib(sc);
6830 if (error != 0) {
6831 device_printf(sc->sc_dev,
6832 "%s: could not configure runtime calibration\n",
6833 __func__);
6834 return error;
6835 }
6836 }
6837
6838 /* Configure valid TX chains for >=5000 Series. */
6839 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
6840 IWN_UCODE_API(sc->ucode_rev) > 1) {
6841 txmask = htole32(sc->txchainmask);
6842 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT,
6843 "%s: configuring valid TX chains 0x%x\n", __func__, txmask);
6844 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask,
6845 sizeof txmask, 0);
6846 if (error != 0) {
6847 device_printf(sc->sc_dev,
6848 "%s: could not configure valid TX chains, "
6849 "error %d\n", __func__, error);
6850 return error;
6851 }
6852 }
6853
6854 /* Configure bluetooth coexistence. */
6855 error = 0;
6856
6857 /* Configure bluetooth coexistence if needed. */
6858 if (sc->base_params->bt_mode == IWN_BT_ADVANCED)
6859 error = iwn_send_advanced_btcoex(sc);
6860 if (sc->base_params->bt_mode == IWN_BT_SIMPLE)
6861 error = iwn_send_btcoex(sc);
6862
6863 if (error != 0) {
6864 device_printf(sc->sc_dev,
6865 "%s: could not configure bluetooth coexistence, error %d\n",
6866 __func__, error);
6867 return error;
6868 }
6869
6870 /* Set mode, channel, RX filter and enable RX. */
6871 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
6872 memset(sc->rxon, 0, sizeof (struct iwn_rxon));
6873 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr;
6874 IEEE80211_ADDR_COPY(sc->rxon->myaddr, macaddr);
6875 IEEE80211_ADDR_COPY(sc->rxon->wlap, macaddr);
6876 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
6877 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
6878 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
6879 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
6880
6881 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST);
6882 switch (ic->ic_opmode) {
6883 case IEEE80211_M_STA:
6884 sc->rxon->mode = IWN_MODE_STA;
6885 break;
6886 case IEEE80211_M_MONITOR:
6887 sc->rxon->mode = IWN_MODE_MONITOR;
6888 break;
6889 default:
6890 /* Should not get there. */
6891 break;
6892 }
6893 iwn_set_promisc(sc);
6894 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */
6895 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */
6896 sc->rxon->ht_single_mask = 0xff;
6897 sc->rxon->ht_dual_mask = 0xff;
6898 sc->rxon->ht_triple_mask = 0xff;
6899 /*
6900 * In active association mode, ensure that
6901 * all the receive chains are enabled.
6902 *
6903 * Since we're not yet doing SMPS, don't allow the
6904 * number of idle RX chains to be less than the active
6905 * number.
6906 */
6907 rxchain =
6908 IWN_RXCHAIN_VALID(sc->rxchainmask) |
6909 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) |
6910 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains);
6911 sc->rxon->rxchain = htole16(rxchain);
6912 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT,
6913 "%s: rxchainmask=0x%x, nrxchains=%d\n",
6914 __func__,
6915 sc->rxchainmask,
6916 sc->nrxchains);
6917
6918 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ic->ic_curchan));
6919
6920 DPRINTF(sc, IWN_DEBUG_RESET,
6921 "%s: setting configuration; flags=0x%08x\n",
6922 __func__, le32toh(sc->rxon->flags));
6923 if ((error = iwn_send_rxon(sc, 0, 0)) != 0) {
6924 device_printf(sc->sc_dev, "%s: could not send RXON\n",
6925 __func__);
6926 return error;
6927 }
6928
6929 if ((error = iwn_set_critical_temp(sc)) != 0) {
6930 device_printf(sc->sc_dev,
6931 "%s: could not set critical temperature\n", __func__);
6932 return error;
6933 }
6934
6935 /* Set power saving level to CAM during initialization. */
6936 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) {
6937 device_printf(sc->sc_dev,
6938 "%s: could not set power saving level\n", __func__);
6939 return error;
6940 }
6941
6942 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
6943
6944 return 0;
6945 }
6946
6947 static uint16_t
iwn_get_active_dwell_time(struct iwn_softc * sc,struct ieee80211_channel * c,uint8_t n_probes)6948 iwn_get_active_dwell_time(struct iwn_softc *sc,
6949 struct ieee80211_channel *c, uint8_t n_probes)
6950 {
6951 /* No channel? Default to 2GHz settings */
6952 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) {
6953 return (IWN_ACTIVE_DWELL_TIME_2GHZ +
6954 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1));
6955 }
6956
6957 /* 5GHz dwell time */
6958 return (IWN_ACTIVE_DWELL_TIME_5GHZ +
6959 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1));
6960 }
6961
6962 /*
6963 * Limit the total dwell time to 85% of the beacon interval.
6964 *
6965 * Returns the dwell time in milliseconds.
6966 */
6967 static uint16_t
iwn_limit_dwell(struct iwn_softc * sc,uint16_t dwell_time)6968 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time)
6969 {
6970 struct ieee80211com *ic = &sc->sc_ic;
6971 struct ieee80211vap *vap = NULL;
6972 int bintval = 0;
6973
6974 /* bintval is in TU (1.024mS) */
6975 if (! TAILQ_EMPTY(&ic->ic_vaps)) {
6976 vap = TAILQ_FIRST(&ic->ic_vaps);
6977 bintval = vap->iv_bss->ni_intval;
6978 }
6979
6980 /*
6981 * If it's non-zero, we should calculate the minimum of
6982 * it and the DWELL_BASE.
6983 *
6984 * XXX Yes, the math should take into account that bintval
6985 * is 1.024mS, not 1mS..
6986 */
6987 if (bintval > 0) {
6988 DPRINTF(sc, IWN_DEBUG_SCAN,
6989 "%s: bintval=%d\n",
6990 __func__,
6991 bintval);
6992 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100)));
6993 }
6994
6995 /* No association context? Default */
6996 return (IWN_PASSIVE_DWELL_BASE);
6997 }
6998
6999 static uint16_t
iwn_get_passive_dwell_time(struct iwn_softc * sc,struct ieee80211_channel * c)7000 iwn_get_passive_dwell_time(struct iwn_softc *sc, struct ieee80211_channel *c)
7001 {
7002 uint16_t passive;
7003
7004 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) {
7005 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ;
7006 } else {
7007 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ;
7008 }
7009
7010 /* Clamp to the beacon interval if we're associated */
7011 return (iwn_limit_dwell(sc, passive));
7012 }
7013
7014 static int
iwn_scan(struct iwn_softc * sc,struct ieee80211vap * vap,struct ieee80211_scan_state * ss,struct ieee80211_channel * c)7015 iwn_scan(struct iwn_softc *sc, struct ieee80211vap *vap,
7016 struct ieee80211_scan_state *ss, struct ieee80211_channel *c)
7017 {
7018 struct ieee80211com *ic = &sc->sc_ic;
7019 struct ieee80211_node *ni = vap->iv_bss;
7020 struct iwn_scan_hdr *hdr;
7021 struct iwn_cmd_data *tx;
7022 struct iwn_scan_essid *essid;
7023 struct iwn_scan_chan *chan;
7024 struct ieee80211_frame *wh;
7025 struct ieee80211_rateset *rs;
7026 uint8_t *buf, *frm;
7027 uint16_t rxchain;
7028 uint8_t txant;
7029 int buflen, error;
7030 int is_active;
7031 uint16_t dwell_active, dwell_passive;
7032 uint32_t scan_service_time;
7033
7034 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
7035
7036 /*
7037 * We are absolutely not allowed to send a scan command when another
7038 * scan command is pending.
7039 */
7040 if (sc->sc_is_scanning) {
7041 device_printf(sc->sc_dev, "%s: called whilst scanning!\n",
7042 __func__);
7043 return (EAGAIN);
7044 }
7045
7046 /* Assign the scan channel */
7047 c = ic->ic_curchan;
7048
7049 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
7050 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO);
7051 if (buf == NULL) {
7052 device_printf(sc->sc_dev,
7053 "%s: could not allocate buffer for scan command\n",
7054 __func__);
7055 return ENOMEM;
7056 }
7057 hdr = (struct iwn_scan_hdr *)buf;
7058 /*
7059 * Move to the next channel if no frames are received within 10ms
7060 * after sending the probe request.
7061 */
7062 hdr->quiet_time = htole16(10); /* timeout in milliseconds */
7063 hdr->quiet_threshold = htole16(1); /* min # of packets */
7064 /*
7065 * Max needs to be greater than active and passive and quiet!
7066 * It's also in microseconds!
7067 */
7068 hdr->max_svc = htole32(250 * 1024);
7069
7070 /*
7071 * Reset scan: interval=100
7072 * Normal scan: interval=becaon interval
7073 * suspend_time: 100 (TU)
7074 *
7075 */
7076 #if 0
7077 extra = (100 /* suspend_time */ / 100 /* beacon interval */) << 22;
7078 scan_service_time = extra | ((100 /* susp */ % 100 /* int */) * 1024);
7079 #else
7080 scan_service_time = (4 << 22) | (100 * 1024); /* Hardcode for now! */
7081 #endif
7082 hdr->pause_svc = htole32(scan_service_time);
7083
7084 /* Select antennas for scanning. */
7085 rxchain =
7086 IWN_RXCHAIN_VALID(sc->rxchainmask) |
7087 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) |
7088 IWN_RXCHAIN_DRIVER_FORCE;
7089 if (IEEE80211_IS_CHAN_A(c) &&
7090 sc->hw_type == IWN_HW_REV_TYPE_4965) {
7091 /* Ant A must be avoided in 5GHz because of an HW bug. */
7092 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B);
7093 } else /* Use all available RX antennas. */
7094 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask);
7095 hdr->rxchain = htole16(rxchain);
7096 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON);
7097
7098 tx = (struct iwn_cmd_data *)(hdr + 1);
7099 tx->flags = htole32(IWN_TX_AUTO_SEQ);
7100 tx->id = sc->broadcast_id;
7101 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
7102
7103 if (IEEE80211_IS_CHAN_5GHZ(c)) {
7104 /* Send probe requests at 6Mbps. */
7105 tx->rate = htole32(0xd);
7106 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A];
7107 } else {
7108 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO);
7109 if (sc->hw_type == IWN_HW_REV_TYPE_4965 &&
7110 sc->rxon->associd && sc->rxon->chan > 14)
7111 tx->rate = htole32(0xd);
7112 else {
7113 /* Send probe requests at 1Mbps. */
7114 tx->rate = htole32(10 | IWN_RFLAG_CCK);
7115 }
7116 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G];
7117 }
7118 /* Use the first valid TX antenna. */
7119 txant = IWN_LSB(sc->txchainmask);
7120 tx->rate |= htole32(IWN_RFLAG_ANT(txant));
7121
7122 /*
7123 * Only do active scanning if we're announcing a probe request
7124 * for a given SSID (or more, if we ever add it to the driver.)
7125 */
7126 is_active = 0;
7127
7128 /*
7129 * If we're scanning for a specific SSID, add it to the command.
7130 *
7131 * XXX maybe look at adding support for scanning multiple SSIDs?
7132 */
7133 essid = (struct iwn_scan_essid *)(tx + 1);
7134 if (ss != NULL) {
7135 if (ss->ss_ssid[0].len != 0) {
7136 essid[0].id = IEEE80211_ELEMID_SSID;
7137 essid[0].len = ss->ss_ssid[0].len;
7138 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len);
7139 }
7140
7141 DPRINTF(sc, IWN_DEBUG_SCAN, "%s: ssid_len=%d, ssid=%*s\n",
7142 __func__,
7143 ss->ss_ssid[0].len,
7144 ss->ss_ssid[0].len,
7145 ss->ss_ssid[0].ssid);
7146
7147 if (ss->ss_nssid > 0)
7148 is_active = 1;
7149 }
7150
7151 /*
7152 * Build a probe request frame. Most of the following code is a
7153 * copy & paste of what is done in net80211.
7154 */
7155 wh = (struct ieee80211_frame *)(essid + 20);
7156 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
7157 IEEE80211_FC0_SUBTYPE_PROBE_REQ;
7158 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
7159 IEEE80211_ADDR_COPY(wh->i_addr1, if_getbroadcastaddr(vap->iv_ifp));
7160 IEEE80211_ADDR_COPY(wh->i_addr2, if_getlladdr(vap->iv_ifp));
7161 IEEE80211_ADDR_COPY(wh->i_addr3, if_getbroadcastaddr(vap->iv_ifp));
7162 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */
7163 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */
7164
7165 frm = (uint8_t *)(wh + 1);
7166 frm = ieee80211_add_ssid(frm, NULL, 0);
7167 frm = ieee80211_add_rates(frm, rs);
7168 if (rs->rs_nrates > IEEE80211_RATE_SIZE)
7169 frm = ieee80211_add_xrates(frm, rs);
7170 if (ic->ic_htcaps & IEEE80211_HTC_HT)
7171 frm = ieee80211_add_htcap(frm, ni);
7172
7173 /* Set length of probe request. */
7174 tx->len = htole16(frm - (uint8_t *)wh);
7175
7176 /*
7177 * If active scanning is requested but a certain channel is
7178 * marked passive, we can do active scanning if we detect
7179 * transmissions.
7180 *
7181 * There is an issue with some firmware versions that triggers
7182 * a sysassert on a "good CRC threshold" of zero (== disabled),
7183 * on a radar channel even though this means that we should NOT
7184 * send probes.
7185 *
7186 * The "good CRC threshold" is the number of frames that we
7187 * need to receive during our dwell time on a channel before
7188 * sending out probes -- setting this to a huge value will
7189 * mean we never reach it, but at the same time work around
7190 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
7191 * here instead of IWL_GOOD_CRC_TH_DISABLED.
7192 *
7193 * This was fixed in later versions along with some other
7194 * scan changes, and the threshold behaves as a flag in those
7195 * versions.
7196 */
7197
7198 /*
7199 * If we're doing active scanning, set the crc_threshold
7200 * to a suitable value. This is different to active veruss
7201 * passive scanning depending upon the channel flags; the
7202 * firmware will obey that particular check for us.
7203 */
7204 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN)
7205 hdr->crc_threshold = is_active ?
7206 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED;
7207 else
7208 hdr->crc_threshold = is_active ?
7209 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER;
7210
7211 chan = (struct iwn_scan_chan *)frm;
7212 chan->chan = htole16(ieee80211_chan2ieee(ic, c));
7213 chan->flags = 0;
7214 if (ss->ss_nssid > 0)
7215 chan->flags |= htole32(IWN_CHAN_NPBREQS(1));
7216 chan->dsp_gain = 0x6e;
7217
7218 /*
7219 * Set the passive/active flag depending upon the channel mode.
7220 * XXX TODO: take the is_active flag into account as well?
7221 */
7222 if (c->ic_flags & IEEE80211_CHAN_PASSIVE)
7223 chan->flags |= htole32(IWN_CHAN_PASSIVE);
7224 else
7225 chan->flags |= htole32(IWN_CHAN_ACTIVE);
7226
7227 /*
7228 * Calculate the active/passive dwell times.
7229 */
7230
7231 dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid);
7232 dwell_passive = iwn_get_passive_dwell_time(sc, c);
7233
7234 /* Make sure they're valid */
7235 if (dwell_passive <= dwell_active)
7236 dwell_passive = dwell_active + 1;
7237
7238 chan->active = htole16(dwell_active);
7239 chan->passive = htole16(dwell_passive);
7240
7241 if (IEEE80211_IS_CHAN_5GHZ(c))
7242 chan->rf_gain = 0x3b;
7243 else
7244 chan->rf_gain = 0x28;
7245
7246 DPRINTF(sc, IWN_DEBUG_STATE,
7247 "%s: chan %u flags 0x%x rf_gain 0x%x "
7248 "dsp_gain 0x%x active %d passive %d scan_svc_time %d crc 0x%x "
7249 "isactive=%d numssid=%d\n", __func__,
7250 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain,
7251 dwell_active, dwell_passive, scan_service_time,
7252 hdr->crc_threshold, is_active, ss->ss_nssid);
7253
7254 hdr->nchan++;
7255 chan++;
7256 buflen = (uint8_t *)chan - buf;
7257 hdr->len = htole16(buflen);
7258
7259 if (sc->sc_is_scanning) {
7260 device_printf(sc->sc_dev,
7261 "%s: called with is_scanning set!\n",
7262 __func__);
7263 }
7264 sc->sc_is_scanning = 1;
7265
7266 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n",
7267 hdr->nchan);
7268 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1);
7269 free(buf, M_DEVBUF);
7270 if (error == 0)
7271 callout_reset(&sc->scan_timeout, 5*hz, iwn_scan_timeout, sc);
7272
7273 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
7274
7275 return error;
7276 }
7277
7278 static int
iwn_auth(struct iwn_softc * sc,struct ieee80211vap * vap)7279 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap)
7280 {
7281 struct ieee80211com *ic = &sc->sc_ic;
7282 struct ieee80211_node *ni = vap->iv_bss;
7283 int error;
7284
7285 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
7286
7287 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
7288 /* Update adapter configuration. */
7289 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid);
7290 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan);
7291 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
7292 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
7293 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
7294
7295 /*
7296 * We always set short slot on 5GHz channels.
7297 * We optionally set it for 2.4GHz channels.
7298 */
7299 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan))
7300 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT);
7301 else if (vap->iv_flags & IEEE80211_F_SHSLOT)
7302 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT);
7303
7304 if (vap->iv_flags & IEEE80211_F_SHPREAMBLE)
7305 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE);
7306 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
7307 sc->rxon->cck_mask = 0;
7308 sc->rxon->ofdm_mask = 0x15;
7309 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
7310 sc->rxon->cck_mask = 0x03;
7311 sc->rxon->ofdm_mask = 0;
7312 } else {
7313 /* Assume 802.11b/g. */
7314 sc->rxon->cck_mask = 0x03;
7315 sc->rxon->ofdm_mask = 0x15;
7316 }
7317
7318 /* try HT */
7319 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ic->ic_curchan));
7320
7321 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n",
7322 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask,
7323 sc->rxon->ofdm_mask);
7324
7325 if ((error = iwn_send_rxon(sc, 0, 1)) != 0) {
7326 device_printf(sc->sc_dev, "%s: could not send RXON\n",
7327 __func__);
7328 return (error);
7329 }
7330
7331 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
7332
7333 return (0);
7334 }
7335
7336 static int
iwn_run(struct iwn_softc * sc,struct ieee80211vap * vap)7337 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap)
7338 {
7339 struct iwn_ops *ops = &sc->ops;
7340 struct ieee80211com *ic = &sc->sc_ic;
7341 struct ieee80211_node *ni = vap->iv_bss;
7342 struct iwn_node_info node;
7343 int error;
7344
7345 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
7346
7347 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
7348 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
7349 /* Link LED blinks while monitoring. */
7350 iwn_set_led(sc, IWN_LED_LINK, 5, 5);
7351 return 0;
7352 }
7353 if ((error = iwn_set_timing(sc, ni)) != 0) {
7354 device_printf(sc->sc_dev,
7355 "%s: could not set timing, error %d\n", __func__, error);
7356 return error;
7357 }
7358
7359 /* Update adapter configuration. */
7360 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid);
7361 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd));
7362 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan);
7363 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
7364 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
7365 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
7366
7367 /* As previously - short slot only on 5GHz */
7368 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan))
7369 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT);
7370 else if (vap->iv_flags & IEEE80211_F_SHSLOT)
7371 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT);
7372
7373 if (vap->iv_flags & IEEE80211_F_SHPREAMBLE)
7374 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE);
7375 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
7376 sc->rxon->cck_mask = 0;
7377 sc->rxon->ofdm_mask = 0x15;
7378 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
7379 sc->rxon->cck_mask = 0x03;
7380 sc->rxon->ofdm_mask = 0;
7381 } else {
7382 /* Assume 802.11b/g. */
7383 sc->rxon->cck_mask = 0x0f;
7384 sc->rxon->ofdm_mask = 0x15;
7385 }
7386 /* try HT */
7387 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ni->ni_chan));
7388 sc->rxon->filter |= htole32(IWN_FILTER_BSS);
7389 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x, curhtprotmode=%d\n",
7390 sc->rxon->chan, le32toh(sc->rxon->flags), vap->iv_curhtprotmode);
7391
7392 if ((error = iwn_send_rxon(sc, 0, 1)) != 0) {
7393 device_printf(sc->sc_dev, "%s: could not send RXON\n",
7394 __func__);
7395 return error;
7396 }
7397
7398 /* Fake a join to initialize the TX rate. */
7399 ((struct iwn_node *)ni)->id = IWN_ID_BSS;
7400 iwn_newassoc(ni, 1);
7401
7402 /* Add BSS node. */
7403 memset(&node, 0, sizeof node);
7404 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr);
7405 node.id = IWN_ID_BSS;
7406 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
7407 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) {
7408 case IEEE80211_HTCAP_SMPS_ENA:
7409 node.htflags |= htole32(IWN_SMPS_MIMO_DIS);
7410 break;
7411 case IEEE80211_HTCAP_SMPS_DYNAMIC:
7412 node.htflags |= htole32(IWN_SMPS_MIMO_PROT);
7413 break;
7414 }
7415 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) |
7416 IWN_AMDPU_DENSITY(5)); /* 4us */
7417 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan))
7418 node.htflags |= htole32(IWN_NODE_HT40);
7419 }
7420 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__);
7421 error = ops->add_node(sc, &node, 1);
7422 if (error != 0) {
7423 device_printf(sc->sc_dev,
7424 "%s: could not add BSS node, error %d\n", __func__, error);
7425 return error;
7426 }
7427 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n",
7428 __func__, node.id);
7429 if ((error = iwn_set_link_quality(sc, ni)) != 0) {
7430 device_printf(sc->sc_dev,
7431 "%s: could not setup link quality for node %d, error %d\n",
7432 __func__, node.id, error);
7433 return error;
7434 }
7435
7436 if ((error = iwn_init_sensitivity(sc)) != 0) {
7437 device_printf(sc->sc_dev,
7438 "%s: could not set sensitivity, error %d\n", __func__,
7439 error);
7440 return error;
7441 }
7442 /* Start periodic calibration timer. */
7443 sc->calib.state = IWN_CALIB_STATE_ASSOC;
7444 sc->calib_cnt = 0;
7445 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
7446 sc);
7447
7448 /* Link LED always on while associated. */
7449 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
7450
7451 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
7452
7453 return 0;
7454 }
7455
7456 /*
7457 * This function is called by upper layer when an ADDBA request is received
7458 * from another STA and before the ADDBA response is sent.
7459 */
7460 static int
iwn_ampdu_rx_start(struct ieee80211_node * ni,struct ieee80211_rx_ampdu * rap,int baparamset,int batimeout,int baseqctl)7461 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap,
7462 int baparamset, int batimeout, int baseqctl)
7463 {
7464 struct iwn_softc *sc = ni->ni_ic->ic_softc;
7465 struct iwn_ops *ops = &sc->ops;
7466 struct iwn_node *wn = (void *)ni;
7467 struct iwn_node_info node;
7468 uint16_t ssn;
7469 uint8_t tid;
7470 int error;
7471
7472 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7473
7474 tid = _IEEE80211_MASKSHIFT(le16toh(baparamset), IEEE80211_BAPS_TID);
7475 ssn = _IEEE80211_MASKSHIFT(le16toh(baseqctl), IEEE80211_BASEQ_START);
7476
7477 if (wn->id == IWN_ID_UNDEFINED)
7478 return (ENOENT);
7479
7480 memset(&node, 0, sizeof node);
7481 node.id = wn->id;
7482 node.control = IWN_NODE_UPDATE;
7483 node.flags = IWN_FLAG_SET_ADDBA;
7484 node.addba_tid = tid;
7485 node.addba_ssn = htole16(ssn);
7486 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n",
7487 wn->id, tid, ssn);
7488 error = ops->add_node(sc, &node, 1);
7489 if (error != 0)
7490 return error;
7491 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl);
7492 }
7493
7494 /*
7495 * This function is called by upper layer on teardown of an HT-immediate
7496 * Block Ack agreement (eg. uppon receipt of a DELBA frame).
7497 */
7498 static void
iwn_ampdu_rx_stop(struct ieee80211_node * ni,struct ieee80211_rx_ampdu * rap)7499 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap)
7500 {
7501 struct ieee80211com *ic = ni->ni_ic;
7502 struct iwn_softc *sc = ic->ic_softc;
7503 struct iwn_ops *ops = &sc->ops;
7504 struct iwn_node *wn = (void *)ni;
7505 struct iwn_node_info node;
7506 uint8_t tid;
7507
7508 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7509
7510 if (wn->id == IWN_ID_UNDEFINED)
7511 goto end;
7512
7513 /* XXX: tid as an argument */
7514 for (tid = 0; tid < WME_NUM_TID; tid++) {
7515 if (&ni->ni_rx_ampdu[tid] == rap)
7516 break;
7517 }
7518
7519 memset(&node, 0, sizeof node);
7520 node.id = wn->id;
7521 node.control = IWN_NODE_UPDATE;
7522 node.flags = IWN_FLAG_SET_DELBA;
7523 node.delba_tid = tid;
7524 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid);
7525 (void)ops->add_node(sc, &node, 1);
7526 end:
7527 sc->sc_ampdu_rx_stop(ni, rap);
7528 }
7529
7530 static int
iwn_addba_request(struct ieee80211_node * ni,struct ieee80211_tx_ampdu * tap,int dialogtoken,int baparamset,int batimeout)7531 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
7532 int dialogtoken, int baparamset, int batimeout)
7533 {
7534 struct iwn_softc *sc = ni->ni_ic->ic_softc;
7535 int qid;
7536
7537 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7538
7539 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) {
7540 if (sc->qid2tap[qid] == NULL)
7541 break;
7542 }
7543 if (qid == sc->ntxqs) {
7544 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: no free aggregation queue\n",
7545 __func__);
7546 return 0;
7547 }
7548 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
7549 if (tap->txa_private == NULL) {
7550 device_printf(sc->sc_dev,
7551 "%s: failed to alloc TX aggregation structure\n", __func__);
7552 return 0;
7553 }
7554 sc->qid2tap[qid] = tap;
7555 *(int *)tap->txa_private = qid;
7556 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset,
7557 batimeout);
7558 }
7559
7560 static int
iwn_addba_response(struct ieee80211_node * ni,struct ieee80211_tx_ampdu * tap,int code,int baparamset,int batimeout)7561 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
7562 int code, int baparamset, int batimeout)
7563 {
7564 struct iwn_softc *sc = ni->ni_ic->ic_softc;
7565 int qid = *(int *)tap->txa_private;
7566 uint8_t tid = tap->txa_tid;
7567 int ret;
7568
7569 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7570
7571 if (code == IEEE80211_STATUS_SUCCESS) {
7572 ni->ni_txseqs[tid] = tap->txa_start & 0xfff;
7573 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid);
7574 if (ret != 1)
7575 return ret;
7576 } else {
7577 sc->qid2tap[qid] = NULL;
7578 free(tap->txa_private, M_DEVBUF);
7579 tap->txa_private = NULL;
7580 }
7581 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout);
7582 }
7583
7584 /*
7585 * This function is called by upper layer when an ADDBA response is received
7586 * from another STA.
7587 */
7588 static int
iwn_ampdu_tx_start(struct ieee80211com * ic,struct ieee80211_node * ni,uint8_t tid)7589 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
7590 uint8_t tid)
7591 {
7592 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid];
7593 struct iwn_softc *sc = ni->ni_ic->ic_softc;
7594 struct iwn_ops *ops = &sc->ops;
7595 struct iwn_node *wn = (void *)ni;
7596 struct iwn_node_info node;
7597 int error, qid;
7598
7599 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7600
7601 if (wn->id == IWN_ID_UNDEFINED)
7602 return (0);
7603
7604 /* Enable TX for the specified RA/TID. */
7605 wn->disable_tid &= ~(1 << tid);
7606 memset(&node, 0, sizeof node);
7607 node.id = wn->id;
7608 node.control = IWN_NODE_UPDATE;
7609 node.flags = IWN_FLAG_SET_DISABLE_TID;
7610 node.disable_tid = htole16(wn->disable_tid);
7611 error = ops->add_node(sc, &node, 1);
7612 if (error != 0)
7613 return 0;
7614
7615 if ((error = iwn_nic_lock(sc)) != 0)
7616 return 0;
7617 qid = *(int *)tap->txa_private;
7618 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n",
7619 __func__, wn->id, tid, tap->txa_start, qid);
7620 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff);
7621 iwn_nic_unlock(sc);
7622
7623 iwn_set_link_quality(sc, ni);
7624 return 1;
7625 }
7626
7627 static void
iwn_ampdu_tx_stop(struct ieee80211_node * ni,struct ieee80211_tx_ampdu * tap)7628 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap)
7629 {
7630 struct iwn_softc *sc = ni->ni_ic->ic_softc;
7631 struct iwn_ops *ops = &sc->ops;
7632 uint8_t tid = tap->txa_tid;
7633 int qid;
7634
7635 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7636
7637 sc->sc_addba_stop(ni, tap);
7638
7639 if (tap->txa_private == NULL)
7640 return;
7641
7642 qid = *(int *)tap->txa_private;
7643 if (sc->txq[qid].queued != 0)
7644 return;
7645 if (iwn_nic_lock(sc) != 0)
7646 return;
7647 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff);
7648 iwn_nic_unlock(sc);
7649 sc->qid2tap[qid] = NULL;
7650 free(tap->txa_private, M_DEVBUF);
7651 tap->txa_private = NULL;
7652 }
7653
7654 static void
iwn4965_ampdu_tx_start(struct iwn_softc * sc,struct ieee80211_node * ni,int qid,uint8_t tid,uint16_t ssn)7655 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
7656 int qid, uint8_t tid, uint16_t ssn)
7657 {
7658 struct iwn_node *wn = (void *)ni;
7659
7660 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7661
7662 /* Stop TX scheduler while we're changing its configuration. */
7663 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
7664 IWN4965_TXQ_STATUS_CHGACT);
7665
7666 /* Assign RA/TID translation to the queue. */
7667 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid),
7668 wn->id << 4 | tid);
7669
7670 /* Enable chain-building mode for the queue. */
7671 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid);
7672
7673 /* Set starting sequence number from the ADDBA request. */
7674 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
7675 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7676 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
7677
7678 /* Set scheduler window size. */
7679 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid),
7680 IWN_SCHED_WINSZ);
7681 /* Set scheduler frame limit. */
7682 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
7683 IWN_SCHED_LIMIT << 16);
7684
7685 /* Enable interrupts for the queue. */
7686 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
7687
7688 /* Mark the queue as active. */
7689 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
7690 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA |
7691 iwn_tid2fifo[tid] << 1);
7692 }
7693
7694 static void
iwn4965_ampdu_tx_stop(struct iwn_softc * sc,int qid,uint8_t tid,uint16_t ssn)7695 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
7696 {
7697 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7698
7699 /* Stop TX scheduler while we're changing its configuration. */
7700 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
7701 IWN4965_TXQ_STATUS_CHGACT);
7702
7703 /* Set starting sequence number from the ADDBA request. */
7704 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7705 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
7706
7707 /* Disable interrupts for the queue. */
7708 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
7709
7710 /* Mark the queue as inactive. */
7711 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
7712 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1);
7713 }
7714
7715 static void
iwn5000_ampdu_tx_start(struct iwn_softc * sc,struct ieee80211_node * ni,int qid,uint8_t tid,uint16_t ssn)7716 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
7717 int qid, uint8_t tid, uint16_t ssn)
7718 {
7719 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7720
7721 struct iwn_node *wn = (void *)ni;
7722
7723 /* Stop TX scheduler while we're changing its configuration. */
7724 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
7725 IWN5000_TXQ_STATUS_CHGACT);
7726
7727 /* Assign RA/TID translation to the queue. */
7728 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid),
7729 wn->id << 4 | tid);
7730
7731 /* Enable chain-building mode for the queue. */
7732 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid);
7733
7734 /* Enable aggregation for the queue. */
7735 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
7736
7737 /* Set starting sequence number from the ADDBA request. */
7738 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
7739 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7740 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
7741
7742 /* Set scheduler window size and frame limit. */
7743 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
7744 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
7745
7746 /* Enable interrupts for the queue. */
7747 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
7748
7749 /* Mark the queue as active. */
7750 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
7751 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]);
7752 }
7753
7754 static void
iwn5000_ampdu_tx_stop(struct iwn_softc * sc,int qid,uint8_t tid,uint16_t ssn)7755 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
7756 {
7757 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7758
7759 /* Stop TX scheduler while we're changing its configuration. */
7760 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
7761 IWN5000_TXQ_STATUS_CHGACT);
7762
7763 /* Disable aggregation for the queue. */
7764 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
7765
7766 /* Set starting sequence number from the ADDBA request. */
7767 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
7768 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
7769
7770 /* Disable interrupts for the queue. */
7771 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
7772
7773 /* Mark the queue as inactive. */
7774 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
7775 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]);
7776 }
7777
7778 /*
7779 * Query calibration tables from the initialization firmware. We do this
7780 * only once at first boot. Called from a process context.
7781 */
7782 static int
iwn5000_query_calibration(struct iwn_softc * sc)7783 iwn5000_query_calibration(struct iwn_softc *sc)
7784 {
7785 struct iwn5000_calib_config cmd;
7786 int error;
7787
7788 memset(&cmd, 0, sizeof cmd);
7789 cmd.ucode.once.enable = htole32(0xffffffff);
7790 cmd.ucode.once.start = htole32(0xffffffff);
7791 cmd.ucode.once.send = htole32(0xffffffff);
7792 cmd.ucode.flags = htole32(0xffffffff);
7793 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n",
7794 __func__);
7795 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0);
7796 if (error != 0)
7797 return error;
7798
7799 /* Wait at most two seconds for calibration to complete. */
7800 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE))
7801 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz);
7802 return error;
7803 }
7804
7805 /*
7806 * Send calibration results to the runtime firmware. These results were
7807 * obtained on first boot from the initialization firmware.
7808 */
7809 static int
iwn5000_send_calibration(struct iwn_softc * sc)7810 iwn5000_send_calibration(struct iwn_softc *sc)
7811 {
7812 int idx, error;
7813
7814 for (idx = 0; idx < IWN5000_PHY_CALIB_MAX_RESULT; idx++) {
7815 if (!(sc->base_params->calib_need & (1<<idx))) {
7816 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
7817 "No need of calib %d\n",
7818 idx);
7819 continue; /* no need for this calib */
7820 }
7821 if (sc->calibcmd[idx].buf == NULL) {
7822 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
7823 "Need calib idx : %d but no available data\n",
7824 idx);
7825 continue;
7826 }
7827
7828 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
7829 "send calibration result idx=%d len=%d\n", idx,
7830 sc->calibcmd[idx].len);
7831 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf,
7832 sc->calibcmd[idx].len, 0);
7833 if (error != 0) {
7834 device_printf(sc->sc_dev,
7835 "%s: could not send calibration result, error %d\n",
7836 __func__, error);
7837 return error;
7838 }
7839 }
7840 return 0;
7841 }
7842
7843 static int
iwn5000_send_wimax_coex(struct iwn_softc * sc)7844 iwn5000_send_wimax_coex(struct iwn_softc *sc)
7845 {
7846 struct iwn5000_wimax_coex wimax;
7847
7848 #if 0
7849 if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
7850 /* Enable WiMAX coexistence for combo adapters. */
7851 wimax.flags =
7852 IWN_WIMAX_COEX_ASSOC_WA_UNMASK |
7853 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK |
7854 IWN_WIMAX_COEX_STA_TABLE_VALID |
7855 IWN_WIMAX_COEX_ENABLE;
7856 memcpy(wimax.events, iwn6050_wimax_events,
7857 sizeof iwn6050_wimax_events);
7858 } else
7859 #endif
7860 {
7861 /* Disable WiMAX coexistence. */
7862 wimax.flags = 0;
7863 memset(wimax.events, 0, sizeof wimax.events);
7864 }
7865 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n",
7866 __func__);
7867 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0);
7868 }
7869
7870 static int
iwn5000_crystal_calib(struct iwn_softc * sc)7871 iwn5000_crystal_calib(struct iwn_softc *sc)
7872 {
7873 struct iwn5000_phy_calib_crystal cmd;
7874
7875 memset(&cmd, 0, sizeof cmd);
7876 cmd.code = IWN5000_PHY_CALIB_CRYSTAL;
7877 cmd.ngroups = 1;
7878 cmd.isvalid = 1;
7879 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff;
7880 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff;
7881 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n",
7882 cmd.cap_pin[0], cmd.cap_pin[1]);
7883 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
7884 }
7885
7886 static int
iwn5000_temp_offset_calib(struct iwn_softc * sc)7887 iwn5000_temp_offset_calib(struct iwn_softc *sc)
7888 {
7889 struct iwn5000_phy_calib_temp_offset cmd;
7890
7891 memset(&cmd, 0, sizeof cmd);
7892 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET;
7893 cmd.ngroups = 1;
7894 cmd.isvalid = 1;
7895 if (sc->eeprom_temp != 0)
7896 cmd.offset = htole16(sc->eeprom_temp);
7897 else
7898 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET);
7899 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n",
7900 le16toh(cmd.offset));
7901 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
7902 }
7903
7904 static int
iwn5000_temp_offset_calibv2(struct iwn_softc * sc)7905 iwn5000_temp_offset_calibv2(struct iwn_softc *sc)
7906 {
7907 struct iwn5000_phy_calib_temp_offsetv2 cmd;
7908
7909 memset(&cmd, 0, sizeof cmd);
7910 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET;
7911 cmd.ngroups = 1;
7912 cmd.isvalid = 1;
7913 if (sc->eeprom_temp != 0) {
7914 cmd.offset_low = htole16(sc->eeprom_temp);
7915 cmd.offset_high = htole16(sc->eeprom_temp_high);
7916 } else {
7917 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET);
7918 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET);
7919 }
7920 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage);
7921
7922 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
7923 "setting radio sensor low offset to %d, high offset to %d, voltage to %d\n",
7924 le16toh(cmd.offset_low),
7925 le16toh(cmd.offset_high),
7926 le16toh(cmd.burnt_voltage_ref));
7927
7928 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
7929 }
7930
7931 /*
7932 * This function is called after the runtime firmware notifies us of its
7933 * readiness (called in a process context).
7934 */
7935 static int
iwn4965_post_alive(struct iwn_softc * sc)7936 iwn4965_post_alive(struct iwn_softc *sc)
7937 {
7938 int error, qid;
7939
7940 if ((error = iwn_nic_lock(sc)) != 0)
7941 return error;
7942
7943 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7944
7945 /* Clear TX scheduler state in SRAM. */
7946 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
7947 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0,
7948 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t));
7949
7950 /* Set physical address of TX scheduler rings (1KB aligned). */
7951 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
7952
7953 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
7954
7955 /* Disable chain mode for all our 16 queues. */
7956 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0);
7957
7958 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) {
7959 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0);
7960 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
7961
7962 /* Set scheduler window size. */
7963 iwn_mem_write(sc, sc->sched_base +
7964 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ);
7965 /* Set scheduler frame limit. */
7966 iwn_mem_write(sc, sc->sched_base +
7967 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
7968 IWN_SCHED_LIMIT << 16);
7969 }
7970
7971 /* Enable interrupts for all our 16 queues. */
7972 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff);
7973 /* Identify TX FIFO rings (0-7). */
7974 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff);
7975
7976 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
7977 for (qid = 0; qid < 7; qid++) {
7978 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
7979 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
7980 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1);
7981 }
7982 iwn_nic_unlock(sc);
7983 return 0;
7984 }
7985
7986 /*
7987 * This function is called after the initialization or runtime firmware
7988 * notifies us of its readiness (called in a process context).
7989 */
7990 static int
iwn5000_post_alive(struct iwn_softc * sc)7991 iwn5000_post_alive(struct iwn_softc *sc)
7992 {
7993 int error, qid;
7994
7995 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
7996
7997 /* Switch to using ICT interrupt mode. */
7998 iwn5000_ict_reset(sc);
7999
8000 if ((error = iwn_nic_lock(sc)) != 0){
8001 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__);
8002 return error;
8003 }
8004
8005 /* Clear TX scheduler state in SRAM. */
8006 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
8007 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0,
8008 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t));
8009
8010 /* Set physical address of TX scheduler rings (1KB aligned). */
8011 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
8012
8013 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
8014
8015 /* Enable chain mode for all queues, except command queue. */
8016 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT)
8017 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffdf);
8018 else
8019 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef);
8020 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0);
8021
8022 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) {
8023 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0);
8024 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
8025
8026 iwn_mem_write(sc, sc->sched_base +
8027 IWN5000_SCHED_QUEUE_OFFSET(qid), 0);
8028 /* Set scheduler window size and frame limit. */
8029 iwn_mem_write(sc, sc->sched_base +
8030 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
8031 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
8032 }
8033
8034 /* Enable interrupts for all our 20 queues. */
8035 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff);
8036 /* Identify TX FIFO rings (0-7). */
8037 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff);
8038
8039 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
8040 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) {
8041 /* Mark TX rings as active. */
8042 for (qid = 0; qid < 11; qid++) {
8043 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 };
8044 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
8045 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]);
8046 }
8047 } else {
8048 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
8049 for (qid = 0; qid < 7; qid++) {
8050 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
8051 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
8052 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]);
8053 }
8054 }
8055 iwn_nic_unlock(sc);
8056
8057 /* Configure WiMAX coexistence for combo adapters. */
8058 error = iwn5000_send_wimax_coex(sc);
8059 if (error != 0) {
8060 device_printf(sc->sc_dev,
8061 "%s: could not configure WiMAX coexistence, error %d\n",
8062 __func__, error);
8063 return error;
8064 }
8065 if (sc->hw_type != IWN_HW_REV_TYPE_5150) {
8066 /* Perform crystal calibration. */
8067 error = iwn5000_crystal_calib(sc);
8068 if (error != 0) {
8069 device_printf(sc->sc_dev,
8070 "%s: crystal calibration failed, error %d\n",
8071 __func__, error);
8072 return error;
8073 }
8074 }
8075 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) {
8076 /* Query calibration from the initialization firmware. */
8077 if ((error = iwn5000_query_calibration(sc)) != 0) {
8078 device_printf(sc->sc_dev,
8079 "%s: could not query calibration, error %d\n",
8080 __func__, error);
8081 return error;
8082 }
8083 /*
8084 * We have the calibration results now, reboot with the
8085 * runtime firmware (call ourselves recursively!)
8086 */
8087 iwn_hw_stop(sc);
8088 error = iwn_hw_init(sc);
8089 } else {
8090 /* Send calibration results to runtime firmware. */
8091 error = iwn5000_send_calibration(sc);
8092 }
8093
8094 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
8095
8096 return error;
8097 }
8098
8099 /*
8100 * The firmware boot code is small and is intended to be copied directly into
8101 * the NIC internal memory (no DMA transfer).
8102 */
8103 static int
iwn4965_load_bootcode(struct iwn_softc * sc,const uint8_t * ucode,int size)8104 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size)
8105 {
8106 int error, ntries;
8107
8108 size /= sizeof (uint32_t);
8109
8110 if ((error = iwn_nic_lock(sc)) != 0)
8111 return error;
8112
8113 /* Copy microcode image into NIC memory. */
8114 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE,
8115 (const uint32_t *)ucode, size);
8116
8117 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0);
8118 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE);
8119 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size);
8120
8121 /* Start boot load now. */
8122 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START);
8123
8124 /* Wait for transfer to complete. */
8125 for (ntries = 0; ntries < 1000; ntries++) {
8126 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) &
8127 IWN_BSM_WR_CTRL_START))
8128 break;
8129 DELAY(10);
8130 }
8131 if (ntries == 1000) {
8132 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
8133 __func__);
8134 iwn_nic_unlock(sc);
8135 return ETIMEDOUT;
8136 }
8137
8138 /* Enable boot after power up. */
8139 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN);
8140
8141 iwn_nic_unlock(sc);
8142 return 0;
8143 }
8144
8145 static int
iwn4965_load_firmware(struct iwn_softc * sc)8146 iwn4965_load_firmware(struct iwn_softc *sc)
8147 {
8148 struct iwn_fw_info *fw = &sc->fw;
8149 struct iwn_dma_info *dma = &sc->fw_dma;
8150 int error;
8151
8152 /* Copy initialization sections into pre-allocated DMA-safe memory. */
8153 memcpy(dma->vaddr, fw->init.data, fw->init.datasz);
8154 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
8155 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
8156 fw->init.text, fw->init.textsz);
8157 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
8158
8159 /* Tell adapter where to find initialization sections. */
8160 if ((error = iwn_nic_lock(sc)) != 0)
8161 return error;
8162 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
8163 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz);
8164 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
8165 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
8166 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz);
8167 iwn_nic_unlock(sc);
8168
8169 /* Load firmware boot code. */
8170 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz);
8171 if (error != 0) {
8172 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
8173 __func__);
8174 return error;
8175 }
8176 /* Now press "execute". */
8177 IWN_WRITE(sc, IWN_RESET, 0);
8178
8179 /* Wait at most one second for first alive notification. */
8180 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
8181 device_printf(sc->sc_dev,
8182 "%s: timeout waiting for adapter to initialize, error %d\n",
8183 __func__, error);
8184 return error;
8185 }
8186
8187 /* Retrieve current temperature for initial TX power calibration. */
8188 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz;
8189 sc->temp = iwn4965_get_temperature(sc);
8190
8191 /* Copy runtime sections into pre-allocated DMA-safe memory. */
8192 memcpy(dma->vaddr, fw->main.data, fw->main.datasz);
8193 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
8194 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
8195 fw->main.text, fw->main.textsz);
8196 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
8197
8198 /* Tell adapter where to find runtime sections. */
8199 if ((error = iwn_nic_lock(sc)) != 0)
8200 return error;
8201 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
8202 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz);
8203 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
8204 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
8205 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE,
8206 IWN_FW_UPDATED | fw->main.textsz);
8207 iwn_nic_unlock(sc);
8208
8209 return 0;
8210 }
8211
8212 static int
iwn5000_load_firmware_section(struct iwn_softc * sc,uint32_t dst,const uint8_t * section,int size)8213 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst,
8214 const uint8_t *section, int size)
8215 {
8216 struct iwn_dma_info *dma = &sc->fw_dma;
8217 int error;
8218
8219 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8220
8221 /* Copy firmware section into pre-allocated DMA-safe memory. */
8222 memcpy(dma->vaddr, section, size);
8223 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
8224
8225 if ((error = iwn_nic_lock(sc)) != 0)
8226 return error;
8227
8228 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
8229 IWN_FH_TX_CONFIG_DMA_PAUSE);
8230
8231 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst);
8232 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL),
8233 IWN_LOADDR(dma->paddr));
8234 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL),
8235 IWN_HIADDR(dma->paddr) << 28 | size);
8236 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL),
8237 IWN_FH_TXBUF_STATUS_TBNUM(1) |
8238 IWN_FH_TXBUF_STATUS_TBIDX(1) |
8239 IWN_FH_TXBUF_STATUS_TFBD_VALID);
8240
8241 /* Kick Flow Handler to start DMA transfer. */
8242 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
8243 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD);
8244
8245 iwn_nic_unlock(sc);
8246
8247 /* Wait at most five seconds for FH DMA transfer to complete. */
8248 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz);
8249 }
8250
8251 static int
iwn5000_load_firmware(struct iwn_softc * sc)8252 iwn5000_load_firmware(struct iwn_softc *sc)
8253 {
8254 struct iwn_fw_part *fw;
8255 int error;
8256
8257 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8258
8259 /* Load the initialization firmware on first boot only. */
8260 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ?
8261 &sc->fw.main : &sc->fw.init;
8262
8263 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE,
8264 fw->text, fw->textsz);
8265 if (error != 0) {
8266 device_printf(sc->sc_dev,
8267 "%s: could not load firmware %s section, error %d\n",
8268 __func__, ".text", error);
8269 return error;
8270 }
8271 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE,
8272 fw->data, fw->datasz);
8273 if (error != 0) {
8274 device_printf(sc->sc_dev,
8275 "%s: could not load firmware %s section, error %d\n",
8276 __func__, ".data", error);
8277 return error;
8278 }
8279
8280 /* Now press "execute". */
8281 IWN_WRITE(sc, IWN_RESET, 0);
8282 return 0;
8283 }
8284
8285 /*
8286 * Extract text and data sections from a legacy firmware image.
8287 */
8288 static int
iwn_read_firmware_leg(struct iwn_softc * sc,struct iwn_fw_info * fw)8289 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw)
8290 {
8291 const uint32_t *ptr;
8292 size_t hdrlen = 24;
8293 uint32_t rev;
8294
8295 ptr = (const uint32_t *)fw->data;
8296 rev = le32toh(*ptr++);
8297
8298 sc->ucode_rev = rev;
8299
8300 /* Check firmware API version. */
8301 if (IWN_FW_API(rev) <= 1) {
8302 device_printf(sc->sc_dev,
8303 "%s: bad firmware, need API version >=2\n", __func__);
8304 return EINVAL;
8305 }
8306 if (IWN_FW_API(rev) >= 3) {
8307 /* Skip build number (version 2 header). */
8308 hdrlen += 4;
8309 ptr++;
8310 }
8311 if (fw->size < hdrlen) {
8312 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8313 __func__, fw->size);
8314 return EINVAL;
8315 }
8316 fw->main.textsz = le32toh(*ptr++);
8317 fw->main.datasz = le32toh(*ptr++);
8318 fw->init.textsz = le32toh(*ptr++);
8319 fw->init.datasz = le32toh(*ptr++);
8320 fw->boot.textsz = le32toh(*ptr++);
8321
8322 /* Check that all firmware sections fit. */
8323 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz +
8324 fw->init.textsz + fw->init.datasz + fw->boot.textsz) {
8325 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8326 __func__, fw->size);
8327 return EINVAL;
8328 }
8329
8330 /* Get pointers to firmware sections. */
8331 fw->main.text = (const uint8_t *)ptr;
8332 fw->main.data = fw->main.text + fw->main.textsz;
8333 fw->init.text = fw->main.data + fw->main.datasz;
8334 fw->init.data = fw->init.text + fw->init.textsz;
8335 fw->boot.text = fw->init.data + fw->init.datasz;
8336 return 0;
8337 }
8338
8339 /*
8340 * Extract text and data sections from a TLV firmware image.
8341 */
8342 static int
iwn_read_firmware_tlv(struct iwn_softc * sc,struct iwn_fw_info * fw,uint16_t alt)8343 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw,
8344 uint16_t alt)
8345 {
8346 const struct iwn_fw_tlv_hdr *hdr;
8347 const struct iwn_fw_tlv *tlv;
8348 const uint8_t *ptr, *end;
8349 uint64_t altmask;
8350 uint32_t len, tmp;
8351
8352 if (fw->size < sizeof (*hdr)) {
8353 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8354 __func__, fw->size);
8355 return EINVAL;
8356 }
8357 hdr = (const struct iwn_fw_tlv_hdr *)fw->data;
8358 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) {
8359 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n",
8360 __func__, le32toh(hdr->signature));
8361 return EINVAL;
8362 }
8363 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr,
8364 le32toh(hdr->build));
8365 sc->ucode_rev = le32toh(hdr->rev);
8366
8367 /*
8368 * Select the closest supported alternative that is less than
8369 * or equal to the specified one.
8370 */
8371 altmask = le64toh(hdr->altmask);
8372 while (alt > 0 && !(altmask & (1ULL << alt)))
8373 alt--; /* Downgrade. */
8374 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt);
8375
8376 ptr = (const uint8_t *)(hdr + 1);
8377 end = (const uint8_t *)(fw->data + fw->size);
8378
8379 /* Parse type-length-value fields. */
8380 while (ptr + sizeof (*tlv) <= end) {
8381 tlv = (const struct iwn_fw_tlv *)ptr;
8382 len = le32toh(tlv->len);
8383
8384 ptr += sizeof (*tlv);
8385 if (ptr + len > end) {
8386 device_printf(sc->sc_dev,
8387 "%s: firmware too short: %zu bytes\n", __func__,
8388 fw->size);
8389 return EINVAL;
8390 }
8391 /* Skip other alternatives. */
8392 if (tlv->alt != 0 && tlv->alt != htole16(alt))
8393 goto next;
8394
8395 switch (le16toh(tlv->type)) {
8396 case IWN_FW_TLV_MAIN_TEXT:
8397 fw->main.text = ptr;
8398 fw->main.textsz = len;
8399 break;
8400 case IWN_FW_TLV_MAIN_DATA:
8401 fw->main.data = ptr;
8402 fw->main.datasz = len;
8403 break;
8404 case IWN_FW_TLV_INIT_TEXT:
8405 fw->init.text = ptr;
8406 fw->init.textsz = len;
8407 break;
8408 case IWN_FW_TLV_INIT_DATA:
8409 fw->init.data = ptr;
8410 fw->init.datasz = len;
8411 break;
8412 case IWN_FW_TLV_BOOT_TEXT:
8413 fw->boot.text = ptr;
8414 fw->boot.textsz = len;
8415 break;
8416 case IWN_FW_TLV_ENH_SENS:
8417 if (!len)
8418 sc->sc_flags |= IWN_FLAG_ENH_SENS;
8419 break;
8420 case IWN_FW_TLV_PHY_CALIB:
8421 tmp = le32toh(*ptr);
8422 if (tmp < 253) {
8423 sc->reset_noise_gain = tmp;
8424 sc->noise_gain = tmp + 1;
8425 }
8426 break;
8427 case IWN_FW_TLV_PAN:
8428 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT;
8429 DPRINTF(sc, IWN_DEBUG_RESET,
8430 "PAN Support found: %d\n", 1);
8431 break;
8432 case IWN_FW_TLV_FLAGS:
8433 if (len < sizeof(uint32_t))
8434 break;
8435 if (len % sizeof(uint32_t))
8436 break;
8437 sc->tlv_feature_flags = le32toh(*ptr);
8438 DPRINTF(sc, IWN_DEBUG_RESET,
8439 "%s: feature: 0x%08x\n",
8440 __func__,
8441 sc->tlv_feature_flags);
8442 break;
8443 case IWN_FW_TLV_PBREQ_MAXLEN:
8444 case IWN_FW_TLV_RUNT_EVTLOG_PTR:
8445 case IWN_FW_TLV_RUNT_EVTLOG_SIZE:
8446 case IWN_FW_TLV_RUNT_ERRLOG_PTR:
8447 case IWN_FW_TLV_INIT_EVTLOG_PTR:
8448 case IWN_FW_TLV_INIT_EVTLOG_SIZE:
8449 case IWN_FW_TLV_INIT_ERRLOG_PTR:
8450 case IWN_FW_TLV_WOWLAN_INST:
8451 case IWN_FW_TLV_WOWLAN_DATA:
8452 DPRINTF(sc, IWN_DEBUG_RESET,
8453 "TLV type %d recognized but not handled\n",
8454 le16toh(tlv->type));
8455 break;
8456 default:
8457 DPRINTF(sc, IWN_DEBUG_RESET,
8458 "TLV type %d not handled\n", le16toh(tlv->type));
8459 break;
8460 }
8461 next: /* TLV fields are 32-bit aligned. */
8462 ptr += (len + 3) & ~3;
8463 }
8464 return 0;
8465 }
8466
8467 static int
iwn_read_firmware(struct iwn_softc * sc)8468 iwn_read_firmware(struct iwn_softc *sc)
8469 {
8470 struct iwn_fw_info *fw = &sc->fw;
8471 int error;
8472
8473 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8474
8475 IWN_UNLOCK(sc);
8476
8477 memset(fw, 0, sizeof (*fw));
8478
8479 /* Read firmware image from filesystem. */
8480 sc->fw_fp = firmware_get(sc->fwname);
8481 if (sc->fw_fp == NULL) {
8482 device_printf(sc->sc_dev, "%s: could not read firmware %s\n",
8483 __func__, sc->fwname);
8484 IWN_LOCK(sc);
8485 return EINVAL;
8486 }
8487 IWN_LOCK(sc);
8488
8489 fw->size = sc->fw_fp->datasize;
8490 fw->data = (const uint8_t *)sc->fw_fp->data;
8491 if (fw->size < sizeof (uint32_t)) {
8492 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8493 __func__, fw->size);
8494 error = EINVAL;
8495 goto fail;
8496 }
8497
8498 /* Retrieve text and data sections. */
8499 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */
8500 error = iwn_read_firmware_leg(sc, fw);
8501 else
8502 error = iwn_read_firmware_tlv(sc, fw, 1);
8503 if (error != 0) {
8504 device_printf(sc->sc_dev,
8505 "%s: could not read firmware sections, error %d\n",
8506 __func__, error);
8507 goto fail;
8508 }
8509
8510 device_printf(sc->sc_dev, "%s: ucode rev=0x%08x\n", __func__, sc->ucode_rev);
8511
8512 /* Make sure text and data sections fit in hardware memory. */
8513 if (fw->main.textsz > sc->fw_text_maxsz ||
8514 fw->main.datasz > sc->fw_data_maxsz ||
8515 fw->init.textsz > sc->fw_text_maxsz ||
8516 fw->init.datasz > sc->fw_data_maxsz ||
8517 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ ||
8518 (fw->boot.textsz & 3) != 0) {
8519 device_printf(sc->sc_dev, "%s: firmware sections too large\n",
8520 __func__);
8521 error = EINVAL;
8522 goto fail;
8523 }
8524
8525 /* We can proceed with loading the firmware. */
8526 return 0;
8527
8528 fail: iwn_unload_firmware(sc);
8529 return error;
8530 }
8531
8532 static void
iwn_unload_firmware(struct iwn_softc * sc)8533 iwn_unload_firmware(struct iwn_softc *sc)
8534 {
8535 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
8536 sc->fw_fp = NULL;
8537 }
8538
8539 static int
iwn_clock_wait(struct iwn_softc * sc)8540 iwn_clock_wait(struct iwn_softc *sc)
8541 {
8542 int ntries;
8543
8544 /* Set "initialization complete" bit. */
8545 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
8546
8547 /* Wait for clock stabilization. */
8548 for (ntries = 0; ntries < 2500; ntries++) {
8549 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY)
8550 return 0;
8551 DELAY(10);
8552 }
8553 device_printf(sc->sc_dev,
8554 "%s: timeout waiting for clock stabilization\n", __func__);
8555 return ETIMEDOUT;
8556 }
8557
8558 static int
iwn_apm_init(struct iwn_softc * sc)8559 iwn_apm_init(struct iwn_softc *sc)
8560 {
8561 uint32_t reg;
8562 int error;
8563
8564 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8565
8566 /* Disable L0s exit timer (NMI bug workaround). */
8567 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER);
8568 /* Don't wait for ICH L0s (ICH bug workaround). */
8569 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX);
8570
8571 /* Set FH wait threshold to max (HW bug under stress workaround). */
8572 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000);
8573
8574 /* Enable HAP INTA to move adapter from L1a to L0s. */
8575 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A);
8576
8577 /* Retrieve PCIe Active State Power Management (ASPM). */
8578 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);
8579 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
8580 if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */
8581 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
8582 else
8583 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
8584
8585 if (sc->base_params->pll_cfg_val)
8586 IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val);
8587
8588 /* Wait for clock stabilization before accessing prph. */
8589 if ((error = iwn_clock_wait(sc)) != 0)
8590 return error;
8591
8592 if ((error = iwn_nic_lock(sc)) != 0)
8593 return error;
8594 if (sc->hw_type == IWN_HW_REV_TYPE_4965) {
8595 /* Enable DMA and BSM (Bootstrap State Machine). */
8596 iwn_prph_write(sc, IWN_APMG_CLK_EN,
8597 IWN_APMG_CLK_CTRL_DMA_CLK_RQT |
8598 IWN_APMG_CLK_CTRL_BSM_CLK_RQT);
8599 } else {
8600 /* Enable DMA. */
8601 iwn_prph_write(sc, IWN_APMG_CLK_EN,
8602 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
8603 }
8604 DELAY(20);
8605 /* Disable L1-Active. */
8606 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS);
8607 iwn_nic_unlock(sc);
8608
8609 return 0;
8610 }
8611
8612 static void
iwn_apm_stop_master(struct iwn_softc * sc)8613 iwn_apm_stop_master(struct iwn_softc *sc)
8614 {
8615 int ntries;
8616
8617 /* Stop busmaster DMA activity. */
8618 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER);
8619 for (ntries = 0; ntries < 100; ntries++) {
8620 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED)
8621 return;
8622 DELAY(10);
8623 }
8624 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__);
8625 }
8626
8627 static void
iwn_apm_stop(struct iwn_softc * sc)8628 iwn_apm_stop(struct iwn_softc *sc)
8629 {
8630 iwn_apm_stop_master(sc);
8631
8632 /* Reset the entire device. */
8633 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW);
8634 DELAY(10);
8635 /* Clear "initialization complete" bit. */
8636 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
8637 }
8638
8639 static int
iwn4965_nic_config(struct iwn_softc * sc)8640 iwn4965_nic_config(struct iwn_softc *sc)
8641 {
8642 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8643
8644 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) {
8645 /*
8646 * I don't believe this to be correct but this is what the
8647 * vendor driver is doing. Probably the bits should not be
8648 * shifted in IWN_RFCFG_*.
8649 */
8650 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
8651 IWN_RFCFG_TYPE(sc->rfcfg) |
8652 IWN_RFCFG_STEP(sc->rfcfg) |
8653 IWN_RFCFG_DASH(sc->rfcfg));
8654 }
8655 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
8656 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
8657 return 0;
8658 }
8659
8660 static int
iwn5000_nic_config(struct iwn_softc * sc)8661 iwn5000_nic_config(struct iwn_softc *sc)
8662 {
8663 uint32_t tmp;
8664 int error;
8665
8666 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8667
8668 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) {
8669 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
8670 IWN_RFCFG_TYPE(sc->rfcfg) |
8671 IWN_RFCFG_STEP(sc->rfcfg) |
8672 IWN_RFCFG_DASH(sc->rfcfg));
8673 }
8674 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
8675 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
8676
8677 if ((error = iwn_nic_lock(sc)) != 0)
8678 return error;
8679 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS);
8680
8681 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
8682 /*
8683 * Select first Switching Voltage Regulator (1.32V) to
8684 * solve a stability issue related to noisy DC2DC line
8685 * in the silicon of 1000 Series.
8686 */
8687 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR);
8688 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK;
8689 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32;
8690 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp);
8691 }
8692 iwn_nic_unlock(sc);
8693
8694 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) {
8695 /* Use internal power amplifier only. */
8696 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA);
8697 }
8698 if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) {
8699 /* Indicate that ROM calibration version is >=6. */
8700 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6);
8701 }
8702 if (sc->base_params->additional_gp_drv_bit)
8703 IWN_SETBITS(sc, IWN_GP_DRIVER,
8704 sc->base_params->additional_gp_drv_bit);
8705 return 0;
8706 }
8707
8708 /*
8709 * Take NIC ownership over Intel Active Management Technology (AMT).
8710 */
8711 static int
iwn_hw_prepare(struct iwn_softc * sc)8712 iwn_hw_prepare(struct iwn_softc *sc)
8713 {
8714 int ntries;
8715
8716 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8717
8718 /* Check if hardware is ready. */
8719 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
8720 for (ntries = 0; ntries < 5; ntries++) {
8721 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
8722 IWN_HW_IF_CONFIG_NIC_READY)
8723 return 0;
8724 DELAY(10);
8725 }
8726
8727 /* Hardware not ready, force into ready state. */
8728 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE);
8729 for (ntries = 0; ntries < 15000; ntries++) {
8730 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) &
8731 IWN_HW_IF_CONFIG_PREPARE_DONE))
8732 break;
8733 DELAY(10);
8734 }
8735 if (ntries == 15000)
8736 return ETIMEDOUT;
8737
8738 /* Hardware should be ready now. */
8739 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
8740 for (ntries = 0; ntries < 5; ntries++) {
8741 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
8742 IWN_HW_IF_CONFIG_NIC_READY)
8743 return 0;
8744 DELAY(10);
8745 }
8746 return ETIMEDOUT;
8747 }
8748
8749 static int
iwn_hw_init(struct iwn_softc * sc)8750 iwn_hw_init(struct iwn_softc *sc)
8751 {
8752 struct iwn_ops *ops = &sc->ops;
8753 int error, chnl, qid;
8754
8755 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
8756
8757 /* Clear pending interrupts. */
8758 IWN_WRITE(sc, IWN_INT, 0xffffffff);
8759
8760 if ((error = iwn_apm_init(sc)) != 0) {
8761 device_printf(sc->sc_dev,
8762 "%s: could not power ON adapter, error %d\n", __func__,
8763 error);
8764 return error;
8765 }
8766
8767 /* Select VMAIN power source. */
8768 if ((error = iwn_nic_lock(sc)) != 0)
8769 return error;
8770 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK);
8771 iwn_nic_unlock(sc);
8772
8773 /* Perform adapter-specific initialization. */
8774 if ((error = ops->nic_config(sc)) != 0)
8775 return error;
8776
8777 /* Initialize RX ring. */
8778 if ((error = iwn_nic_lock(sc)) != 0)
8779 return error;
8780 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
8781 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0);
8782 /* Set physical address of RX ring (256-byte aligned). */
8783 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8);
8784 /* Set physical address of RX status (16-byte aligned). */
8785 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4);
8786 /* Enable RX. */
8787 IWN_WRITE(sc, IWN_FH_RX_CONFIG,
8788 IWN_FH_RX_CONFIG_ENA |
8789 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */
8790 IWN_FH_RX_CONFIG_IRQ_DST_HOST |
8791 IWN_FH_RX_CONFIG_SINGLE_FRAME |
8792 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) |
8793 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG));
8794 iwn_nic_unlock(sc);
8795 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7);
8796
8797 if ((error = iwn_nic_lock(sc)) != 0)
8798 return error;
8799
8800 /* Initialize TX scheduler. */
8801 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
8802
8803 /* Set physical address of "keep warm" page (16-byte aligned). */
8804 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4);
8805
8806 /* Initialize TX rings. */
8807 for (qid = 0; qid < sc->ntxqs; qid++) {
8808 struct iwn_tx_ring *txq = &sc->txq[qid];
8809
8810 /* Set physical address of TX ring (256-byte aligned). */
8811 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid),
8812 txq->desc_dma.paddr >> 8);
8813 }
8814 iwn_nic_unlock(sc);
8815
8816 /* Enable DMA channels. */
8817 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
8818 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl),
8819 IWN_FH_TX_CONFIG_DMA_ENA |
8820 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA);
8821 }
8822
8823 /* Clear "radio off" and "commands blocked" bits. */
8824 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
8825 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED);
8826
8827 /* Clear pending interrupts. */
8828 IWN_WRITE(sc, IWN_INT, 0xffffffff);
8829 /* Enable interrupt coalescing. */
8830 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8);
8831 /* Enable interrupts. */
8832 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
8833
8834 /* _Really_ make sure "radio off" bit is cleared! */
8835 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
8836 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
8837
8838 /* Enable shadow registers. */
8839 if (sc->base_params->shadow_reg_enable)
8840 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff);
8841
8842 if ((error = ops->load_firmware(sc)) != 0) {
8843 device_printf(sc->sc_dev,
8844 "%s: could not load firmware, error %d\n", __func__,
8845 error);
8846 return error;
8847 }
8848 /* Wait at most one second for firmware alive notification. */
8849 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
8850 device_printf(sc->sc_dev,
8851 "%s: timeout waiting for adapter to initialize, error %d\n",
8852 __func__, error);
8853 return error;
8854 }
8855 /* Do post-firmware initialization. */
8856
8857 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
8858
8859 return ops->post_alive(sc);
8860 }
8861
8862 static void
iwn_hw_stop(struct iwn_softc * sc)8863 iwn_hw_stop(struct iwn_softc *sc)
8864 {
8865 int chnl, qid, ntries;
8866
8867 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8868
8869 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO);
8870
8871 /* Disable interrupts. */
8872 IWN_WRITE(sc, IWN_INT_MASK, 0);
8873 IWN_WRITE(sc, IWN_INT, 0xffffffff);
8874 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff);
8875 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
8876
8877 /* Make sure we no longer hold the NIC lock. */
8878 iwn_nic_unlock(sc);
8879
8880 /* Stop TX scheduler. */
8881 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
8882
8883 /* Stop all DMA channels. */
8884 if (iwn_nic_lock(sc) == 0) {
8885 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
8886 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0);
8887 for (ntries = 0; ntries < 200; ntries++) {
8888 if (IWN_READ(sc, IWN_FH_TX_STATUS) &
8889 IWN_FH_TX_STATUS_IDLE(chnl))
8890 break;
8891 DELAY(10);
8892 }
8893 }
8894 iwn_nic_unlock(sc);
8895 }
8896
8897 /* Stop RX ring. */
8898 iwn_reset_rx_ring(sc, &sc->rxq);
8899
8900 /* Reset all TX rings. */
8901 for (qid = 0; qid < sc->ntxqs; qid++)
8902 iwn_reset_tx_ring(sc, &sc->txq[qid]);
8903
8904 if (iwn_nic_lock(sc) == 0) {
8905 iwn_prph_write(sc, IWN_APMG_CLK_DIS,
8906 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
8907 iwn_nic_unlock(sc);
8908 }
8909 DELAY(5);
8910 /* Power OFF adapter. */
8911 iwn_apm_stop(sc);
8912 }
8913
8914 static void
iwn_panicked(void * arg0,int pending)8915 iwn_panicked(void *arg0, int pending)
8916 {
8917 struct iwn_softc *sc = arg0;
8918 struct ieee80211com *ic = &sc->sc_ic;
8919 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
8920 #if 0
8921 int error;
8922 #endif
8923
8924 if (vap == NULL) {
8925 printf("%s: null vap\n", __func__);
8926 return;
8927 }
8928
8929 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; "
8930 "restarting\n", __func__, vap->iv_state);
8931
8932 /*
8933 * This is not enough work. We need to also reinitialise
8934 * the correct transmit state for aggregation enabled queues,
8935 * which has a very specific requirement of
8936 * ring index = 802.11 seqno % 256. If we don't do this (which
8937 * we definitely don't!) then the firmware will just panic again.
8938 */
8939 #if 1
8940 ieee80211_restart_all(ic);
8941 #else
8942 IWN_LOCK(sc);
8943
8944 iwn_stop_locked(sc);
8945 if ((error = iwn_init_locked(sc)) != 0) {
8946 device_printf(sc->sc_dev,
8947 "%s: could not init hardware\n", __func__);
8948 goto unlock;
8949 }
8950 if (vap->iv_state >= IEEE80211_S_AUTH &&
8951 (error = iwn_auth(sc, vap)) != 0) {
8952 device_printf(sc->sc_dev,
8953 "%s: could not move to auth state\n", __func__);
8954 }
8955 if (vap->iv_state >= IEEE80211_S_RUN &&
8956 (error = iwn_run(sc, vap)) != 0) {
8957 device_printf(sc->sc_dev,
8958 "%s: could not move to run state\n", __func__);
8959 }
8960
8961 unlock:
8962 IWN_UNLOCK(sc);
8963 #endif
8964 }
8965
8966 static int
iwn_init_locked(struct iwn_softc * sc)8967 iwn_init_locked(struct iwn_softc *sc)
8968 {
8969 int error;
8970
8971 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
8972
8973 IWN_LOCK_ASSERT(sc);
8974
8975 if (sc->sc_flags & IWN_FLAG_RUNNING)
8976 goto end;
8977
8978 sc->sc_flags |= IWN_FLAG_RUNNING;
8979
8980 if ((error = iwn_hw_prepare(sc)) != 0) {
8981 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n",
8982 __func__, error);
8983 goto fail;
8984 }
8985
8986 /* Initialize interrupt mask to default value. */
8987 sc->int_mask = IWN_INT_MASK_DEF;
8988 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
8989
8990 /* Check that the radio is not disabled by hardware switch. */
8991 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) {
8992 iwn_stop_locked(sc);
8993 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
8994
8995 return (1);
8996 }
8997
8998 /* Read firmware images from the filesystem. */
8999 if ((error = iwn_read_firmware(sc)) != 0) {
9000 device_printf(sc->sc_dev,
9001 "%s: could not read firmware, error %d\n", __func__,
9002 error);
9003 goto fail;
9004 }
9005
9006 /* Initialize hardware and upload firmware. */
9007 error = iwn_hw_init(sc);
9008 iwn_unload_firmware(sc);
9009 if (error != 0) {
9010 device_printf(sc->sc_dev,
9011 "%s: could not initialize hardware, error %d\n", __func__,
9012 error);
9013 goto fail;
9014 }
9015
9016 /* Configure adapter now that it is ready. */
9017 if ((error = iwn_config(sc)) != 0) {
9018 device_printf(sc->sc_dev,
9019 "%s: could not configure device, error %d\n", __func__,
9020 error);
9021 goto fail;
9022 }
9023
9024 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
9025
9026 end:
9027 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
9028
9029 return (0);
9030
9031 fail:
9032 iwn_stop_locked(sc);
9033
9034 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__);
9035
9036 return (-1);
9037 }
9038
9039 static int
iwn_init(struct iwn_softc * sc)9040 iwn_init(struct iwn_softc *sc)
9041 {
9042 int error;
9043
9044 IWN_LOCK(sc);
9045 error = iwn_init_locked(sc);
9046 IWN_UNLOCK(sc);
9047
9048 return (error);
9049 }
9050
9051 static void
iwn_stop_locked(struct iwn_softc * sc)9052 iwn_stop_locked(struct iwn_softc *sc)
9053 {
9054
9055 IWN_LOCK_ASSERT(sc);
9056
9057 if (!(sc->sc_flags & IWN_FLAG_RUNNING))
9058 return;
9059
9060 sc->sc_is_scanning = 0;
9061 sc->sc_tx_timer = 0;
9062 callout_stop(&sc->watchdog_to);
9063 callout_stop(&sc->scan_timeout);
9064 callout_stop(&sc->calib_to);
9065 sc->sc_flags &= ~IWN_FLAG_RUNNING;
9066
9067 /* Power OFF hardware. */
9068 iwn_hw_stop(sc);
9069 }
9070
9071 static void
iwn_stop(struct iwn_softc * sc)9072 iwn_stop(struct iwn_softc *sc)
9073 {
9074 IWN_LOCK(sc);
9075 iwn_stop_locked(sc);
9076 IWN_UNLOCK(sc);
9077 }
9078
9079 /*
9080 * Callback from net80211 to start a scan.
9081 */
9082 static void
iwn_scan_start(struct ieee80211com * ic)9083 iwn_scan_start(struct ieee80211com *ic)
9084 {
9085 struct iwn_softc *sc = ic->ic_softc;
9086
9087 IWN_LOCK(sc);
9088 /* make the link LED blink while we're scanning */
9089 iwn_set_led(sc, IWN_LED_LINK, 20, 2);
9090 IWN_UNLOCK(sc);
9091 }
9092
9093 /*
9094 * Callback from net80211 to terminate a scan.
9095 */
9096 static void
iwn_scan_end(struct ieee80211com * ic)9097 iwn_scan_end(struct ieee80211com *ic)
9098 {
9099 struct iwn_softc *sc = ic->ic_softc;
9100 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
9101
9102 IWN_LOCK(sc);
9103 if (vap->iv_state == IEEE80211_S_RUN) {
9104 /* Set link LED to ON status if we are associated */
9105 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
9106 }
9107 IWN_UNLOCK(sc);
9108 }
9109
9110 /*
9111 * Callback from net80211 to force a channel change.
9112 */
9113 static void
iwn_set_channel(struct ieee80211com * ic)9114 iwn_set_channel(struct ieee80211com *ic)
9115 {
9116 struct iwn_softc *sc = ic->ic_softc;
9117 int error;
9118
9119 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
9120
9121 IWN_LOCK(sc);
9122 /*
9123 * Only need to set the channel in Monitor mode. AP scanning and auth
9124 * are already taken care of by their respective firmware commands.
9125 */
9126 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
9127 error = iwn_config(sc);
9128 if (error != 0)
9129 device_printf(sc->sc_dev,
9130 "%s: error %d setting channel\n", __func__, error);
9131 }
9132 IWN_UNLOCK(sc);
9133 }
9134
9135 /*
9136 * Callback from net80211 to start scanning of the current channel.
9137 */
9138 static void
iwn_scan_curchan(struct ieee80211_scan_state * ss,unsigned long maxdwell)9139 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell)
9140 {
9141 struct ieee80211vap *vap = ss->ss_vap;
9142 struct ieee80211com *ic = vap->iv_ic;
9143 struct iwn_softc *sc = ic->ic_softc;
9144 int error;
9145
9146 IWN_LOCK(sc);
9147 error = iwn_scan(sc, vap, ss, ic->ic_curchan);
9148 IWN_UNLOCK(sc);
9149 if (error != 0)
9150 ieee80211_cancel_scan(vap);
9151 }
9152
9153 /*
9154 * Callback from net80211 to handle the minimum dwell time being met.
9155 * The intent is to terminate the scan but we just let the firmware
9156 * notify us when it's finished as we have no safe way to abort it.
9157 */
9158 static void
iwn_scan_mindwell(struct ieee80211_scan_state * ss)9159 iwn_scan_mindwell(struct ieee80211_scan_state *ss)
9160 {
9161 /* NB: don't try to abort scan; wait for firmware to finish */
9162 }
9163 #ifdef IWN_DEBUG
9164 #define IWN_DESC(x) case x: return #x
9165
9166 /*
9167 * Translate CSR code to string
9168 */
iwn_get_csr_string(int csr)9169 static char *iwn_get_csr_string(int csr)
9170 {
9171 switch (csr) {
9172 IWN_DESC(IWN_HW_IF_CONFIG);
9173 IWN_DESC(IWN_INT_COALESCING);
9174 IWN_DESC(IWN_INT);
9175 IWN_DESC(IWN_INT_MASK);
9176 IWN_DESC(IWN_FH_INT);
9177 IWN_DESC(IWN_GPIO_IN);
9178 IWN_DESC(IWN_RESET);
9179 IWN_DESC(IWN_GP_CNTRL);
9180 IWN_DESC(IWN_HW_REV);
9181 IWN_DESC(IWN_EEPROM);
9182 IWN_DESC(IWN_EEPROM_GP);
9183 IWN_DESC(IWN_OTP_GP);
9184 IWN_DESC(IWN_GIO);
9185 IWN_DESC(IWN_GP_UCODE);
9186 IWN_DESC(IWN_GP_DRIVER);
9187 IWN_DESC(IWN_UCODE_GP1);
9188 IWN_DESC(IWN_UCODE_GP2);
9189 IWN_DESC(IWN_LED);
9190 IWN_DESC(IWN_DRAM_INT_TBL);
9191 IWN_DESC(IWN_GIO_CHICKEN);
9192 IWN_DESC(IWN_ANA_PLL);
9193 IWN_DESC(IWN_HW_REV_WA);
9194 IWN_DESC(IWN_DBG_HPET_MEM);
9195 default:
9196 return "UNKNOWN CSR";
9197 }
9198 }
9199
9200 /*
9201 * This function print firmware register
9202 */
9203 static void
iwn_debug_register(struct iwn_softc * sc)9204 iwn_debug_register(struct iwn_softc *sc)
9205 {
9206 int i;
9207 static const uint32_t csr_tbl[] = {
9208 IWN_HW_IF_CONFIG,
9209 IWN_INT_COALESCING,
9210 IWN_INT,
9211 IWN_INT_MASK,
9212 IWN_FH_INT,
9213 IWN_GPIO_IN,
9214 IWN_RESET,
9215 IWN_GP_CNTRL,
9216 IWN_HW_REV,
9217 IWN_EEPROM,
9218 IWN_EEPROM_GP,
9219 IWN_OTP_GP,
9220 IWN_GIO,
9221 IWN_GP_UCODE,
9222 IWN_GP_DRIVER,
9223 IWN_UCODE_GP1,
9224 IWN_UCODE_GP2,
9225 IWN_LED,
9226 IWN_DRAM_INT_TBL,
9227 IWN_GIO_CHICKEN,
9228 IWN_ANA_PLL,
9229 IWN_HW_REV_WA,
9230 IWN_DBG_HPET_MEM,
9231 };
9232 DPRINTF(sc, IWN_DEBUG_REGISTER,
9233 "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s",
9234 "\n");
9235 for (i = 0; i < nitems(csr_tbl); i++){
9236 DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ",
9237 iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i]));
9238 if ((i+1) % 3 == 0)
9239 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n");
9240 }
9241 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n");
9242 }
9243 #endif
9244
9245
9246