1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2015-2017 Broadcom
3
4 #include <linux/bitops.h>
5 #include <linux/gpio/driver.h>
6 #include <linux/of.h>
7 #include <linux/module.h>
8 #include <linux/irqdomain.h>
9 #include <linux/irqchip/chained_irq.h>
10 #include <linux/interrupt.h>
11 #include <linux/platform_device.h>
12 #include <linux/string_choices.h>
13
14 enum gio_reg_index {
15 GIO_REG_ODEN = 0,
16 GIO_REG_DATA,
17 GIO_REG_IODIR,
18 GIO_REG_EC,
19 GIO_REG_EI,
20 GIO_REG_MASK,
21 GIO_REG_LEVEL,
22 GIO_REG_STAT,
23 NUMBER_OF_GIO_REGISTERS
24 };
25
26 #define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
27 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
28 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
29 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
30 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
31 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
32 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
33 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
34 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
35 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
36
37 struct brcmstb_gpio_bank {
38 struct list_head node;
39 int id;
40 struct gpio_chip gc;
41 struct brcmstb_gpio_priv *parent_priv;
42 u32 width;
43 u32 wake_active;
44 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
45 };
46
47 struct brcmstb_gpio_priv {
48 struct list_head bank_list;
49 void __iomem *reg_base;
50 struct platform_device *pdev;
51 struct irq_domain *irq_domain;
52 struct irq_chip irq_chip;
53 int parent_irq;
54 int num_gpios;
55 int parent_wake_irq;
56 };
57
58 #define MAX_GPIO_PER_BANK 32
59 #define GPIO_BANK(gpio) ((gpio) >> 5)
60 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
61 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
62
63 static inline struct brcmstb_gpio_priv *
brcmstb_gpio_gc_to_priv(struct gpio_chip * gc)64 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
65 {
66 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
67 return bank->parent_priv;
68 }
69
70 static unsigned long
__brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank * bank)71 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
72 {
73 void __iomem *reg_base = bank->parent_priv->reg_base;
74
75 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
76 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
77 }
78
79 static unsigned long
brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank * bank)80 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
81 {
82 unsigned long status;
83 unsigned long flags;
84
85 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
86 status = __brcmstb_gpio_get_active_irqs(bank);
87 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
88
89 return status;
90 }
91
brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,struct brcmstb_gpio_bank * bank)92 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
93 struct brcmstb_gpio_bank *bank)
94 {
95 return hwirq - bank->gc.offset;
96 }
97
brcmstb_gpio_set_imask(struct brcmstb_gpio_bank * bank,unsigned int hwirq,bool enable)98 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
99 unsigned int hwirq, bool enable)
100 {
101 struct gpio_chip *gc = &bank->gc;
102 struct brcmstb_gpio_priv *priv = bank->parent_priv;
103 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
104 u32 imask;
105 unsigned long flags;
106
107 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
108 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
109 if (enable)
110 imask |= mask;
111 else
112 imask &= ~mask;
113 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
114 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
115 }
116
brcmstb_gpio_to_irq(struct gpio_chip * gc,unsigned offset)117 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
118 {
119 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
120 /* gc_offset is relative to this gpio_chip; want real offset */
121 int hwirq = offset + gc->offset;
122
123 if (hwirq >= priv->num_gpios)
124 return -ENXIO;
125 return irq_create_mapping(priv->irq_domain, hwirq);
126 }
127
128 /* -------------------- IRQ chip functions -------------------- */
129
brcmstb_gpio_irq_mask(struct irq_data * d)130 static void brcmstb_gpio_irq_mask(struct irq_data *d)
131 {
132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
133 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
134
135 brcmstb_gpio_set_imask(bank, d->hwirq, false);
136 }
137
brcmstb_gpio_irq_unmask(struct irq_data * d)138 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
139 {
140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
141 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
142
143 brcmstb_gpio_set_imask(bank, d->hwirq, true);
144 }
145
brcmstb_gpio_irq_ack(struct irq_data * d)146 static void brcmstb_gpio_irq_ack(struct irq_data *d)
147 {
148 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
149 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
150 struct brcmstb_gpio_priv *priv = bank->parent_priv;
151 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
152
153 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
154 }
155
brcmstb_gpio_irq_set_type(struct irq_data * d,unsigned int type)156 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
157 {
158 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
159 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
160 struct brcmstb_gpio_priv *priv = bank->parent_priv;
161 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
162 u32 edge_insensitive, iedge_insensitive;
163 u32 edge_config, iedge_config;
164 u32 level, ilevel;
165 unsigned long flags;
166
167 switch (type) {
168 case IRQ_TYPE_LEVEL_LOW:
169 level = mask;
170 edge_config = 0;
171 edge_insensitive = 0;
172 break;
173 case IRQ_TYPE_LEVEL_HIGH:
174 level = mask;
175 edge_config = mask;
176 edge_insensitive = 0;
177 break;
178 case IRQ_TYPE_EDGE_FALLING:
179 level = 0;
180 edge_config = 0;
181 edge_insensitive = 0;
182 break;
183 case IRQ_TYPE_EDGE_RISING:
184 level = 0;
185 edge_config = mask;
186 edge_insensitive = 0;
187 break;
188 case IRQ_TYPE_EDGE_BOTH:
189 level = 0;
190 edge_config = 0; /* don't care, but want known value */
191 edge_insensitive = mask;
192 break;
193 default:
194 return -EINVAL;
195 }
196
197 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
198
199 iedge_config = bank->gc.read_reg(priv->reg_base +
200 GIO_EC(bank->id)) & ~mask;
201 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
202 GIO_EI(bank->id)) & ~mask;
203 ilevel = bank->gc.read_reg(priv->reg_base +
204 GIO_LEVEL(bank->id)) & ~mask;
205
206 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
207 iedge_config | edge_config);
208 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
209 iedge_insensitive | edge_insensitive);
210 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
211 ilevel | level);
212
213 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
214 return 0;
215 }
216
brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv * priv,unsigned int enable)217 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
218 unsigned int enable)
219 {
220 int ret = 0;
221
222 if (enable)
223 ret = enable_irq_wake(priv->parent_wake_irq);
224 else
225 ret = disable_irq_wake(priv->parent_wake_irq);
226 if (ret)
227 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
228 str_enable_disable(enable));
229 return ret;
230 }
231
brcmstb_gpio_irq_set_wake(struct irq_data * d,unsigned int enable)232 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
233 {
234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
235 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
236 struct brcmstb_gpio_priv *priv = bank->parent_priv;
237 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
238
239 /*
240 * Do not do anything specific for now, suspend/resume callbacks will
241 * configure the interrupt mask appropriately
242 */
243 if (enable)
244 bank->wake_active |= mask;
245 else
246 bank->wake_active &= ~mask;
247
248 return brcmstb_gpio_priv_set_wake(priv, enable);
249 }
250
brcmstb_gpio_wake_irq_handler(int irq,void * data)251 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
252 {
253 struct brcmstb_gpio_priv *priv = data;
254
255 if (!priv || irq != priv->parent_wake_irq)
256 return IRQ_NONE;
257
258 /* Nothing to do */
259 return IRQ_HANDLED;
260 }
261
brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank * bank)262 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
263 {
264 struct brcmstb_gpio_priv *priv = bank->parent_priv;
265 struct irq_domain *domain = priv->irq_domain;
266 int hwbase = bank->gc.offset;
267 unsigned long status;
268
269 while ((status = brcmstb_gpio_get_active_irqs(bank))) {
270 unsigned int offset;
271
272 for_each_set_bit(offset, &status, 32) {
273 if (offset >= bank->width)
274 dev_warn(&priv->pdev->dev,
275 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
276 bank->id, offset);
277 generic_handle_domain_irq(domain, hwbase + offset);
278 }
279 }
280 }
281
282 /* Each UPG GIO block has one IRQ for all banks */
brcmstb_gpio_irq_handler(struct irq_desc * desc)283 static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
284 {
285 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
286 struct irq_chip *chip = irq_desc_get_chip(desc);
287 struct brcmstb_gpio_bank *bank;
288
289 /* Interrupts weren't properly cleared during probe */
290 BUG_ON(!priv || !chip);
291
292 chained_irq_enter(chip, desc);
293 list_for_each_entry(bank, &priv->bank_list, node)
294 brcmstb_gpio_irq_bank_handler(bank);
295 chained_irq_exit(chip, desc);
296 }
297
brcmstb_gpio_hwirq_to_bank(struct brcmstb_gpio_priv * priv,irq_hw_number_t hwirq)298 static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
299 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
300 {
301 struct brcmstb_gpio_bank *bank;
302 int i = 0;
303
304 /* banks are in descending order */
305 list_for_each_entry_reverse(bank, &priv->bank_list, node) {
306 i += bank->gc.ngpio;
307 if (hwirq < i)
308 return bank;
309 }
310 return NULL;
311 }
312
313 /*
314 * This lock class tells lockdep that GPIO irqs are in a different
315 * category than their parents, so it won't report false recursion.
316 */
317 static struct lock_class_key brcmstb_gpio_irq_lock_class;
318 static struct lock_class_key brcmstb_gpio_irq_request_class;
319
320
brcmstb_gpio_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)321 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
322 irq_hw_number_t hwirq)
323 {
324 struct brcmstb_gpio_priv *priv = d->host_data;
325 struct brcmstb_gpio_bank *bank =
326 brcmstb_gpio_hwirq_to_bank(priv, hwirq);
327 struct platform_device *pdev = priv->pdev;
328 int ret;
329
330 if (!bank)
331 return -EINVAL;
332
333 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
334 irq, (int)hwirq, bank->id);
335 ret = irq_set_chip_data(irq, &bank->gc);
336 if (ret < 0)
337 return ret;
338 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
339 &brcmstb_gpio_irq_request_class);
340 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
341 irq_set_noprobe(irq);
342 return 0;
343 }
344
brcmstb_gpio_irq_unmap(struct irq_domain * d,unsigned int irq)345 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
346 {
347 irq_set_chip_and_handler(irq, NULL, NULL);
348 irq_set_chip_data(irq, NULL);
349 }
350
351 static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
352 .map = brcmstb_gpio_irq_map,
353 .unmap = brcmstb_gpio_irq_unmap,
354 .xlate = irq_domain_xlate_twocell,
355 };
356
357 /* Make sure that the number of banks matches up between properties */
brcmstb_gpio_sanity_check_banks(struct device * dev,struct device_node * np,struct resource * res)358 static int brcmstb_gpio_sanity_check_banks(struct device *dev,
359 struct device_node *np, struct resource *res)
360 {
361 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
362 int num_banks =
363 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
364
365 if (res_num_banks != num_banks) {
366 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
367 res_num_banks, num_banks);
368 return -EINVAL;
369 } else {
370 return 0;
371 }
372 }
373
brcmstb_gpio_remove(struct platform_device * pdev)374 static void brcmstb_gpio_remove(struct platform_device *pdev)
375 {
376 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
377 struct brcmstb_gpio_bank *bank;
378 int offset, virq;
379
380 if (priv->parent_irq > 0)
381 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
382
383 /* Remove all IRQ mappings and delete the domain */
384 if (priv->irq_domain) {
385 for (offset = 0; offset < priv->num_gpios; offset++) {
386 virq = irq_find_mapping(priv->irq_domain, offset);
387 irq_dispose_mapping(virq);
388 }
389 irq_domain_remove(priv->irq_domain);
390 }
391
392 /*
393 * You can lose return values below, but we report all errors, and it's
394 * more important to actually perform all of the steps.
395 */
396 list_for_each_entry(bank, &priv->bank_list, node)
397 gpiochip_remove(&bank->gc);
398 }
399
brcmstb_gpio_of_xlate(struct gpio_chip * gc,const struct of_phandle_args * gpiospec,u32 * flags)400 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
401 const struct of_phandle_args *gpiospec, u32 *flags)
402 {
403 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
404 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
405 int offset;
406
407 if (gc->of_gpio_n_cells != 2) {
408 WARN_ON(1);
409 return -EINVAL;
410 }
411
412 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
413 return -EINVAL;
414
415 offset = gpiospec->args[0] - bank->gc.offset;
416 if (offset >= gc->ngpio || offset < 0)
417 return -EINVAL;
418
419 if (unlikely(offset >= bank->width)) {
420 dev_warn_ratelimited(&priv->pdev->dev,
421 "Received request for invalid GPIO offset %d\n",
422 gpiospec->args[0]);
423 }
424
425 if (flags)
426 *flags = gpiospec->args[1];
427
428 return offset;
429 }
430
431 /* priv->parent_irq and priv->num_gpios must be set before calling */
brcmstb_gpio_irq_setup(struct platform_device * pdev,struct brcmstb_gpio_priv * priv)432 static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
433 struct brcmstb_gpio_priv *priv)
434 {
435 struct device *dev = &pdev->dev;
436 struct device_node *np = dev->of_node;
437 int err;
438
439 priv->irq_domain = irq_domain_create_linear(dev_fwnode(dev), priv->num_gpios,
440 &brcmstb_gpio_irq_domain_ops, priv);
441 if (!priv->irq_domain) {
442 dev_err(dev, "Couldn't allocate IRQ domain\n");
443 return -ENXIO;
444 }
445
446 if (of_property_read_bool(np, "wakeup-source")) {
447 priv->parent_wake_irq = platform_get_irq(pdev, 1);
448 if (priv->parent_wake_irq < 0) {
449 priv->parent_wake_irq = 0;
450 dev_warn(dev,
451 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
452 } else {
453 /*
454 * Set wakeup capability so we can process boot-time
455 * "wakeups" (e.g., from S5 cold boot)
456 */
457 device_set_wakeup_capable(dev, true);
458 device_wakeup_enable(dev);
459 err = devm_request_irq(dev, priv->parent_wake_irq,
460 brcmstb_gpio_wake_irq_handler,
461 IRQF_SHARED,
462 "brcmstb-gpio-wake", priv);
463
464 if (err < 0) {
465 dev_err(dev, "Couldn't request wake IRQ");
466 goto out_free_domain;
467 }
468 }
469 }
470
471 priv->irq_chip.name = dev_name(dev);
472 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
473 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
474 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
475 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
476 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
477
478 if (priv->parent_wake_irq)
479 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
480
481 irq_set_chained_handler_and_data(priv->parent_irq,
482 brcmstb_gpio_irq_handler, priv);
483 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
484
485 return 0;
486
487 out_free_domain:
488 irq_domain_remove(priv->irq_domain);
489
490 return err;
491 }
492
brcmstb_gpio_bank_save(struct brcmstb_gpio_priv * priv,struct brcmstb_gpio_bank * bank)493 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
494 struct brcmstb_gpio_bank *bank)
495 {
496 struct gpio_chip *gc = &bank->gc;
497 unsigned int i;
498
499 for (i = 0; i < GIO_REG_STAT; i++)
500 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
501 GIO_BANK_OFF(bank->id, i));
502 }
503
brcmstb_gpio_quiesce(struct device * dev,bool save)504 static void brcmstb_gpio_quiesce(struct device *dev, bool save)
505 {
506 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
507 struct brcmstb_gpio_bank *bank;
508 struct gpio_chip *gc;
509 u32 imask;
510
511 /* disable non-wake interrupt */
512 if (priv->parent_irq >= 0)
513 disable_irq(priv->parent_irq);
514
515 list_for_each_entry(bank, &priv->bank_list, node) {
516 gc = &bank->gc;
517
518 if (save)
519 brcmstb_gpio_bank_save(priv, bank);
520
521 /* Unmask GPIOs which have been flagged as wake-up sources */
522 if (priv->parent_wake_irq)
523 imask = bank->wake_active;
524 else
525 imask = 0;
526 gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
527 imask);
528 }
529 }
530
brcmstb_gpio_shutdown(struct platform_device * pdev)531 static void brcmstb_gpio_shutdown(struct platform_device *pdev)
532 {
533 /* Enable GPIO for S5 cold boot */
534 brcmstb_gpio_quiesce(&pdev->dev, false);
535 }
536
537 #ifdef CONFIG_PM_SLEEP
brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv * priv,struct brcmstb_gpio_bank * bank)538 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
539 struct brcmstb_gpio_bank *bank)
540 {
541 struct gpio_chip *gc = &bank->gc;
542 unsigned int i;
543
544 for (i = 0; i < GIO_REG_STAT; i++)
545 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
546 bank->saved_regs[i]);
547 }
548
brcmstb_gpio_suspend(struct device * dev)549 static int brcmstb_gpio_suspend(struct device *dev)
550 {
551 brcmstb_gpio_quiesce(dev, true);
552 return 0;
553 }
554
brcmstb_gpio_resume(struct device * dev)555 static int brcmstb_gpio_resume(struct device *dev)
556 {
557 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
558 struct brcmstb_gpio_bank *bank;
559 bool need_wakeup_event = false;
560
561 list_for_each_entry(bank, &priv->bank_list, node) {
562 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
563 brcmstb_gpio_bank_restore(priv, bank);
564 }
565
566 if (priv->parent_wake_irq && need_wakeup_event)
567 pm_wakeup_event(dev, 0);
568
569 /* enable non-wake interrupt */
570 if (priv->parent_irq >= 0)
571 enable_irq(priv->parent_irq);
572
573 return 0;
574 }
575
576 #else
577 #define brcmstb_gpio_suspend NULL
578 #define brcmstb_gpio_resume NULL
579 #endif /* CONFIG_PM_SLEEP */
580
581 static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
582 .suspend_noirq = brcmstb_gpio_suspend,
583 .resume_noirq = brcmstb_gpio_resume,
584 };
585
brcmstb_gpio_probe(struct platform_device * pdev)586 static int brcmstb_gpio_probe(struct platform_device *pdev)
587 {
588 struct device *dev = &pdev->dev;
589 struct device_node *np = dev->of_node;
590 void __iomem *reg_base;
591 struct brcmstb_gpio_priv *priv;
592 struct resource *res;
593 u32 bank_width;
594 int num_banks = 0;
595 int num_gpios = 0;
596 int err;
597 unsigned long flags = 0;
598 bool need_wakeup_event = false;
599
600 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
601 if (!priv)
602 return -ENOMEM;
603 platform_set_drvdata(pdev, priv);
604 INIT_LIST_HEAD(&priv->bank_list);
605
606 reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
607 if (IS_ERR(reg_base))
608 return PTR_ERR(reg_base);
609
610 priv->reg_base = reg_base;
611 priv->pdev = pdev;
612
613 if (of_property_read_bool(np, "interrupt-controller")) {
614 priv->parent_irq = platform_get_irq(pdev, 0);
615 if (priv->parent_irq <= 0)
616 return -ENOENT;
617 } else {
618 priv->parent_irq = -ENOENT;
619 }
620
621 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
622 return -EINVAL;
623
624 /*
625 * MIPS endianness is configured by boot strap, which also reverses all
626 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
627 * endian I/O).
628 *
629 * Other architectures (e.g., ARM) either do not support big endian, or
630 * else leave I/O in little endian mode.
631 */
632 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
633 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
634 #endif
635
636 of_property_for_each_u32(np, "brcm,gpio-bank-widths", bank_width) {
637 struct brcmstb_gpio_bank *bank;
638 struct gpio_chip *gc;
639
640 /*
641 * If bank_width is 0, then there is an empty bank in the
642 * register block. Special handling for this case.
643 */
644 if (bank_width == 0) {
645 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
646 num_banks);
647 num_banks++;
648 num_gpios += MAX_GPIO_PER_BANK;
649 continue;
650 }
651
652 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
653 if (!bank) {
654 err = -ENOMEM;
655 goto fail;
656 }
657
658 bank->parent_priv = priv;
659 bank->id = num_banks;
660 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
661 dev_err(dev, "Invalid bank width %d\n", bank_width);
662 err = -EINVAL;
663 goto fail;
664 } else {
665 bank->width = bank_width;
666 }
667
668 /*
669 * Regs are 4 bytes wide, have data reg, no set/clear regs,
670 * and direction bits have 0 = output and 1 = input
671 */
672 gc = &bank->gc;
673 err = bgpio_init(gc, dev, 4,
674 reg_base + GIO_DATA(bank->id),
675 NULL, NULL, NULL,
676 reg_base + GIO_IODIR(bank->id), flags);
677 if (err) {
678 dev_err(dev, "bgpio_init() failed\n");
679 goto fail;
680 }
681
682 gc->owner = THIS_MODULE;
683 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
684 if (!gc->label) {
685 err = -ENOMEM;
686 goto fail;
687 }
688 gc->of_gpio_n_cells = 2;
689 gc->of_xlate = brcmstb_gpio_of_xlate;
690 /* not all ngpio lines are valid, will use bank width later */
691 gc->ngpio = MAX_GPIO_PER_BANK;
692 gc->offset = bank->id * MAX_GPIO_PER_BANK;
693 gc->request = gpiochip_generic_request;
694 gc->free = gpiochip_generic_free;
695 if (priv->parent_irq > 0)
696 gc->to_irq = brcmstb_gpio_to_irq;
697
698 /*
699 * Mask all interrupts by default, since wakeup interrupts may
700 * be retained from S5 cold boot
701 */
702 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
703 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
704
705 err = gpiochip_add_data(gc, bank);
706 if (err) {
707 dev_err(dev, "Could not add gpiochip for bank %d\n",
708 bank->id);
709 goto fail;
710 }
711 num_gpios += gc->ngpio;
712
713 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
714 gc->base, gc->ngpio, bank->width);
715
716 /* Everything looks good, so add bank to list */
717 list_add(&bank->node, &priv->bank_list);
718
719 num_banks++;
720 }
721
722 priv->num_gpios = num_gpios;
723 if (priv->parent_irq > 0) {
724 err = brcmstb_gpio_irq_setup(pdev, priv);
725 if (err)
726 goto fail;
727 }
728
729 if (priv->parent_wake_irq && need_wakeup_event)
730 pm_wakeup_event(dev, 0);
731
732 return 0;
733
734 fail:
735 (void) brcmstb_gpio_remove(pdev);
736 return err;
737 }
738
739 static const struct of_device_id brcmstb_gpio_of_match[] = {
740 { .compatible = "brcm,brcmstb-gpio" },
741 {},
742 };
743
744 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
745
746 static struct platform_driver brcmstb_gpio_driver = {
747 .driver = {
748 .name = "brcmstb-gpio",
749 .of_match_table = brcmstb_gpio_of_match,
750 .pm = &brcmstb_gpio_pm_ops,
751 },
752 .probe = brcmstb_gpio_probe,
753 .remove = brcmstb_gpio_remove,
754 .shutdown = brcmstb_gpio_shutdown,
755 };
756 module_platform_driver(brcmstb_gpio_driver);
757
758 MODULE_AUTHOR("Gregory Fong");
759 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
760 MODULE_LICENSE("GPL v2");
761