1 /*-
2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /*
27 * Allwinner Gigabit Ethernet MAC (EMAC) controller
28 */
29
30 #include "opt_device_polling.h"
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/rman.h>
36 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/mbuf.h>
39 #include <sys/socket.h>
40 #include <sys/sockio.h>
41 #include <sys/module.h>
42 #include <sys/gpio.h>
43
44 #include <net/bpf.h>
45 #include <net/if.h>
46 #include <net/ethernet.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
49 #include <net/if_types.h>
50 #include <net/if_var.h>
51
52 #include <machine/bus.h>
53
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
56
57 #include <arm/allwinner/if_awgreg.h>
58 #include <arm/allwinner/aw_sid.h>
59 #include <dev/mii/mii.h>
60 #include <dev/mii/miivar.h>
61
62 #include <dev/clk/clk.h>
63 #include <dev/hwreset/hwreset.h>
64 #include <dev/regulator/regulator.h>
65 #include <dev/syscon/syscon.h>
66
67 #include "syscon_if.h"
68 #include "miibus_if.h"
69 #include "gpio_if.h"
70
71 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
72 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
73
74 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
75 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
76 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
77 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
78
79 #define DESC_ALIGN 4
80 #define TX_DESC_COUNT 1024
81 #define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT)
82 #define RX_DESC_COUNT 256
83 #define RX_DESC_SIZE (sizeof(struct emac_desc) * RX_DESC_COUNT)
84
85 #define DESC_OFF(n) ((n) * sizeof(struct emac_desc))
86 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1))
87 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1))
88 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1))
89
90 #define TX_MAX_SEGS 20
91
92 #define SOFT_RST_RETRY 1000
93 #define MII_BUSY_RETRY 1000
94 #define MDIO_FREQ 2500000
95
96 #define BURST_LEN_DEFAULT 8
97 #define RX_TX_PRI_DEFAULT 0
98 #define PAUSE_TIME_DEFAULT 0x400
99 #define TX_INTERVAL_DEFAULT 64
100 #define RX_BATCH_DEFAULT 64
101
102 /* syscon EMAC clock register */
103 #define EMAC_CLK_REG 0x30
104 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */
105 #define EMAC_CLK_EPHY_ADDR_SHIFT 20
106 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */
107 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */
108 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */
109 #define EMAC_CLK_RMII_EN (1 << 13)
110 #define EMAC_CLK_ETXDC (0x7 << 10)
111 #define EMAC_CLK_ETXDC_SHIFT 10
112 #define EMAC_CLK_ERXDC (0x1f << 5)
113 #define EMAC_CLK_ERXDC_SHIFT 5
114 #define EMAC_CLK_PIT (0x1 << 2)
115 #define EMAC_CLK_PIT_MII (0 << 2)
116 #define EMAC_CLK_PIT_RGMII (1 << 2)
117 #define EMAC_CLK_SRC (0x3 << 0)
118 #define EMAC_CLK_SRC_MII (0 << 0)
119 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0)
120 #define EMAC_CLK_SRC_RGMII (2 << 0)
121
122 /* Burst length of RX and TX DMA transfers */
123 static int awg_burst_len = BURST_LEN_DEFAULT;
124 TUNABLE_INT("hw.awg.burst_len", &awg_burst_len);
125
126 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */
127 static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT;
128 TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri);
129
130 /* Pause time field in the transmitted control frame */
131 static int awg_pause_time = PAUSE_TIME_DEFAULT;
132 TUNABLE_INT("hw.awg.pause_time", &awg_pause_time);
133
134 /* Request a TX interrupt every <n> descriptors */
135 static int awg_tx_interval = TX_INTERVAL_DEFAULT;
136 TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval);
137
138 /* Maximum number of mbufs to send to if_input */
139 static int awg_rx_batch = RX_BATCH_DEFAULT;
140 TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch);
141
142 enum awg_type {
143 EMAC_A83T = 1,
144 EMAC_H3,
145 EMAC_A64,
146 EMAC_D1,
147 EMAC_H616,
148 };
149
150 static struct ofw_compat_data compat_data[] = {
151 { "allwinner,sun8i-a83t-emac", EMAC_A83T },
152 { "allwinner,sun8i-h3-emac", EMAC_H3 },
153 { "allwinner,sun50i-a64-emac", EMAC_A64 },
154 { "allwinner,sun20i-d1-emac", EMAC_D1 },
155 { "allwinner,sun50i-h616-emac", EMAC_H616 },
156 { NULL, 0 }
157 };
158
159 struct awg_bufmap {
160 bus_dmamap_t map;
161 struct mbuf *mbuf;
162 };
163
164 struct awg_txring {
165 bus_dma_tag_t desc_tag;
166 bus_dmamap_t desc_map;
167 struct emac_desc *desc_ring;
168 bus_addr_t desc_ring_paddr;
169 bus_dma_tag_t buf_tag;
170 struct awg_bufmap buf_map[TX_DESC_COUNT];
171 u_int cur, next, queued;
172 u_int segs;
173 };
174
175 struct awg_rxring {
176 bus_dma_tag_t desc_tag;
177 bus_dmamap_t desc_map;
178 struct emac_desc *desc_ring;
179 bus_addr_t desc_ring_paddr;
180 bus_dma_tag_t buf_tag;
181 struct awg_bufmap buf_map[RX_DESC_COUNT];
182 bus_dmamap_t buf_spare_map;
183 u_int cur;
184 };
185
186 enum {
187 _RES_EMAC,
188 _RES_IRQ,
189 _RES_SYSCON,
190 _RES_NITEMS
191 };
192
193 struct awg_softc {
194 struct resource *res[_RES_NITEMS];
195 struct mtx mtx;
196 if_t ifp;
197 device_t dev;
198 device_t miibus;
199 struct callout stat_ch;
200 void *ih;
201 u_int mdc_div_ratio_m;
202 int link;
203 int if_flags;
204 enum awg_type type;
205 struct syscon *syscon;
206
207 struct awg_txring tx;
208 struct awg_rxring rx;
209 };
210
211 static struct resource_spec awg_spec[] = {
212 { SYS_RES_MEMORY, 0, RF_ACTIVE },
213 { SYS_RES_IRQ, 0, RF_ACTIVE },
214 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
215 { -1, 0 }
216 };
217
218 static void awg_txeof(struct awg_softc *sc);
219 static void awg_start_locked(struct awg_softc *sc);
220
221 static void awg_tick(void *softc);
222
223 static int awg_parse_delay(device_t dev, uint32_t *tx_delay,
224 uint32_t *rx_delay);
225 static uint32_t syscon_read_emac_clk_reg(device_t dev);
226 static void syscon_write_emac_clk_reg(device_t dev, uint32_t val);
227 static phandle_t awg_get_phy_node(device_t dev);
228 static bool awg_has_internal_phy(device_t dev);
229 #ifdef DEVICE_POLLING
230 static int awg_poll(if_t ifp, enum poll_cmd cmd, int count);
231 #endif
232
233 /*
234 * MII functions
235 */
236
237 static int
awg_miibus_readreg(device_t dev,int phy,int reg)238 awg_miibus_readreg(device_t dev, int phy, int reg)
239 {
240 struct awg_softc *sc;
241 int retry, val;
242
243 sc = device_get_softc(dev);
244 val = 0;
245
246 WR4(sc, EMAC_MII_CMD,
247 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) |
248 (phy << PHY_ADDR_SHIFT) |
249 (reg << PHY_REG_ADDR_SHIFT) |
250 MII_BUSY);
251 for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
252 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) {
253 val = RD4(sc, EMAC_MII_DATA);
254 break;
255 }
256 DELAY(10);
257 }
258
259 if (retry == 0)
260 device_printf(dev, "phy read timeout, phy=%d reg=%d\n",
261 phy, reg);
262
263 return (val);
264 }
265
266 static int
awg_miibus_writereg(device_t dev,int phy,int reg,int val)267 awg_miibus_writereg(device_t dev, int phy, int reg, int val)
268 {
269 struct awg_softc *sc;
270 int retry;
271
272 sc = device_get_softc(dev);
273
274 WR4(sc, EMAC_MII_DATA, val);
275 WR4(sc, EMAC_MII_CMD,
276 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) |
277 (phy << PHY_ADDR_SHIFT) |
278 (reg << PHY_REG_ADDR_SHIFT) |
279 MII_WR | MII_BUSY);
280 for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
281 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0)
282 break;
283 DELAY(10);
284 }
285
286 if (retry == 0)
287 device_printf(dev, "phy write timeout, phy=%d reg=%d\n",
288 phy, reg);
289
290 return (0);
291 }
292
293 static void
awg_miibus_statchg(device_t dev)294 awg_miibus_statchg(device_t dev)
295 {
296 struct awg_softc *sc;
297 struct mii_data *mii;
298 uint32_t val;
299
300 sc = device_get_softc(dev);
301
302 AWG_ASSERT_LOCKED(sc);
303
304 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0)
305 return;
306 mii = device_get_softc(sc->miibus);
307
308 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
309 (IFM_ACTIVE | IFM_AVALID)) {
310 switch (IFM_SUBTYPE(mii->mii_media_active)) {
311 case IFM_1000_T:
312 case IFM_1000_SX:
313 case IFM_100_TX:
314 case IFM_10_T:
315 sc->link = 1;
316 break;
317 default:
318 sc->link = 0;
319 break;
320 }
321 } else
322 sc->link = 0;
323
324 if (sc->link == 0)
325 return;
326
327 val = RD4(sc, EMAC_BASIC_CTL_0);
328 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX);
329
330 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
331 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
332 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT;
333 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
334 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT;
335 else
336 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT;
337
338 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
339 val |= BASIC_CTL_DUPLEX;
340
341 WR4(sc, EMAC_BASIC_CTL_0, val);
342
343 val = RD4(sc, EMAC_RX_CTL_0);
344 val &= ~RX_FLOW_CTL_EN;
345 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
346 val |= RX_FLOW_CTL_EN;
347 WR4(sc, EMAC_RX_CTL_0, val);
348
349 val = RD4(sc, EMAC_TX_FLOW_CTL);
350 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN);
351 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
352 val |= TX_FLOW_CTL_EN;
353 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
354 val |= awg_pause_time << PAUSE_TIME_SHIFT;
355 WR4(sc, EMAC_TX_FLOW_CTL, val);
356 }
357
358 /*
359 * Media functions
360 */
361
362 static void
awg_media_status(if_t ifp,struct ifmediareq * ifmr)363 awg_media_status(if_t ifp, struct ifmediareq *ifmr)
364 {
365 struct awg_softc *sc;
366 struct mii_data *mii;
367
368 sc = if_getsoftc(ifp);
369 mii = device_get_softc(sc->miibus);
370
371 AWG_LOCK(sc);
372 mii_pollstat(mii);
373 ifmr->ifm_active = mii->mii_media_active;
374 ifmr->ifm_status = mii->mii_media_status;
375 AWG_UNLOCK(sc);
376 }
377
378 static int
awg_media_change(if_t ifp)379 awg_media_change(if_t ifp)
380 {
381 struct awg_softc *sc;
382 struct mii_data *mii;
383 int error;
384
385 sc = if_getsoftc(ifp);
386 mii = device_get_softc(sc->miibus);
387
388 AWG_LOCK(sc);
389 error = mii_mediachg(mii);
390 AWG_UNLOCK(sc);
391
392 return (error);
393 }
394
395 /*
396 * Core functions
397 */
398
399 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */
400 static uint32_t
bitrev32(uint32_t x)401 bitrev32(uint32_t x)
402 {
403 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
404 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
405 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
406 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
407
408 return (x >> 16) | (x << 16);
409 }
410
411 static u_int
awg_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)412 awg_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
413 {
414 uint32_t crc, hashreg, hashbit, *hash = arg;
415
416 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7f;
417 crc = bitrev32(~crc) >> 26;
418 hashreg = (crc >> 5);
419 hashbit = (crc & 0x1f);
420 hash[hashreg] |= (1 << hashbit);
421
422 return (1);
423 }
424
425 static void
awg_setup_rxfilter(struct awg_softc * sc)426 awg_setup_rxfilter(struct awg_softc *sc)
427 {
428 uint32_t val, hash[2], machi, maclo;
429 uint8_t *eaddr;
430 if_t ifp;
431
432 AWG_ASSERT_LOCKED(sc);
433
434 ifp = sc->ifp;
435 val = 0;
436 hash[0] = hash[1] = 0;
437
438 if (if_getflags(ifp) & IFF_PROMISC)
439 val |= DIS_ADDR_FILTER;
440 else if (if_getflags(ifp) & IFF_ALLMULTI) {
441 val |= RX_ALL_MULTICAST;
442 hash[0] = hash[1] = ~0;
443 } else if (if_foreach_llmaddr(ifp, awg_hash_maddr, hash) > 0)
444 val |= HASH_MULTICAST;
445
446 /* Write our unicast address */
447 eaddr = if_getlladdr(ifp);
448 machi = (eaddr[5] << 8) | eaddr[4];
449 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) |
450 (eaddr[0] << 0);
451 WR4(sc, EMAC_ADDR_HIGH(0), machi);
452 WR4(sc, EMAC_ADDR_LOW(0), maclo);
453
454 /* Multicast hash filters */
455 WR4(sc, EMAC_RX_HASH_0, hash[1]);
456 WR4(sc, EMAC_RX_HASH_1, hash[0]);
457
458 /* RX frame filter config */
459 WR4(sc, EMAC_RX_FRM_FLT, val);
460 }
461
462 static void
awg_setup_core(struct awg_softc * sc)463 awg_setup_core(struct awg_softc *sc)
464 {
465 uint32_t val;
466
467 AWG_ASSERT_LOCKED(sc);
468 /* Configure DMA burst length and priorities */
469 val = awg_burst_len << BASIC_CTL_BURST_LEN_SHIFT;
470 if (awg_rx_tx_pri)
471 val |= BASIC_CTL_RX_TX_PRI;
472 WR4(sc, EMAC_BASIC_CTL_1, val);
473
474 }
475
476 static void
awg_enable_mac(struct awg_softc * sc,bool enable)477 awg_enable_mac(struct awg_softc *sc, bool enable)
478 {
479 uint32_t tx, rx;
480
481 AWG_ASSERT_LOCKED(sc);
482
483 tx = RD4(sc, EMAC_TX_CTL_0);
484 rx = RD4(sc, EMAC_RX_CTL_0);
485 if (enable) {
486 tx |= TX_EN;
487 rx |= RX_EN | CHECK_CRC;
488 } else {
489 tx &= ~TX_EN;
490 rx &= ~(RX_EN | CHECK_CRC);
491 }
492
493 WR4(sc, EMAC_TX_CTL_0, tx);
494 WR4(sc, EMAC_RX_CTL_0, rx);
495 }
496
497 static void
awg_get_eaddr(device_t dev,uint8_t * eaddr)498 awg_get_eaddr(device_t dev, uint8_t *eaddr)
499 {
500 struct awg_softc *sc;
501 uint32_t maclo, machi, rnd;
502 u_char rootkey[16];
503 uint32_t rootkey_size;
504
505 sc = device_get_softc(dev);
506
507 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff;
508 maclo = RD4(sc, EMAC_ADDR_LOW(0));
509
510 rootkey_size = sizeof(rootkey);
511 if (maclo == 0xffffffff && machi == 0xffff) {
512 /* MAC address in hardware is invalid, create one */
513 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey,
514 &rootkey_size) == 0 &&
515 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] |
516 rootkey[15]) != 0) {
517 /* MAC address is derived from the root key in SID */
518 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) |
519 (rootkey[3] << 8) | 0x02;
520 machi = (rootkey[15] << 8) | rootkey[14];
521 } else {
522 /* Create one */
523 rnd = arc4random();
524 maclo = 0x00f2 | (rnd & 0xffff0000);
525 machi = rnd & 0xffff;
526 }
527 }
528
529 eaddr[0] = maclo & 0xff;
530 eaddr[1] = (maclo >> 8) & 0xff;
531 eaddr[2] = (maclo >> 16) & 0xff;
532 eaddr[3] = (maclo >> 24) & 0xff;
533 eaddr[4] = machi & 0xff;
534 eaddr[5] = (machi >> 8) & 0xff;
535 }
536
537 /*
538 * DMA functions
539 */
540
541 static void
awg_enable_dma_intr(struct awg_softc * sc)542 awg_enable_dma_intr(struct awg_softc *sc)
543 {
544 /* Enable interrupts */
545 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN);
546 }
547
548 static void
awg_disable_dma_intr(struct awg_softc * sc)549 awg_disable_dma_intr(struct awg_softc *sc)
550 {
551 /* Disable interrupts */
552 WR4(sc, EMAC_INT_EN, 0);
553 }
554
555 static void
awg_init_dma(struct awg_softc * sc)556 awg_init_dma(struct awg_softc *sc)
557 {
558 uint32_t val;
559
560 AWG_ASSERT_LOCKED(sc);
561
562 /* Enable interrupts */
563 #ifdef DEVICE_POLLING
564 if ((if_getcapenable(sc->ifp) & IFCAP_POLLING) == 0)
565 awg_enable_dma_intr(sc);
566 else
567 awg_disable_dma_intr(sc);
568 #else
569 awg_enable_dma_intr(sc);
570 #endif
571
572 /* Enable transmit DMA */
573 val = RD4(sc, EMAC_TX_CTL_1);
574 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME);
575
576 /* Enable receive DMA */
577 val = RD4(sc, EMAC_RX_CTL_1);
578 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD);
579 }
580
581 static void
awg_stop_dma(struct awg_softc * sc)582 awg_stop_dma(struct awg_softc *sc)
583 {
584 uint32_t val;
585
586 AWG_ASSERT_LOCKED(sc);
587
588 /* Stop transmit DMA and flush data in the TX FIFO */
589 val = RD4(sc, EMAC_TX_CTL_1);
590 val &= ~TX_DMA_EN;
591 val |= FLUSH_TX_FIFO;
592 WR4(sc, EMAC_TX_CTL_1, val);
593
594 /* Disable interrupts */
595 awg_disable_dma_intr(sc);
596
597 /* Disable transmit DMA */
598 val = RD4(sc, EMAC_TX_CTL_1);
599 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN);
600
601 /* Disable receive DMA */
602 val = RD4(sc, EMAC_RX_CTL_1);
603 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN);
604 }
605
606 static int
awg_encap(struct awg_softc * sc,struct mbuf ** mp)607 awg_encap(struct awg_softc *sc, struct mbuf **mp)
608 {
609 bus_dmamap_t map;
610 bus_dma_segment_t segs[TX_MAX_SEGS];
611 int error, nsegs, cur, first, last, i;
612 u_int csum_flags;
613 uint32_t flags, status;
614 struct mbuf *m;
615
616 cur = first = sc->tx.cur;
617 map = sc->tx.buf_map[first].map;
618
619 m = *mp;
620 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, segs,
621 &nsegs, BUS_DMA_NOWAIT);
622 if (error == EFBIG) {
623 m = m_collapse(m, M_NOWAIT, TX_MAX_SEGS);
624 if (m == NULL) {
625 device_printf(sc->dev, "awg_encap: m_collapse failed\n");
626 m_freem(*mp);
627 *mp = NULL;
628 return (ENOMEM);
629 }
630 *mp = m;
631 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m,
632 segs, &nsegs, BUS_DMA_NOWAIT);
633 if (error != 0) {
634 m_freem(*mp);
635 *mp = NULL;
636 }
637 }
638 if (error != 0) {
639 device_printf(sc->dev, "awg_encap: bus_dmamap_load_mbuf_sg failed\n");
640 return (error);
641 }
642 if (nsegs == 0) {
643 m_freem(*mp);
644 *mp = NULL;
645 return (EIO);
646 }
647
648 if (sc->tx.queued + nsegs > TX_DESC_COUNT) {
649 bus_dmamap_unload(sc->tx.buf_tag, map);
650 return (ENOBUFS);
651 }
652
653 bus_dmamap_sync(sc->tx.buf_tag, map, BUS_DMASYNC_PREWRITE);
654
655 flags = TX_FIR_DESC;
656 status = 0;
657 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0)
658 csum_flags = TX_CHECKSUM_CTL_FULL;
659 else if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
660 csum_flags = TX_CHECKSUM_CTL_IP;
661 else
662 csum_flags = 0;
663 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT);
664
665 for (i = 0; i < nsegs; i++) {
666 sc->tx.segs++;
667 if (i == nsegs - 1) {
668 flags |= TX_LAST_DESC;
669 /*
670 * Can only request TX completion
671 * interrupt on last descriptor.
672 */
673 if (sc->tx.segs >= awg_tx_interval) {
674 sc->tx.segs = 0;
675 flags |= TX_INT_CTL;
676 }
677 }
678
679 sc->tx.desc_ring[cur].addr = htole32((uint32_t)segs[i].ds_addr);
680 sc->tx.desc_ring[cur].size = htole32(flags | segs[i].ds_len);
681 sc->tx.desc_ring[cur].status = htole32(status);
682
683 flags &= ~TX_FIR_DESC;
684 /*
685 * Setting of the valid bit in the first descriptor is
686 * deferred until the whole chain is fully set up.
687 */
688 status = TX_DESC_CTL;
689
690 ++sc->tx.queued;
691 cur = TX_NEXT(cur);
692 }
693
694 sc->tx.cur = cur;
695
696 /* Store mapping and mbuf in the last segment */
697 last = TX_SKIP(cur, TX_DESC_COUNT - 1);
698 sc->tx.buf_map[first].map = sc->tx.buf_map[last].map;
699 sc->tx.buf_map[last].map = map;
700 sc->tx.buf_map[last].mbuf = m;
701
702 /*
703 * The whole mbuf chain has been DMA mapped,
704 * fix the first descriptor.
705 */
706 sc->tx.desc_ring[first].status = htole32(TX_DESC_CTL);
707
708 return (0);
709 }
710
711 static void
awg_clean_txbuf(struct awg_softc * sc,int index)712 awg_clean_txbuf(struct awg_softc *sc, int index)
713 {
714 struct awg_bufmap *bmap;
715
716 --sc->tx.queued;
717
718 bmap = &sc->tx.buf_map[index];
719 if (bmap->mbuf != NULL) {
720 bus_dmamap_sync(sc->tx.buf_tag, bmap->map,
721 BUS_DMASYNC_POSTWRITE);
722 bus_dmamap_unload(sc->tx.buf_tag, bmap->map);
723 m_freem(bmap->mbuf);
724 bmap->mbuf = NULL;
725 }
726 }
727
728 static void
awg_setup_rxdesc(struct awg_softc * sc,int index,bus_addr_t paddr)729 awg_setup_rxdesc(struct awg_softc *sc, int index, bus_addr_t paddr)
730 {
731 uint32_t status, size;
732
733 status = RX_DESC_CTL;
734 size = MCLBYTES - 1;
735
736 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr);
737 sc->rx.desc_ring[index].size = htole32(size);
738 sc->rx.desc_ring[index].status = htole32(status);
739 }
740
741 static void
awg_reuse_rxdesc(struct awg_softc * sc,int index)742 awg_reuse_rxdesc(struct awg_softc *sc, int index)
743 {
744
745 sc->rx.desc_ring[index].status = htole32(RX_DESC_CTL);
746 }
747
748 static int
awg_newbuf_rx(struct awg_softc * sc,int index)749 awg_newbuf_rx(struct awg_softc *sc, int index)
750 {
751 struct mbuf *m;
752 bus_dma_segment_t seg;
753 bus_dmamap_t map;
754 int nsegs;
755
756 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
757 if (m == NULL)
758 return (ENOBUFS);
759
760 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
761 m_adj(m, ETHER_ALIGN);
762
763 if (bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, sc->rx.buf_spare_map,
764 m, &seg, &nsegs, BUS_DMA_NOWAIT) != 0) {
765 m_freem(m);
766 return (ENOBUFS);
767 }
768
769 if (sc->rx.buf_map[index].mbuf != NULL) {
770 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map,
771 BUS_DMASYNC_POSTREAD);
772 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map);
773 }
774 map = sc->rx.buf_map[index].map;
775 sc->rx.buf_map[index].map = sc->rx.buf_spare_map;
776 sc->rx.buf_spare_map = map;
777 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map,
778 BUS_DMASYNC_PREREAD);
779
780 sc->rx.buf_map[index].mbuf = m;
781 awg_setup_rxdesc(sc, index, seg.ds_addr);
782
783 return (0);
784 }
785
786 static void
awg_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)787 awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
788 {
789 if (error != 0)
790 return;
791 *(bus_addr_t *)arg = segs[0].ds_addr;
792 }
793
794 static int
awg_setup_dma(device_t dev)795 awg_setup_dma(device_t dev)
796 {
797 struct awg_softc *sc;
798 int error, i;
799
800 sc = device_get_softc(dev);
801
802 /* Setup TX ring */
803 error = bus_dma_tag_create(
804 bus_get_dma_tag(dev), /* Parent tag */
805 DESC_ALIGN, 0, /* alignment, boundary */
806 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
807 BUS_SPACE_MAXADDR, /* highaddr */
808 NULL, NULL, /* filter, filterarg */
809 TX_DESC_SIZE, 1, /* maxsize, nsegs */
810 TX_DESC_SIZE, /* maxsegsize */
811 0, /* flags */
812 NULL, NULL, /* lockfunc, lockarg */
813 &sc->tx.desc_tag);
814 if (error != 0) {
815 device_printf(dev, "cannot create TX descriptor ring tag\n");
816 return (error);
817 }
818
819 error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring,
820 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map);
821 if (error != 0) {
822 device_printf(dev, "cannot allocate TX descriptor ring\n");
823 return (error);
824 }
825
826 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map,
827 sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb,
828 &sc->tx.desc_ring_paddr, 0);
829 if (error != 0) {
830 device_printf(dev, "cannot load TX descriptor ring\n");
831 return (error);
832 }
833
834 for (i = 0; i < TX_DESC_COUNT; i++)
835 sc->tx.desc_ring[i].next =
836 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i)));
837
838 error = bus_dma_tag_create(
839 bus_get_dma_tag(dev), /* Parent tag */
840 1, 0, /* alignment, boundary */
841 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
842 BUS_SPACE_MAXADDR, /* highaddr */
843 NULL, NULL, /* filter, filterarg */
844 MCLBYTES, TX_MAX_SEGS, /* maxsize, nsegs */
845 MCLBYTES, /* maxsegsize */
846 0, /* flags */
847 NULL, NULL, /* lockfunc, lockarg */
848 &sc->tx.buf_tag);
849 if (error != 0) {
850 device_printf(dev, "cannot create TX buffer tag\n");
851 return (error);
852 }
853
854 sc->tx.queued = 0;
855 for (i = 0; i < TX_DESC_COUNT; i++) {
856 error = bus_dmamap_create(sc->tx.buf_tag, 0,
857 &sc->tx.buf_map[i].map);
858 if (error != 0) {
859 device_printf(dev, "cannot create TX buffer map\n");
860 return (error);
861 }
862 }
863
864 /* Setup RX ring */
865 error = bus_dma_tag_create(
866 bus_get_dma_tag(dev), /* Parent tag */
867 DESC_ALIGN, 0, /* alignment, boundary */
868 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
869 BUS_SPACE_MAXADDR, /* highaddr */
870 NULL, NULL, /* filter, filterarg */
871 RX_DESC_SIZE, 1, /* maxsize, nsegs */
872 RX_DESC_SIZE, /* maxsegsize */
873 0, /* flags */
874 NULL, NULL, /* lockfunc, lockarg */
875 &sc->rx.desc_tag);
876 if (error != 0) {
877 device_printf(dev, "cannot create RX descriptor ring tag\n");
878 return (error);
879 }
880
881 error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring,
882 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map);
883 if (error != 0) {
884 device_printf(dev, "cannot allocate RX descriptor ring\n");
885 return (error);
886 }
887
888 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map,
889 sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb,
890 &sc->rx.desc_ring_paddr, 0);
891 if (error != 0) {
892 device_printf(dev, "cannot load RX descriptor ring\n");
893 return (error);
894 }
895
896 error = bus_dma_tag_create(
897 bus_get_dma_tag(dev), /* Parent tag */
898 1, 0, /* alignment, boundary */
899 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
900 BUS_SPACE_MAXADDR, /* highaddr */
901 NULL, NULL, /* filter, filterarg */
902 MCLBYTES, 1, /* maxsize, nsegs */
903 MCLBYTES, /* maxsegsize */
904 0, /* flags */
905 NULL, NULL, /* lockfunc, lockarg */
906 &sc->rx.buf_tag);
907 if (error != 0) {
908 device_printf(dev, "cannot create RX buffer tag\n");
909 return (error);
910 }
911
912 error = bus_dmamap_create(sc->rx.buf_tag, 0, &sc->rx.buf_spare_map);
913 if (error != 0) {
914 device_printf(dev,
915 "cannot create RX buffer spare map\n");
916 return (error);
917 }
918
919 for (i = 0; i < RX_DESC_COUNT; i++) {
920 sc->rx.desc_ring[i].next =
921 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(i)));
922
923 error = bus_dmamap_create(sc->rx.buf_tag, 0,
924 &sc->rx.buf_map[i].map);
925 if (error != 0) {
926 device_printf(dev, "cannot create RX buffer map\n");
927 return (error);
928 }
929 sc->rx.buf_map[i].mbuf = NULL;
930 error = awg_newbuf_rx(sc, i);
931 if (error != 0) {
932 device_printf(dev, "cannot create RX buffer\n");
933 return (error);
934 }
935 }
936 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
937 BUS_DMASYNC_PREWRITE);
938
939 /* Write transmit and receive descriptor base address registers */
940 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
941 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
942
943 return (0);
944 }
945
946 static void
awg_dma_start_tx(struct awg_softc * sc)947 awg_dma_start_tx(struct awg_softc *sc)
948 {
949 uint32_t val;
950
951 AWG_ASSERT_LOCKED(sc);
952
953 /* Start and run TX DMA */
954 val = RD4(sc, EMAC_TX_CTL_1);
955 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START);
956 }
957
958 /*
959 * if_ functions
960 */
961
962 static void
awg_start_locked(struct awg_softc * sc)963 awg_start_locked(struct awg_softc *sc)
964 {
965 struct mbuf *m;
966 if_t ifp;
967 int cnt, err;
968
969 AWG_ASSERT_LOCKED(sc);
970
971 if (!sc->link)
972 return;
973
974 ifp = sc->ifp;
975
976 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
977 IFF_DRV_RUNNING)
978 return;
979
980 for (cnt = 0; ; cnt++) {
981 m = if_dequeue(ifp);
982 if (m == NULL)
983 break;
984
985 err = awg_encap(sc, &m);
986 if (err != 0) {
987 if (err == ENOBUFS)
988 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
989 if (m != NULL)
990 if_sendq_prepend(ifp, m);
991 break;
992 }
993 bpf_mtap_if(ifp, m);
994 }
995
996 if (cnt != 0) {
997 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
998 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
999
1000 awg_dma_start_tx(sc);
1001 }
1002 }
1003
1004 static void
awg_start(if_t ifp)1005 awg_start(if_t ifp)
1006 {
1007 struct awg_softc *sc;
1008
1009 sc = if_getsoftc(ifp);
1010
1011 AWG_LOCK(sc);
1012 awg_start_locked(sc);
1013 AWG_UNLOCK(sc);
1014 }
1015
1016 static void
awg_init_locked(struct awg_softc * sc)1017 awg_init_locked(struct awg_softc *sc)
1018 {
1019 struct mii_data *mii;
1020 if_t ifp;
1021
1022 mii = device_get_softc(sc->miibus);
1023 ifp = sc->ifp;
1024
1025 AWG_ASSERT_LOCKED(sc);
1026
1027 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1028 return;
1029
1030 awg_setup_rxfilter(sc);
1031 awg_setup_core(sc);
1032 awg_enable_mac(sc, true);
1033 awg_init_dma(sc);
1034
1035 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
1036
1037 mii_mediachg(mii);
1038 callout_reset(&sc->stat_ch, hz, awg_tick, sc);
1039 }
1040
1041 static void
awg_init(void * softc)1042 awg_init(void *softc)
1043 {
1044 struct awg_softc *sc;
1045
1046 sc = softc;
1047
1048 AWG_LOCK(sc);
1049 awg_init_locked(sc);
1050 AWG_UNLOCK(sc);
1051 }
1052
1053 static void
awg_stop(struct awg_softc * sc)1054 awg_stop(struct awg_softc *sc)
1055 {
1056 if_t ifp;
1057 uint32_t val;
1058 int i;
1059
1060 AWG_ASSERT_LOCKED(sc);
1061
1062 ifp = sc->ifp;
1063
1064 callout_stop(&sc->stat_ch);
1065
1066 awg_stop_dma(sc);
1067 awg_enable_mac(sc, false);
1068
1069 sc->link = 0;
1070
1071 /* Finish handling transmitted buffers */
1072 awg_txeof(sc);
1073
1074 /* Release any untransmitted buffers. */
1075 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) {
1076 val = le32toh(sc->tx.desc_ring[i].status);
1077 if ((val & TX_DESC_CTL) != 0)
1078 break;
1079 awg_clean_txbuf(sc, i);
1080 }
1081 sc->tx.next = i;
1082 for (; sc->tx.queued > 0; i = TX_NEXT(i)) {
1083 sc->tx.desc_ring[i].status = 0;
1084 awg_clean_txbuf(sc, i);
1085 }
1086 sc->tx.cur = sc->tx.next;
1087 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
1088 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1089
1090 /* Setup RX buffers for reuse */
1091 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1092 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1093
1094 for (i = sc->rx.cur; ; i = RX_NEXT(i)) {
1095 val = le32toh(sc->rx.desc_ring[i].status);
1096 if ((val & RX_DESC_CTL) != 0)
1097 break;
1098 awg_reuse_rxdesc(sc, i);
1099 }
1100 sc->rx.cur = i;
1101 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1102 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1103
1104 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1105 }
1106
1107 static int
awg_ioctl(if_t ifp,u_long cmd,caddr_t data)1108 awg_ioctl(if_t ifp, u_long cmd, caddr_t data)
1109 {
1110 struct awg_softc *sc;
1111 struct mii_data *mii;
1112 struct ifreq *ifr;
1113 int flags, mask, error;
1114
1115 sc = if_getsoftc(ifp);
1116 mii = device_get_softc(sc->miibus);
1117 ifr = (struct ifreq *)data;
1118 error = 0;
1119
1120 switch (cmd) {
1121 case SIOCSIFFLAGS:
1122 AWG_LOCK(sc);
1123 if (if_getflags(ifp) & IFF_UP) {
1124 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1125 flags = if_getflags(ifp) ^ sc->if_flags;
1126 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0)
1127 awg_setup_rxfilter(sc);
1128 } else
1129 awg_init_locked(sc);
1130 } else {
1131 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1132 awg_stop(sc);
1133 }
1134 sc->if_flags = if_getflags(ifp);
1135 AWG_UNLOCK(sc);
1136 break;
1137 case SIOCADDMULTI:
1138 case SIOCDELMULTI:
1139 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1140 AWG_LOCK(sc);
1141 awg_setup_rxfilter(sc);
1142 AWG_UNLOCK(sc);
1143 }
1144 break;
1145 case SIOCSIFMEDIA:
1146 case SIOCGIFMEDIA:
1147 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1148 break;
1149 case SIOCSIFCAP:
1150 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1151 #ifdef DEVICE_POLLING
1152 if (mask & IFCAP_POLLING) {
1153 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1154 error = ether_poll_register(awg_poll, ifp);
1155 if (error != 0)
1156 break;
1157 AWG_LOCK(sc);
1158 awg_disable_dma_intr(sc);
1159 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1160 AWG_UNLOCK(sc);
1161 } else {
1162 error = ether_poll_deregister(ifp);
1163 AWG_LOCK(sc);
1164 awg_enable_dma_intr(sc);
1165 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1166 AWG_UNLOCK(sc);
1167 }
1168 }
1169 #endif
1170 if (mask & IFCAP_VLAN_MTU)
1171 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
1172 if (mask & IFCAP_RXCSUM)
1173 if_togglecapenable(ifp, IFCAP_RXCSUM);
1174 if (mask & IFCAP_TXCSUM)
1175 if_togglecapenable(ifp, IFCAP_TXCSUM);
1176 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1177 if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0);
1178 else
1179 if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP);
1180 break;
1181 default:
1182 error = ether_ioctl(ifp, cmd, data);
1183 break;
1184 }
1185
1186 return (error);
1187 }
1188
1189 /*
1190 * Interrupts functions
1191 */
1192
1193 static int
awg_rxintr(struct awg_softc * sc)1194 awg_rxintr(struct awg_softc *sc)
1195 {
1196 if_t ifp;
1197 struct mbuf *m, *mh, *mt;
1198 int error, index, len, cnt, npkt;
1199 uint32_t status;
1200
1201 ifp = sc->ifp;
1202 mh = mt = NULL;
1203 cnt = 0;
1204 npkt = 0;
1205
1206 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1207 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1208
1209 for (index = sc->rx.cur; ; index = RX_NEXT(index)) {
1210 status = le32toh(sc->rx.desc_ring[index].status);
1211 if ((status & RX_DESC_CTL) != 0)
1212 break;
1213
1214 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT;
1215
1216 if (len == 0) {
1217 if ((status & (RX_NO_ENOUGH_BUF_ERR | RX_OVERFLOW_ERR)) != 0)
1218 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1219 awg_reuse_rxdesc(sc, index);
1220 continue;
1221 }
1222
1223 m = sc->rx.buf_map[index].mbuf;
1224
1225 error = awg_newbuf_rx(sc, index);
1226 if (error != 0) {
1227 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1228 awg_reuse_rxdesc(sc, index);
1229 continue;
1230 }
1231
1232 m->m_pkthdr.rcvif = ifp;
1233 m->m_pkthdr.len = len;
1234 m->m_len = len;
1235 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1236
1237 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
1238 (status & RX_FRM_TYPE) != 0) {
1239 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
1240 if ((status & RX_HEADER_ERR) == 0)
1241 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1242 if ((status & RX_PAYLOAD_ERR) == 0) {
1243 m->m_pkthdr.csum_flags |=
1244 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1245 m->m_pkthdr.csum_data = 0xffff;
1246 }
1247 }
1248
1249 m->m_nextpkt = NULL;
1250 if (mh == NULL)
1251 mh = m;
1252 else
1253 mt->m_nextpkt = m;
1254 mt = m;
1255 ++cnt;
1256 ++npkt;
1257
1258 if (cnt == awg_rx_batch) {
1259 AWG_UNLOCK(sc);
1260 if_input(ifp, mh);
1261 AWG_LOCK(sc);
1262 mh = mt = NULL;
1263 cnt = 0;
1264 }
1265 }
1266
1267 if (index != sc->rx.cur) {
1268 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1269 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1270 }
1271
1272 if (mh != NULL) {
1273 AWG_UNLOCK(sc);
1274 if_input(ifp, mh);
1275 AWG_LOCK(sc);
1276 }
1277
1278 sc->rx.cur = index;
1279
1280 return (npkt);
1281 }
1282
1283 static void
awg_txeof(struct awg_softc * sc)1284 awg_txeof(struct awg_softc *sc)
1285 {
1286 struct emac_desc *desc;
1287 uint32_t status, size;
1288 if_t ifp;
1289 int i, prog;
1290
1291 AWG_ASSERT_LOCKED(sc);
1292
1293 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
1294 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1295
1296 ifp = sc->ifp;
1297
1298 prog = 0;
1299 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) {
1300 desc = &sc->tx.desc_ring[i];
1301 status = le32toh(desc->status);
1302 if ((status & TX_DESC_CTL) != 0)
1303 break;
1304 size = le32toh(desc->size);
1305 if (size & TX_LAST_DESC) {
1306 if ((status & (TX_HEADER_ERR | TX_PAYLOAD_ERR)) != 0)
1307 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1308 else
1309 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1310 }
1311 prog++;
1312 awg_clean_txbuf(sc, i);
1313 }
1314
1315 if (prog > 0) {
1316 sc->tx.next = i;
1317 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1318 }
1319 }
1320
1321 static void
awg_intr(void * arg)1322 awg_intr(void *arg)
1323 {
1324 struct awg_softc *sc;
1325 uint32_t val;
1326
1327 sc = arg;
1328
1329 AWG_LOCK(sc);
1330 val = RD4(sc, EMAC_INT_STA);
1331 WR4(sc, EMAC_INT_STA, val);
1332
1333 if (val & RX_INT)
1334 awg_rxintr(sc);
1335
1336 if (val & TX_INT)
1337 awg_txeof(sc);
1338
1339 if (val & (TX_INT | TX_BUF_UA_INT)) {
1340 if (!if_sendq_empty(sc->ifp))
1341 awg_start_locked(sc);
1342 }
1343
1344 AWG_UNLOCK(sc);
1345 }
1346
1347 #ifdef DEVICE_POLLING
1348 static int
awg_poll(if_t ifp,enum poll_cmd cmd,int count)1349 awg_poll(if_t ifp, enum poll_cmd cmd, int count)
1350 {
1351 struct awg_softc *sc;
1352 uint32_t val;
1353 int rx_npkts;
1354
1355 sc = if_getsoftc(ifp);
1356 rx_npkts = 0;
1357
1358 AWG_LOCK(sc);
1359
1360 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1361 AWG_UNLOCK(sc);
1362 return (0);
1363 }
1364
1365 rx_npkts = awg_rxintr(sc);
1366 awg_txeof(sc);
1367 if (!if_sendq_empty(ifp))
1368 awg_start_locked(sc);
1369
1370 if (cmd == POLL_AND_CHECK_STATUS) {
1371 val = RD4(sc, EMAC_INT_STA);
1372 if (val != 0)
1373 WR4(sc, EMAC_INT_STA, val);
1374 }
1375
1376 AWG_UNLOCK(sc);
1377
1378 return (rx_npkts);
1379 }
1380 #endif
1381
1382 /*
1383 * syscon functions
1384 */
1385 static uint32_t
syscon_read_emac_clk_reg(device_t dev)1386 syscon_read_emac_clk_reg(device_t dev)
1387 {
1388 struct awg_softc *sc;
1389
1390 sc = device_get_softc(dev);
1391 if (sc->syscon != NULL)
1392 return (SYSCON_READ_4(sc->syscon, EMAC_CLK_REG));
1393 else if (sc->res[_RES_SYSCON] != NULL)
1394 return (bus_read_4(sc->res[_RES_SYSCON], 0));
1395
1396 return (0);
1397 }
1398
1399 static void
syscon_write_emac_clk_reg(device_t dev,uint32_t val)1400 syscon_write_emac_clk_reg(device_t dev, uint32_t val)
1401 {
1402 struct awg_softc *sc;
1403
1404 sc = device_get_softc(dev);
1405 if (sc->syscon != NULL)
1406 SYSCON_WRITE_4(sc->syscon, EMAC_CLK_REG, val);
1407 else if (sc->res[_RES_SYSCON] != NULL)
1408 bus_write_4(sc->res[_RES_SYSCON], 0, val);
1409 }
1410
1411 /*
1412 * PHY functions
1413 */
1414
1415 static phandle_t
awg_get_phy_node(device_t dev)1416 awg_get_phy_node(device_t dev)
1417 {
1418 phandle_t node;
1419 pcell_t phy_handle;
1420
1421 node = ofw_bus_get_node(dev);
1422 if (OF_getencprop(node, "phy-handle", (void *)&phy_handle,
1423 sizeof(phy_handle)) <= 0)
1424 return (0);
1425
1426 return (OF_node_from_xref(phy_handle));
1427 }
1428
1429 static bool
awg_has_internal_phy(device_t dev)1430 awg_has_internal_phy(device_t dev)
1431 {
1432 phandle_t node, phy_node;
1433
1434 node = ofw_bus_get_node(dev);
1435 /* Legacy binding */
1436 if (OF_hasprop(node, "allwinner,use-internal-phy"))
1437 return (true);
1438
1439 phy_node = awg_get_phy_node(dev);
1440 return (phy_node != 0 && ofw_bus_node_is_compatible(OF_parent(phy_node),
1441 "allwinner,sun8i-h3-mdio-internal") != 0);
1442 }
1443
1444 static int
awg_parse_delay(device_t dev,uint32_t * tx_delay,uint32_t * rx_delay)1445 awg_parse_delay(device_t dev, uint32_t *tx_delay, uint32_t *rx_delay)
1446 {
1447 phandle_t node;
1448 uint32_t delay;
1449
1450 if (tx_delay == NULL || rx_delay == NULL)
1451 return (EINVAL);
1452 *tx_delay = *rx_delay = 0;
1453 node = ofw_bus_get_node(dev);
1454
1455 if (OF_getencprop(node, "tx-delay", &delay, sizeof(delay)) >= 0)
1456 *tx_delay = delay;
1457 else if (OF_getencprop(node, "allwinner,tx-delay-ps", &delay,
1458 sizeof(delay)) >= 0) {
1459 if ((delay % 100) != 0) {
1460 device_printf(dev, "tx-delay-ps is not a multiple of 100\n");
1461 return (EDOM);
1462 }
1463 *tx_delay = delay / 100;
1464 }
1465 if (*tx_delay > 7) {
1466 device_printf(dev, "tx-delay out of range\n");
1467 return (ERANGE);
1468 }
1469
1470 if (OF_getencprop(node, "rx-delay", &delay, sizeof(delay)) >= 0)
1471 *rx_delay = delay;
1472 else if (OF_getencprop(node, "allwinner,rx-delay-ps", &delay,
1473 sizeof(delay)) >= 0) {
1474 if ((delay % 100) != 0) {
1475 device_printf(dev, "rx-delay-ps is not within documented domain\n");
1476 return (EDOM);
1477 }
1478 *rx_delay = delay / 100;
1479 }
1480 if (*rx_delay > 31) {
1481 device_printf(dev, "rx-delay out of range\n");
1482 return (ERANGE);
1483 }
1484
1485 return (0);
1486 }
1487
1488 static int
awg_setup_phy(device_t dev)1489 awg_setup_phy(device_t dev)
1490 {
1491 struct awg_softc *sc;
1492 clk_t clk_tx, clk_tx_parent;
1493 const char *tx_parent_name;
1494 char *phy_type;
1495 phandle_t node;
1496 uint32_t reg, tx_delay, rx_delay;
1497 int error;
1498 bool use_syscon;
1499
1500 sc = device_get_softc(dev);
1501 node = ofw_bus_get_node(dev);
1502 use_syscon = false;
1503
1504 if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_type) == 0)
1505 return (0);
1506
1507 if (sc->syscon != NULL || sc->res[_RES_SYSCON] != NULL)
1508 use_syscon = true;
1509
1510 if (bootverbose)
1511 device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type,
1512 use_syscon ? "reg" : "clk");
1513
1514 if (use_syscon) {
1515 /*
1516 * Abstract away writing to syscon for devices like the pine64.
1517 * For the pine64, we get dtb from U-Boot and it still uses the
1518 * legacy setup of specifying syscon register in emac node
1519 * rather than as its own node and using an xref in emac.
1520 * These abstractions can go away once U-Boot dts is up-to-date.
1521 */
1522 reg = syscon_read_emac_clk_reg(dev);
1523 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN);
1524 if (strncmp(phy_type, "rgmii", 5) == 0)
1525 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII;
1526 else if (strcmp(phy_type, "rmii") == 0)
1527 reg |= EMAC_CLK_RMII_EN;
1528 else
1529 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII;
1530
1531 /*
1532 * Fail attach if we fail to parse either of the delay
1533 * parameters. If we don't have the proper delay to write to
1534 * syscon, then awg likely won't function properly anyways.
1535 * Lack of delay is not an error!
1536 */
1537 error = awg_parse_delay(dev, &tx_delay, &rx_delay);
1538 if (error != 0)
1539 goto fail;
1540
1541 /* Default to 0 and we'll increase it if we need to. */
1542 reg &= ~(EMAC_CLK_ETXDC | EMAC_CLK_ERXDC);
1543 if (tx_delay > 0)
1544 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT);
1545 if (rx_delay > 0)
1546 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT);
1547
1548 if (sc->type == EMAC_H3) {
1549 if (awg_has_internal_phy(dev)) {
1550 reg |= EMAC_CLK_EPHY_SELECT;
1551 reg &= ~EMAC_CLK_EPHY_SHUTDOWN;
1552 if (OF_hasprop(node,
1553 "allwinner,leds-active-low"))
1554 reg |= EMAC_CLK_EPHY_LED_POL;
1555 else
1556 reg &= ~EMAC_CLK_EPHY_LED_POL;
1557
1558 /* Set internal PHY addr to 1 */
1559 reg &= ~EMAC_CLK_EPHY_ADDR;
1560 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT);
1561 } else {
1562 reg &= ~EMAC_CLK_EPHY_SELECT;
1563 }
1564 }
1565
1566 if (bootverbose)
1567 device_printf(dev, "EMAC clock: 0x%08x\n", reg);
1568 syscon_write_emac_clk_reg(dev, reg);
1569 } else {
1570 if (strncmp(phy_type, "rgmii", 5) == 0)
1571 tx_parent_name = "emac_int_tx";
1572 else
1573 tx_parent_name = "mii_phy_tx";
1574
1575 /* Get the TX clock */
1576 error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx);
1577 if (error != 0) {
1578 device_printf(dev, "cannot get tx clock\n");
1579 goto fail;
1580 }
1581
1582 /* Find the desired parent clock based on phy-mode property */
1583 error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent);
1584 if (error != 0) {
1585 device_printf(dev, "cannot get clock '%s'\n",
1586 tx_parent_name);
1587 goto fail;
1588 }
1589
1590 /* Set TX clock parent */
1591 error = clk_set_parent_by_clk(clk_tx, clk_tx_parent);
1592 if (error != 0) {
1593 device_printf(dev, "cannot set tx clock parent\n");
1594 goto fail;
1595 }
1596
1597 /* Enable TX clock */
1598 error = clk_enable(clk_tx);
1599 if (error != 0) {
1600 device_printf(dev, "cannot enable tx clock\n");
1601 goto fail;
1602 }
1603 }
1604
1605 error = 0;
1606
1607 fail:
1608 OF_prop_free(phy_type);
1609 return (error);
1610 }
1611
1612 static int
awg_setup_extres(device_t dev)1613 awg_setup_extres(device_t dev)
1614 {
1615 struct awg_softc *sc;
1616 phandle_t node, phy_node;
1617 hwreset_t rst_ahb, rst_ephy;
1618 clk_t clk_ahb, clk_ephy;
1619 regulator_t reg;
1620 uint64_t freq;
1621 int error, div;
1622
1623 sc = device_get_softc(dev);
1624 rst_ahb = rst_ephy = NULL;
1625 clk_ahb = clk_ephy = NULL;
1626 reg = NULL;
1627 node = ofw_bus_get_node(dev);
1628 phy_node = awg_get_phy_node(dev);
1629
1630 if (phy_node == 0 && OF_hasprop(node, "phy-handle")) {
1631 error = ENXIO;
1632 device_printf(dev, "cannot get phy handle\n");
1633 goto fail;
1634 }
1635
1636 /* Get AHB clock and reset resources */
1637 error = hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst_ahb);
1638 if (error != 0)
1639 error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb);
1640 if (error != 0) {
1641 device_printf(dev, "cannot get ahb reset\n");
1642 goto fail;
1643 }
1644 if (hwreset_get_by_ofw_name(dev, 0, "ephy", &rst_ephy) != 0)
1645 if (phy_node == 0 || hwreset_get_by_ofw_idx(dev, phy_node, 0,
1646 &rst_ephy) != 0)
1647 rst_ephy = NULL;
1648 error = clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk_ahb);
1649 if (error != 0)
1650 error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb);
1651 if (error != 0) {
1652 device_printf(dev, "cannot get ahb clock\n");
1653 goto fail;
1654 }
1655 if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0)
1656 if (phy_node == 0 || clk_get_by_ofw_index(dev, phy_node, 0,
1657 &clk_ephy) != 0)
1658 clk_ephy = NULL;
1659
1660 if (OF_hasprop(node, "syscon") && syscon_get_by_ofw_property(dev, node,
1661 "syscon", &sc->syscon) != 0) {
1662 device_printf(dev, "cannot get syscon driver handle\n");
1663 goto fail;
1664 }
1665
1666 /* Configure PHY for MII or RGMII mode */
1667 if (awg_setup_phy(dev) != 0)
1668 goto fail;
1669
1670 /* Enable clocks */
1671 error = clk_enable(clk_ahb);
1672 if (error != 0) {
1673 device_printf(dev, "cannot enable ahb clock\n");
1674 goto fail;
1675 }
1676 if (clk_ephy != NULL) {
1677 error = clk_enable(clk_ephy);
1678 if (error != 0) {
1679 device_printf(dev, "cannot enable ephy clock\n");
1680 goto fail;
1681 }
1682 }
1683
1684 /* De-assert reset */
1685 error = hwreset_deassert(rst_ahb);
1686 if (error != 0) {
1687 device_printf(dev, "cannot de-assert ahb reset\n");
1688 goto fail;
1689 }
1690 if (rst_ephy != NULL) {
1691 /*
1692 * The ephy reset is left de-asserted by U-Boot. Assert it
1693 * here to make sure that we're in a known good state going
1694 * into the PHY reset.
1695 */
1696 hwreset_assert(rst_ephy);
1697 error = hwreset_deassert(rst_ephy);
1698 if (error != 0) {
1699 device_printf(dev, "cannot de-assert ephy reset\n");
1700 goto fail;
1701 }
1702 }
1703
1704 /* Enable PHY regulator if applicable */
1705 if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) {
1706 error = regulator_enable(reg);
1707 if (error != 0) {
1708 device_printf(dev, "cannot enable PHY regulator\n");
1709 goto fail;
1710 }
1711 }
1712
1713 /* Determine MDC clock divide ratio based on AHB clock */
1714 error = clk_get_freq(clk_ahb, &freq);
1715 if (error != 0) {
1716 device_printf(dev, "cannot get AHB clock frequency\n");
1717 goto fail;
1718 }
1719 div = freq / MDIO_FREQ;
1720 if (div <= 16)
1721 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16;
1722 else if (div <= 32)
1723 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32;
1724 else if (div <= 64)
1725 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64;
1726 else if (div <= 128)
1727 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128;
1728 else {
1729 device_printf(dev, "cannot determine MDC clock divide ratio\n");
1730 error = ENXIO;
1731 goto fail;
1732 }
1733
1734 if (bootverbose)
1735 device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n",
1736 (uintmax_t)freq, sc->mdc_div_ratio_m);
1737
1738 return (0);
1739
1740 fail:
1741 if (reg != NULL)
1742 regulator_release(reg);
1743 if (clk_ephy != NULL)
1744 clk_release(clk_ephy);
1745 if (clk_ahb != NULL)
1746 clk_release(clk_ahb);
1747 if (rst_ephy != NULL)
1748 hwreset_release(rst_ephy);
1749 if (rst_ahb != NULL)
1750 hwreset_release(rst_ahb);
1751 return (error);
1752 }
1753
1754 #ifdef AWG_DEBUG
1755 static void
awg_dump_regs(device_t dev)1756 awg_dump_regs(device_t dev)
1757 {
1758 static const struct {
1759 const char *name;
1760 u_int reg;
1761 } regs[] = {
1762 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 },
1763 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 },
1764 { "INT_STA", EMAC_INT_STA },
1765 { "INT_EN", EMAC_INT_EN },
1766 { "TX_CTL_0", EMAC_TX_CTL_0 },
1767 { "TX_CTL_1", EMAC_TX_CTL_1 },
1768 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL },
1769 { "TX_DMA_LIST", EMAC_TX_DMA_LIST },
1770 { "RX_CTL_0", EMAC_RX_CTL_0 },
1771 { "RX_CTL_1", EMAC_RX_CTL_1 },
1772 { "RX_DMA_LIST", EMAC_RX_DMA_LIST },
1773 { "RX_FRM_FLT", EMAC_RX_FRM_FLT },
1774 { "RX_HASH_0", EMAC_RX_HASH_0 },
1775 { "RX_HASH_1", EMAC_RX_HASH_1 },
1776 { "MII_CMD", EMAC_MII_CMD },
1777 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) },
1778 { "ADDR_LOW0", EMAC_ADDR_LOW(0) },
1779 { "TX_DMA_STA", EMAC_TX_DMA_STA },
1780 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC },
1781 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF },
1782 { "RX_DMA_STA", EMAC_RX_DMA_STA },
1783 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC },
1784 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF },
1785 { "RGMII_STA", EMAC_RGMII_STA },
1786 };
1787 struct awg_softc *sc;
1788 unsigned int n;
1789
1790 sc = device_get_softc(dev);
1791
1792 for (n = 0; n < nitems(regs); n++)
1793 device_printf(dev, " %-20s %08x\n", regs[n].name,
1794 RD4(sc, regs[n].reg));
1795 }
1796 #endif
1797
1798 #define GPIO_ACTIVE_LOW 1
1799
1800 static int
awg_phy_reset(device_t dev)1801 awg_phy_reset(device_t dev)
1802 {
1803 pcell_t gpio_prop[4], delay_prop[3];
1804 phandle_t node, gpio_node;
1805 device_t gpio;
1806 uint32_t pin, flags;
1807 uint32_t pin_value;
1808
1809 node = ofw_bus_get_node(dev);
1810 if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop,
1811 sizeof(gpio_prop)) <= 0)
1812 return (0);
1813
1814 if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop,
1815 sizeof(delay_prop)) <= 0)
1816 return (ENXIO);
1817
1818 gpio_node = OF_node_from_xref(gpio_prop[0]);
1819 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL)
1820 return (ENXIO);
1821
1822 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1,
1823 gpio_prop + 1, &pin, &flags) != 0)
1824 return (ENXIO);
1825
1826 pin_value = GPIO_PIN_LOW;
1827 if (OF_hasprop(node, "allwinner,reset-active-low"))
1828 pin_value = GPIO_PIN_HIGH;
1829
1830 if (flags & GPIO_ACTIVE_LOW)
1831 pin_value = !pin_value;
1832
1833 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
1834 GPIO_PIN_SET(gpio, pin, pin_value);
1835 DELAY(delay_prop[0]);
1836 GPIO_PIN_SET(gpio, pin, !pin_value);
1837 DELAY(delay_prop[1]);
1838 GPIO_PIN_SET(gpio, pin, pin_value);
1839 DELAY(delay_prop[2]);
1840
1841 return (0);
1842 }
1843
1844 static int
awg_reset(device_t dev)1845 awg_reset(device_t dev)
1846 {
1847 struct awg_softc *sc;
1848 int retry;
1849
1850 sc = device_get_softc(dev);
1851
1852 /* Reset PHY if necessary */
1853 if (awg_phy_reset(dev) != 0) {
1854 device_printf(dev, "failed to reset PHY\n");
1855 return (ENXIO);
1856 }
1857
1858 /* Soft reset all registers and logic */
1859 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
1860
1861 /* Wait for soft reset bit to self-clear */
1862 for (retry = SOFT_RST_RETRY; retry > 0; retry--) {
1863 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0)
1864 break;
1865 DELAY(10);
1866 }
1867 if (retry == 0) {
1868 device_printf(dev, "soft reset timed out\n");
1869 #ifdef AWG_DEBUG
1870 awg_dump_regs(dev);
1871 #endif
1872 return (ETIMEDOUT);
1873 }
1874
1875 return (0);
1876 }
1877
1878 /*
1879 * Stats
1880 */
1881
1882 static void
awg_tick(void * softc)1883 awg_tick(void *softc)
1884 {
1885 struct awg_softc *sc;
1886 struct mii_data *mii;
1887 if_t ifp;
1888 int link;
1889
1890 sc = softc;
1891 ifp = sc->ifp;
1892 mii = device_get_softc(sc->miibus);
1893
1894 AWG_ASSERT_LOCKED(sc);
1895
1896 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1897 return;
1898
1899 link = sc->link;
1900 mii_tick(mii);
1901 if (sc->link && !link)
1902 awg_start_locked(sc);
1903
1904 callout_reset(&sc->stat_ch, hz, awg_tick, sc);
1905 }
1906
1907 /*
1908 * Probe/attach functions
1909 */
1910
1911 static int
awg_probe(device_t dev)1912 awg_probe(device_t dev)
1913 {
1914 if (!ofw_bus_status_okay(dev))
1915 return (ENXIO);
1916
1917 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1918 return (ENXIO);
1919
1920 device_set_desc(dev, "Allwinner Gigabit Ethernet");
1921 return (BUS_PROBE_DEFAULT);
1922 }
1923
1924 static int
awg_attach(device_t dev)1925 awg_attach(device_t dev)
1926 {
1927 uint8_t eaddr[ETHER_ADDR_LEN];
1928 struct awg_softc *sc;
1929 int error;
1930
1931 sc = device_get_softc(dev);
1932 sc->dev = dev;
1933 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1934
1935 if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) {
1936 device_printf(dev, "cannot allocate resources for device\n");
1937 return (ENXIO);
1938 }
1939
1940 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF);
1941 callout_init_mtx(&sc->stat_ch, &sc->mtx, 0);
1942
1943 /* Setup clocks and regulators */
1944 error = awg_setup_extres(dev);
1945 if (error != 0)
1946 return (error);
1947
1948 /* Read MAC address before resetting the chip */
1949 awg_get_eaddr(dev, eaddr);
1950
1951 /* Soft reset EMAC core */
1952 error = awg_reset(dev);
1953 if (error != 0)
1954 return (error);
1955
1956 /* Setup DMA descriptors */
1957 error = awg_setup_dma(dev);
1958 if (error != 0)
1959 return (error);
1960
1961 /* Install interrupt handler */
1962 error = bus_setup_intr(dev, sc->res[_RES_IRQ],
1963 INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih);
1964 if (error != 0) {
1965 device_printf(dev, "cannot setup interrupt handler\n");
1966 return (error);
1967 }
1968
1969 /* Setup ethernet interface */
1970 sc->ifp = if_alloc(IFT_ETHER);
1971 if_setsoftc(sc->ifp, sc);
1972 if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev));
1973 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1974 if_setstartfn(sc->ifp, awg_start);
1975 if_setioctlfn(sc->ifp, awg_ioctl);
1976 if_setinitfn(sc->ifp, awg_init);
1977 if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1);
1978 if_setsendqready(sc->ifp);
1979 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP);
1980 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM);
1981 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp));
1982 #ifdef DEVICE_POLLING
1983 if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0);
1984 #endif
1985
1986 /* Attach MII driver */
1987 error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change,
1988 awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
1989 MIIF_DOPAUSE);
1990 if (error != 0) {
1991 device_printf(dev, "cannot attach PHY\n");
1992 return (error);
1993 }
1994
1995 /* Attach ethernet interface */
1996 ether_ifattach(sc->ifp, eaddr);
1997
1998 return (0);
1999 }
2000
2001 static device_method_t awg_methods[] = {
2002 /* Device interface */
2003 DEVMETHOD(device_probe, awg_probe),
2004 DEVMETHOD(device_attach, awg_attach),
2005
2006 /* MII interface */
2007 DEVMETHOD(miibus_readreg, awg_miibus_readreg),
2008 DEVMETHOD(miibus_writereg, awg_miibus_writereg),
2009 DEVMETHOD(miibus_statchg, awg_miibus_statchg),
2010
2011 DEVMETHOD_END
2012 };
2013
2014 static driver_t awg_driver = {
2015 "awg",
2016 awg_methods,
2017 sizeof(struct awg_softc),
2018 };
2019
2020 DRIVER_MODULE(awg, simplebus, awg_driver, 0, 0);
2021 DRIVER_MODULE(miibus, awg, miibus_driver, 0, 0);
2022 MODULE_DEPEND(awg, ether, 1, 1, 1);
2023 MODULE_DEPEND(awg, miibus, 1, 1, 1);
2024 MODULE_DEPEND(awg, aw_sid, 1, 1, 1);
2025 SIMPLEBUS_PNP_INFO(compat_data);
2026