1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15 * redistribution must be conditioned upon including a substantially
16 * similar Disclaimer requirement for further binary redistribution.
17 *
18 * NO WARRANTY
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGES.
30 */
31
32 #include <sys/cdefs.h>
33 /*
34 * Driver for the Atheros Wireless LAN controller.
35 *
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
38 */
39
40 #include "opt_inet.h"
41 #include "opt_ath.h"
42 /*
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
45 *
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
48 */
49 #include "opt_ah.h"
50 #include "opt_wlan.h"
51
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
55 #include <sys/mbuf.h>
56 #include <sys/malloc.h>
57 #include <sys/lock.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
64 #include <sys/bus.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
68 #include <sys/priv.h>
69 #include <sys/module.h>
70 #include <sys/ktr.h>
71 #include <sys/smp.h> /* for mp_ncpus */
72
73 #include <machine/bus.h>
74
75 #include <net/if.h>
76 #include <net/if_var.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_arp.h>
81 #include <net/ethernet.h>
82 #include <net/if_llc.h>
83
84 #include <net80211/ieee80211_var.h>
85 #include <net80211/ieee80211_regdomain.h>
86 #ifdef IEEE80211_SUPPORT_SUPERG
87 #include <net80211/ieee80211_superg.h>
88 #endif
89 #ifdef IEEE80211_SUPPORT_TDMA
90 #include <net80211/ieee80211_tdma.h>
91 #endif
92
93 #include <net/bpf.h>
94
95 #ifdef INET
96 #include <netinet/in.h>
97 #include <netinet/if_ether.h>
98 #endif
99
100 #include <dev/ath/if_athvar.h>
101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
102 #include <dev/ath/ath_hal/ah_diagcodes.h>
103
104 #include <dev/ath/if_ath_debug.h>
105 #include <dev/ath/if_ath_misc.h>
106 #include <dev/ath/if_ath_tsf.h>
107 #include <dev/ath/if_ath_tx.h>
108 #include <dev/ath/if_ath_sysctl.h>
109 #include <dev/ath/if_ath_led.h>
110 #include <dev/ath/if_ath_keycache.h>
111 #include <dev/ath/if_ath_rx.h>
112 #include <dev/ath/if_ath_rx_edma.h>
113 #include <dev/ath/if_ath_tx_edma.h>
114 #include <dev/ath/if_ath_beacon.h>
115 #include <dev/ath/if_ath_btcoex.h>
116 #include <dev/ath/if_ath_btcoex_mci.h>
117 #include <dev/ath/if_ath_spectral.h>
118 #include <dev/ath/if_ath_lna_div.h>
119 #include <dev/ath/if_athdfs.h>
120 #include <dev/ath/if_ath_ioctl.h>
121 #include <dev/ath/if_ath_descdma.h>
122
123 #ifdef ATH_TX99_DIAG
124 #include <dev/ath/ath_tx99/ath_tx99.h>
125 #endif
126
127 #ifdef ATH_DEBUG_ALQ
128 #include <dev/ath/if_ath_alq.h>
129 #endif
130
131 /*
132 * Only enable this if you're working on PS-POLL support.
133 */
134 #define ATH_SW_PSQ
135
136 /*
137 * ATH_BCBUF determines the number of vap's that can transmit
138 * beacons and also (currently) the number of vap's that can
139 * have unique mac addresses/bssid. When staggering beacons
140 * 4 is probably a good max as otherwise the beacons become
141 * very closely spaced and there is limited time for cab q traffic
142 * to go out. You can burst beacons instead but that is not good
143 * for stations in power save and at some point you really want
144 * another radio (and channel).
145 *
146 * The limit on the number of mac addresses is tied to our use of
147 * the U/L bit and tracking addresses in a byte; it would be
148 * worthwhile to allow more for applications like proxy sta.
149 */
150 CTASSERT(ATH_BCBUF <= 8);
151
152 static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
153 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
154 const uint8_t [IEEE80211_ADDR_LEN],
155 const uint8_t [IEEE80211_ADDR_LEN]);
156 static void ath_vap_delete(struct ieee80211vap *);
157 static int ath_init(struct ath_softc *);
158 static void ath_stop(struct ath_softc *);
159 static int ath_reset_vap(struct ieee80211vap *, u_long);
160 static int ath_transmit(struct ieee80211com *, struct mbuf *);
161 static void ath_watchdog(void *);
162 static void ath_parent(struct ieee80211com *);
163 static void ath_fatal_proc(void *, int);
164 static void ath_bmiss_vap(struct ieee80211vap *);
165 static void ath_bmiss_proc(void *, int);
166 static void ath_tsfoor_proc(void *, int);
167 static void ath_key_update_begin(struct ieee80211vap *);
168 static void ath_key_update_end(struct ieee80211vap *);
169 static void ath_update_mcast_hw(struct ath_softc *);
170 static void ath_update_mcast(struct ieee80211com *);
171 static void ath_update_promisc(struct ieee80211com *);
172 static void ath_updateslot(struct ieee80211com *);
173 static void ath_bstuck_proc(void *, int);
174 static void ath_reset_proc(void *, int);
175 static int ath_desc_alloc(struct ath_softc *);
176 static void ath_desc_free(struct ath_softc *);
177 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *,
178 const uint8_t [IEEE80211_ADDR_LEN]);
179 static void ath_node_cleanup(struct ieee80211_node *);
180 static void ath_node_free(struct ieee80211_node *);
181 static void ath_node_getsignal(const struct ieee80211_node *,
182 int8_t *, int8_t *);
183 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
184 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
185 static int ath_tx_setup(struct ath_softc *, int, int);
186 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
187 static void ath_tx_cleanup(struct ath_softc *);
188 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq,
189 int dosched);
190 static void ath_tx_proc_q0(void *, int);
191 static void ath_tx_proc_q0123(void *, int);
192 static void ath_tx_proc(void *, int);
193 static void ath_txq_sched_tasklet(void *, int);
194 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
195 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
196 static void ath_scan_start(struct ieee80211com *);
197 static void ath_scan_end(struct ieee80211com *);
198 static void ath_set_channel(struct ieee80211com *);
199 #ifdef ATH_ENABLE_11N
200 static void ath_update_chw(struct ieee80211com *);
201 #endif /* ATH_ENABLE_11N */
202 static int ath_set_quiet_ie(struct ieee80211_node *, uint8_t *);
203 static void ath_calibrate(void *);
204 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int);
205 static void ath_setup_stationkey(struct ieee80211_node *);
206 static void ath_newassoc(struct ieee80211_node *, int);
207 static int ath_setregdomain(struct ieee80211com *,
208 struct ieee80211_regdomain *, int,
209 struct ieee80211_channel []);
210 static void ath_getradiocaps(struct ieee80211com *, int, int *,
211 struct ieee80211_channel []);
212 static int ath_getchannels(struct ath_softc *);
213
214 static int ath_rate_setup(struct ath_softc *, u_int mode);
215 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
216
217 static void ath_announce(struct ath_softc *);
218
219 static void ath_dfs_tasklet(void *, int);
220 static void ath_node_powersave(struct ieee80211_node *, int);
221 static int ath_node_set_tim(struct ieee80211_node *, int);
222 static void ath_node_recv_pspoll(struct ieee80211_node *, struct mbuf *);
223
224 #ifdef IEEE80211_SUPPORT_TDMA
225 #include <dev/ath/if_ath_tdma.h>
226 #endif
227
228 SYSCTL_DECL(_hw_ath);
229
230 /* XXX validate sysctl values */
231 static int ath_longcalinterval = 30; /* long cals every 30 secs */
232 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval,
233 0, "long chip calibration interval (secs)");
234 static int ath_shortcalinterval = 100; /* short cals every 100 ms */
235 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval,
236 0, "short chip calibration interval (msecs)");
237 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */
238 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval,
239 0, "reset chip calibration results (secs)");
240 static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */
241 SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval,
242 0, "ANI calibration (msecs)");
243
244 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
245 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RWTUN, &ath_rxbuf,
246 0, "rx buffers allocated");
247 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
248 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RWTUN, &ath_txbuf,
249 0, "tx buffers allocated");
250 int ath_txbuf_mgmt = ATH_MGMT_TXBUF; /* # mgmt tx buffers to allocate */
251 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf_mgmt, CTLFLAG_RWTUN, &ath_txbuf_mgmt,
252 0, "tx (mgmt) buffers allocated");
253
254 int ath_bstuck_threshold = 4; /* max missed beacons */
255 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold,
256 0, "max missed beacon xmits before chip reset");
257
258 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
259
260 void
ath_legacy_attach_comp_func(struct ath_softc * sc)261 ath_legacy_attach_comp_func(struct ath_softc *sc)
262 {
263
264 /*
265 * Special case certain configurations. Note the
266 * CAB queue is handled by these specially so don't
267 * include them when checking the txq setup mask.
268 */
269 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
270 case 0x01:
271 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
272 break;
273 case 0x0f:
274 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
275 break;
276 default:
277 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
278 break;
279 }
280 }
281
282 /*
283 * Set the target power mode.
284 *
285 * If this is called during a point in time where
286 * the hardware is being programmed elsewhere, it will
287 * simply store it away and update it when all current
288 * uses of the hardware are completed.
289 *
290 * If the chip is going into network sleep or power off, then
291 * we will wait until all uses of the chip are done before
292 * going into network sleep or power off.
293 *
294 * If the chip is being programmed full-awake, then immediately
295 * program it full-awake so we can actually stay awake rather than
296 * the chip potentially going to sleep underneath us.
297 */
298 void
_ath_power_setpower(struct ath_softc * sc,int power_state,int selfgen,const char * file,int line)299 _ath_power_setpower(struct ath_softc *sc, int power_state, int selfgen,
300 const char *file, int line)
301 {
302 ATH_LOCK_ASSERT(sc);
303
304 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d, target=%d, cur=%d\n",
305 __func__,
306 file,
307 line,
308 power_state,
309 sc->sc_powersave_refcnt,
310 sc->sc_target_powerstate,
311 sc->sc_cur_powerstate);
312
313 sc->sc_target_powerstate = power_state;
314
315 /*
316 * Don't program the chip into network sleep if the chip
317 * is being programmed elsewhere.
318 *
319 * However, if the chip is being programmed /awake/, force
320 * the chip awake so we stay awake.
321 */
322 if ((sc->sc_powersave_refcnt == 0 || power_state == HAL_PM_AWAKE) &&
323 power_state != sc->sc_cur_powerstate) {
324 sc->sc_cur_powerstate = power_state;
325 ath_hal_setpower(sc->sc_ah, power_state);
326
327 /*
328 * If the NIC is force-awake, then set the
329 * self-gen frame state appropriately.
330 *
331 * If the nic is in network sleep or full-sleep,
332 * we let the above call leave the self-gen
333 * state as "sleep".
334 */
335 if (selfgen &&
336 sc->sc_cur_powerstate == HAL_PM_AWAKE &&
337 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
338 ath_hal_setselfgenpower(sc->sc_ah,
339 sc->sc_target_selfgen_state);
340 }
341 }
342 }
343
344 /*
345 * Set the current self-generated frames state.
346 *
347 * This is separate from the target power mode. The chip may be
348 * awake but the desired state is "sleep", so frames sent to the
349 * destination has PWRMGT=1 in the 802.11 header. The NIC also
350 * needs to know to set PWRMGT=1 in self-generated frames.
351 */
352 void
_ath_power_set_selfgen(struct ath_softc * sc,int power_state,const char * file,int line)353 _ath_power_set_selfgen(struct ath_softc *sc, int power_state, const char *file, int line)
354 {
355
356 ATH_LOCK_ASSERT(sc);
357
358 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
359 __func__,
360 file,
361 line,
362 power_state,
363 sc->sc_target_selfgen_state);
364
365 sc->sc_target_selfgen_state = power_state;
366
367 /*
368 * If the NIC is force-awake, then set the power state.
369 * Network-state and full-sleep will already transition it to
370 * mark self-gen frames as sleeping - and we can't
371 * guarantee the NIC is awake to program the self-gen frame
372 * setting anyway.
373 */
374 if (sc->sc_cur_powerstate == HAL_PM_AWAKE) {
375 ath_hal_setselfgenpower(sc->sc_ah, power_state);
376 }
377 }
378
379 /*
380 * Set the hardware power mode and take a reference.
381 *
382 * This doesn't update the target power mode in the driver;
383 * it just updates the hardware power state.
384 *
385 * XXX it should only ever force the hardware awake; it should
386 * never be called to set it asleep.
387 */
388 void
_ath_power_set_power_state(struct ath_softc * sc,int power_state,const char * file,int line)389 _ath_power_set_power_state(struct ath_softc *sc, int power_state, const char *file, int line)
390 {
391 ATH_LOCK_ASSERT(sc);
392
393 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
394 __func__,
395 file,
396 line,
397 power_state,
398 sc->sc_powersave_refcnt);
399
400 sc->sc_powersave_refcnt++;
401
402 /*
403 * Only do the power state change if we're not programming
404 * it elsewhere.
405 */
406 if (power_state != sc->sc_cur_powerstate) {
407 ath_hal_setpower(sc->sc_ah, power_state);
408 sc->sc_cur_powerstate = power_state;
409 /*
410 * Adjust the self-gen powerstate if appropriate.
411 */
412 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
413 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
414 ath_hal_setselfgenpower(sc->sc_ah,
415 sc->sc_target_selfgen_state);
416 }
417 }
418 }
419
420 /*
421 * Restore the power save mode to what it once was.
422 *
423 * This will decrement the reference counter and once it hits
424 * zero, it'll restore the powersave state.
425 */
426 void
_ath_power_restore_power_state(struct ath_softc * sc,const char * file,int line)427 _ath_power_restore_power_state(struct ath_softc *sc, const char *file, int line)
428 {
429
430 ATH_LOCK_ASSERT(sc);
431
432 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) refcnt=%d, target state=%d\n",
433 __func__,
434 file,
435 line,
436 sc->sc_powersave_refcnt,
437 sc->sc_target_powerstate);
438
439 if (sc->sc_powersave_refcnt == 0)
440 device_printf(sc->sc_dev, "%s: refcnt=0?\n", __func__);
441 else
442 sc->sc_powersave_refcnt--;
443
444 if (sc->sc_powersave_refcnt == 0 &&
445 sc->sc_target_powerstate != sc->sc_cur_powerstate) {
446 sc->sc_cur_powerstate = sc->sc_target_powerstate;
447 ath_hal_setpower(sc->sc_ah, sc->sc_target_powerstate);
448 }
449
450 /*
451 * Adjust the self-gen powerstate if appropriate.
452 */
453 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
454 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
455 ath_hal_setselfgenpower(sc->sc_ah,
456 sc->sc_target_selfgen_state);
457 }
458
459 }
460
461 /*
462 * Configure the initial HAL configuration values based on bus
463 * specific parameters.
464 *
465 * Some PCI IDs and other information may need tweaking.
466 *
467 * XXX TODO: ath9k and the Atheros HAL only program comm2g_switch_enable
468 * if BT antenna diversity isn't enabled.
469 *
470 * So, let's also figure out how to enable BT diversity for AR9485.
471 */
472 static void
ath_setup_hal_config(struct ath_softc * sc,HAL_OPS_CONFIG * ah_config)473 ath_setup_hal_config(struct ath_softc *sc, HAL_OPS_CONFIG *ah_config)
474 {
475 /* XXX TODO: only for PCI devices? */
476
477 if (sc->sc_pci_devinfo & (ATH_PCI_CUS198 | ATH_PCI_CUS230)) {
478 ah_config->ath_hal_ext_lna_ctl_gpio = 0x200; /* bit 9 */
479 ah_config->ath_hal_ext_atten_margin_cfg = AH_TRUE;
480 ah_config->ath_hal_min_gainidx = AH_TRUE;
481 ah_config->ath_hal_ant_ctrl_comm2g_switch_enable = 0x000bbb88;
482 /* XXX low_rssi_thresh */
483 /* XXX fast_div_bias */
484 device_printf(sc->sc_dev, "configuring for %s\n",
485 (sc->sc_pci_devinfo & ATH_PCI_CUS198) ?
486 "CUS198" : "CUS230");
487 }
488
489 if (sc->sc_pci_devinfo & ATH_PCI_CUS217)
490 device_printf(sc->sc_dev, "CUS217 card detected\n");
491
492 if (sc->sc_pci_devinfo & ATH_PCI_CUS252)
493 device_printf(sc->sc_dev, "CUS252 card detected\n");
494
495 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_1ANT)
496 device_printf(sc->sc_dev, "WB335 1-ANT card detected\n");
497
498 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_2ANT)
499 device_printf(sc->sc_dev, "WB335 2-ANT card detected\n");
500
501 if (sc->sc_pci_devinfo & ATH_PCI_BT_ANT_DIV)
502 device_printf(sc->sc_dev,
503 "Bluetooth Antenna Diversity card detected\n");
504
505 if (sc->sc_pci_devinfo & ATH_PCI_KILLER)
506 device_printf(sc->sc_dev, "Killer Wireless card detected\n");
507
508 #if 0
509 /*
510 * Some WB335 cards do not support antenna diversity. Since
511 * we use a hardcoded value for AR9565 instead of using the
512 * EEPROM/OTP data, remove the combining feature from
513 * the HW capabilities bitmap.
514 */
515 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
516 if (!(sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV))
517 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
518 }
519
520 if (sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV) {
521 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
522 device_printf(sc->sc_dev, "Set BT/WLAN RX diversity capability\n");
523 }
524 #endif
525
526 if (sc->sc_pci_devinfo & ATH_PCI_D3_L1_WAR) {
527 ah_config->ath_hal_pcie_waen = 0x0040473b;
528 device_printf(sc->sc_dev, "Enable WAR for ASPM D3/L1\n");
529 }
530
531 #if 0
532 if (sc->sc_pci_devinfo & ATH9K_PCI_NO_PLL_PWRSAVE) {
533 ah->config.no_pll_pwrsave = true;
534 device_printf(sc->sc_dev, "Disable PLL PowerSave\n");
535 }
536 #endif
537
538 }
539
540 /*
541 * Attempt to fetch the MAC address from the kernel environment.
542 *
543 * Returns 0, macaddr in macaddr if successful; -1 otherwise.
544 */
545 static int
ath_fetch_mac_kenv(struct ath_softc * sc,uint8_t * macaddr)546 ath_fetch_mac_kenv(struct ath_softc *sc, uint8_t *macaddr)
547 {
548 char devid_str[32];
549 int local_mac = 0;
550 char *local_macstr;
551
552 /*
553 * Fetch from the kenv rather than using hints.
554 *
555 * Hints would be nice but the transition to dynamic
556 * hints/kenv doesn't happen early enough for this
557 * to work reliably (eg on anything embedded.)
558 */
559 snprintf(devid_str, 32, "hint.%s.%d.macaddr",
560 device_get_name(sc->sc_dev),
561 device_get_unit(sc->sc_dev));
562
563 if ((local_macstr = kern_getenv(devid_str)) != NULL) {
564 uint32_t tmpmac[ETHER_ADDR_LEN];
565 int count;
566 int i;
567
568 /* Have a MAC address; should use it */
569 device_printf(sc->sc_dev,
570 "Overriding MAC address from environment: '%s'\n",
571 local_macstr);
572
573 /* Extract out the MAC address */
574 count = sscanf(local_macstr, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
575 &tmpmac[0], &tmpmac[1],
576 &tmpmac[2], &tmpmac[3],
577 &tmpmac[4], &tmpmac[5]);
578 if (count == 6) {
579 /* Valid! */
580 local_mac = 1;
581 for (i = 0; i < ETHER_ADDR_LEN; i++)
582 macaddr[i] = tmpmac[i];
583 }
584 /* Done! */
585 freeenv(local_macstr);
586 local_macstr = NULL;
587 }
588
589 if (local_mac)
590 return (0);
591 return (-1);
592 }
593
594 #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20)
595 #define HAL_MODE_HT40 \
596 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \
597 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)
598 int
ath_attach(u_int16_t devid,struct ath_softc * sc)599 ath_attach(u_int16_t devid, struct ath_softc *sc)
600 {
601 struct ieee80211com *ic = &sc->sc_ic;
602 struct ath_hal *ah = NULL;
603 HAL_STATUS status;
604 int error = 0, i;
605 u_int wmodes;
606 int rx_chainmask, tx_chainmask;
607 HAL_OPS_CONFIG ah_config;
608
609 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
610
611 ic->ic_softc = sc;
612 ic->ic_name = device_get_nameunit(sc->sc_dev);
613
614 /*
615 * Configure the initial configuration data.
616 *
617 * This is stuff that may be needed early during attach
618 * rather than done via configuration calls later.
619 */
620 bzero(&ah_config, sizeof(ah_config));
621 ath_setup_hal_config(sc, &ah_config);
622
623 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh,
624 sc->sc_eepromdata, &ah_config, &status);
625 if (ah == NULL) {
626 device_printf(sc->sc_dev,
627 "unable to attach hardware; HAL status %u\n", status);
628 error = ENXIO;
629 goto bad;
630 }
631 sc->sc_ah = ah;
632 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
633 #ifdef ATH_DEBUG
634 sc->sc_debug = ath_debug;
635 #endif
636
637 /*
638 * Force the chip awake during setup, just to keep
639 * the HAL/driver power tracking happy.
640 *
641 * There are some methods (eg ath_hal_setmac())
642 * that poke the hardware.
643 */
644 ATH_LOCK(sc);
645 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
646 ATH_UNLOCK(sc);
647
648 /*
649 * Setup the DMA/EDMA functions based on the current
650 * hardware support.
651 *
652 * This is required before the descriptors are allocated.
653 */
654 if (ath_hal_hasedma(sc->sc_ah)) {
655 sc->sc_isedma = 1;
656 ath_recv_setup_edma(sc);
657 ath_xmit_setup_edma(sc);
658 } else {
659 ath_recv_setup_legacy(sc);
660 ath_xmit_setup_legacy(sc);
661 }
662
663 if (ath_hal_hasmybeacon(sc->sc_ah)) {
664 sc->sc_do_mybeacon = 1;
665 }
666
667 /*
668 * Check if the MAC has multi-rate retry support.
669 * We do this by trying to setup a fake extended
670 * descriptor. MAC's that don't have support will
671 * return false w/o doing anything. MAC's that do
672 * support it will return true w/o doing anything.
673 */
674 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
675
676 /*
677 * Check if the device has hardware counters for PHY
678 * errors. If so we need to enable the MIB interrupt
679 * so we can act on stat triggers.
680 */
681 if (ath_hal_hwphycounters(ah))
682 sc->sc_needmib = 1;
683
684 /*
685 * Get the hardware key cache size.
686 */
687 sc->sc_keymax = ath_hal_keycachesize(ah);
688 if (sc->sc_keymax > ATH_KEYMAX) {
689 device_printf(sc->sc_dev,
690 "Warning, using only %u of %u key cache slots\n",
691 ATH_KEYMAX, sc->sc_keymax);
692 sc->sc_keymax = ATH_KEYMAX;
693 }
694 /*
695 * Reset the key cache since some parts do not
696 * reset the contents on initial power up.
697 */
698 for (i = 0; i < sc->sc_keymax; i++)
699 ath_hal_keyreset(ah, i);
700
701 /*
702 * Collect the default channel list.
703 */
704 error = ath_getchannels(sc);
705 if (error != 0)
706 goto bad;
707
708 /*
709 * Setup rate tables for all potential media types.
710 */
711 ath_rate_setup(sc, IEEE80211_MODE_11A);
712 ath_rate_setup(sc, IEEE80211_MODE_11B);
713 ath_rate_setup(sc, IEEE80211_MODE_11G);
714 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
715 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
716 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
717 ath_rate_setup(sc, IEEE80211_MODE_11NA);
718 ath_rate_setup(sc, IEEE80211_MODE_11NG);
719 ath_rate_setup(sc, IEEE80211_MODE_HALF);
720 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
721
722 /* NB: setup here so ath_rate_update is happy */
723 ath_setcurmode(sc, IEEE80211_MODE_11A);
724
725 /*
726 * Allocate TX descriptors and populate the lists.
727 */
728 error = ath_desc_alloc(sc);
729 if (error != 0) {
730 device_printf(sc->sc_dev,
731 "failed to allocate TX descriptors: %d\n", error);
732 goto bad;
733 }
734 error = ath_txdma_setup(sc);
735 if (error != 0) {
736 device_printf(sc->sc_dev,
737 "failed to allocate TX descriptors: %d\n", error);
738 goto bad;
739 }
740
741 /*
742 * Allocate RX descriptors and populate the lists.
743 */
744 error = ath_rxdma_setup(sc);
745 if (error != 0) {
746 device_printf(sc->sc_dev,
747 "failed to allocate RX descriptors: %d\n", error);
748 goto bad;
749 }
750
751 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0);
752 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0);
753
754 ATH_TXBUF_LOCK_INIT(sc);
755
756 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
757 taskqueue_thread_enqueue, &sc->sc_tq);
758 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
759 device_get_nameunit(sc->sc_dev));
760
761 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc);
762 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
763 TASK_INIT(&sc->sc_tsfoortask, 0, ath_tsfoor_proc, sc);
764 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
765 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc);
766 TASK_INIT(&sc->sc_txqtask, 0, ath_txq_sched_tasklet, sc);
767 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc);
768
769 /*
770 * Allocate hardware transmit queues: one queue for
771 * beacon frames and one data queue for each QoS
772 * priority. Note that the hal handles resetting
773 * these queues at the needed time.
774 *
775 * XXX PS-Poll
776 */
777 sc->sc_bhalq = ath_beaconq_setup(sc);
778 if (sc->sc_bhalq == (u_int) -1) {
779 device_printf(sc->sc_dev,
780 "unable to setup a beacon xmit queue!\n");
781 error = EIO;
782 goto bad2;
783 }
784 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
785 if (sc->sc_cabq == NULL) {
786 device_printf(sc->sc_dev, "unable to setup CAB xmit queue!\n");
787 error = EIO;
788 goto bad2;
789 }
790 /* NB: insure BK queue is the lowest priority h/w queue */
791 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
792 device_printf(sc->sc_dev,
793 "unable to setup xmit queue for %s traffic!\n",
794 ieee80211_wme_acnames[WME_AC_BK]);
795 error = EIO;
796 goto bad2;
797 }
798 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
799 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
800 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
801 /*
802 * Not enough hardware tx queues to properly do WME;
803 * just punt and assign them all to the same h/w queue.
804 * We could do a better job of this if, for example,
805 * we allocate queues when we switch from station to
806 * AP mode.
807 */
808 if (sc->sc_ac2q[WME_AC_VI] != NULL)
809 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
810 if (sc->sc_ac2q[WME_AC_BE] != NULL)
811 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
812 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
813 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
814 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
815 }
816
817 /*
818 * Attach the TX completion function.
819 *
820 * The non-EDMA chips may have some special case optimisations;
821 * this method gives everyone a chance to attach cleanly.
822 */
823 sc->sc_tx.xmit_attach_comp_func(sc);
824
825 /*
826 * Setup rate control. Some rate control modules
827 * call back to change the anntena state so expose
828 * the necessary entry points.
829 * XXX maybe belongs in struct ath_ratectrl?
830 */
831 sc->sc_setdefantenna = ath_setdefantenna;
832 sc->sc_rc = ath_rate_attach(sc);
833 if (sc->sc_rc == NULL) {
834 error = EIO;
835 goto bad2;
836 }
837
838 /* Attach DFS module */
839 if (! ath_dfs_attach(sc)) {
840 device_printf(sc->sc_dev,
841 "%s: unable to attach DFS\n", __func__);
842 error = EIO;
843 goto bad2;
844 }
845
846 /* Attach spectral module */
847 if (ath_spectral_attach(sc) < 0) {
848 device_printf(sc->sc_dev,
849 "%s: unable to attach spectral\n", __func__);
850 error = EIO;
851 goto bad2;
852 }
853
854 /* Attach bluetooth coexistence module */
855 if (ath_btcoex_attach(sc) < 0) {
856 device_printf(sc->sc_dev,
857 "%s: unable to attach bluetooth coexistence\n", __func__);
858 error = EIO;
859 goto bad2;
860 }
861
862 /* Attach LNA diversity module */
863 if (ath_lna_div_attach(sc) < 0) {
864 device_printf(sc->sc_dev,
865 "%s: unable to attach LNA diversity\n", __func__);
866 error = EIO;
867 goto bad2;
868 }
869
870 /* Start DFS processing tasklet */
871 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
872
873 /* Configure LED state */
874 sc->sc_blinking = 0;
875 sc->sc_ledstate = 1;
876 sc->sc_ledon = 0; /* low true */
877 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
878 callout_init(&sc->sc_ledtimer, 1);
879
880 /*
881 * Don't setup hardware-based blinking.
882 *
883 * Although some NICs may have this configured in the
884 * default reset register values, the user may wish
885 * to alter which pins have which function.
886 *
887 * The reference driver attaches the MAC network LED to GPIO1 and
888 * the MAC power LED to GPIO2. However, the DWA-552 cardbus
889 * NIC has these reversed.
890 */
891 sc->sc_hardled = (1 == 0);
892 sc->sc_led_net_pin = -1;
893 sc->sc_led_pwr_pin = -1;
894 /*
895 * Auto-enable soft led processing for IBM cards and for
896 * 5211 minipci cards. Users can also manually enable/disable
897 * support with a sysctl.
898 */
899 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
900 ath_led_config(sc);
901 ath_hal_setledstate(ah, HAL_LED_INIT);
902
903 /* XXX not right but it's not used anywhere important */
904 ic->ic_phytype = IEEE80211_T_OFDM;
905 ic->ic_opmode = IEEE80211_M_STA;
906 ic->ic_caps =
907 IEEE80211_C_STA /* station mode */
908 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
909 | IEEE80211_C_HOSTAP /* hostap mode */
910 | IEEE80211_C_MONITOR /* monitor mode */
911 | IEEE80211_C_AHDEMO /* adhoc demo mode */
912 | IEEE80211_C_WDS /* 4-address traffic works */
913 | IEEE80211_C_MBSS /* mesh point link mode */
914 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
915 | IEEE80211_C_SHSLOT /* short slot time supported */
916 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
917 #ifndef ATH_ENABLE_11N
918 | IEEE80211_C_BGSCAN /* capable of bg scanning */
919 #endif
920 | IEEE80211_C_TXFRAG /* handle tx frags */
921 #ifdef ATH_ENABLE_DFS
922 | IEEE80211_C_DFS /* Enable radar detection */
923 #endif
924 | IEEE80211_C_PMGT /* Station side power mgmt */
925 | IEEE80211_C_SWSLEEP
926 ;
927
928 ic->ic_flags_ext |= IEEE80211_FEXT_SEQNO_OFFLOAD;
929
930 /*
931 * Query the hal to figure out h/w crypto support.
932 */
933 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
934 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
935 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
936 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB;
937 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
938 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM;
939 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
940 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP;
941 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
942 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP;
943 /*
944 * Check if h/w does the MIC and/or whether the
945 * separate key cache entries are required to
946 * handle both tx+rx MIC keys.
947 */
948 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
949 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
950 /*
951 * If the h/w supports storing tx+rx MIC keys
952 * in one cache slot automatically enable use.
953 */
954 if (ath_hal_hastkipsplit(ah) ||
955 !ath_hal_settkipsplit(ah, AH_FALSE))
956 sc->sc_splitmic = 1;
957 /*
958 * If the h/w can do TKIP MIC together with WME then
959 * we use it; otherwise we force the MIC to be done
960 * in software by the net80211 layer.
961 */
962 if (ath_hal_haswmetkipmic(ah))
963 sc->sc_wmetkipmic = 1;
964 }
965 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
966 /*
967 * Check for multicast key search support.
968 */
969 if (ath_hal_hasmcastkeysearch(sc->sc_ah) &&
970 !ath_hal_getmcastkeysearch(sc->sc_ah)) {
971 ath_hal_setmcastkeysearch(sc->sc_ah, 1);
972 }
973 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
974 /*
975 * Mark key cache slots associated with global keys
976 * as in use. If we knew TKIP was not to be used we
977 * could leave the +32, +64, and +32+64 slots free.
978 */
979 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
980 setbit(sc->sc_keymap, i);
981 setbit(sc->sc_keymap, i+64);
982 if (sc->sc_splitmic) {
983 setbit(sc->sc_keymap, i+32);
984 setbit(sc->sc_keymap, i+32+64);
985 }
986 }
987 /*
988 * TPC support can be done either with a global cap or
989 * per-packet support. The latter is not available on
990 * all parts. We're a bit pedantic here as all parts
991 * support a global cap.
992 */
993 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
994 ic->ic_caps |= IEEE80211_C_TXPMGT;
995
996 /*
997 * Mark WME capability only if we have sufficient
998 * hardware queues to do proper priority scheduling.
999 */
1000 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
1001 ic->ic_caps |= IEEE80211_C_WME;
1002 /*
1003 * Check for misc other capabilities.
1004 */
1005 if (ath_hal_hasbursting(ah))
1006 ic->ic_caps |= IEEE80211_C_BURST;
1007 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
1008 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);
1009 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
1010 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah);
1011
1012 /* XXX TODO: just make this a "store tx/rx timestamp length" operation */
1013 if (ath_hal_get_rx_tsf_prec(ah, &i)) {
1014 if (i == 32) {
1015 sc->sc_rxtsf32 = 1;
1016 }
1017 if (bootverbose)
1018 device_printf(sc->sc_dev, "RX timestamp: %d bits\n", i);
1019 }
1020 if (ath_hal_get_tx_tsf_prec(ah, &i)) {
1021 if (bootverbose)
1022 device_printf(sc->sc_dev, "TX timestamp: %d bits\n", i);
1023 }
1024
1025 sc->sc_hasenforcetxop = ath_hal_hasenforcetxop(ah);
1026 sc->sc_rx_lnamixer = ath_hal_hasrxlnamixer(ah);
1027 sc->sc_hasdivcomb = ath_hal_hasdivantcomb(ah);
1028
1029 /*
1030 * Some WB335 cards do not support antenna diversity. Since
1031 * we use a hardcoded value for AR9565 instead of using the
1032 * EEPROM/OTP data, remove the combining feature from
1033 * the HW capabilities bitmap.
1034 */
1035 /*
1036 * XXX TODO: check reference driver and ath9k for what to do
1037 * here for WB335. I think we have to actually disable the
1038 * LNA div processing in the HAL and instead use the hard
1039 * coded values; and then use BT diversity.
1040 *
1041 * .. but also need to setup MCI too for WB335..
1042 */
1043 #if 0
1044 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
1045 device_printf(sc->sc_dev, "%s: WB335: disabling LNA mixer diversity\n",
1046 __func__);
1047 sc->sc_dolnadiv = 0;
1048 }
1049 #endif
1050
1051 if (ath_hal_hasfastframes(ah))
1052 ic->ic_caps |= IEEE80211_C_FF;
1053 wmodes = ath_hal_getwirelessmodes(ah);
1054 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO))
1055 ic->ic_caps |= IEEE80211_C_TURBOP;
1056 #ifdef IEEE80211_SUPPORT_TDMA
1057 if (ath_hal_macversion(ah) > 0x78) {
1058 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */
1059 ic->ic_tdma_update = ath_tdma_update;
1060 }
1061 #endif
1062
1063 /*
1064 * TODO: enforce that at least this many frames are available
1065 * in the txbuf list before allowing data frames (raw or
1066 * otherwise) to be transmitted.
1067 */
1068 sc->sc_txq_data_minfree = 10;
1069
1070 /*
1071 * Shorten this to 64 packets, or 1/4 ath_txbuf, whichever
1072 * is smaller.
1073 *
1074 * Anything bigger can potentially see the cabq consume
1075 * almost all buffers, starving everything else, only to
1076 * see most fail to transmit in the given beacon interval.
1077 */
1078 sc->sc_txq_mcastq_maxdepth = MIN(64, ath_txbuf / 4);
1079
1080 /*
1081 * How deep can the node software TX queue get whilst it's asleep.
1082 */
1083 sc->sc_txq_node_psq_maxdepth = 16;
1084
1085 /*
1086 * Default the maximum queue to 1/4'th the TX buffers, or
1087 * 128, whichever is smaller.
1088 *
1089 * Set it to 128 instead of the previous default (64) because
1090 * at 64, two full A-MPDU subframes of 32 frames each is
1091 * enough to treat this node queue as full and all subsequent
1092 * traffic is dropped. Setting it to 128 means there'll
1093 * hopefully be another 64 frames in the software queue
1094 * to begin making A-MPDU frames out of.
1095 */
1096 sc->sc_txq_node_maxdepth = MIN(128, ath_txbuf / 4);
1097
1098 /* Enable CABQ by default */
1099 sc->sc_cabq_enable = 1;
1100
1101 /*
1102 * Allow the TX and RX chainmasks to be overridden by
1103 * environment variables and/or device.hints.
1104 *
1105 * This must be done early - before the hardware is
1106 * calibrated or before the 802.11n stream calculation
1107 * is done.
1108 */
1109 if (resource_int_value(device_get_name(sc->sc_dev),
1110 device_get_unit(sc->sc_dev), "rx_chainmask",
1111 &rx_chainmask) == 0) {
1112 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n",
1113 rx_chainmask);
1114 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask);
1115 }
1116 if (resource_int_value(device_get_name(sc->sc_dev),
1117 device_get_unit(sc->sc_dev), "tx_chainmask",
1118 &tx_chainmask) == 0) {
1119 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n",
1120 tx_chainmask);
1121 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask);
1122 }
1123
1124 /*
1125 * Query the TX/RX chainmask configuration.
1126 *
1127 * This is only relevant for 11n devices.
1128 */
1129 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask);
1130 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask);
1131
1132 /*
1133 * Disable MRR with protected frames by default.
1134 * Only 802.11n series NICs can handle this.
1135 */
1136 sc->sc_mrrprot = 0; /* XXX should be a capability */
1137
1138 /*
1139 * Query the enterprise mode information the HAL.
1140 */
1141 if (ath_hal_getcapability(ah, HAL_CAP_ENTERPRISE_MODE, 0,
1142 &sc->sc_ent_cfg) == HAL_OK)
1143 sc->sc_use_ent = 1;
1144
1145 #ifdef ATH_ENABLE_11N
1146 /*
1147 * Query HT capabilities
1148 */
1149 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK &&
1150 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) {
1151 uint32_t rxs, txs;
1152 uint32_t ldpc;
1153
1154 device_printf(sc->sc_dev, "[HT] enabling HT modes\n");
1155
1156 sc->sc_mrrprot = 1; /* XXX should be a capability */
1157
1158 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */
1159 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */
1160 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */
1161 | IEEE80211_HTCAP_MAXAMSDU_3839
1162 /* max A-MSDU length */
1163 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */
1164
1165 /*
1166 * Enable short-GI for HT20 only if the hardware
1167 * advertises support.
1168 * Notably, anything earlier than the AR9287 doesn't.
1169 */
1170 if ((ath_hal_getcapability(ah,
1171 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) &&
1172 (wmodes & HAL_MODE_HT20)) {
1173 device_printf(sc->sc_dev,
1174 "[HT] enabling short-GI in 20MHz mode\n");
1175 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20;
1176 }
1177
1178 if (wmodes & HAL_MODE_HT40)
1179 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40
1180 | IEEE80211_HTCAP_SHORTGI40;
1181
1182 /*
1183 * TX/RX streams need to be taken into account when
1184 * negotiating which MCS rates it'll receive and
1185 * what MCS rates are available for TX.
1186 */
1187 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs);
1188 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs);
1189 ic->ic_txstream = txs;
1190 ic->ic_rxstream = rxs;
1191
1192 /*
1193 * Setup TX and RX STBC based on what the HAL allows and
1194 * the currently configured chainmask set.
1195 * Ie - don't enable STBC TX if only one chain is enabled.
1196 * STBC RX is fine on a single RX chain; it just won't
1197 * provide any real benefit.
1198 */
1199 if (ath_hal_getcapability(ah, HAL_CAP_RX_STBC, 0,
1200 NULL) == HAL_OK) {
1201 sc->sc_rx_stbc = 1;
1202 device_printf(sc->sc_dev,
1203 "[HT] 1 stream STBC receive enabled\n");
1204 ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_1STREAM;
1205 }
1206 if (txs > 1 && ath_hal_getcapability(ah, HAL_CAP_TX_STBC, 0,
1207 NULL) == HAL_OK) {
1208 sc->sc_tx_stbc = 1;
1209 device_printf(sc->sc_dev,
1210 "[HT] 1 stream STBC transmit enabled\n");
1211 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC;
1212 }
1213
1214 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1,
1215 &sc->sc_rts_aggr_limit);
1216 if (sc->sc_rts_aggr_limit != (64 * 1024))
1217 device_printf(sc->sc_dev,
1218 "[HT] RTS aggregates limited to %d KiB\n",
1219 sc->sc_rts_aggr_limit / 1024);
1220
1221 /*
1222 * LDPC
1223 */
1224 if ((ath_hal_getcapability(ah, HAL_CAP_LDPC, 0, &ldpc))
1225 == HAL_OK && (ldpc == 1)) {
1226 sc->sc_has_ldpc = 1;
1227 device_printf(sc->sc_dev,
1228 "[HT] LDPC transmit/receive enabled\n");
1229 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC |
1230 IEEE80211_HTC_TXLDPC;
1231 }
1232
1233 device_printf(sc->sc_dev,
1234 "[HT] %d RX streams; %d TX streams\n", rxs, txs);
1235 }
1236 #endif
1237
1238 /*
1239 * Initial aggregation settings.
1240 */
1241 sc->sc_hwq_limit_aggr = ATH_AGGR_MIN_QDEPTH;
1242 sc->sc_hwq_limit_nonaggr = ATH_NONAGGR_MIN_QDEPTH;
1243 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
1244 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
1245 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE;
1246 sc->sc_delim_min_pad = 0;
1247
1248 /*
1249 * Check if the hardware requires PCI register serialisation.
1250 * Some of the Owl based MACs require this.
1251 */
1252 if (mp_ncpus > 1 &&
1253 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
1254 0, NULL) == HAL_OK) {
1255 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
1256 device_printf(sc->sc_dev,
1257 "Enabling register serialisation\n");
1258 }
1259
1260 /*
1261 * Initialise the deferred completed RX buffer list.
1262 */
1263 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]);
1264 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]);
1265
1266 /*
1267 * Indicate we need the 802.11 header padded to a
1268 * 32-bit boundary for 4-address and QoS frames.
1269 */
1270 ic->ic_flags |= IEEE80211_F_DATAPAD;
1271
1272 /*
1273 * Query the hal about antenna support.
1274 */
1275 sc->sc_defant = ath_hal_getdefantenna(ah);
1276
1277 /*
1278 * Not all chips have the VEOL support we want to
1279 * use with IBSS beacons; check here for it.
1280 */
1281 sc->sc_hasveol = ath_hal_hasveol(ah);
1282
1283 /* get mac address from kenv first, then hardware */
1284 if (ath_fetch_mac_kenv(sc, ic->ic_macaddr) == 0) {
1285 /* Tell the HAL now about the new MAC */
1286 ath_hal_setmac(ah, ic->ic_macaddr);
1287 } else {
1288 ath_hal_getmac(ah, ic->ic_macaddr);
1289 }
1290
1291 if (sc->sc_hasbmask)
1292 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
1293
1294 /* NB: used to size node table key mapping array */
1295 ic->ic_max_keyix = sc->sc_keymax;
1296 /* call MI attach routine. */
1297 ieee80211_ifattach(ic);
1298 ic->ic_setregdomain = ath_setregdomain;
1299 ic->ic_getradiocaps = ath_getradiocaps;
1300 sc->sc_opmode = HAL_M_STA;
1301
1302 /* override default methods */
1303 ic->ic_ioctl = ath_ioctl;
1304 ic->ic_parent = ath_parent;
1305 ic->ic_transmit = ath_transmit;
1306 ic->ic_newassoc = ath_newassoc;
1307 ic->ic_updateslot = ath_updateslot;
1308 ic->ic_wme.wme_update = ath_wme_update;
1309 ic->ic_vap_create = ath_vap_create;
1310 ic->ic_vap_delete = ath_vap_delete;
1311 ic->ic_raw_xmit = ath_raw_xmit;
1312 ic->ic_update_mcast = ath_update_mcast;
1313 ic->ic_update_promisc = ath_update_promisc;
1314 ic->ic_node_alloc = ath_node_alloc;
1315 sc->sc_node_free = ic->ic_node_free;
1316 ic->ic_node_free = ath_node_free;
1317 sc->sc_node_cleanup = ic->ic_node_cleanup;
1318 ic->ic_node_cleanup = ath_node_cleanup;
1319 ic->ic_node_getsignal = ath_node_getsignal;
1320 ic->ic_scan_start = ath_scan_start;
1321 ic->ic_scan_end = ath_scan_end;
1322 ic->ic_set_channel = ath_set_channel;
1323 #ifdef ATH_ENABLE_11N
1324 /* 802.11n specific - but just override anyway */
1325 sc->sc_addba_request = ic->ic_addba_request;
1326 sc->sc_addba_response = ic->ic_addba_response;
1327 sc->sc_addba_stop = ic->ic_addba_stop;
1328 sc->sc_bar_response = ic->ic_bar_response;
1329 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout;
1330
1331 ic->ic_addba_request = ath_addba_request;
1332 ic->ic_addba_response = ath_addba_response;
1333 ic->ic_addba_response_timeout = ath_addba_response_timeout;
1334 ic->ic_addba_stop = ath_addba_stop;
1335 ic->ic_bar_response = ath_bar_response;
1336
1337 ic->ic_update_chw = ath_update_chw;
1338 #endif /* ATH_ENABLE_11N */
1339 ic->ic_set_quiet = ath_set_quiet_ie;
1340
1341 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
1342 /*
1343 * There's one vendor bitmap entry in the RX radiotap
1344 * header; make sure that's taken into account.
1345 */
1346 ieee80211_radiotap_attachv(ic,
1347 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0,
1348 ATH_TX_RADIOTAP_PRESENT,
1349 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1,
1350 ATH_RX_RADIOTAP_PRESENT);
1351 #else
1352 /*
1353 * No vendor bitmap/extensions are present.
1354 */
1355 ieee80211_radiotap_attach(ic,
1356 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
1357 ATH_TX_RADIOTAP_PRESENT,
1358 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
1359 ATH_RX_RADIOTAP_PRESENT);
1360 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
1361
1362 /*
1363 * Setup the ALQ logging if required
1364 */
1365 #ifdef ATH_DEBUG_ALQ
1366 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev));
1367 if_ath_alq_setcfg(&sc->sc_alq,
1368 sc->sc_ah->ah_macVersion,
1369 sc->sc_ah->ah_macRev,
1370 sc->sc_ah->ah_phyRev,
1371 sc->sc_ah->ah_magic);
1372 #endif
1373
1374 /*
1375 * Setup dynamic sysctl's now that country code and
1376 * regdomain are available from the hal.
1377 */
1378 ath_sysctlattach(sc);
1379 ath_sysctl_stats_attach(sc);
1380 ath_sysctl_hal_attach(sc);
1381
1382 if (bootverbose)
1383 ieee80211_announce(ic);
1384 ath_announce(sc);
1385
1386 /*
1387 * Put it to sleep for now.
1388 */
1389 ATH_LOCK(sc);
1390 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1);
1391 ATH_UNLOCK(sc);
1392
1393 return 0;
1394 bad2:
1395 ath_tx_cleanup(sc);
1396 ath_desc_free(sc);
1397 ath_txdma_teardown(sc);
1398 ath_rxdma_teardown(sc);
1399
1400 bad:
1401 if (ah)
1402 ath_hal_detach(ah);
1403 sc->sc_invalid = 1;
1404 return error;
1405 }
1406
1407 int
ath_detach(struct ath_softc * sc)1408 ath_detach(struct ath_softc *sc)
1409 {
1410
1411 /*
1412 * NB: the order of these is important:
1413 * o stop the chip so no more interrupts will fire
1414 * o call the 802.11 layer before detaching the hal to
1415 * insure callbacks into the driver to delete global
1416 * key cache entries can be handled
1417 * o free the taskqueue which drains any pending tasks
1418 * o reclaim the tx queue data structures after calling
1419 * the 802.11 layer as we'll get called back to reclaim
1420 * node state and potentially want to use them
1421 * o to cleanup the tx queues the hal is called, so detach
1422 * it last
1423 * Other than that, it's straightforward...
1424 */
1425
1426 /*
1427 * XXX Wake the hardware up first. ath_stop() will still
1428 * wake it up first, but I'd rather do it here just to
1429 * ensure it's awake.
1430 */
1431 ATH_LOCK(sc);
1432 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1433 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
1434
1435 /*
1436 * Stop things cleanly.
1437 */
1438 ath_stop(sc);
1439 ATH_UNLOCK(sc);
1440
1441 ieee80211_ifdetach(&sc->sc_ic);
1442 taskqueue_free(sc->sc_tq);
1443 #ifdef ATH_TX99_DIAG
1444 if (sc->sc_tx99 != NULL)
1445 sc->sc_tx99->detach(sc->sc_tx99);
1446 #endif
1447 ath_rate_detach(sc->sc_rc);
1448 #ifdef ATH_DEBUG_ALQ
1449 if_ath_alq_tidyup(&sc->sc_alq);
1450 #endif
1451 ath_lna_div_detach(sc);
1452 ath_btcoex_detach(sc);
1453 ath_spectral_detach(sc);
1454 ath_dfs_detach(sc);
1455 ath_desc_free(sc);
1456 ath_txdma_teardown(sc);
1457 ath_rxdma_teardown(sc);
1458 ath_tx_cleanup(sc);
1459 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
1460
1461 return 0;
1462 }
1463
1464 /*
1465 * MAC address handling for multiple BSS on the same radio.
1466 * The first vap uses the MAC address from the EEPROM. For
1467 * subsequent vap's we set the U/L bit (bit 1) in the MAC
1468 * address and use the next six bits as an index.
1469 */
1470 static void
assign_address(struct ath_softc * sc,uint8_t mac[IEEE80211_ADDR_LEN],int clone)1471 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
1472 {
1473 int i;
1474
1475 if (clone && sc->sc_hasbmask) {
1476 /* NB: we only do this if h/w supports multiple bssid */
1477 for (i = 0; i < 8; i++)
1478 if ((sc->sc_bssidmask & (1<<i)) == 0)
1479 break;
1480 if (i != 0)
1481 mac[0] |= (i << 2)|0x2;
1482 } else
1483 i = 0;
1484 sc->sc_bssidmask |= 1<<i;
1485 sc->sc_hwbssidmask[0] &= ~mac[0];
1486 if (i == 0)
1487 sc->sc_nbssid0++;
1488 }
1489
1490 static void
reclaim_address(struct ath_softc * sc,const uint8_t mac[IEEE80211_ADDR_LEN])1491 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
1492 {
1493 int i = mac[0] >> 2;
1494 uint8_t mask;
1495
1496 if (i != 0 || --sc->sc_nbssid0 == 0) {
1497 sc->sc_bssidmask &= ~(1<<i);
1498 /* recalculate bssid mask from remaining addresses */
1499 mask = 0xff;
1500 for (i = 1; i < 8; i++)
1501 if (sc->sc_bssidmask & (1<<i))
1502 mask &= ~((i<<2)|0x2);
1503 sc->sc_hwbssidmask[0] |= mask;
1504 }
1505 }
1506
1507 /*
1508 * Assign a beacon xmit slot. We try to space out
1509 * assignments so when beacons are staggered the
1510 * traffic coming out of the cab q has maximal time
1511 * to go out before the next beacon is scheduled.
1512 */
1513 static int
assign_bslot(struct ath_softc * sc)1514 assign_bslot(struct ath_softc *sc)
1515 {
1516 u_int slot, free;
1517
1518 free = 0;
1519 for (slot = 0; slot < ATH_BCBUF; slot++)
1520 if (sc->sc_bslot[slot] == NULL) {
1521 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
1522 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
1523 return slot;
1524 free = slot;
1525 /* NB: keep looking for a double slot */
1526 }
1527 return free;
1528 }
1529
1530 static struct ieee80211vap *
ath_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac0[IEEE80211_ADDR_LEN])1531 ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1532 enum ieee80211_opmode opmode, int flags,
1533 const uint8_t bssid[IEEE80211_ADDR_LEN],
1534 const uint8_t mac0[IEEE80211_ADDR_LEN])
1535 {
1536 struct ath_softc *sc = ic->ic_softc;
1537 struct ath_vap *avp;
1538 struct ieee80211vap *vap;
1539 uint8_t mac[IEEE80211_ADDR_LEN];
1540 int needbeacon, error;
1541 enum ieee80211_opmode ic_opmode;
1542
1543 avp = malloc(sizeof(struct ath_vap), M_80211_VAP, M_WAITOK | M_ZERO);
1544 needbeacon = 0;
1545 IEEE80211_ADDR_COPY(mac, mac0);
1546
1547 ATH_LOCK(sc);
1548 ic_opmode = opmode; /* default to opmode of new vap */
1549 switch (opmode) {
1550 case IEEE80211_M_STA:
1551 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
1552 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
1553 goto bad;
1554 }
1555 if (sc->sc_nvaps) {
1556 /*
1557 * With multiple vaps we must fall back
1558 * to s/w beacon miss handling.
1559 */
1560 flags |= IEEE80211_CLONE_NOBEACONS;
1561 }
1562 if (flags & IEEE80211_CLONE_NOBEACONS) {
1563 /*
1564 * Station mode w/o beacons are implemented w/ AP mode.
1565 */
1566 ic_opmode = IEEE80211_M_HOSTAP;
1567 }
1568 break;
1569 case IEEE80211_M_IBSS:
1570 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
1571 device_printf(sc->sc_dev,
1572 "only 1 ibss vap supported\n");
1573 goto bad;
1574 }
1575 needbeacon = 1;
1576 break;
1577 case IEEE80211_M_AHDEMO:
1578 #ifdef IEEE80211_SUPPORT_TDMA
1579 if (flags & IEEE80211_CLONE_TDMA) {
1580 if (sc->sc_nvaps != 0) {
1581 device_printf(sc->sc_dev,
1582 "only 1 tdma vap supported\n");
1583 goto bad;
1584 }
1585 needbeacon = 1;
1586 flags |= IEEE80211_CLONE_NOBEACONS;
1587 }
1588 /* fall thru... */
1589 #endif
1590 case IEEE80211_M_MONITOR:
1591 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
1592 /*
1593 * Adopt existing mode. Adding a monitor or ahdemo
1594 * vap to an existing configuration is of dubious
1595 * value but should be ok.
1596 */
1597 /* XXX not right for monitor mode */
1598 ic_opmode = ic->ic_opmode;
1599 }
1600 break;
1601 case IEEE80211_M_HOSTAP:
1602 case IEEE80211_M_MBSS:
1603 needbeacon = 1;
1604 break;
1605 case IEEE80211_M_WDS:
1606 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
1607 device_printf(sc->sc_dev,
1608 "wds not supported in sta mode\n");
1609 goto bad;
1610 }
1611 /*
1612 * Silently remove any request for a unique
1613 * bssid; WDS vap's always share the local
1614 * mac address.
1615 */
1616 flags &= ~IEEE80211_CLONE_BSSID;
1617 if (sc->sc_nvaps == 0)
1618 ic_opmode = IEEE80211_M_HOSTAP;
1619 else
1620 ic_opmode = ic->ic_opmode;
1621 break;
1622 default:
1623 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
1624 goto bad;
1625 }
1626 /*
1627 * Check that a beacon buffer is available; the code below assumes it.
1628 */
1629 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) {
1630 device_printf(sc->sc_dev, "no beacon buffer available\n");
1631 goto bad;
1632 }
1633
1634 /* STA, AHDEMO? */
1635 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS || opmode == IEEE80211_M_STA) {
1636 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
1637 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1638 }
1639
1640 vap = &avp->av_vap;
1641 /* XXX can't hold mutex across if_alloc */
1642 ATH_UNLOCK(sc);
1643 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
1644 ATH_LOCK(sc);
1645 if (error != 0) {
1646 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
1647 __func__, error);
1648 goto bad2;
1649 }
1650
1651 /* h/w crypto support */
1652 vap->iv_key_alloc = ath_key_alloc;
1653 vap->iv_key_delete = ath_key_delete;
1654 vap->iv_key_set = ath_key_set;
1655 vap->iv_key_update_begin = ath_key_update_begin;
1656 vap->iv_key_update_end = ath_key_update_end;
1657
1658 /* override various methods */
1659 avp->av_recv_mgmt = vap->iv_recv_mgmt;
1660 vap->iv_recv_mgmt = ath_recv_mgmt;
1661 vap->iv_reset = ath_reset_vap;
1662 vap->iv_update_beacon = ath_beacon_update;
1663 avp->av_newstate = vap->iv_newstate;
1664 vap->iv_newstate = ath_newstate;
1665 avp->av_bmiss = vap->iv_bmiss;
1666 vap->iv_bmiss = ath_bmiss_vap;
1667
1668 avp->av_node_ps = vap->iv_node_ps;
1669 vap->iv_node_ps = ath_node_powersave;
1670
1671 avp->av_set_tim = vap->iv_set_tim;
1672 vap->iv_set_tim = ath_node_set_tim;
1673
1674 avp->av_recv_pspoll = vap->iv_recv_pspoll;
1675 vap->iv_recv_pspoll = ath_node_recv_pspoll;
1676
1677 /* Set default parameters */
1678
1679 /*
1680 * Anything earlier than some AR9300 series MACs don't
1681 * support a smaller MPDU density.
1682 */
1683 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8;
1684 /*
1685 * All NICs can handle the maximum size, however
1686 * AR5416 based MACs can only TX aggregates w/ RTS
1687 * protection when the total aggregate size is <= 8k.
1688 * However, for now that's enforced by the TX path.
1689 */
1690 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1691 vap->iv_ampdu_limit = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1692
1693 avp->av_bslot = -1;
1694 if (needbeacon) {
1695 /*
1696 * Allocate beacon state and setup the q for buffered
1697 * multicast frames. We know a beacon buffer is
1698 * available because we checked above.
1699 */
1700 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf);
1701 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list);
1702 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1703 /*
1704 * Assign the vap to a beacon xmit slot. As above
1705 * this cannot fail to find a free one.
1706 */
1707 avp->av_bslot = assign_bslot(sc);
1708 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1709 ("beacon slot %u not empty", avp->av_bslot));
1710 sc->sc_bslot[avp->av_bslot] = vap;
1711 sc->sc_nbcnvaps++;
1712 }
1713 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1714 /*
1715 * Multple vaps are to transmit beacons and we
1716 * have h/w support for TSF adjusting; enable
1717 * use of staggered beacons.
1718 */
1719 sc->sc_stagbeacons = 1;
1720 }
1721 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1722 }
1723
1724 ic->ic_opmode = ic_opmode;
1725 if (opmode != IEEE80211_M_WDS) {
1726 sc->sc_nvaps++;
1727 if (opmode == IEEE80211_M_STA)
1728 sc->sc_nstavaps++;
1729 if (opmode == IEEE80211_M_MBSS)
1730 sc->sc_nmeshvaps++;
1731 }
1732 switch (ic_opmode) {
1733 case IEEE80211_M_IBSS:
1734 sc->sc_opmode = HAL_M_IBSS;
1735 break;
1736 case IEEE80211_M_STA:
1737 sc->sc_opmode = HAL_M_STA;
1738 break;
1739 case IEEE80211_M_AHDEMO:
1740 #ifdef IEEE80211_SUPPORT_TDMA
1741 if (vap->iv_caps & IEEE80211_C_TDMA) {
1742 sc->sc_tdma = 1;
1743 /* NB: disable tsf adjust */
1744 sc->sc_stagbeacons = 0;
1745 }
1746 /*
1747 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1748 * just ap mode.
1749 */
1750 /* fall thru... */
1751 #endif
1752 case IEEE80211_M_HOSTAP:
1753 case IEEE80211_M_MBSS:
1754 sc->sc_opmode = HAL_M_HOSTAP;
1755 break;
1756 case IEEE80211_M_MONITOR:
1757 sc->sc_opmode = HAL_M_MONITOR;
1758 break;
1759 default:
1760 /* XXX should not happen */
1761 break;
1762 }
1763 if (sc->sc_hastsfadd) {
1764 /*
1765 * Configure whether or not TSF adjust should be done.
1766 */
1767 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1768 }
1769 if (flags & IEEE80211_CLONE_NOBEACONS) {
1770 /*
1771 * Enable s/w beacon miss handling.
1772 */
1773 sc->sc_swbmiss = 1;
1774 }
1775 ATH_UNLOCK(sc);
1776
1777 /* complete setup */
1778 ieee80211_vap_attach(vap, ieee80211_media_change,
1779 ieee80211_media_status, mac);
1780 return vap;
1781 bad2:
1782 reclaim_address(sc, mac);
1783 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1784 bad:
1785 free(avp, M_80211_VAP);
1786 ATH_UNLOCK(sc);
1787 return NULL;
1788 }
1789
1790 static void
ath_vap_delete(struct ieee80211vap * vap)1791 ath_vap_delete(struct ieee80211vap *vap)
1792 {
1793 struct ieee80211com *ic = vap->iv_ic;
1794 struct ath_softc *sc = ic->ic_softc;
1795 struct ath_hal *ah = sc->sc_ah;
1796 struct ath_vap *avp = ATH_VAP(vap);
1797
1798 ATH_LOCK(sc);
1799 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1800 ATH_UNLOCK(sc);
1801
1802 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
1803 if (sc->sc_running) {
1804 /*
1805 * Quiesce the hardware while we remove the vap. In
1806 * particular we need to reclaim all references to
1807 * the vap state by any frames pending on the tx queues.
1808 */
1809 ath_hal_intrset(ah, 0); /* disable interrupts */
1810 /* XXX Do all frames from all vaps/nodes need draining here? */
1811 ath_stoprecv(sc, 1); /* stop recv side */
1812 ath_rx_flush(sc);
1813 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */
1814 }
1815
1816 /* .. leave the hardware awake for now. */
1817
1818 ieee80211_vap_detach(vap);
1819
1820 /*
1821 * XXX Danger Will Robinson! Danger!
1822 *
1823 * Because ieee80211_vap_detach() can queue a frame (the station
1824 * diassociate message?) after we've drained the TXQ and
1825 * flushed the software TXQ, we will end up with a frame queued
1826 * to a node whose vap is about to be freed.
1827 *
1828 * To work around this, flush the hardware/software again.
1829 * This may be racy - the ath task may be running and the packet
1830 * may be being scheduled between sw->hw txq. Tsk.
1831 *
1832 * TODO: figure out why a new node gets allocated somewhere around
1833 * here (after the ath_tx_swq() call; and after an ath_stop()
1834 * call!)
1835 */
1836
1837 ath_draintxq(sc, ATH_RESET_DEFAULT);
1838
1839 ATH_LOCK(sc);
1840 /*
1841 * Reclaim beacon state. Note this must be done before
1842 * the vap instance is reclaimed as we may have a reference
1843 * to it in the buffer for the beacon frame.
1844 */
1845 if (avp->av_bcbuf != NULL) {
1846 if (avp->av_bslot != -1) {
1847 sc->sc_bslot[avp->av_bslot] = NULL;
1848 sc->sc_nbcnvaps--;
1849 }
1850 ath_beacon_return(sc, avp->av_bcbuf);
1851 avp->av_bcbuf = NULL;
1852 if (sc->sc_nbcnvaps == 0) {
1853 sc->sc_stagbeacons = 0;
1854 if (sc->sc_hastsfadd)
1855 ath_hal_settsfadjust(sc->sc_ah, 0);
1856 }
1857 /*
1858 * Reclaim any pending mcast frames for the vap.
1859 */
1860 ath_tx_draintxq(sc, &avp->av_mcastq);
1861 }
1862 /*
1863 * Update bookkeeping.
1864 */
1865 if (vap->iv_opmode == IEEE80211_M_STA) {
1866 sc->sc_nstavaps--;
1867 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1868 sc->sc_swbmiss = 0;
1869 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1870 vap->iv_opmode == IEEE80211_M_STA ||
1871 vap->iv_opmode == IEEE80211_M_MBSS) {
1872 reclaim_address(sc, vap->iv_myaddr);
1873 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1874 if (vap->iv_opmode == IEEE80211_M_MBSS)
1875 sc->sc_nmeshvaps--;
1876 }
1877 if (vap->iv_opmode != IEEE80211_M_WDS)
1878 sc->sc_nvaps--;
1879 #ifdef IEEE80211_SUPPORT_TDMA
1880 /* TDMA operation ceases when the last vap is destroyed */
1881 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1882 sc->sc_tdma = 0;
1883 sc->sc_swbmiss = 0;
1884 }
1885 #endif
1886 free(avp, M_80211_VAP);
1887
1888 if (sc->sc_running) {
1889 /*
1890 * Restart rx+tx machines if still running (RUNNING will
1891 * be reset if we just destroyed the last vap).
1892 */
1893 if (ath_startrecv(sc) != 0)
1894 device_printf(sc->sc_dev,
1895 "%s: unable to restart recv logic\n", __func__);
1896 if (sc->sc_beacons) { /* restart beacons */
1897 #ifdef IEEE80211_SUPPORT_TDMA
1898 if (sc->sc_tdma)
1899 ath_tdma_config(sc, NULL);
1900 else
1901 #endif
1902 ath_beacon_config(sc, NULL);
1903 }
1904 ath_hal_intrset(ah, sc->sc_imask);
1905 }
1906
1907 /* Ok, let the hardware asleep. */
1908 ath_power_restore_power_state(sc);
1909 ATH_UNLOCK(sc);
1910 }
1911
1912 void
ath_suspend(struct ath_softc * sc)1913 ath_suspend(struct ath_softc *sc)
1914 {
1915 struct ieee80211com *ic = &sc->sc_ic;
1916
1917 sc->sc_resume_up = ic->ic_nrunning != 0;
1918
1919 ieee80211_suspend_all(ic);
1920 /*
1921 * NB: don't worry about putting the chip in low power
1922 * mode; pci will power off our socket on suspend and
1923 * CardBus detaches the device.
1924 *
1925 * XXX TODO: well, that's great, except for non-cardbus
1926 * devices!
1927 */
1928
1929 /*
1930 * XXX This doesn't wait until all pending taskqueue
1931 * items and parallel transmit/receive/other threads
1932 * are running!
1933 */
1934 ath_hal_intrset(sc->sc_ah, 0);
1935 taskqueue_block(sc->sc_tq);
1936
1937 ATH_LOCK(sc);
1938 callout_stop(&sc->sc_cal_ch);
1939 ATH_UNLOCK(sc);
1940
1941 /*
1942 * XXX ensure sc_invalid is 1
1943 */
1944
1945 /* Disable the PCIe PHY, complete with workarounds */
1946 ath_hal_enablepcie(sc->sc_ah, 1, 1);
1947 }
1948
1949 /*
1950 * Reset the key cache since some parts do not reset the
1951 * contents on resume. First we clear all entries, then
1952 * re-load keys that the 802.11 layer assumes are setup
1953 * in h/w.
1954 */
1955 static void
ath_reset_keycache(struct ath_softc * sc)1956 ath_reset_keycache(struct ath_softc *sc)
1957 {
1958 struct ieee80211com *ic = &sc->sc_ic;
1959 struct ath_hal *ah = sc->sc_ah;
1960 int i;
1961
1962 ATH_LOCK(sc);
1963 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1964 for (i = 0; i < sc->sc_keymax; i++)
1965 ath_hal_keyreset(ah, i);
1966 ath_power_restore_power_state(sc);
1967 ATH_UNLOCK(sc);
1968 ieee80211_crypto_reload_keys(ic);
1969 }
1970
1971 /*
1972 * Fetch the current chainmask configuration based on the current
1973 * operating channel and options.
1974 */
1975 static void
ath_update_chainmasks(struct ath_softc * sc,struct ieee80211_channel * chan)1976 ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan)
1977 {
1978
1979 /*
1980 * Set TX chainmask to the currently configured chainmask;
1981 * the TX chainmask depends upon the current operating mode.
1982 */
1983 sc->sc_cur_rxchainmask = sc->sc_rxchainmask;
1984 if (IEEE80211_IS_CHAN_HT(chan)) {
1985 sc->sc_cur_txchainmask = sc->sc_txchainmask;
1986 } else {
1987 sc->sc_cur_txchainmask = 1;
1988 }
1989
1990 DPRINTF(sc, ATH_DEBUG_RESET,
1991 "%s: TX chainmask is now 0x%x, RX is now 0x%x\n",
1992 __func__,
1993 sc->sc_cur_txchainmask,
1994 sc->sc_cur_rxchainmask);
1995 }
1996
1997 void
ath_resume(struct ath_softc * sc)1998 ath_resume(struct ath_softc *sc)
1999 {
2000 struct ieee80211com *ic = &sc->sc_ic;
2001 struct ath_hal *ah = sc->sc_ah;
2002 HAL_STATUS status;
2003
2004 ath_hal_enablepcie(ah, 0, 0);
2005
2006 /*
2007 * Must reset the chip before we reload the
2008 * keycache as we were powered down on suspend.
2009 */
2010 ath_update_chainmasks(sc,
2011 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan);
2012 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2013 sc->sc_cur_rxchainmask);
2014
2015 /* Ensure we set the current power state to on */
2016 ATH_LOCK(sc);
2017 ath_power_setselfgen(sc, HAL_PM_AWAKE);
2018 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2019 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
2020 ATH_UNLOCK(sc);
2021
2022 ath_hal_reset(ah, sc->sc_opmode,
2023 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
2024 AH_FALSE, HAL_RESET_NORMAL, &status);
2025 ath_reset_keycache(sc);
2026
2027 ATH_RX_LOCK(sc);
2028 sc->sc_rx_stopped = 1;
2029 sc->sc_rx_resetted = 1;
2030 ATH_RX_UNLOCK(sc);
2031
2032 /* Let DFS at it in case it's a DFS channel */
2033 ath_dfs_radar_enable(sc, ic->ic_curchan);
2034
2035 /* Let spectral at in case spectral is enabled */
2036 ath_spectral_enable(sc, ic->ic_curchan);
2037
2038 /*
2039 * Let bluetooth coexistence at in case it's needed for this channel
2040 */
2041 ath_btcoex_enable(sc, ic->ic_curchan);
2042
2043 /*
2044 * If we're doing TDMA, enforce the TXOP limitation for chips that
2045 * support it.
2046 */
2047 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2048 ath_hal_setenforcetxop(sc->sc_ah, 1);
2049 else
2050 ath_hal_setenforcetxop(sc->sc_ah, 0);
2051
2052 /* Restore the LED configuration */
2053 ath_led_config(sc);
2054 ath_hal_setledstate(ah, HAL_LED_INIT);
2055
2056 if (sc->sc_resume_up)
2057 ieee80211_resume_all(ic);
2058
2059 ATH_LOCK(sc);
2060 ath_power_restore_power_state(sc);
2061 ATH_UNLOCK(sc);
2062
2063 /* XXX beacons ? */
2064 }
2065
2066 void
ath_shutdown(struct ath_softc * sc)2067 ath_shutdown(struct ath_softc *sc)
2068 {
2069
2070 ATH_LOCK(sc);
2071 ath_stop(sc);
2072 ATH_UNLOCK(sc);
2073 /* NB: no point powering down chip as we're about to reboot */
2074 }
2075
2076 /*
2077 * Interrupt handler. Most of the actual processing is deferred.
2078 */
2079 void
ath_intr(void * arg)2080 ath_intr(void *arg)
2081 {
2082 struct ath_softc *sc = arg;
2083 struct ath_hal *ah = sc->sc_ah;
2084 HAL_INT status = 0;
2085 uint32_t txqs;
2086
2087 /*
2088 * If we're inside a reset path, just print a warning and
2089 * clear the ISR. The reset routine will finish it for us.
2090 */
2091 ATH_PCU_LOCK(sc);
2092 if (sc->sc_inreset_cnt) {
2093 HAL_INT status;
2094 ath_hal_getisr(ah, &status); /* clear ISR */
2095 ath_hal_intrset(ah, 0); /* disable further intr's */
2096 DPRINTF(sc, ATH_DEBUG_ANY,
2097 "%s: in reset, ignoring: status=0x%x\n",
2098 __func__, status);
2099 ATH_PCU_UNLOCK(sc);
2100 return;
2101 }
2102
2103 if (sc->sc_invalid) {
2104 /*
2105 * The hardware is not ready/present, don't touch anything.
2106 * Note this can happen early on if the IRQ is shared.
2107 */
2108 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
2109 ATH_PCU_UNLOCK(sc);
2110 return;
2111 }
2112 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */
2113 ATH_PCU_UNLOCK(sc);
2114 return;
2115 }
2116
2117 ATH_LOCK(sc);
2118 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2119 ATH_UNLOCK(sc);
2120
2121 if (sc->sc_ic.ic_nrunning == 0 && sc->sc_running == 0) {
2122 HAL_INT status;
2123
2124 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_nrunning %d sc_running %d\n",
2125 __func__, sc->sc_ic.ic_nrunning, sc->sc_running);
2126 ath_hal_getisr(ah, &status); /* clear ISR */
2127 ath_hal_intrset(ah, 0); /* disable further intr's */
2128 ATH_PCU_UNLOCK(sc);
2129
2130 ATH_LOCK(sc);
2131 ath_power_restore_power_state(sc);
2132 ATH_UNLOCK(sc);
2133 return;
2134 }
2135
2136 /*
2137 * Figure out the reason(s) for the interrupt. Note
2138 * that the hal returns a pseudo-ISR that may include
2139 * bits we haven't explicitly enabled so we mask the
2140 * value to insure we only process bits we requested.
2141 */
2142 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
2143 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
2144 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status);
2145 #ifdef ATH_DEBUG_ALQ
2146 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate,
2147 ah->ah_syncstate);
2148 #endif /* ATH_DEBUG_ALQ */
2149 #ifdef ATH_KTR_INTR_DEBUG
2150 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5,
2151 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x",
2152 ah->ah_intrstate[0],
2153 ah->ah_intrstate[1],
2154 ah->ah_intrstate[2],
2155 ah->ah_intrstate[3],
2156 ah->ah_intrstate[6]);
2157 #endif
2158
2159 /* Squirrel away SYNC interrupt debugging */
2160 if (ah->ah_syncstate != 0) {
2161 int i;
2162 for (i = 0; i < 32; i++)
2163 if (ah->ah_syncstate & (1 << i))
2164 sc->sc_intr_stats.sync_intr[i]++;
2165 }
2166
2167 status &= sc->sc_imask; /* discard unasked for bits */
2168
2169 /* Short-circuit un-handled interrupts */
2170 if (status == 0x0) {
2171 ATH_PCU_UNLOCK(sc);
2172
2173 ATH_LOCK(sc);
2174 ath_power_restore_power_state(sc);
2175 ATH_UNLOCK(sc);
2176
2177 return;
2178 }
2179
2180 /*
2181 * Take a note that we're inside the interrupt handler, so
2182 * the reset routines know to wait.
2183 */
2184 sc->sc_intr_cnt++;
2185 ATH_PCU_UNLOCK(sc);
2186
2187 /*
2188 * Handle the interrupt. We won't run concurrent with the reset
2189 * or channel change routines as they'll wait for sc_intr_cnt
2190 * to be 0 before continuing.
2191 */
2192 if (status & HAL_INT_FATAL) {
2193 sc->sc_stats.ast_hardware++;
2194 ath_hal_intrset(ah, 0); /* disable intr's until reset */
2195 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
2196 } else {
2197 if (status & HAL_INT_SWBA) {
2198 /*
2199 * Software beacon alert--time to send a beacon.
2200 * Handle beacon transmission directly; deferring
2201 * this is too slow to meet timing constraints
2202 * under load.
2203 */
2204 #ifdef IEEE80211_SUPPORT_TDMA
2205 if (sc->sc_tdma) {
2206 if (sc->sc_tdmaswba == 0) {
2207 struct ieee80211com *ic = &sc->sc_ic;
2208 struct ieee80211vap *vap =
2209 TAILQ_FIRST(&ic->ic_vaps);
2210 ath_tdma_beacon_send(sc, vap);
2211 sc->sc_tdmaswba =
2212 vap->iv_tdma->tdma_bintval;
2213 } else
2214 sc->sc_tdmaswba--;
2215 } else
2216 #endif
2217 {
2218 ath_beacon_proc(sc, 0);
2219 #ifdef IEEE80211_SUPPORT_SUPERG
2220 /*
2221 * Schedule the rx taskq in case there's no
2222 * traffic so any frames held on the staging
2223 * queue are aged and potentially flushed.
2224 */
2225 sc->sc_rx.recv_sched(sc, 1);
2226 #endif
2227 }
2228 }
2229 if (status & HAL_INT_RXEOL) {
2230 int imask;
2231 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL");
2232 if (! sc->sc_isedma) {
2233 ATH_PCU_LOCK(sc);
2234 /*
2235 * NB: the hardware should re-read the link when
2236 * RXE bit is written, but it doesn't work at
2237 * least on older hardware revs.
2238 */
2239 sc->sc_stats.ast_rxeol++;
2240 /*
2241 * Disable RXEOL/RXORN - prevent an interrupt
2242 * storm until the PCU logic can be reset.
2243 * In case the interface is reset some other
2244 * way before "sc_kickpcu" is called, don't
2245 * modify sc_imask - that way if it is reset
2246 * by a call to ath_reset() somehow, the
2247 * interrupt mask will be correctly reprogrammed.
2248 */
2249 imask = sc->sc_imask;
2250 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN);
2251 ath_hal_intrset(ah, imask);
2252 /*
2253 * Only blank sc_rxlink if we've not yet kicked
2254 * the PCU.
2255 *
2256 * This isn't entirely correct - the correct solution
2257 * would be to have a PCU lock and engage that for
2258 * the duration of the PCU fiddling; which would include
2259 * running the RX process. Otherwise we could end up
2260 * messing up the RX descriptor chain and making the
2261 * RX desc list much shorter.
2262 */
2263 if (! sc->sc_kickpcu)
2264 sc->sc_rxlink = NULL;
2265 sc->sc_kickpcu = 1;
2266 ATH_PCU_UNLOCK(sc);
2267 }
2268 /*
2269 * Enqueue an RX proc to handle whatever
2270 * is in the RX queue.
2271 * This will then kick the PCU if required.
2272 */
2273 sc->sc_rx.recv_sched(sc, 1);
2274 }
2275 if (status & HAL_INT_TXURN) {
2276 sc->sc_stats.ast_txurn++;
2277 /* bump tx trigger level */
2278 ath_hal_updatetxtriglevel(ah, AH_TRUE);
2279 }
2280 /*
2281 * Handle both the legacy and RX EDMA interrupt bits.
2282 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC.
2283 */
2284 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) {
2285 sc->sc_stats.ast_rx_intr++;
2286 sc->sc_rx.recv_sched(sc, 1);
2287 }
2288 if (status & HAL_INT_TX) {
2289 sc->sc_stats.ast_tx_intr++;
2290 /*
2291 * Grab all the currently set bits in the HAL txq bitmap
2292 * and blank them. This is the only place we should be
2293 * doing this.
2294 */
2295 if (! sc->sc_isedma) {
2296 ATH_PCU_LOCK(sc);
2297 txqs = 0xffffffff;
2298 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs);
2299 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3,
2300 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x",
2301 txqs,
2302 sc->sc_txq_active,
2303 sc->sc_txq_active | txqs);
2304 sc->sc_txq_active |= txqs;
2305 ATH_PCU_UNLOCK(sc);
2306 }
2307 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
2308 }
2309 if (status & HAL_INT_BMISS) {
2310 sc->sc_stats.ast_bmiss++;
2311 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
2312 }
2313 if (status & HAL_INT_GTT)
2314 sc->sc_stats.ast_tx_timeout++;
2315 if (status & HAL_INT_CST)
2316 sc->sc_stats.ast_tx_cst++;
2317 if (status & HAL_INT_MIB) {
2318 sc->sc_stats.ast_mib++;
2319 ATH_PCU_LOCK(sc);
2320 /*
2321 * Disable interrupts until we service the MIB
2322 * interrupt; otherwise it will continue to fire.
2323 */
2324 ath_hal_intrset(ah, 0);
2325 /*
2326 * Let the hal handle the event. We assume it will
2327 * clear whatever condition caused the interrupt.
2328 */
2329 ath_hal_mibevent(ah, &sc->sc_halstats);
2330 /*
2331 * Don't reset the interrupt if we've just
2332 * kicked the PCU, or we may get a nested
2333 * RXEOL before the rxproc has had a chance
2334 * to run.
2335 */
2336 if (sc->sc_kickpcu == 0)
2337 ath_hal_intrset(ah, sc->sc_imask);
2338 ATH_PCU_UNLOCK(sc);
2339 }
2340 if (status & HAL_INT_RXORN) {
2341 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
2342 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN");
2343 sc->sc_stats.ast_rxorn++;
2344 }
2345 if (status & HAL_INT_TSFOOR) {
2346 /*
2347 * out of range beacon - wake the chip up,
2348 * but don't modify self-gen frame config.
2349 * Do a full reset to clear any potential stuck
2350 * PHY/MAC that generated this condition.
2351 */
2352 sc->sc_stats.ast_tsfoor++;
2353 ATH_LOCK(sc);
2354 ath_power_setpower(sc, HAL_PM_AWAKE, 0);
2355 ATH_UNLOCK(sc);
2356 taskqueue_enqueue(sc->sc_tq, &sc->sc_tsfoortask);
2357 device_printf(sc->sc_dev, "%s: TSFOOR\n", __func__);
2358 }
2359 if (status & HAL_INT_MCI) {
2360 ath_btcoex_mci_intr(sc);
2361 }
2362 }
2363 ATH_PCU_LOCK(sc);
2364 sc->sc_intr_cnt--;
2365 ATH_PCU_UNLOCK(sc);
2366
2367 ATH_LOCK(sc);
2368 ath_power_restore_power_state(sc);
2369 ATH_UNLOCK(sc);
2370 }
2371
2372 static void
ath_fatal_proc(void * arg,int pending)2373 ath_fatal_proc(void *arg, int pending)
2374 {
2375 struct ath_softc *sc = arg;
2376 u_int32_t *state;
2377 u_int32_t len;
2378 void *sp;
2379
2380 if (sc->sc_invalid)
2381 return;
2382
2383 device_printf(sc->sc_dev, "hardware error; resetting\n");
2384 /*
2385 * Fatal errors are unrecoverable. Typically these
2386 * are caused by DMA errors. Collect h/w state from
2387 * the hal so we can diagnose what's going on.
2388 */
2389 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
2390 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
2391 state = sp;
2392 device_printf(sc->sc_dev,
2393 "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", state[0],
2394 state[1] , state[2], state[3], state[4], state[5]);
2395 }
2396 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
2397 }
2398
2399 static void
ath_bmiss_vap(struct ieee80211vap * vap)2400 ath_bmiss_vap(struct ieee80211vap *vap)
2401 {
2402 struct ath_softc *sc = vap->iv_ic->ic_softc;
2403
2404 /*
2405 * Workaround phantom bmiss interrupts by sanity-checking
2406 * the time of our last rx'd frame. If it is within the
2407 * beacon miss interval then ignore the interrupt. If it's
2408 * truly a bmiss we'll get another interrupt soon and that'll
2409 * be dispatched up for processing. Note this applies only
2410 * for h/w beacon miss events.
2411 */
2412
2413 /*
2414 * XXX TODO: Just read the TSF during the interrupt path;
2415 * that way we don't have to wake up again just to read it
2416 * again.
2417 */
2418 ATH_LOCK(sc);
2419 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2420 ATH_UNLOCK(sc);
2421
2422 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
2423 u_int64_t lastrx = sc->sc_lastrx;
2424 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
2425 /* XXX should take a locked ref to iv_bss */
2426 u_int bmisstimeout =
2427 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
2428
2429 DPRINTF(sc, ATH_DEBUG_BEACON,
2430 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
2431 __func__, (unsigned long long) tsf,
2432 (unsigned long long)(tsf - lastrx),
2433 (unsigned long long) lastrx, bmisstimeout);
2434
2435 if (tsf - lastrx <= bmisstimeout) {
2436 sc->sc_stats.ast_bmiss_phantom++;
2437
2438 ATH_LOCK(sc);
2439 ath_power_restore_power_state(sc);
2440 ATH_UNLOCK(sc);
2441
2442 return;
2443 }
2444 }
2445
2446 /*
2447 * Keep the hardware awake if it's asleep (and leave self-gen
2448 * frame config alone) until the next beacon, so we can resync
2449 * against the next beacon.
2450 *
2451 * This handles three common beacon miss cases in STA powersave mode -
2452 * (a) the beacon TBTT isn't a multiple of bintval;
2453 * (b) the beacon was missed; and
2454 * (c) the beacons are being delayed because the AP is busy and
2455 * isn't reliably able to meet its TBTT.
2456 */
2457 ATH_LOCK(sc);
2458 ath_power_setpower(sc, HAL_PM_AWAKE, 0);
2459 ath_power_restore_power_state(sc);
2460 ATH_UNLOCK(sc);
2461
2462 DPRINTF(sc, ATH_DEBUG_BEACON,
2463 "%s: forced awake; force syncbeacon=1\n", __func__);
2464 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
2465 /*
2466 * Attempt to force a beacon resync.
2467 */
2468 sc->sc_syncbeacon = 1;
2469 }
2470
2471 ATH_VAP(vap)->av_bmiss(vap);
2472 }
2473
2474 /* XXX this needs a force wakeup! */
2475 int
ath_hal_gethangstate(struct ath_hal * ah,uint32_t mask,uint32_t * hangs)2476 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
2477 {
2478 uint32_t rsize;
2479 void *sp;
2480
2481 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize))
2482 return 0;
2483 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
2484 *hangs = *(uint32_t *)sp;
2485 return 1;
2486 }
2487
2488 static void
ath_bmiss_proc(void * arg,int pending)2489 ath_bmiss_proc(void *arg, int pending)
2490 {
2491 struct ath_softc *sc = arg;
2492 uint32_t hangs;
2493
2494 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
2495
2496 ATH_LOCK(sc);
2497 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2498 ATH_UNLOCK(sc);
2499
2500 ath_beacon_miss(sc);
2501
2502 /*
2503 * Do a reset upon any beacon miss event.
2504 *
2505 * It may be a non-recognised RX clear hang which needs a reset
2506 * to clear.
2507 */
2508 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
2509 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_BBPANIC);
2510 device_printf(sc->sc_dev,
2511 "bb hang detected (0x%x), resetting\n", hangs);
2512 } else {
2513 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
2514 ieee80211_beacon_miss(&sc->sc_ic);
2515 }
2516
2517 /* Force a beacon resync, in case they've drifted */
2518 sc->sc_syncbeacon = 1;
2519
2520 ATH_LOCK(sc);
2521 ath_power_restore_power_state(sc);
2522 ATH_UNLOCK(sc);
2523 }
2524
2525 /*
2526 * Handle a TSF out of range interrupt in STA mode.
2527 *
2528 * This may be due to a partially deaf looking radio, so
2529 * do a full reset just in case it is indeed deaf and
2530 * resync the beacon.
2531 */
2532 static void
ath_tsfoor_proc(void * arg,int pending)2533 ath_tsfoor_proc(void *arg, int pending)
2534 {
2535 struct ath_softc *sc = arg;
2536
2537 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
2538
2539 ATH_LOCK(sc);
2540 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2541 ATH_UNLOCK(sc);
2542
2543 /*
2544 * Do a full reset after any TSFOOR. It's possible that
2545 * we've gone deaf or partially deaf (eg due to calibration
2546 * failures) and this should clean things up a bit.
2547 */
2548 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
2549
2550 /* Force a beacon resync, in case they've drifted */
2551 sc->sc_syncbeacon = 1;
2552
2553 ATH_LOCK(sc);
2554 ath_power_restore_power_state(sc);
2555 ATH_UNLOCK(sc);
2556 }
2557
2558 /*
2559 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
2560 * calcs together with WME. If necessary disable the crypto
2561 * hardware and mark the 802.11 state so keys will be setup
2562 * with the MIC work done in software.
2563 */
2564 static void
ath_settkipmic(struct ath_softc * sc)2565 ath_settkipmic(struct ath_softc *sc)
2566 {
2567 struct ieee80211com *ic = &sc->sc_ic;
2568
2569 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
2570 if (ic->ic_flags & IEEE80211_F_WME) {
2571 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
2572 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
2573 } else {
2574 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
2575 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
2576 }
2577 }
2578 }
2579
2580 static void
ath_vap_clear_quiet_ie(struct ath_softc * sc)2581 ath_vap_clear_quiet_ie(struct ath_softc *sc)
2582 {
2583 struct ieee80211com *ic = &sc->sc_ic;
2584 struct ieee80211vap *vap;
2585 struct ath_vap *avp;
2586
2587 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
2588 avp = ATH_VAP(vap);
2589 /* Quiet time handling - ensure we resync */
2590 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));
2591 }
2592 }
2593
2594 static int
ath_init(struct ath_softc * sc)2595 ath_init(struct ath_softc *sc)
2596 {
2597 struct ieee80211com *ic = &sc->sc_ic;
2598 struct ath_hal *ah = sc->sc_ah;
2599 HAL_STATUS status;
2600
2601 ATH_LOCK_ASSERT(sc);
2602
2603 /*
2604 * Force the sleep state awake.
2605 */
2606 ath_power_setselfgen(sc, HAL_PM_AWAKE);
2607 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2608 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
2609
2610 /*
2611 * Stop anything previously setup. This is safe
2612 * whether this is the first time through or not.
2613 */
2614 ath_stop(sc);
2615
2616 /*
2617 * The basic interface to setting the hardware in a good
2618 * state is ``reset''. On return the hardware is known to
2619 * be powered up and with interrupts disabled. This must
2620 * be followed by initialization of the appropriate bits
2621 * and then setup of the interrupt mask.
2622 */
2623 ath_settkipmic(sc);
2624 ath_update_chainmasks(sc, ic->ic_curchan);
2625 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2626 sc->sc_cur_rxchainmask);
2627
2628 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE,
2629 HAL_RESET_NORMAL, &status)) {
2630 device_printf(sc->sc_dev,
2631 "unable to reset hardware; hal status %u\n", status);
2632 return (ENODEV);
2633 }
2634
2635 ATH_RX_LOCK(sc);
2636 sc->sc_rx_stopped = 1;
2637 sc->sc_rx_resetted = 1;
2638 ATH_RX_UNLOCK(sc);
2639
2640 /* Clear quiet IE state for each VAP */
2641 ath_vap_clear_quiet_ie(sc);
2642
2643 ath_chan_change(sc, ic->ic_curchan);
2644
2645 /* Let DFS at it in case it's a DFS channel */
2646 ath_dfs_radar_enable(sc, ic->ic_curchan);
2647
2648 /* Let spectral at in case spectral is enabled */
2649 ath_spectral_enable(sc, ic->ic_curchan);
2650
2651 /*
2652 * Let bluetooth coexistence at in case it's needed for this channel
2653 */
2654 ath_btcoex_enable(sc, ic->ic_curchan);
2655
2656 /*
2657 * If we're doing TDMA, enforce the TXOP limitation for chips that
2658 * support it.
2659 */
2660 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2661 ath_hal_setenforcetxop(sc->sc_ah, 1);
2662 else
2663 ath_hal_setenforcetxop(sc->sc_ah, 0);
2664
2665 /*
2666 * Likewise this is set during reset so update
2667 * state cached in the driver.
2668 */
2669 sc->sc_diversity = ath_hal_getdiversity(ah);
2670 sc->sc_lastlongcal = ticks;
2671 sc->sc_resetcal = 1;
2672 sc->sc_lastcalreset = 0;
2673 sc->sc_lastani = ticks;
2674 sc->sc_lastshortcal = ticks;
2675 sc->sc_doresetcal = AH_FALSE;
2676 /*
2677 * Beacon timers were cleared here; give ath_newstate()
2678 * a hint that the beacon timers should be poked when
2679 * things transition to the RUN state.
2680 */
2681 sc->sc_beacons = 0;
2682
2683 /*
2684 * Setup the hardware after reset: the key cache
2685 * is filled as needed and the receive engine is
2686 * set going. Frame transmit is handled entirely
2687 * in the frame output path; there's nothing to do
2688 * here except setup the interrupt mask.
2689 */
2690 if (ath_startrecv(sc) != 0) {
2691 device_printf(sc->sc_dev, "unable to start recv logic\n");
2692 ath_power_restore_power_state(sc);
2693 return (ENODEV);
2694 }
2695
2696 /*
2697 * Enable interrupts.
2698 */
2699 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
2700 | HAL_INT_RXORN | HAL_INT_TXURN
2701 | HAL_INT_FATAL | HAL_INT_GLOBAL;
2702
2703 /*
2704 * Enable RX EDMA bits. Note these overlap with
2705 * HAL_INT_RX and HAL_INT_RXDESC respectively.
2706 */
2707 if (sc->sc_isedma)
2708 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP);
2709
2710 /*
2711 * If we're an EDMA NIC, we don't care about RXEOL.
2712 * Writing a new descriptor in will simply restart
2713 * RX DMA.
2714 */
2715 if (! sc->sc_isedma)
2716 sc->sc_imask |= HAL_INT_RXEOL;
2717
2718 /*
2719 * Enable MCI interrupt for MCI devices.
2720 */
2721 if (sc->sc_btcoex_mci)
2722 sc->sc_imask |= HAL_INT_MCI;
2723
2724 /*
2725 * Enable MIB interrupts when there are hardware phy counters.
2726 * Note we only do this (at the moment) for station mode.
2727 */
2728 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
2729 sc->sc_imask |= HAL_INT_MIB;
2730
2731 /*
2732 * XXX add capability for this.
2733 *
2734 * If we're in STA mode (and maybe IBSS?) then register for
2735 * TSFOOR interrupts.
2736 */
2737 if (ic->ic_opmode == IEEE80211_M_STA)
2738 sc->sc_imask |= HAL_INT_TSFOOR;
2739
2740 /* Enable global TX timeout and carrier sense timeout if available */
2741 if (ath_hal_gtxto_supported(ah))
2742 sc->sc_imask |= HAL_INT_GTT;
2743
2744 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n",
2745 __func__, sc->sc_imask);
2746
2747 sc->sc_running = 1;
2748 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
2749 ath_hal_intrset(ah, sc->sc_imask);
2750
2751 ath_power_restore_power_state(sc);
2752
2753 return (0);
2754 }
2755
2756 static void
ath_stop(struct ath_softc * sc)2757 ath_stop(struct ath_softc *sc)
2758 {
2759 struct ath_hal *ah = sc->sc_ah;
2760
2761 ATH_LOCK_ASSERT(sc);
2762
2763 /*
2764 * Wake the hardware up before fiddling with it.
2765 */
2766 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2767
2768 if (sc->sc_running) {
2769 /*
2770 * Shutdown the hardware and driver:
2771 * reset 802.11 state machine
2772 * turn off timers
2773 * disable interrupts
2774 * turn off the radio
2775 * clear transmit machinery
2776 * clear receive machinery
2777 * drain and release tx queues
2778 * reclaim beacon resources
2779 * power down hardware
2780 *
2781 * Note that some of this work is not possible if the
2782 * hardware is gone (invalid).
2783 */
2784 #ifdef ATH_TX99_DIAG
2785 if (sc->sc_tx99 != NULL)
2786 sc->sc_tx99->stop(sc->sc_tx99);
2787 #endif
2788 callout_stop(&sc->sc_wd_ch);
2789 sc->sc_wd_timer = 0;
2790 sc->sc_running = 0;
2791 if (!sc->sc_invalid) {
2792 if (sc->sc_softled) {
2793 callout_stop(&sc->sc_ledtimer);
2794 ath_hal_gpioset(ah, sc->sc_ledpin,
2795 !sc->sc_ledon);
2796 sc->sc_blinking = 0;
2797 }
2798 ath_hal_intrset(ah, 0);
2799 }
2800 /* XXX we should stop RX regardless of whether it's valid */
2801 if (!sc->sc_invalid) {
2802 ath_stoprecv(sc, 1);
2803 ath_hal_phydisable(ah);
2804 } else
2805 sc->sc_rxlink = NULL;
2806 ath_draintxq(sc, ATH_RESET_DEFAULT);
2807 ath_beacon_free(sc); /* XXX not needed */
2808 }
2809
2810 /* And now, restore the current power state */
2811 ath_power_restore_power_state(sc);
2812 }
2813
2814 /*
2815 * Wait until all pending TX/RX has completed.
2816 *
2817 * This waits until all existing transmit, receive and interrupts
2818 * have completed. It's assumed that the caller has first
2819 * grabbed the reset lock so it doesn't try to do overlapping
2820 * chip resets.
2821 */
2822 #define MAX_TXRX_ITERATIONS 100
2823 static void
ath_txrx_stop_locked(struct ath_softc * sc)2824 ath_txrx_stop_locked(struct ath_softc *sc)
2825 {
2826 int i = MAX_TXRX_ITERATIONS;
2827
2828 ATH_UNLOCK_ASSERT(sc);
2829 ATH_PCU_LOCK_ASSERT(sc);
2830
2831 /*
2832 * Sleep until all the pending operations have completed.
2833 *
2834 * The caller must ensure that reset has been incremented
2835 * or the pending operations may continue being queued.
2836 */
2837 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt ||
2838 sc->sc_txstart_cnt || sc->sc_intr_cnt) {
2839 if (i <= 0)
2840 break;
2841 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop",
2842 msecs_to_ticks(10));
2843 i--;
2844 }
2845
2846 if (i <= 0)
2847 device_printf(sc->sc_dev,
2848 "%s: didn't finish after %d iterations\n",
2849 __func__, MAX_TXRX_ITERATIONS);
2850 }
2851 #undef MAX_TXRX_ITERATIONS
2852
2853 #if 0
2854 static void
2855 ath_txrx_stop(struct ath_softc *sc)
2856 {
2857 ATH_UNLOCK_ASSERT(sc);
2858 ATH_PCU_UNLOCK_ASSERT(sc);
2859
2860 ATH_PCU_LOCK(sc);
2861 ath_txrx_stop_locked(sc);
2862 ATH_PCU_UNLOCK(sc);
2863 }
2864 #endif
2865
2866 static void
ath_txrx_start(struct ath_softc * sc)2867 ath_txrx_start(struct ath_softc *sc)
2868 {
2869
2870 taskqueue_unblock(sc->sc_tq);
2871 }
2872
2873 /*
2874 * Grab the reset lock, and wait around until no one else
2875 * is trying to do anything with it.
2876 *
2877 * This is totally horrible but we can't hold this lock for
2878 * long enough to do TX/RX or we end up with net80211/ip stack
2879 * LORs and eventual deadlock.
2880 *
2881 * "dowait" signals whether to spin, waiting for the reset
2882 * lock count to reach 0. This should (for now) only be used
2883 * during the reset path, as the rest of the code may not
2884 * be locking-reentrant enough to behave correctly.
2885 *
2886 * Another, cleaner way should be found to serialise all of
2887 * these operations.
2888 */
2889 #define MAX_RESET_ITERATIONS 25
2890 static int
ath_reset_grablock(struct ath_softc * sc,int dowait)2891 ath_reset_grablock(struct ath_softc *sc, int dowait)
2892 {
2893 int w = 0;
2894 int i = MAX_RESET_ITERATIONS;
2895
2896 ATH_PCU_LOCK_ASSERT(sc);
2897 do {
2898 if (sc->sc_inreset_cnt == 0) {
2899 w = 1;
2900 break;
2901 }
2902 if (dowait == 0) {
2903 w = 0;
2904 break;
2905 }
2906 ATH_PCU_UNLOCK(sc);
2907 /*
2908 * 1 tick is likely not enough time for long calibrations
2909 * to complete. So we should wait quite a while.
2910 */
2911 pause("ath_reset_grablock", msecs_to_ticks(100));
2912 i--;
2913 ATH_PCU_LOCK(sc);
2914 } while (i > 0);
2915
2916 /*
2917 * We always increment the refcounter, regardless
2918 * of whether we succeeded to get it in an exclusive
2919 * way.
2920 */
2921 sc->sc_inreset_cnt++;
2922
2923 if (i <= 0)
2924 device_printf(sc->sc_dev,
2925 "%s: didn't finish after %d iterations\n",
2926 __func__, MAX_RESET_ITERATIONS);
2927
2928 if (w == 0)
2929 device_printf(sc->sc_dev,
2930 "%s: warning, recursive reset path!\n",
2931 __func__);
2932
2933 return w;
2934 }
2935 #undef MAX_RESET_ITERATIONS
2936
2937 /*
2938 * Reset the hardware w/o losing operational state. This is
2939 * basically a more efficient way of doing ath_stop, ath_init,
2940 * followed by state transitions to the current 802.11
2941 * operational state. Used to recover from various errors and
2942 * to reset or reload hardware state.
2943 */
2944 int
ath_reset(struct ath_softc * sc,ATH_RESET_TYPE reset_type,HAL_RESET_TYPE ah_reset_type)2945 ath_reset(struct ath_softc *sc, ATH_RESET_TYPE reset_type,
2946 HAL_RESET_TYPE ah_reset_type)
2947 {
2948 struct ieee80211com *ic = &sc->sc_ic;
2949 struct ath_hal *ah = sc->sc_ah;
2950 HAL_STATUS status;
2951 int i;
2952
2953 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
2954
2955 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */
2956 ATH_PCU_UNLOCK_ASSERT(sc);
2957 ATH_UNLOCK_ASSERT(sc);
2958
2959 /* Try to (stop any further TX/RX from occurring */
2960 taskqueue_block(sc->sc_tq);
2961
2962 /*
2963 * Wake the hardware up.
2964 */
2965 ATH_LOCK(sc);
2966 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2967 ATH_UNLOCK(sc);
2968
2969 ATH_PCU_LOCK(sc);
2970
2971 /*
2972 * Grab the reset lock before TX/RX is stopped.
2973 *
2974 * This is needed to ensure that when the TX/RX actually does finish,
2975 * no further TX/RX/reset runs in parallel with this.
2976 */
2977 if (ath_reset_grablock(sc, 1) == 0) {
2978 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
2979 __func__);
2980 }
2981
2982 /* disable interrupts */
2983 ath_hal_intrset(ah, 0);
2984
2985 /*
2986 * Now, ensure that any in progress TX/RX completes before we
2987 * continue.
2988 */
2989 ath_txrx_stop_locked(sc);
2990
2991 ATH_PCU_UNLOCK(sc);
2992
2993 /*
2994 * Regardless of whether we're doing a no-loss flush or
2995 * not, stop the PCU and handle what's in the RX queue.
2996 * That way frames aren't dropped which shouldn't be.
2997 */
2998 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS));
2999 ath_rx_flush(sc);
3000
3001 /*
3002 * Should now wait for pending TX/RX to complete
3003 * and block future ones from occurring. This needs to be
3004 * done before the TX queue is drained.
3005 */
3006 ath_draintxq(sc, reset_type); /* stop xmit side */
3007
3008 ath_settkipmic(sc); /* configure TKIP MIC handling */
3009 /* NB: indicate channel change so we do a full reset */
3010 ath_update_chainmasks(sc, ic->ic_curchan);
3011 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
3012 sc->sc_cur_rxchainmask);
3013 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE,
3014 ah_reset_type, &status))
3015 device_printf(sc->sc_dev,
3016 "%s: unable to reset hardware; hal status %u\n",
3017 __func__, status);
3018 sc->sc_diversity = ath_hal_getdiversity(ah);
3019
3020 ATH_RX_LOCK(sc);
3021 sc->sc_rx_stopped = 1;
3022 sc->sc_rx_resetted = 1;
3023 ATH_RX_UNLOCK(sc);
3024
3025 /* Quiet time handling - ensure we resync */
3026 ath_vap_clear_quiet_ie(sc);
3027
3028 /* Let DFS at it in case it's a DFS channel */
3029 ath_dfs_radar_enable(sc, ic->ic_curchan);
3030
3031 /* Let spectral at in case spectral is enabled */
3032 ath_spectral_enable(sc, ic->ic_curchan);
3033
3034 /*
3035 * Let bluetooth coexistence at in case it's needed for this channel
3036 */
3037 ath_btcoex_enable(sc, ic->ic_curchan);
3038
3039 /*
3040 * If we're doing TDMA, enforce the TXOP limitation for chips that
3041 * support it.
3042 */
3043 if (sc->sc_hasenforcetxop && sc->sc_tdma)
3044 ath_hal_setenforcetxop(sc->sc_ah, 1);
3045 else
3046 ath_hal_setenforcetxop(sc->sc_ah, 0);
3047
3048 if (ath_startrecv(sc) != 0) /* restart recv */
3049 device_printf(sc->sc_dev,
3050 "%s: unable to start recv logic\n", __func__);
3051 /*
3052 * We may be doing a reset in response to an ioctl
3053 * that changes the channel so update any state that
3054 * might change as a result.
3055 */
3056 ath_chan_change(sc, ic->ic_curchan);
3057 if (sc->sc_beacons) { /* restart beacons */
3058 #ifdef IEEE80211_SUPPORT_TDMA
3059 if (sc->sc_tdma)
3060 ath_tdma_config(sc, NULL);
3061 else
3062 #endif
3063 ath_beacon_config(sc, NULL);
3064 }
3065
3066 /*
3067 * Release the reset lock and re-enable interrupts here.
3068 * If an interrupt was being processed in ath_intr(),
3069 * it would disable interrupts at this point. So we have
3070 * to atomically enable interrupts and decrement the
3071 * reset counter - this way ath_intr() doesn't end up
3072 * disabling interrupts without a corresponding enable
3073 * in the rest or channel change path.
3074 *
3075 * Grab the TX reference in case we need to transmit.
3076 * That way a parallel transmit doesn't.
3077 */
3078 ATH_PCU_LOCK(sc);
3079 sc->sc_inreset_cnt--;
3080 sc->sc_txstart_cnt++;
3081 /* XXX only do this if sc_inreset_cnt == 0? */
3082 ath_hal_intrset(ah, sc->sc_imask);
3083 ATH_PCU_UNLOCK(sc);
3084
3085 /*
3086 * TX and RX can be started here. If it were started with
3087 * sc_inreset_cnt > 0, the TX and RX path would abort.
3088 * Thus if this is a nested call through the reset or
3089 * channel change code, TX completion will occur but
3090 * RX completion and ath_start / ath_tx_start will not
3091 * run.
3092 */
3093
3094 /* Restart TX/RX as needed */
3095 ath_txrx_start(sc);
3096
3097 /* XXX TODO: we need to hold the tx refcount here! */
3098
3099 /* Restart TX completion and pending TX */
3100 if (reset_type == ATH_RESET_NOLOSS) {
3101 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
3102 if (ATH_TXQ_SETUP(sc, i)) {
3103 ATH_TXQ_LOCK(&sc->sc_txq[i]);
3104 ath_txq_restart_dma(sc, &sc->sc_txq[i]);
3105 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
3106
3107 ATH_TX_LOCK(sc);
3108 ath_txq_sched(sc, &sc->sc_txq[i]);
3109 ATH_TX_UNLOCK(sc);
3110 }
3111 }
3112 }
3113
3114 ATH_LOCK(sc);
3115 ath_power_restore_power_state(sc);
3116 ATH_UNLOCK(sc);
3117
3118 ATH_PCU_LOCK(sc);
3119 sc->sc_txstart_cnt--;
3120 ATH_PCU_UNLOCK(sc);
3121
3122 /* Handle any frames in the TX queue */
3123 /*
3124 * XXX should this be done by the caller, rather than
3125 * ath_reset() ?
3126 */
3127 ath_tx_kick(sc); /* restart xmit */
3128 return 0;
3129 }
3130
3131 static int
ath_reset_vap(struct ieee80211vap * vap,u_long cmd)3132 ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
3133 {
3134 struct ieee80211com *ic = vap->iv_ic;
3135 struct ath_softc *sc = ic->ic_softc;
3136 struct ath_hal *ah = sc->sc_ah;
3137
3138 switch (cmd) {
3139 case IEEE80211_IOC_TXPOWER:
3140 /*
3141 * If per-packet TPC is enabled, then we have nothing
3142 * to do; otherwise we need to force the global limit.
3143 * All this can happen directly; no need to reset.
3144 */
3145 if (!ath_hal_gettpc(ah))
3146 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
3147 return 0;
3148 }
3149 /* XXX? Full or NOLOSS? */
3150 return ath_reset(sc, ATH_RESET_FULL, HAL_RESET_NORMAL);
3151 }
3152
3153 struct ath_buf *
_ath_getbuf_locked(struct ath_softc * sc,ath_buf_type_t btype)3154 _ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype)
3155 {
3156 struct ath_buf *bf;
3157
3158 ATH_TXBUF_LOCK_ASSERT(sc);
3159
3160 if (btype == ATH_BUFTYPE_MGMT)
3161 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt);
3162 else
3163 bf = TAILQ_FIRST(&sc->sc_txbuf);
3164
3165 if (bf == NULL) {
3166 sc->sc_stats.ast_tx_getnobuf++;
3167 } else {
3168 if (bf->bf_flags & ATH_BUF_BUSY) {
3169 sc->sc_stats.ast_tx_getbusybuf++;
3170 bf = NULL;
3171 }
3172 }
3173
3174 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) {
3175 if (btype == ATH_BUFTYPE_MGMT)
3176 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list);
3177 else {
3178 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list);
3179 sc->sc_txbuf_cnt--;
3180
3181 /*
3182 * This shuldn't happen; however just to be
3183 * safe print a warning and fudge the txbuf
3184 * count.
3185 */
3186 if (sc->sc_txbuf_cnt < 0) {
3187 device_printf(sc->sc_dev,
3188 "%s: sc_txbuf_cnt < 0?\n",
3189 __func__);
3190 sc->sc_txbuf_cnt = 0;
3191 }
3192 }
3193 } else
3194 bf = NULL;
3195
3196 if (bf == NULL) {
3197 /* XXX should check which list, mgmt or otherwise */
3198 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
3199 TAILQ_FIRST(&sc->sc_txbuf) == NULL ?
3200 "out of xmit buffers" : "xmit buffer busy");
3201 return NULL;
3202 }
3203
3204 /* XXX TODO: should do this at buffer list initialisation */
3205 /* XXX (then, ensure the buffer has the right flag set) */
3206 bf->bf_flags = 0;
3207 if (btype == ATH_BUFTYPE_MGMT)
3208 bf->bf_flags |= ATH_BUF_MGMT;
3209 else
3210 bf->bf_flags &= (~ATH_BUF_MGMT);
3211
3212 /* Valid bf here; clear some basic fields */
3213 bf->bf_next = NULL; /* XXX just to be sure */
3214 bf->bf_last = NULL; /* XXX again, just to be sure */
3215 bf->bf_comp = NULL; /* XXX again, just to be sure */
3216 bzero(&bf->bf_state, sizeof(bf->bf_state));
3217
3218 /*
3219 * Track the descriptor ID only if doing EDMA
3220 */
3221 if (sc->sc_isedma) {
3222 bf->bf_descid = sc->sc_txbuf_descid;
3223 sc->sc_txbuf_descid++;
3224 }
3225
3226 return bf;
3227 }
3228
3229 /*
3230 * When retrying a software frame, buffers marked ATH_BUF_BUSY
3231 * can't be thrown back on the queue as they could still be
3232 * in use by the hardware.
3233 *
3234 * This duplicates the buffer, or returns NULL.
3235 *
3236 * The descriptor is also copied but the link pointers and
3237 * the DMA segments aren't copied; this frame should thus
3238 * be again passed through the descriptor setup/chain routines
3239 * so the link is correct.
3240 *
3241 * The caller must free the buffer using ath_freebuf().
3242 */
3243 struct ath_buf *
ath_buf_clone(struct ath_softc * sc,struct ath_buf * bf)3244 ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf)
3245 {
3246 struct ath_buf *tbf;
3247
3248 tbf = ath_getbuf(sc,
3249 (bf->bf_flags & ATH_BUF_MGMT) ?
3250 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL);
3251 if (tbf == NULL)
3252 return NULL; /* XXX failure? Why? */
3253
3254 /* Copy basics */
3255 tbf->bf_next = NULL;
3256 tbf->bf_nseg = bf->bf_nseg;
3257 tbf->bf_flags = bf->bf_flags & ATH_BUF_FLAGS_CLONE;
3258 tbf->bf_status = bf->bf_status;
3259 tbf->bf_m = bf->bf_m;
3260 tbf->bf_node = bf->bf_node;
3261 KASSERT((bf->bf_node != NULL), ("%s: bf_node=NULL!", __func__));
3262 /* will be setup by the chain/setup function */
3263 tbf->bf_lastds = NULL;
3264 /* for now, last == self */
3265 tbf->bf_last = tbf;
3266 tbf->bf_comp = bf->bf_comp;
3267
3268 /* NOTE: DMA segments will be setup by the setup/chain functions */
3269
3270 /* The caller has to re-init the descriptor + links */
3271
3272 /*
3273 * Free the DMA mapping here, before we NULL the mbuf.
3274 * We must only call bus_dmamap_unload() once per mbuf chain
3275 * or behaviour is undefined.
3276 */
3277 if (bf->bf_m != NULL) {
3278 /*
3279 * XXX is this POSTWRITE call required?
3280 */
3281 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3282 BUS_DMASYNC_POSTWRITE);
3283 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3284 }
3285
3286 bf->bf_m = NULL;
3287 bf->bf_node = NULL;
3288
3289 /* Copy state */
3290 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state));
3291
3292 return tbf;
3293 }
3294
3295 struct ath_buf *
ath_getbuf(struct ath_softc * sc,ath_buf_type_t btype)3296 ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype)
3297 {
3298 struct ath_buf *bf;
3299
3300 ATH_TXBUF_LOCK(sc);
3301 bf = _ath_getbuf_locked(sc, btype);
3302 /*
3303 * If a mgmt buffer was requested but we're out of those,
3304 * try requesting a normal one.
3305 */
3306 if (bf == NULL && btype == ATH_BUFTYPE_MGMT)
3307 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
3308 ATH_TXBUF_UNLOCK(sc);
3309 if (bf == NULL) {
3310 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
3311 sc->sc_stats.ast_tx_qstop++;
3312 }
3313 return bf;
3314 }
3315
3316 /*
3317 * Transmit a single frame.
3318 *
3319 * net80211 will free the node reference if the transmit
3320 * fails, so don't free the node reference here.
3321 */
3322 static int
ath_transmit(struct ieee80211com * ic,struct mbuf * m)3323 ath_transmit(struct ieee80211com *ic, struct mbuf *m)
3324 {
3325 struct ath_softc *sc = ic->ic_softc;
3326 struct ieee80211_node *ni;
3327 struct mbuf *next;
3328 struct ath_buf *bf;
3329 ath_bufhead frags;
3330 int retval = 0;
3331
3332 /*
3333 * Tell the reset path that we're currently transmitting.
3334 */
3335 ATH_PCU_LOCK(sc);
3336 if (sc->sc_inreset_cnt > 0) {
3337 DPRINTF(sc, ATH_DEBUG_XMIT,
3338 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
3339 ATH_PCU_UNLOCK(sc);
3340 sc->sc_stats.ast_tx_qstop++;
3341 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish");
3342 return (ENOBUFS); /* XXX should be EINVAL or? */
3343 }
3344 sc->sc_txstart_cnt++;
3345 ATH_PCU_UNLOCK(sc);
3346
3347 /* Wake the hardware up already */
3348 ATH_LOCK(sc);
3349 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3350 ATH_UNLOCK(sc);
3351
3352 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: start");
3353 /*
3354 * Grab the TX lock - it's ok to do this here; we haven't
3355 * yet started transmitting.
3356 */
3357 ATH_TX_LOCK(sc);
3358
3359 /*
3360 * Node reference, if there's one.
3361 */
3362 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
3363
3364 /*
3365 * Enforce how deep a node queue can get.
3366 *
3367 * XXX it would be nicer if we kept an mbuf queue per
3368 * node and only whacked them into ath_bufs when we
3369 * are ready to schedule some traffic from them.
3370 * .. that may come later.
3371 *
3372 * XXX we should also track the per-node hardware queue
3373 * depth so it is easy to limit the _SUM_ of the swq and
3374 * hwq frames. Since we only schedule two HWQ frames
3375 * at a time, this should be OK for now.
3376 */
3377 if ((!(m->m_flags & M_EAPOL)) &&
3378 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) {
3379 sc->sc_stats.ast_tx_nodeq_overflow++;
3380 retval = ENOBUFS;
3381 goto finish;
3382 }
3383
3384 /*
3385 * Check how many TX buffers are available.
3386 *
3387 * If this is for non-EAPOL traffic, just leave some
3388 * space free in order for buffer cloning and raw
3389 * frame transmission to occur.
3390 *
3391 * If it's for EAPOL traffic, ignore this for now.
3392 * Management traffic will be sent via the raw transmit
3393 * method which bypasses this check.
3394 *
3395 * This is needed to ensure that EAPOL frames during
3396 * (re) keying have a chance to go out.
3397 *
3398 * See kern/138379 for more information.
3399 */
3400 if ((!(m->m_flags & M_EAPOL)) &&
3401 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) {
3402 sc->sc_stats.ast_tx_nobuf++;
3403 retval = ENOBUFS;
3404 goto finish;
3405 }
3406
3407 /*
3408 * Grab a TX buffer and associated resources.
3409 *
3410 * If it's an EAPOL frame, allocate a MGMT ath_buf.
3411 * That way even with temporary buffer exhaustion due to
3412 * the data path doesn't leave us without the ability
3413 * to transmit management frames.
3414 *
3415 * Otherwise allocate a normal buffer.
3416 */
3417 if (m->m_flags & M_EAPOL)
3418 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT);
3419 else
3420 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL);
3421
3422 if (bf == NULL) {
3423 /*
3424 * If we failed to allocate a buffer, fail.
3425 *
3426 * We shouldn't fail normally, due to the check
3427 * above.
3428 */
3429 sc->sc_stats.ast_tx_nobuf++;
3430 retval = ENOBUFS;
3431 goto finish;
3432 }
3433
3434 /*
3435 * At this point we have a buffer; so we need to free it
3436 * if we hit any error conditions.
3437 */
3438
3439 /*
3440 * Check for fragmentation. If this frame
3441 * has been broken up verify we have enough
3442 * buffers to send all the fragments so all
3443 * go out or none...
3444 */
3445 TAILQ_INIT(&frags);
3446 if ((m->m_flags & M_FRAG) &&
3447 !ath_txfrag_setup(sc, &frags, m, ni)) {
3448 DPRINTF(sc, ATH_DEBUG_XMIT,
3449 "%s: out of txfrag buffers\n", __func__);
3450 sc->sc_stats.ast_tx_nofrag++;
3451 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1);
3452 /*
3453 * XXXGL: is mbuf valid after ath_txfrag_setup? If yes,
3454 * we shouldn't free it but return back.
3455 */
3456 ieee80211_free_mbuf(m);
3457 m = NULL;
3458 goto bad;
3459 }
3460
3461 /*
3462 * At this point if we have any TX fragments, then we will
3463 * have bumped the node reference once for each of those.
3464 */
3465
3466 /*
3467 * XXX Is there anything actually _enforcing_ that the
3468 * fragments are being transmitted in one hit, rather than
3469 * being interleaved with other transmissions on that
3470 * hardware queue?
3471 *
3472 * The ATH TX output lock is the only thing serialising this
3473 * right now.
3474 */
3475
3476 /*
3477 * Calculate the "next fragment" length field in ath_buf
3478 * in order to let the transmit path know enough about
3479 * what to next write to the hardware.
3480 */
3481 if (m->m_flags & M_FRAG) {
3482 struct ath_buf *fbf = bf;
3483 struct ath_buf *n_fbf = NULL;
3484 struct mbuf *fm = m->m_nextpkt;
3485
3486 /*
3487 * We need to walk the list of fragments and set
3488 * the next size to the following buffer.
3489 * However, the first buffer isn't in the frag
3490 * list, so we have to do some gymnastics here.
3491 */
3492 TAILQ_FOREACH(n_fbf, &frags, bf_list) {
3493 fbf->bf_nextfraglen = fm->m_pkthdr.len;
3494 fbf = n_fbf;
3495 fm = fm->m_nextpkt;
3496 }
3497 }
3498
3499 nextfrag:
3500 /*
3501 * Pass the frame to the h/w for transmission.
3502 * Fragmented frames have each frag chained together
3503 * with m_nextpkt. We know there are sufficient ath_buf's
3504 * to send all the frags because of work done by
3505 * ath_txfrag_setup. We leave m_nextpkt set while
3506 * calling ath_tx_start so it can use it to extend the
3507 * the tx duration to cover the subsequent frag and
3508 * so it can reclaim all the mbufs in case of an error;
3509 * ath_tx_start clears m_nextpkt once it commits to
3510 * handing the frame to the hardware.
3511 *
3512 * Note: if this fails, then the mbufs are freed but
3513 * not the node reference.
3514 *
3515 * So, we now have to free the node reference ourselves here
3516 * and return OK up to the stack.
3517 */
3518 next = m->m_nextpkt;
3519 if (ath_tx_start(sc, ni, bf, m)) {
3520 bad:
3521 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1);
3522 reclaim:
3523 bf->bf_m = NULL;
3524 bf->bf_node = NULL;
3525 ATH_TXBUF_LOCK(sc);
3526 ath_returnbuf_head(sc, bf);
3527 /*
3528 * Free the rest of the node references and
3529 * buffers for the fragment list.
3530 */
3531 ath_txfrag_cleanup(sc, &frags, ni);
3532 ATH_TXBUF_UNLOCK(sc);
3533
3534 /*
3535 * XXX: And free the node/return OK; ath_tx_start() may have
3536 * modified the buffer. We currently have no way to
3537 * signify that the mbuf was freed but there was an error.
3538 */
3539 ieee80211_free_node(ni);
3540 retval = 0;
3541 goto finish;
3542 }
3543
3544 /*
3545 * Check here if the node is in power save state.
3546 */
3547 ath_tx_update_tim(sc, ni, 1);
3548
3549 if (next != NULL) {
3550 /*
3551 * Beware of state changing between frags.
3552 * XXX check sta power-save state?
3553 */
3554 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
3555 DPRINTF(sc, ATH_DEBUG_XMIT,
3556 "%s: flush fragmented packet, state %s\n",
3557 __func__,
3558 ieee80211_state_name[ni->ni_vap->iv_state]);
3559 /* XXX dmamap */
3560 ieee80211_free_mbuf(next);
3561 goto reclaim;
3562 }
3563 m = next;
3564 bf = TAILQ_FIRST(&frags);
3565 KASSERT(bf != NULL, ("no buf for txfrag"));
3566 TAILQ_REMOVE(&frags, bf, bf_list);
3567 goto nextfrag;
3568 }
3569
3570 /*
3571 * Bump watchdog timer.
3572 */
3573 sc->sc_wd_timer = 5;
3574
3575 finish:
3576 ATH_TX_UNLOCK(sc);
3577
3578 /*
3579 * Finished transmitting!
3580 */
3581 ATH_PCU_LOCK(sc);
3582 sc->sc_txstart_cnt--;
3583 ATH_PCU_UNLOCK(sc);
3584
3585 /* Sleep the hardware if required */
3586 ATH_LOCK(sc);
3587 ath_power_restore_power_state(sc);
3588 ATH_UNLOCK(sc);
3589
3590 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: finished");
3591
3592 return (retval);
3593 }
3594
3595 /*
3596 * Block/unblock tx+rx processing while a key change is done.
3597 * We assume the caller serializes key management operations
3598 * so we only need to worry about synchronization with other
3599 * uses that originate in the driver.
3600 */
3601 static void
ath_key_update_begin(struct ieee80211vap * vap)3602 ath_key_update_begin(struct ieee80211vap *vap)
3603 {
3604 struct ath_softc *sc = vap->iv_ic->ic_softc;
3605
3606 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
3607 taskqueue_block(sc->sc_tq);
3608 }
3609
3610 static void
ath_key_update_end(struct ieee80211vap * vap)3611 ath_key_update_end(struct ieee80211vap *vap)
3612 {
3613 struct ath_softc *sc = vap->iv_ic->ic_softc;
3614
3615 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
3616 taskqueue_unblock(sc->sc_tq);
3617 }
3618
3619 static void
ath_update_promisc(struct ieee80211com * ic)3620 ath_update_promisc(struct ieee80211com *ic)
3621 {
3622 struct ath_softc *sc = ic->ic_softc;
3623 u_int32_t rfilt;
3624
3625 /* configure rx filter */
3626 ATH_LOCK(sc);
3627 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3628 rfilt = ath_calcrxfilter(sc);
3629 ath_hal_setrxfilter(sc->sc_ah, rfilt);
3630 ath_power_restore_power_state(sc);
3631 ATH_UNLOCK(sc);
3632
3633 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
3634 }
3635
3636 static u_int
ath_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)3637 ath_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
3638 {
3639 uint32_t val, *mfilt = arg;
3640 char *dl;
3641 uint8_t pos;
3642
3643 /* calculate XOR of eight 6bit values */
3644 dl = LLADDR(sdl);
3645 val = le32dec(dl + 0);
3646 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3647 val = le32dec(dl + 3);
3648 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3649 pos &= 0x3f;
3650 mfilt[pos / 32] |= (1 << (pos % 32));
3651
3652 return (1);
3653 }
3654
3655 /*
3656 * Driver-internal mcast update call.
3657 *
3658 * Assumes the hardware is already awake.
3659 */
3660 static void
ath_update_mcast_hw(struct ath_softc * sc)3661 ath_update_mcast_hw(struct ath_softc *sc)
3662 {
3663 struct ieee80211com *ic = &sc->sc_ic;
3664 u_int32_t mfilt[2];
3665
3666 /* calculate and install multicast filter */
3667 if (ic->ic_allmulti == 0) {
3668 struct ieee80211vap *vap;
3669
3670 /*
3671 * Merge multicast addresses to form the hardware filter.
3672 */
3673 mfilt[0] = mfilt[1] = 0;
3674 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next)
3675 if_foreach_llmaddr(vap->iv_ifp, ath_hash_maddr, &mfilt);
3676 } else
3677 mfilt[0] = mfilt[1] = ~0;
3678
3679 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
3680
3681 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
3682 __func__, mfilt[0], mfilt[1]);
3683 }
3684
3685 /*
3686 * Called from the net80211 layer - force the hardware
3687 * awake before operating.
3688 */
3689 static void
ath_update_mcast(struct ieee80211com * ic)3690 ath_update_mcast(struct ieee80211com *ic)
3691 {
3692 struct ath_softc *sc = ic->ic_softc;
3693
3694 ATH_LOCK(sc);
3695 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3696 ATH_UNLOCK(sc);
3697
3698 ath_update_mcast_hw(sc);
3699
3700 ATH_LOCK(sc);
3701 ath_power_restore_power_state(sc);
3702 ATH_UNLOCK(sc);
3703 }
3704
3705 void
ath_mode_init(struct ath_softc * sc)3706 ath_mode_init(struct ath_softc *sc)
3707 {
3708 struct ieee80211com *ic = &sc->sc_ic;
3709 struct ath_hal *ah = sc->sc_ah;
3710 u_int32_t rfilt;
3711
3712 /* XXX power state? */
3713
3714 /* configure rx filter */
3715 rfilt = ath_calcrxfilter(sc);
3716 ath_hal_setrxfilter(ah, rfilt);
3717
3718 /* configure operational mode */
3719 ath_hal_setopmode(ah);
3720
3721 /* handle any link-level address change */
3722 ath_hal_setmac(ah, ic->ic_macaddr);
3723
3724 /* calculate and install multicast filter */
3725 ath_update_mcast_hw(sc);
3726 }
3727
3728 /*
3729 * Set the slot time based on the current setting.
3730 */
3731 void
ath_setslottime(struct ath_softc * sc)3732 ath_setslottime(struct ath_softc *sc)
3733 {
3734 struct ieee80211com *ic = &sc->sc_ic;
3735 struct ath_hal *ah = sc->sc_ah;
3736 u_int usec;
3737
3738 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
3739 usec = 13;
3740 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
3741 usec = 21;
3742 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
3743 /* honor short/long slot time only in 11g */
3744 /* XXX shouldn't honor on pure g or turbo g channel */
3745 if (ic->ic_flags & IEEE80211_F_SHSLOT)
3746 usec = HAL_SLOT_TIME_9;
3747 else
3748 usec = HAL_SLOT_TIME_20;
3749 } else
3750 usec = HAL_SLOT_TIME_9;
3751
3752 DPRINTF(sc, ATH_DEBUG_RESET,
3753 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
3754 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
3755 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
3756
3757 /* Wake up the hardware first before updating the slot time */
3758 ATH_LOCK(sc);
3759 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3760 ath_hal_setslottime(ah, usec);
3761 ath_power_restore_power_state(sc);
3762 sc->sc_updateslot = OK;
3763 ATH_UNLOCK(sc);
3764 }
3765
3766 /*
3767 * Callback from the 802.11 layer to update the
3768 * slot time based on the current setting.
3769 */
3770 static void
ath_updateslot(struct ieee80211com * ic)3771 ath_updateslot(struct ieee80211com *ic)
3772 {
3773 struct ath_softc *sc = ic->ic_softc;
3774
3775 /*
3776 * When not coordinating the BSS, change the hardware
3777 * immediately. For other operation we defer the change
3778 * until beacon updates have propagated to the stations.
3779 *
3780 * XXX sc_updateslot isn't changed behind a lock?
3781 */
3782 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3783 ic->ic_opmode == IEEE80211_M_MBSS)
3784 sc->sc_updateslot = UPDATE;
3785 else
3786 ath_setslottime(sc);
3787 }
3788
3789 /*
3790 * Append the contents of src to dst; both queues
3791 * are assumed to be locked.
3792 */
3793 void
ath_txqmove(struct ath_txq * dst,struct ath_txq * src)3794 ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
3795 {
3796
3797 ATH_TXQ_LOCK_ASSERT(src);
3798 ATH_TXQ_LOCK_ASSERT(dst);
3799
3800 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list);
3801 dst->axq_link = src->axq_link;
3802 src->axq_link = NULL;
3803 dst->axq_depth += src->axq_depth;
3804 dst->axq_aggr_depth += src->axq_aggr_depth;
3805 src->axq_depth = 0;
3806 src->axq_aggr_depth = 0;
3807 }
3808
3809 /*
3810 * Reset the hardware, with no loss.
3811 *
3812 * This can't be used for a general case reset.
3813 */
3814 static void
ath_reset_proc(void * arg,int pending)3815 ath_reset_proc(void *arg, int pending)
3816 {
3817 struct ath_softc *sc = arg;
3818
3819 #if 0
3820 device_printf(sc->sc_dev, "%s: resetting\n", __func__);
3821 #endif
3822 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
3823 }
3824
3825 /*
3826 * Reset the hardware after detecting beacons have stopped.
3827 */
3828 static void
ath_bstuck_proc(void * arg,int pending)3829 ath_bstuck_proc(void *arg, int pending)
3830 {
3831 struct ath_softc *sc = arg;
3832 uint32_t hangs = 0;
3833
3834 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0)
3835 device_printf(sc->sc_dev, "bb hang detected (0x%x)\n", hangs);
3836
3837 #ifdef ATH_DEBUG_ALQ
3838 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_STUCK_BEACON))
3839 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_STUCK_BEACON, 0, NULL);
3840 #endif
3841
3842 device_printf(sc->sc_dev, "stuck beacon; resetting (bmiss count %u)\n",
3843 sc->sc_bmisscount);
3844 sc->sc_stats.ast_bstuck++;
3845 /*
3846 * This assumes that there's no simultaneous channel mode change
3847 * occurring.
3848 */
3849 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
3850 }
3851
3852 static int
ath_desc_alloc(struct ath_softc * sc)3853 ath_desc_alloc(struct ath_softc *sc)
3854 {
3855 int error;
3856
3857 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3858 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER);
3859 if (error != 0) {
3860 return error;
3861 }
3862 sc->sc_txbuf_cnt = ath_txbuf;
3863
3864 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt,
3865 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt,
3866 ATH_TXDESC);
3867 if (error != 0) {
3868 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3869 return error;
3870 }
3871
3872 /*
3873 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the
3874 * flag doesn't have to be set in ath_getbuf_locked().
3875 */
3876
3877 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3878 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1);
3879 if (error != 0) {
3880 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3881 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3882 &sc->sc_txbuf_mgmt);
3883 return error;
3884 }
3885 return 0;
3886 }
3887
3888 static void
ath_desc_free(struct ath_softc * sc)3889 ath_desc_free(struct ath_softc *sc)
3890 {
3891
3892 if (sc->sc_bdma.dd_desc_len != 0)
3893 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3894 if (sc->sc_txdma.dd_desc_len != 0)
3895 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3896 if (sc->sc_txdma_mgmt.dd_desc_len != 0)
3897 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3898 &sc->sc_txbuf_mgmt);
3899 }
3900
3901 static struct ieee80211_node *
ath_node_alloc(struct ieee80211vap * vap,const uint8_t mac[IEEE80211_ADDR_LEN])3902 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
3903 {
3904 struct ieee80211com *ic = vap->iv_ic;
3905 struct ath_softc *sc = ic->ic_softc;
3906 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3907 struct ath_node *an;
3908
3909 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
3910 if (an == NULL) {
3911 /* XXX stat+msg */
3912 return NULL;
3913 }
3914 ath_rate_node_init(sc, an);
3915
3916 /* Setup the mutex - there's no associd yet so set the name to NULL */
3917 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p",
3918 device_get_nameunit(sc->sc_dev), an);
3919 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF);
3920
3921 /* XXX setup ath_tid */
3922 ath_tx_tid_init(sc, an);
3923
3924 an->an_node_stats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
3925 an->an_node_stats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
3926 an->an_node_stats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
3927
3928 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, mac, ":", an);
3929 return &an->an_node;
3930 }
3931
3932 static void
ath_node_cleanup(struct ieee80211_node * ni)3933 ath_node_cleanup(struct ieee80211_node *ni)
3934 {
3935 struct ieee80211com *ic = ni->ni_ic;
3936 struct ath_softc *sc = ic->ic_softc;
3937
3938 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3939 ni->ni_macaddr, ":", ATH_NODE(ni));
3940
3941 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */
3942 ath_tx_node_flush(sc, ATH_NODE(ni));
3943 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3944 sc->sc_node_cleanup(ni);
3945 }
3946
3947 static void
ath_node_free(struct ieee80211_node * ni)3948 ath_node_free(struct ieee80211_node *ni)
3949 {
3950 struct ieee80211com *ic = ni->ni_ic;
3951 struct ath_softc *sc = ic->ic_softc;
3952
3953 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3954 ni->ni_macaddr, ":", ATH_NODE(ni));
3955 mtx_destroy(&ATH_NODE(ni)->an_mtx);
3956 sc->sc_node_free(ni);
3957 }
3958
3959 static void
ath_node_getsignal(const struct ieee80211_node * ni,int8_t * rssi,int8_t * noise)3960 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
3961 {
3962 struct ieee80211com *ic = ni->ni_ic;
3963 struct ath_softc *sc = ic->ic_softc;
3964 struct ath_hal *ah = sc->sc_ah;
3965
3966 *rssi = ic->ic_node_getrssi(ni);
3967 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
3968 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
3969 else
3970 *noise = -95; /* nominally correct */
3971 }
3972
3973 /*
3974 * Set the default antenna.
3975 */
3976 void
ath_setdefantenna(struct ath_softc * sc,u_int antenna)3977 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3978 {
3979 struct ath_hal *ah = sc->sc_ah;
3980
3981 /* XXX block beacon interrupts */
3982 ath_hal_setdefantenna(ah, antenna);
3983 if (sc->sc_defant != antenna)
3984 sc->sc_stats.ast_ant_defswitch++;
3985 sc->sc_defant = antenna;
3986 sc->sc_rxotherant = 0;
3987 }
3988
3989 static void
ath_txq_init(struct ath_softc * sc,struct ath_txq * txq,int qnum)3990 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
3991 {
3992 txq->axq_qnum = qnum;
3993 txq->axq_ac = 0;
3994 txq->axq_depth = 0;
3995 txq->axq_aggr_depth = 0;
3996 txq->axq_intrcnt = 0;
3997 txq->axq_link = NULL;
3998 txq->axq_softc = sc;
3999 TAILQ_INIT(&txq->axq_q);
4000 TAILQ_INIT(&txq->axq_tidq);
4001 TAILQ_INIT(&txq->fifo.axq_q);
4002 ATH_TXQ_LOCK_INIT(sc, txq);
4003 }
4004
4005 /*
4006 * Setup a h/w transmit queue.
4007 */
4008 static struct ath_txq *
ath_txq_setup(struct ath_softc * sc,int qtype,int subtype)4009 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
4010 {
4011 struct ath_hal *ah = sc->sc_ah;
4012 HAL_TXQ_INFO qi;
4013 int qnum;
4014
4015 memset(&qi, 0, sizeof(qi));
4016 qi.tqi_subtype = subtype;
4017 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
4018 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
4019 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
4020 /*
4021 * Enable interrupts only for EOL and DESC conditions.
4022 * We mark tx descriptors to receive a DESC interrupt
4023 * when a tx queue gets deep; otherwise waiting for the
4024 * EOL to reap descriptors. Note that this is done to
4025 * reduce interrupt load and this only defers reaping
4026 * descriptors, never transmitting frames. Aside from
4027 * reducing interrupts this also permits more concurrency.
4028 * The only potential downside is if the tx queue backs
4029 * up in which case the top half of the kernel may backup
4030 * due to a lack of tx descriptors.
4031 */
4032 if (sc->sc_isedma)
4033 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
4034 HAL_TXQ_TXOKINT_ENABLE;
4035 else
4036 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
4037 HAL_TXQ_TXDESCINT_ENABLE;
4038
4039 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
4040 if (qnum == -1) {
4041 /*
4042 * NB: don't print a message, this happens
4043 * normally on parts with too few tx queues
4044 */
4045 return NULL;
4046 }
4047 if (qnum >= nitems(sc->sc_txq)) {
4048 device_printf(sc->sc_dev,
4049 "hal qnum %u out of range, max %zu!\n",
4050 qnum, nitems(sc->sc_txq));
4051 ath_hal_releasetxqueue(ah, qnum);
4052 return NULL;
4053 }
4054 if (!ATH_TXQ_SETUP(sc, qnum)) {
4055 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
4056 sc->sc_txqsetup |= 1<<qnum;
4057 }
4058 return &sc->sc_txq[qnum];
4059 }
4060
4061 /*
4062 * Setup a hardware data transmit queue for the specified
4063 * access control. The hal may not support all requested
4064 * queues in which case it will return a reference to a
4065 * previously setup queue. We record the mapping from ac's
4066 * to h/w queues for use by ath_tx_start and also track
4067 * the set of h/w queues being used to optimize work in the
4068 * transmit interrupt handler and related routines.
4069 */
4070 static int
ath_tx_setup(struct ath_softc * sc,int ac,int haltype)4071 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
4072 {
4073 struct ath_txq *txq;
4074
4075 if (ac >= nitems(sc->sc_ac2q)) {
4076 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
4077 ac, nitems(sc->sc_ac2q));
4078 return 0;
4079 }
4080 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
4081 if (txq != NULL) {
4082 txq->axq_ac = ac;
4083 sc->sc_ac2q[ac] = txq;
4084 return 1;
4085 } else
4086 return 0;
4087 }
4088
4089 /*
4090 * Update WME parameters for a transmit queue.
4091 */
4092 static int
ath_txq_update(struct ath_softc * sc,int ac)4093 ath_txq_update(struct ath_softc *sc, int ac)
4094 {
4095 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
4096 struct ieee80211com *ic = &sc->sc_ic;
4097 struct ath_txq *txq = sc->sc_ac2q[ac];
4098 struct chanAccParams chp;
4099 struct wmeParams *wmep;
4100 struct ath_hal *ah = sc->sc_ah;
4101 HAL_TXQ_INFO qi;
4102
4103 ieee80211_wme_ic_getparams(ic, &chp);
4104 wmep = &chp.cap_wmeParams[ac];
4105
4106 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
4107 #ifdef IEEE80211_SUPPORT_TDMA
4108 if (sc->sc_tdma) {
4109 /*
4110 * AIFS is zero so there's no pre-transmit wait. The
4111 * burst time defines the slot duration and is configured
4112 * through net80211. The QCU is setup to not do post-xmit
4113 * back off, lockout all lower-priority QCU's, and fire
4114 * off the DMA beacon alert timer which is setup based
4115 * on the slot configuration.
4116 */
4117 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4118 | HAL_TXQ_TXERRINT_ENABLE
4119 | HAL_TXQ_TXURNINT_ENABLE
4120 | HAL_TXQ_TXEOLINT_ENABLE
4121 | HAL_TXQ_DBA_GATED
4122 | HAL_TXQ_BACKOFF_DISABLE
4123 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
4124 ;
4125 qi.tqi_aifs = 0;
4126 /* XXX +dbaprep? */
4127 qi.tqi_readyTime = sc->sc_tdmaslotlen;
4128 qi.tqi_burstTime = qi.tqi_readyTime;
4129 } else {
4130 #endif
4131 /*
4132 * XXX shouldn't this just use the default flags
4133 * used in the previous queue setup?
4134 */
4135 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4136 | HAL_TXQ_TXERRINT_ENABLE
4137 | HAL_TXQ_TXDESCINT_ENABLE
4138 | HAL_TXQ_TXURNINT_ENABLE
4139 | HAL_TXQ_TXEOLINT_ENABLE
4140 ;
4141 qi.tqi_aifs = wmep->wmep_aifsn;
4142 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
4143 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
4144 qi.tqi_readyTime = 0;
4145 qi.tqi_burstTime = IEEE80211_TXOP_TO_US(wmep->wmep_txopLimit);
4146 #ifdef IEEE80211_SUPPORT_TDMA
4147 }
4148 #endif
4149
4150 DPRINTF(sc, ATH_DEBUG_RESET,
4151 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
4152 __func__, txq->axq_qnum, qi.tqi_qflags,
4153 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
4154
4155 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
4156 device_printf(sc->sc_dev, "unable to update hardware queue "
4157 "parameters for %s traffic!\n", ieee80211_wme_acnames[ac]);
4158 return 0;
4159 } else {
4160 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
4161 return 1;
4162 }
4163 #undef ATH_EXPONENT_TO_VALUE
4164 }
4165
4166 /*
4167 * Callback from the 802.11 layer to update WME parameters.
4168 */
4169 int
ath_wme_update(struct ieee80211com * ic)4170 ath_wme_update(struct ieee80211com *ic)
4171 {
4172 struct ath_softc *sc = ic->ic_softc;
4173
4174 return !ath_txq_update(sc, WME_AC_BE) ||
4175 !ath_txq_update(sc, WME_AC_BK) ||
4176 !ath_txq_update(sc, WME_AC_VI) ||
4177 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
4178 }
4179
4180 /*
4181 * Reclaim resources for a setup queue.
4182 */
4183 static void
ath_tx_cleanupq(struct ath_softc * sc,struct ath_txq * txq)4184 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
4185 {
4186
4187 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
4188 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
4189 ATH_TXQ_LOCK_DESTROY(txq);
4190 }
4191
4192 /*
4193 * Reclaim all tx queue resources.
4194 */
4195 static void
ath_tx_cleanup(struct ath_softc * sc)4196 ath_tx_cleanup(struct ath_softc *sc)
4197 {
4198 int i;
4199
4200 ATH_TXBUF_LOCK_DESTROY(sc);
4201 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4202 if (ATH_TXQ_SETUP(sc, i))
4203 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
4204 }
4205
4206 /*
4207 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
4208 * using the current rates in sc_rixmap.
4209 */
4210 int
ath_tx_findrix(const struct ath_softc * sc,uint8_t rate)4211 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
4212 {
4213 int rix = sc->sc_rixmap[rate];
4214 /* NB: return lowest rix for invalid rate */
4215 return (rix == 0xff ? 0 : rix);
4216 }
4217
4218 static void
ath_tx_update_stats(struct ath_softc * sc,struct ath_tx_status * ts,struct ath_buf * bf)4219 ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts,
4220 struct ath_buf *bf)
4221 {
4222 struct ieee80211_node *ni = bf->bf_node;
4223 struct ieee80211com *ic = &sc->sc_ic;
4224 int sr, lr, pri;
4225
4226 if (ts->ts_status == 0) {
4227 u_int8_t txant = ts->ts_antenna;
4228 /*
4229 * Handle weird/corrupted tx antenna field
4230 */
4231 if (txant >= ATH_IOCTL_STATS_NUM_TX_ANTENNA)
4232 txant = 0;
4233 sc->sc_stats.ast_ant_tx[txant]++;
4234 sc->sc_ant_tx[txant]++;
4235 if (ts->ts_finaltsi != 0)
4236 sc->sc_stats.ast_tx_altrate++;
4237
4238 /* XXX TODO: should do per-pri conuters */
4239 pri = M_WME_GETAC(bf->bf_m);
4240 if (pri >= WME_AC_VO)
4241 ic->ic_wme.wme_hipri_traffic++;
4242
4243 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)
4244 ni->ni_inact = ni->ni_inact_reload;
4245 } else {
4246 if (ts->ts_status & HAL_TXERR_XRETRY)
4247 sc->sc_stats.ast_tx_xretries++;
4248 if (ts->ts_status & HAL_TXERR_FIFO)
4249 sc->sc_stats.ast_tx_fifoerr++;
4250 if (ts->ts_status & HAL_TXERR_FILT)
4251 sc->sc_stats.ast_tx_filtered++;
4252 if (ts->ts_status & HAL_TXERR_XTXOP)
4253 sc->sc_stats.ast_tx_xtxop++;
4254 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED)
4255 sc->sc_stats.ast_tx_timerexpired++;
4256
4257 if (bf->bf_m->m_flags & M_FF)
4258 sc->sc_stats.ast_ff_txerr++;
4259 }
4260 /* XXX when is this valid? */
4261 if (ts->ts_flags & HAL_TX_DESC_CFG_ERR)
4262 sc->sc_stats.ast_tx_desccfgerr++;
4263 /*
4264 * This can be valid for successful frame transmission!
4265 * If there's a TX FIFO underrun during aggregate transmission,
4266 * the MAC will pad the rest of the aggregate with delimiters.
4267 * If a BA is returned, the frame is marked as "OK" and it's up
4268 * to the TX completion code to notice which frames weren't
4269 * successfully transmitted.
4270 */
4271 if (ts->ts_flags & HAL_TX_DATA_UNDERRUN)
4272 sc->sc_stats.ast_tx_data_underrun++;
4273 if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN)
4274 sc->sc_stats.ast_tx_delim_underrun++;
4275
4276 sr = ts->ts_shortretry;
4277 lr = ts->ts_longretry;
4278 sc->sc_stats.ast_tx_shortretry += sr;
4279 sc->sc_stats.ast_tx_longretry += lr;
4280
4281 }
4282
4283 /*
4284 * The default completion. If fail is 1, this means
4285 * "please don't retry the frame, and just return -1 status
4286 * to the net80211 stack.
4287 */
4288 void
ath_tx_default_comp(struct ath_softc * sc,struct ath_buf * bf,int fail)4289 ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
4290 {
4291 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
4292 int st;
4293
4294 if (fail == 1)
4295 st = -1;
4296 else
4297 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ?
4298 ts->ts_status : HAL_TXERR_XRETRY;
4299
4300 #if 0
4301 if (bf->bf_state.bfs_dobaw)
4302 device_printf(sc->sc_dev,
4303 "%s: bf %p: seqno %d: dobaw should've been cleared!\n",
4304 __func__,
4305 bf,
4306 SEQNO(bf->bf_state.bfs_seqno));
4307 #endif
4308 if (bf->bf_next != NULL)
4309 device_printf(sc->sc_dev,
4310 "%s: bf %p: seqno %d: bf_next not NULL!\n",
4311 __func__,
4312 bf,
4313 SEQNO(bf->bf_state.bfs_seqno));
4314
4315 /*
4316 * Check if the node software queue is empty; if so
4317 * then clear the TIM.
4318 *
4319 * This needs to be done before the buffer is freed as
4320 * otherwise the node reference will have been released
4321 * and the node may not actually exist any longer.
4322 *
4323 * XXX I don't like this belonging here, but it's cleaner
4324 * to do it here right now then all the other places
4325 * where ath_tx_default_comp() is called.
4326 *
4327 * XXX TODO: during drain, ensure that the callback is
4328 * being called so we get a chance to update the TIM.
4329 */
4330 if (bf->bf_node) {
4331 ATH_TX_LOCK(sc);
4332 ath_tx_update_tim(sc, bf->bf_node, 0);
4333 ATH_TX_UNLOCK(sc);
4334 }
4335
4336 /*
4337 * Do any tx complete callback. Note this must
4338 * be done before releasing the node reference.
4339 * This will free the mbuf, release the net80211
4340 * node and recycle the ath_buf.
4341 */
4342 ath_tx_freebuf(sc, bf, st);
4343 }
4344
4345 /*
4346 * Update rate control with the given completion status.
4347 */
4348 void
ath_tx_update_ratectrl(struct ath_softc * sc,struct ieee80211_node * ni,struct ath_rc_series * rc,struct ath_tx_status * ts,int frmlen,int rc_framelen,int nframes,int nbad)4349 ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
4350 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen,
4351 int rc_framelen, int nframes, int nbad)
4352 {
4353 struct ath_node *an;
4354
4355 /* Only for unicast frames */
4356 if (ni == NULL)
4357 return;
4358
4359 an = ATH_NODE(ni);
4360 ATH_NODE_UNLOCK_ASSERT(an);
4361
4362 /*
4363 * XXX TODO: teach the rate control about TXERR_FILT and
4364 * see about handling it (eg see how many attempts were
4365 * made before it got filtered and account for that.)
4366 */
4367
4368 if ((ts->ts_status & HAL_TXERR_FILT) == 0) {
4369 ATH_NODE_LOCK(an);
4370 ath_rate_tx_complete(sc, an, rc, ts, frmlen, rc_framelen,
4371 nframes, nbad);
4372 ATH_NODE_UNLOCK(an);
4373 }
4374 }
4375
4376 /*
4377 * Process the completion of the given buffer.
4378 *
4379 * This calls the rate control update and then the buffer completion.
4380 * This will either free the buffer or requeue it. In any case, the
4381 * bf pointer should be treated as invalid after this function is called.
4382 */
4383 void
ath_tx_process_buf_completion(struct ath_softc * sc,struct ath_txq * txq,struct ath_tx_status * ts,struct ath_buf * bf)4384 ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq,
4385 struct ath_tx_status *ts, struct ath_buf *bf)
4386 {
4387 struct ieee80211_node *ni = bf->bf_node;
4388
4389 ATH_TX_UNLOCK_ASSERT(sc);
4390 ATH_TXQ_UNLOCK_ASSERT(txq);
4391
4392 /* If unicast frame, update general statistics */
4393 if (ni != NULL) {
4394 /* update statistics */
4395 ath_tx_update_stats(sc, ts, bf);
4396 }
4397
4398 /*
4399 * Call the completion handler.
4400 * The completion handler is responsible for
4401 * calling the rate control code.
4402 *
4403 * Frames with no completion handler get the
4404 * rate control code called here.
4405 */
4406 if (bf->bf_comp == NULL) {
4407 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
4408 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) {
4409 /*
4410 * XXX assume this isn't an aggregate
4411 * frame.
4412 *
4413 * XXX TODO: also do this for filtered frames?
4414 * Once rate control knows about them?
4415 */
4416 ath_tx_update_ratectrl(sc, ni,
4417 bf->bf_state.bfs_rc, ts,
4418 bf->bf_state.bfs_pktlen,
4419 bf->bf_state.bfs_pktlen,
4420 1,
4421 (ts->ts_status == 0 ? 0 : 1));
4422 }
4423 ath_tx_default_comp(sc, bf, 0);
4424 } else
4425 bf->bf_comp(sc, bf, 0);
4426 }
4427
4428 /*
4429 * Process completed xmit descriptors from the specified queue.
4430 * Kick the packet scheduler if needed. This can occur from this
4431 * particular task.
4432 */
4433 static int
ath_tx_processq(struct ath_softc * sc,struct ath_txq * txq,int dosched)4434 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched)
4435 {
4436 struct ath_hal *ah = sc->sc_ah;
4437 struct ath_buf *bf;
4438 struct ath_desc *ds;
4439 struct ath_tx_status *ts;
4440 struct ieee80211_node *ni;
4441 #ifdef IEEE80211_SUPPORT_SUPERG
4442 struct ieee80211com *ic = &sc->sc_ic;
4443 #endif /* IEEE80211_SUPPORT_SUPERG */
4444 int nacked;
4445 HAL_STATUS status;
4446
4447 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4448 __func__, txq->axq_qnum,
4449 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4450 txq->axq_link);
4451
4452 ATH_KTR(sc, ATH_KTR_TXCOMP, 4,
4453 "ath_tx_processq: txq=%u head %p link %p depth %p",
4454 txq->axq_qnum,
4455 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4456 txq->axq_link,
4457 txq->axq_depth);
4458
4459 nacked = 0;
4460 for (;;) {
4461 ATH_TXQ_LOCK(txq);
4462 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4463 bf = TAILQ_FIRST(&txq->axq_q);
4464 if (bf == NULL) {
4465 ATH_TXQ_UNLOCK(txq);
4466 break;
4467 }
4468 ds = bf->bf_lastds; /* XXX must be setup correctly! */
4469 ts = &bf->bf_status.ds_txstat;
4470
4471 status = ath_hal_txprocdesc(ah, ds, ts);
4472 #ifdef ATH_DEBUG
4473 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4474 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4475 status == HAL_OK);
4476 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0))
4477 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4478 status == HAL_OK);
4479 #endif
4480 #ifdef ATH_DEBUG_ALQ
4481 if (if_ath_alq_checkdebug(&sc->sc_alq,
4482 ATH_ALQ_EDMA_TXSTATUS)) {
4483 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
4484 sc->sc_tx_statuslen,
4485 (char *) ds);
4486 }
4487 #endif
4488
4489 if (status == HAL_EINPROGRESS) {
4490 ATH_KTR(sc, ATH_KTR_TXCOMP, 3,
4491 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS",
4492 txq->axq_qnum, bf, ds);
4493 ATH_TXQ_UNLOCK(txq);
4494 break;
4495 }
4496 ATH_TXQ_REMOVE(txq, bf, bf_list);
4497
4498 /*
4499 * Sanity check.
4500 */
4501 if (txq->axq_qnum != bf->bf_state.bfs_tx_queue) {
4502 device_printf(sc->sc_dev,
4503 "%s: TXQ=%d: bf=%p, bfs_tx_queue=%d\n",
4504 __func__,
4505 txq->axq_qnum,
4506 bf,
4507 bf->bf_state.bfs_tx_queue);
4508 }
4509 if (txq->axq_qnum != bf->bf_last->bf_state.bfs_tx_queue) {
4510 device_printf(sc->sc_dev,
4511 "%s: TXQ=%d: bf_last=%p, bfs_tx_queue=%d\n",
4512 __func__,
4513 txq->axq_qnum,
4514 bf->bf_last,
4515 bf->bf_last->bf_state.bfs_tx_queue);
4516 }
4517
4518 #if 0
4519 if (txq->axq_depth > 0) {
4520 /*
4521 * More frames follow. Mark the buffer busy
4522 * so it's not re-used while the hardware may
4523 * still re-read the link field in the descriptor.
4524 *
4525 * Use the last buffer in an aggregate as that
4526 * is where the hardware may be - intermediate
4527 * descriptors won't be "busy".
4528 */
4529 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4530 } else
4531 txq->axq_link = NULL;
4532 #else
4533 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4534 #endif
4535 if (bf->bf_state.bfs_aggr)
4536 txq->axq_aggr_depth--;
4537
4538 ni = bf->bf_node;
4539
4540 ATH_KTR(sc, ATH_KTR_TXCOMP, 5,
4541 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x",
4542 txq->axq_qnum, bf, ds, ni, ts->ts_status);
4543 /*
4544 * If unicast frame was ack'd update RSSI,
4545 * including the last rx time used to
4546 * workaround phantom bmiss interrupts.
4547 */
4548 if (ni != NULL && ts->ts_status == 0 &&
4549 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
4550 nacked++;
4551 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
4552 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
4553 ts->ts_rssi);
4554 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgtxrssi,
4555 ts->ts_rssi);
4556 }
4557 ATH_TXQ_UNLOCK(txq);
4558
4559 /*
4560 * Update statistics and call completion
4561 */
4562 ath_tx_process_buf_completion(sc, txq, ts, bf);
4563
4564 /* XXX at this point, bf and ni may be totally invalid */
4565 }
4566 #ifdef IEEE80211_SUPPORT_SUPERG
4567 /*
4568 * Flush fast-frame staging queue when traffic slows.
4569 */
4570 if (txq->axq_depth <= 1)
4571 ieee80211_ff_flush(ic, txq->axq_ac);
4572 #endif
4573
4574 /* Kick the software TXQ scheduler */
4575 if (dosched) {
4576 ATH_TX_LOCK(sc);
4577 ath_txq_sched(sc, txq);
4578 ATH_TX_UNLOCK(sc);
4579 }
4580
4581 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4582 "ath_tx_processq: txq=%u: done",
4583 txq->axq_qnum);
4584
4585 return nacked;
4586 }
4587
4588 #define TXQACTIVE(t, q) ( (t) & (1 << (q)))
4589
4590 /*
4591 * Deferred processing of transmit interrupt; special-cased
4592 * for a single hardware transmit queue (e.g. 5210 and 5211).
4593 */
4594 static void
ath_tx_proc_q0(void * arg,int npending)4595 ath_tx_proc_q0(void *arg, int npending)
4596 {
4597 struct ath_softc *sc = arg;
4598 uint32_t txqs;
4599
4600 ATH_PCU_LOCK(sc);
4601 sc->sc_txproc_cnt++;
4602 txqs = sc->sc_txq_active;
4603 sc->sc_txq_active &= ~txqs;
4604 ATH_PCU_UNLOCK(sc);
4605
4606 ATH_LOCK(sc);
4607 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4608 ATH_UNLOCK(sc);
4609
4610 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4611 "ath_tx_proc_q0: txqs=0x%08x", txqs);
4612
4613 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1))
4614 /* XXX why is lastrx updated in tx code? */
4615 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4616 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4617 ath_tx_processq(sc, sc->sc_cabq, 1);
4618 sc->sc_wd_timer = 0;
4619
4620 if (sc->sc_softled)
4621 ath_led_event(sc, sc->sc_txrix);
4622
4623 ATH_PCU_LOCK(sc);
4624 sc->sc_txproc_cnt--;
4625 ATH_PCU_UNLOCK(sc);
4626
4627 ATH_LOCK(sc);
4628 ath_power_restore_power_state(sc);
4629 ATH_UNLOCK(sc);
4630
4631 ath_tx_kick(sc);
4632 }
4633
4634 /*
4635 * Deferred processing of transmit interrupt; special-cased
4636 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
4637 */
4638 static void
ath_tx_proc_q0123(void * arg,int npending)4639 ath_tx_proc_q0123(void *arg, int npending)
4640 {
4641 struct ath_softc *sc = arg;
4642 int nacked;
4643 uint32_t txqs;
4644
4645 ATH_PCU_LOCK(sc);
4646 sc->sc_txproc_cnt++;
4647 txqs = sc->sc_txq_active;
4648 sc->sc_txq_active &= ~txqs;
4649 ATH_PCU_UNLOCK(sc);
4650
4651 ATH_LOCK(sc);
4652 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4653 ATH_UNLOCK(sc);
4654
4655 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4656 "ath_tx_proc_q0123: txqs=0x%08x", txqs);
4657
4658 /*
4659 * Process each active queue.
4660 */
4661 nacked = 0;
4662 if (TXQACTIVE(txqs, 0))
4663 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1);
4664 if (TXQACTIVE(txqs, 1))
4665 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1);
4666 if (TXQACTIVE(txqs, 2))
4667 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1);
4668 if (TXQACTIVE(txqs, 3))
4669 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1);
4670 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4671 ath_tx_processq(sc, sc->sc_cabq, 1);
4672 if (nacked)
4673 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4674
4675 sc->sc_wd_timer = 0;
4676
4677 if (sc->sc_softled)
4678 ath_led_event(sc, sc->sc_txrix);
4679
4680 ATH_PCU_LOCK(sc);
4681 sc->sc_txproc_cnt--;
4682 ATH_PCU_UNLOCK(sc);
4683
4684 ATH_LOCK(sc);
4685 ath_power_restore_power_state(sc);
4686 ATH_UNLOCK(sc);
4687
4688 ath_tx_kick(sc);
4689 }
4690
4691 /*
4692 * Deferred processing of transmit interrupt.
4693 */
4694 static void
ath_tx_proc(void * arg,int npending)4695 ath_tx_proc(void *arg, int npending)
4696 {
4697 struct ath_softc *sc = arg;
4698 int i, nacked;
4699 uint32_t txqs;
4700
4701 ATH_PCU_LOCK(sc);
4702 sc->sc_txproc_cnt++;
4703 txqs = sc->sc_txq_active;
4704 sc->sc_txq_active &= ~txqs;
4705 ATH_PCU_UNLOCK(sc);
4706
4707 ATH_LOCK(sc);
4708 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4709 ATH_UNLOCK(sc);
4710
4711 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs);
4712
4713 /*
4714 * Process each active queue.
4715 */
4716 nacked = 0;
4717 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4718 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i))
4719 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1);
4720 if (nacked)
4721 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4722
4723 sc->sc_wd_timer = 0;
4724
4725 if (sc->sc_softled)
4726 ath_led_event(sc, sc->sc_txrix);
4727
4728 ATH_PCU_LOCK(sc);
4729 sc->sc_txproc_cnt--;
4730 ATH_PCU_UNLOCK(sc);
4731
4732 ATH_LOCK(sc);
4733 ath_power_restore_power_state(sc);
4734 ATH_UNLOCK(sc);
4735
4736 ath_tx_kick(sc);
4737 }
4738 #undef TXQACTIVE
4739
4740 /*
4741 * Deferred processing of TXQ rescheduling.
4742 */
4743 static void
ath_txq_sched_tasklet(void * arg,int npending)4744 ath_txq_sched_tasklet(void *arg, int npending)
4745 {
4746 struct ath_softc *sc = arg;
4747 int i;
4748
4749 /* XXX is skipping ok? */
4750 ATH_PCU_LOCK(sc);
4751 #if 0
4752 if (sc->sc_inreset_cnt > 0) {
4753 device_printf(sc->sc_dev,
4754 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
4755 ATH_PCU_UNLOCK(sc);
4756 return;
4757 }
4758 #endif
4759 sc->sc_txproc_cnt++;
4760 ATH_PCU_UNLOCK(sc);
4761
4762 ATH_LOCK(sc);
4763 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4764 ATH_UNLOCK(sc);
4765
4766 ATH_TX_LOCK(sc);
4767 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4768 if (ATH_TXQ_SETUP(sc, i)) {
4769 ath_txq_sched(sc, &sc->sc_txq[i]);
4770 }
4771 }
4772 ATH_TX_UNLOCK(sc);
4773
4774 ATH_LOCK(sc);
4775 ath_power_restore_power_state(sc);
4776 ATH_UNLOCK(sc);
4777
4778 ATH_PCU_LOCK(sc);
4779 sc->sc_txproc_cnt--;
4780 ATH_PCU_UNLOCK(sc);
4781 }
4782
4783 void
ath_returnbuf_tail(struct ath_softc * sc,struct ath_buf * bf)4784 ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf)
4785 {
4786
4787 ATH_TXBUF_LOCK_ASSERT(sc);
4788
4789 if (bf->bf_flags & ATH_BUF_MGMT)
4790 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list);
4791 else {
4792 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4793 sc->sc_txbuf_cnt++;
4794 if (sc->sc_txbuf_cnt > ath_txbuf) {
4795 device_printf(sc->sc_dev,
4796 "%s: sc_txbuf_cnt > %d?\n",
4797 __func__,
4798 ath_txbuf);
4799 sc->sc_txbuf_cnt = ath_txbuf;
4800 }
4801 }
4802 }
4803
4804 void
ath_returnbuf_head(struct ath_softc * sc,struct ath_buf * bf)4805 ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf)
4806 {
4807
4808 ATH_TXBUF_LOCK_ASSERT(sc);
4809
4810 if (bf->bf_flags & ATH_BUF_MGMT)
4811 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list);
4812 else {
4813 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
4814 sc->sc_txbuf_cnt++;
4815 if (sc->sc_txbuf_cnt > ATH_TXBUF) {
4816 device_printf(sc->sc_dev,
4817 "%s: sc_txbuf_cnt > %d?\n",
4818 __func__,
4819 ATH_TXBUF);
4820 sc->sc_txbuf_cnt = ATH_TXBUF;
4821 }
4822 }
4823 }
4824
4825 /*
4826 * Free the holding buffer if it exists
4827 */
4828 void
ath_txq_freeholdingbuf(struct ath_softc * sc,struct ath_txq * txq)4829 ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq)
4830 {
4831 ATH_TXBUF_UNLOCK_ASSERT(sc);
4832 ATH_TXQ_LOCK_ASSERT(txq);
4833
4834 if (txq->axq_holdingbf == NULL)
4835 return;
4836
4837 txq->axq_holdingbf->bf_flags &= ~ATH_BUF_BUSY;
4838
4839 ATH_TXBUF_LOCK(sc);
4840 ath_returnbuf_tail(sc, txq->axq_holdingbf);
4841 ATH_TXBUF_UNLOCK(sc);
4842
4843 txq->axq_holdingbf = NULL;
4844 }
4845
4846 /*
4847 * Add this buffer to the holding queue, freeing the previous
4848 * one if it exists.
4849 */
4850 static void
ath_txq_addholdingbuf(struct ath_softc * sc,struct ath_buf * bf)4851 ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf)
4852 {
4853 struct ath_txq *txq;
4854
4855 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4856
4857 ATH_TXBUF_UNLOCK_ASSERT(sc);
4858 ATH_TXQ_LOCK_ASSERT(txq);
4859
4860 /* XXX assert ATH_BUF_BUSY is set */
4861
4862 /* XXX assert the tx queue is under the max number */
4863 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) {
4864 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n",
4865 __func__,
4866 bf,
4867 bf->bf_state.bfs_tx_queue);
4868 bf->bf_flags &= ~ATH_BUF_BUSY;
4869 ath_returnbuf_tail(sc, bf);
4870 return;
4871 }
4872 ath_txq_freeholdingbuf(sc, txq);
4873 txq->axq_holdingbf = bf;
4874 }
4875
4876 /*
4877 * Return a buffer to the pool and update the 'busy' flag on the
4878 * previous 'tail' entry.
4879 *
4880 * This _must_ only be called when the buffer is involved in a completed
4881 * TX. The logic is that if it was part of an active TX, the previous
4882 * buffer on the list is now not involved in a halted TX DMA queue, waiting
4883 * for restart (eg for TDMA.)
4884 *
4885 * The caller must free the mbuf and recycle the node reference.
4886 *
4887 * XXX This method of handling busy / holding buffers is insanely stupid.
4888 * It requires bf_state.bfs_tx_queue to be correctly assigned. It would
4889 * be much nicer if buffers in the processq() methods would instead be
4890 * always completed there (pushed onto a txq or ath_bufhead) so we knew
4891 * exactly what hardware queue they came from in the first place.
4892 */
4893 void
ath_freebuf(struct ath_softc * sc,struct ath_buf * bf)4894 ath_freebuf(struct ath_softc *sc, struct ath_buf *bf)
4895 {
4896 struct ath_txq *txq;
4897
4898 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4899
4900 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__));
4901 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__));
4902
4903 /*
4904 * If this buffer is busy, push it onto the holding queue.
4905 */
4906 if (bf->bf_flags & ATH_BUF_BUSY) {
4907 ATH_TXQ_LOCK(txq);
4908 ath_txq_addholdingbuf(sc, bf);
4909 ATH_TXQ_UNLOCK(txq);
4910 return;
4911 }
4912
4913 /*
4914 * Not a busy buffer, so free normally
4915 */
4916 ATH_TXBUF_LOCK(sc);
4917 ath_returnbuf_tail(sc, bf);
4918 ATH_TXBUF_UNLOCK(sc);
4919 }
4920
4921 /*
4922 * This is currently used by ath_tx_draintxq() and
4923 * ath_tx_tid_free_pkts().
4924 *
4925 * It recycles a single ath_buf.
4926 */
4927 void
ath_tx_freebuf(struct ath_softc * sc,struct ath_buf * bf,int status)4928 ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status)
4929 {
4930 struct ieee80211_node *ni = bf->bf_node;
4931 struct mbuf *m0 = bf->bf_m;
4932
4933 /*
4934 * Make sure that we only sync/unload if there's an mbuf.
4935 * If not (eg we cloned a buffer), the unload will have already
4936 * occurred.
4937 */
4938 if (bf->bf_m != NULL) {
4939 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4940 BUS_DMASYNC_POSTWRITE);
4941 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4942 }
4943
4944 bf->bf_node = NULL;
4945 bf->bf_m = NULL;
4946
4947 /* Free the buffer, it's not needed any longer */
4948 ath_freebuf(sc, bf);
4949
4950 /* Pass the buffer back to net80211 - completing it */
4951 ieee80211_tx_complete(ni, m0, status);
4952 }
4953
4954 static struct ath_buf *
ath_tx_draintxq_get_one(struct ath_softc * sc,struct ath_txq * txq)4955 ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq)
4956 {
4957 struct ath_buf *bf;
4958
4959 ATH_TXQ_LOCK_ASSERT(txq);
4960
4961 /*
4962 * Drain the FIFO queue first, then if it's
4963 * empty, move to the normal frame queue.
4964 */
4965 bf = TAILQ_FIRST(&txq->fifo.axq_q);
4966 if (bf != NULL) {
4967 /*
4968 * Is it the last buffer in this set?
4969 * Decrement the FIFO counter.
4970 */
4971 if (bf->bf_flags & ATH_BUF_FIFOEND) {
4972 if (txq->axq_fifo_depth == 0) {
4973 device_printf(sc->sc_dev,
4974 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n",
4975 __func__,
4976 txq->axq_qnum,
4977 txq->fifo.axq_depth);
4978 } else
4979 txq->axq_fifo_depth--;
4980 }
4981 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);
4982 return (bf);
4983 }
4984
4985 /*
4986 * Debugging!
4987 */
4988 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) {
4989 device_printf(sc->sc_dev,
4990 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n",
4991 __func__,
4992 txq->axq_qnum,
4993 txq->axq_fifo_depth,
4994 txq->fifo.axq_depth);
4995 }
4996
4997 /*
4998 * Now drain the pending queue.
4999 */
5000 bf = TAILQ_FIRST(&txq->axq_q);
5001 if (bf == NULL) {
5002 txq->axq_link = NULL;
5003 return (NULL);
5004 }
5005 ATH_TXQ_REMOVE(txq, bf, bf_list);
5006 return (bf);
5007 }
5008
5009 void
ath_tx_draintxq(struct ath_softc * sc,struct ath_txq * txq)5010 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
5011 {
5012 #ifdef ATH_DEBUG
5013 struct ath_hal *ah = sc->sc_ah;
5014 #endif
5015 struct ath_buf *bf;
5016 u_int ix;
5017
5018 /*
5019 * NB: this assumes output has been stopped and
5020 * we do not need to block ath_tx_proc
5021 */
5022 for (ix = 0;; ix++) {
5023 ATH_TXQ_LOCK(txq);
5024 bf = ath_tx_draintxq_get_one(sc, txq);
5025 if (bf == NULL) {
5026 ATH_TXQ_UNLOCK(txq);
5027 break;
5028 }
5029 if (bf->bf_state.bfs_aggr)
5030 txq->axq_aggr_depth--;
5031 #ifdef ATH_DEBUG
5032 if (sc->sc_debug & ATH_DEBUG_RESET) {
5033 struct ieee80211com *ic = &sc->sc_ic;
5034 int status = 0;
5035
5036 /*
5037 * EDMA operation has a TX completion FIFO
5038 * separate from the TX descriptor, so this
5039 * method of checking the "completion" status
5040 * is wrong.
5041 */
5042 if (! sc->sc_isedma) {
5043 status = (ath_hal_txprocdesc(ah,
5044 bf->bf_lastds,
5045 &bf->bf_status.ds_txstat) == HAL_OK);
5046 }
5047 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status);
5048 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
5049 bf->bf_m->m_len, 0, -1);
5050 }
5051 #endif /* ATH_DEBUG */
5052 /*
5053 * Since we're now doing magic in the completion
5054 * functions, we -must- call it for aggregation
5055 * destinations or BAW tracking will get upset.
5056 */
5057 /*
5058 * Clear ATH_BUF_BUSY; the completion handler
5059 * will free the buffer.
5060 */
5061 ATH_TXQ_UNLOCK(txq);
5062 bf->bf_flags &= ~ATH_BUF_BUSY;
5063 if (bf->bf_comp)
5064 bf->bf_comp(sc, bf, 1);
5065 else
5066 ath_tx_default_comp(sc, bf, 1);
5067 }
5068
5069 /*
5070 * Free the holding buffer if it exists
5071 */
5072 ATH_TXQ_LOCK(txq);
5073 ath_txq_freeholdingbuf(sc, txq);
5074 ATH_TXQ_UNLOCK(txq);
5075
5076 /*
5077 * Drain software queued frames which are on
5078 * active TIDs.
5079 */
5080 ath_tx_txq_drain(sc, txq);
5081 }
5082
5083 static void
ath_tx_stopdma(struct ath_softc * sc,struct ath_txq * txq)5084 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
5085 {
5086 struct ath_hal *ah = sc->sc_ah;
5087
5088 ATH_TXQ_LOCK_ASSERT(txq);
5089
5090 DPRINTF(sc, ATH_DEBUG_RESET,
5091 "%s: tx queue [%u] %p, active=%d, hwpending=%d, flags 0x%08x, "
5092 "link %p, holdingbf=%p\n",
5093 __func__,
5094 txq->axq_qnum,
5095 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
5096 (int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)),
5097 (int) ath_hal_numtxpending(ah, txq->axq_qnum),
5098 txq->axq_flags,
5099 txq->axq_link,
5100 txq->axq_holdingbf);
5101
5102 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
5103 /* We've stopped TX DMA, so mark this as stopped. */
5104 txq->axq_flags &= ~ATH_TXQ_PUTRUNNING;
5105
5106 #ifdef ATH_DEBUG
5107 if ((sc->sc_debug & ATH_DEBUG_RESET)
5108 && (txq->axq_holdingbf != NULL)) {
5109 ath_printtxbuf(sc, txq->axq_holdingbf, txq->axq_qnum, 0, 0);
5110 }
5111 #endif
5112 }
5113
5114 int
ath_stoptxdma(struct ath_softc * sc)5115 ath_stoptxdma(struct ath_softc *sc)
5116 {
5117 struct ath_hal *ah = sc->sc_ah;
5118 int i;
5119
5120 /* XXX return value */
5121 if (sc->sc_invalid)
5122 return 0;
5123
5124 if (!sc->sc_invalid) {
5125 /* don't touch the hardware if marked invalid */
5126 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5127 __func__, sc->sc_bhalq,
5128 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
5129 NULL);
5130
5131 /* stop the beacon queue */
5132 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
5133
5134 /* Stop the data queues */
5135 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
5136 if (ATH_TXQ_SETUP(sc, i)) {
5137 ATH_TXQ_LOCK(&sc->sc_txq[i]);
5138 ath_tx_stopdma(sc, &sc->sc_txq[i]);
5139 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
5140 }
5141 }
5142 }
5143
5144 return 1;
5145 }
5146
5147 #ifdef ATH_DEBUG
5148 void
ath_tx_dump(struct ath_softc * sc,struct ath_txq * txq)5149 ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq)
5150 {
5151 struct ath_hal *ah = sc->sc_ah;
5152 struct ath_buf *bf;
5153 int i = 0;
5154
5155 if (! (sc->sc_debug & ATH_DEBUG_RESET))
5156 return;
5157
5158 device_printf(sc->sc_dev, "%s: Q%d: begin\n",
5159 __func__, txq->axq_qnum);
5160 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
5161 ath_printtxbuf(sc, bf, txq->axq_qnum, i,
5162 ath_hal_txprocdesc(ah, bf->bf_lastds,
5163 &bf->bf_status.ds_txstat) == HAL_OK);
5164 i++;
5165 }
5166 device_printf(sc->sc_dev, "%s: Q%d: end\n",
5167 __func__, txq->axq_qnum);
5168 }
5169 #endif /* ATH_DEBUG */
5170
5171 /*
5172 * Drain the transmit queues and reclaim resources.
5173 */
5174 void
ath_legacy_tx_drain(struct ath_softc * sc,ATH_RESET_TYPE reset_type)5175 ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
5176 {
5177 struct ath_hal *ah = sc->sc_ah;
5178 struct ath_buf *bf_last;
5179 int i;
5180
5181 (void) ath_stoptxdma(sc);
5182
5183 /*
5184 * Dump the queue contents
5185 */
5186 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
5187 /*
5188 * XXX TODO: should we just handle the completed TX frames
5189 * here, whether or not the reset is a full one or not?
5190 */
5191 if (ATH_TXQ_SETUP(sc, i)) {
5192 #ifdef ATH_DEBUG
5193 if (sc->sc_debug & ATH_DEBUG_RESET)
5194 ath_tx_dump(sc, &sc->sc_txq[i]);
5195 #endif /* ATH_DEBUG */
5196 if (reset_type == ATH_RESET_NOLOSS) {
5197 ath_tx_processq(sc, &sc->sc_txq[i], 0);
5198 ATH_TXQ_LOCK(&sc->sc_txq[i]);
5199 /*
5200 * Free the holding buffer; DMA is now
5201 * stopped.
5202 */
5203 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]);
5204 /*
5205 * Setup the link pointer to be the
5206 * _last_ buffer/descriptor in the list.
5207 * If there's nothing in the list, set it
5208 * to NULL.
5209 */
5210 bf_last = ATH_TXQ_LAST(&sc->sc_txq[i],
5211 axq_q_s);
5212 if (bf_last != NULL) {
5213 ath_hal_gettxdesclinkptr(ah,
5214 bf_last->bf_lastds,
5215 &sc->sc_txq[i].axq_link);
5216 } else {
5217 sc->sc_txq[i].axq_link = NULL;
5218 }
5219 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
5220 } else
5221 ath_tx_draintxq(sc, &sc->sc_txq[i]);
5222 }
5223 }
5224 #ifdef ATH_DEBUG
5225 if (sc->sc_debug & ATH_DEBUG_RESET) {
5226 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf);
5227 if (bf != NULL && bf->bf_m != NULL) {
5228 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
5229 ath_hal_txprocdesc(ah, bf->bf_lastds,
5230 &bf->bf_status.ds_txstat) == HAL_OK);
5231 ieee80211_dump_pkt(&sc->sc_ic,
5232 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
5233 0, -1);
5234 }
5235 }
5236 #endif /* ATH_DEBUG */
5237 sc->sc_wd_timer = 0;
5238 }
5239
5240 /*
5241 * Update internal state after a channel change.
5242 */
5243 static void
ath_chan_change(struct ath_softc * sc,struct ieee80211_channel * chan)5244 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
5245 {
5246 enum ieee80211_phymode mode;
5247
5248 /*
5249 * Change channels and update the h/w rate map
5250 * if we're switching; e.g. 11a to 11b/g.
5251 */
5252 mode = ieee80211_chan2mode(chan);
5253 if (mode != sc->sc_curmode)
5254 ath_setcurmode(sc, mode);
5255 sc->sc_curchan = chan;
5256 }
5257
5258 /*
5259 * Set/change channels. If the channel is really being changed,
5260 * it's done by resetting the chip. To accomplish this we must
5261 * first cleanup any pending DMA, then restart stuff after a la
5262 * ath_init.
5263 */
5264 static int
ath_chan_set(struct ath_softc * sc,struct ieee80211_channel * chan)5265 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
5266 {
5267 struct ieee80211com *ic = &sc->sc_ic;
5268 struct ath_hal *ah = sc->sc_ah;
5269 int ret = 0;
5270
5271 /* Treat this as an interface reset */
5272 ATH_PCU_UNLOCK_ASSERT(sc);
5273 ATH_UNLOCK_ASSERT(sc);
5274
5275 /* (Try to) stop TX/RX from occurring */
5276 taskqueue_block(sc->sc_tq);
5277
5278 ATH_PCU_LOCK(sc);
5279
5280 /* Disable interrupts */
5281 ath_hal_intrset(ah, 0);
5282
5283 /* Stop new RX/TX/interrupt completion */
5284 if (ath_reset_grablock(sc, 1) == 0) {
5285 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
5286 __func__);
5287 }
5288
5289 /* Stop pending RX/TX completion */
5290 ath_txrx_stop_locked(sc);
5291
5292 ATH_PCU_UNLOCK(sc);
5293
5294 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
5295 __func__, ieee80211_chan2ieee(ic, chan),
5296 chan->ic_freq, chan->ic_flags);
5297 if (chan != sc->sc_curchan) {
5298 HAL_STATUS status;
5299 /*
5300 * To switch channels clear any pending DMA operations;
5301 * wait long enough for the RX fifo to drain, reset the
5302 * hardware at the new frequency, and then re-enable
5303 * the relevant bits of the h/w.
5304 */
5305 #if 0
5306 ath_hal_intrset(ah, 0); /* disable interrupts */
5307 #endif
5308 ath_stoprecv(sc, 1); /* turn off frame recv */
5309 /*
5310 * First, handle completed TX/RX frames.
5311 */
5312 ath_rx_flush(sc);
5313 ath_draintxq(sc, ATH_RESET_NOLOSS);
5314 /*
5315 * Next, flush the non-scheduled frames.
5316 */
5317 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
5318
5319 ath_update_chainmasks(sc, chan);
5320 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
5321 sc->sc_cur_rxchainmask);
5322 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE,
5323 HAL_RESET_NORMAL, &status)) {
5324 device_printf(sc->sc_dev, "%s: unable to reset "
5325 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
5326 __func__, ieee80211_chan2ieee(ic, chan),
5327 chan->ic_freq, chan->ic_flags, status);
5328 ret = EIO;
5329 goto finish;
5330 }
5331 sc->sc_diversity = ath_hal_getdiversity(ah);
5332
5333 ATH_RX_LOCK(sc);
5334 sc->sc_rx_stopped = 1;
5335 sc->sc_rx_resetted = 1;
5336 ATH_RX_UNLOCK(sc);
5337
5338 /* Quiet time handling - ensure we resync */
5339 ath_vap_clear_quiet_ie(sc);
5340
5341 /* Let DFS at it in case it's a DFS channel */
5342 ath_dfs_radar_enable(sc, chan);
5343
5344 /* Let spectral at in case spectral is enabled */
5345 ath_spectral_enable(sc, chan);
5346
5347 /*
5348 * Let bluetooth coexistence at in case it's needed for this
5349 * channel
5350 */
5351 ath_btcoex_enable(sc, ic->ic_curchan);
5352
5353 /*
5354 * If we're doing TDMA, enforce the TXOP limitation for chips
5355 * that support it.
5356 */
5357 if (sc->sc_hasenforcetxop && sc->sc_tdma)
5358 ath_hal_setenforcetxop(sc->sc_ah, 1);
5359 else
5360 ath_hal_setenforcetxop(sc->sc_ah, 0);
5361
5362 /*
5363 * Re-enable rx framework.
5364 */
5365 if (ath_startrecv(sc) != 0) {
5366 device_printf(sc->sc_dev,
5367 "%s: unable to restart recv logic\n", __func__);
5368 ret = EIO;
5369 goto finish;
5370 }
5371
5372 /*
5373 * Change channels and update the h/w rate map
5374 * if we're switching; e.g. 11a to 11b/g.
5375 */
5376 ath_chan_change(sc, chan);
5377
5378 /*
5379 * Reset clears the beacon timers; reset them
5380 * here if needed.
5381 */
5382 if (sc->sc_beacons) { /* restart beacons */
5383 #ifdef IEEE80211_SUPPORT_TDMA
5384 if (sc->sc_tdma)
5385 ath_tdma_config(sc, NULL);
5386 else
5387 #endif
5388 ath_beacon_config(sc, NULL);
5389 }
5390
5391 /*
5392 * Re-enable interrupts.
5393 */
5394 #if 0
5395 ath_hal_intrset(ah, sc->sc_imask);
5396 #endif
5397 }
5398
5399 finish:
5400 ATH_PCU_LOCK(sc);
5401 sc->sc_inreset_cnt--;
5402 /* XXX only do this if sc_inreset_cnt == 0? */
5403 ath_hal_intrset(ah, sc->sc_imask);
5404 ATH_PCU_UNLOCK(sc);
5405
5406 ath_txrx_start(sc);
5407 /* XXX ath_start? */
5408
5409 return ret;
5410 }
5411
5412 /*
5413 * Periodically recalibrate the PHY to account
5414 * for temperature/environment changes.
5415 */
5416 static void
ath_calibrate(void * arg)5417 ath_calibrate(void *arg)
5418 {
5419 struct ath_softc *sc = arg;
5420 struct ath_hal *ah = sc->sc_ah;
5421 struct ieee80211com *ic = &sc->sc_ic;
5422 HAL_BOOL longCal, isCalDone = AH_TRUE;
5423 HAL_BOOL aniCal, shortCal = AH_FALSE;
5424 int nextcal;
5425
5426 ATH_LOCK_ASSERT(sc);
5427
5428 /*
5429 * Force the hardware awake for ANI work.
5430 */
5431 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5432
5433 /* Skip trying to do this if we're in reset */
5434 if (sc->sc_inreset_cnt)
5435 goto restart;
5436
5437 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
5438 goto restart;
5439 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
5440 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000);
5441 if (sc->sc_doresetcal)
5442 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000);
5443
5444 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal);
5445 if (aniCal) {
5446 sc->sc_stats.ast_ani_cal++;
5447 sc->sc_lastani = ticks;
5448 ath_hal_ani_poll(ah, sc->sc_curchan);
5449 }
5450
5451 if (longCal) {
5452 sc->sc_stats.ast_per_cal++;
5453 sc->sc_lastlongcal = ticks;
5454 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
5455 /*
5456 * Rfgain is out of bounds, reset the chip
5457 * to load new gain values.
5458 */
5459 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5460 "%s: rfgain change\n", __func__);
5461 sc->sc_stats.ast_per_rfgain++;
5462 sc->sc_resetcal = 0;
5463 sc->sc_doresetcal = AH_TRUE;
5464 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5465 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5466 ath_power_restore_power_state(sc);
5467 return;
5468 }
5469 /*
5470 * If this long cal is after an idle period, then
5471 * reset the data collection state so we start fresh.
5472 */
5473 if (sc->sc_resetcal) {
5474 (void) ath_hal_calreset(ah, sc->sc_curchan);
5475 sc->sc_lastcalreset = ticks;
5476 sc->sc_lastshortcal = ticks;
5477 sc->sc_resetcal = 0;
5478 sc->sc_doresetcal = AH_TRUE;
5479 }
5480 }
5481
5482 /* Only call if we're doing a short/long cal, not for ANI calibration */
5483 if (shortCal || longCal) {
5484 isCalDone = AH_FALSE;
5485 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5486 if (longCal) {
5487 /*
5488 * Calibrate noise floor data again in case of change.
5489 */
5490 ath_hal_process_noisefloor(ah);
5491 }
5492 } else {
5493 DPRINTF(sc, ATH_DEBUG_ANY,
5494 "%s: calibration of channel %u failed\n",
5495 __func__, sc->sc_curchan->ic_freq);
5496 sc->sc_stats.ast_per_calfail++;
5497 }
5498 /*
5499 * XXX TODO: get the NF calibration results from the HAL.
5500 * If we failed NF cal then schedule a hard reset to potentially
5501 * un-freeze the PHY.
5502 *
5503 * Note we have to be careful here to not get stuck in an
5504 * infinite NIC restart. Ideally we'd not restart if we
5505 * failed the first NF cal - that /can/ fail sometimes in
5506 * a noisy environment.
5507 *
5508 * Instead, we should likely temporarily shorten the longCal
5509 * period to happen pretty quickly and if a subsequent one
5510 * fails, do a full reset.
5511 */
5512 if (shortCal)
5513 sc->sc_lastshortcal = ticks;
5514 }
5515 if (!isCalDone) {
5516 restart:
5517 /*
5518 * Use a shorter interval to potentially collect multiple
5519 * data samples required to complete calibration. Once
5520 * we're told the work is done we drop back to a longer
5521 * interval between requests. We're more aggressive doing
5522 * work when operating as an AP to improve operation right
5523 * after startup.
5524 */
5525 sc->sc_lastshortcal = ticks;
5526 nextcal = ath_shortcalinterval*hz/1000;
5527 if (sc->sc_opmode != HAL_M_HOSTAP)
5528 nextcal *= 10;
5529 sc->sc_doresetcal = AH_TRUE;
5530 } else {
5531 /* nextcal should be the shortest time for next event */
5532 nextcal = ath_longcalinterval*hz;
5533 if (sc->sc_lastcalreset == 0)
5534 sc->sc_lastcalreset = sc->sc_lastlongcal;
5535 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5536 sc->sc_resetcal = 1; /* setup reset next trip */
5537 sc->sc_doresetcal = AH_FALSE;
5538 }
5539 /* ANI calibration may occur more often than short/long/resetcal */
5540 if (ath_anicalinterval > 0)
5541 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000);
5542
5543 if (nextcal != 0) {
5544 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5545 __func__, nextcal, isCalDone ? "" : "!");
5546 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5547 } else {
5548 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5549 __func__);
5550 /* NB: don't rearm timer */
5551 }
5552 /*
5553 * Restore power state now that we're done.
5554 */
5555 ath_power_restore_power_state(sc);
5556 }
5557
5558 static void
ath_scan_start(struct ieee80211com * ic)5559 ath_scan_start(struct ieee80211com *ic)
5560 {
5561 struct ath_softc *sc = ic->ic_softc;
5562 struct ath_hal *ah = sc->sc_ah;
5563 u_int32_t rfilt;
5564
5565 /* XXX calibration timer? */
5566 /* XXXGL: is constant ieee80211broadcastaddr a correct choice? */
5567
5568 ATH_LOCK(sc);
5569 sc->sc_scanning = 1;
5570 sc->sc_syncbeacon = 0;
5571 rfilt = ath_calcrxfilter(sc);
5572 ATH_UNLOCK(sc);
5573
5574 ATH_PCU_LOCK(sc);
5575 ath_hal_setrxfilter(ah, rfilt);
5576 ath_hal_setassocid(ah, ieee80211broadcastaddr, 0);
5577 ATH_PCU_UNLOCK(sc);
5578
5579 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5580 __func__, rfilt, ether_sprintf(ieee80211broadcastaddr));
5581 }
5582
5583 static void
ath_scan_end(struct ieee80211com * ic)5584 ath_scan_end(struct ieee80211com *ic)
5585 {
5586 struct ath_softc *sc = ic->ic_softc;
5587 struct ath_hal *ah = sc->sc_ah;
5588 u_int32_t rfilt;
5589
5590 ATH_LOCK(sc);
5591 sc->sc_scanning = 0;
5592 rfilt = ath_calcrxfilter(sc);
5593 ATH_UNLOCK(sc);
5594
5595 ATH_PCU_LOCK(sc);
5596 ath_hal_setrxfilter(ah, rfilt);
5597 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5598
5599 ath_hal_process_noisefloor(ah);
5600 ATH_PCU_UNLOCK(sc);
5601
5602 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5603 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5604 sc->sc_curaid);
5605 }
5606
5607 #ifdef ATH_ENABLE_11N
5608 /*
5609 * For now, just do a channel change.
5610 *
5611 * Later, we'll go through the hard slog of suspending tx/rx, changing rate
5612 * control state and resetting the hardware without dropping frames out
5613 * of the queue.
5614 *
5615 * The unfortunate trouble here is making absolutely sure that the
5616 * channel width change has propagated enough so the hardware
5617 * absolutely isn't handed bogus frames for it's current operating
5618 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and
5619 * does occur in parallel, we need to make certain we've blocked
5620 * any further ongoing TX (and RX, that can cause raw TX)
5621 * before we do this.
5622 */
5623 static void
ath_update_chw(struct ieee80211com * ic)5624 ath_update_chw(struct ieee80211com *ic)
5625 {
5626 struct ath_softc *sc = ic->ic_softc;
5627
5628 //DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__);
5629 device_printf(sc->sc_dev, "%s: called\n", __func__);
5630
5631 /*
5632 * XXX TODO: schedule a tasklet that stops things without freeing,
5633 * walks the now stopped TX queue(s) looking for frames to retry
5634 * as if we TX filtered them (whch may mean dropping non-ampdu frames!)
5635 * but okay) then place them back on the software queue so they
5636 * can have the rate control lookup done again.
5637 */
5638 ath_set_channel(ic);
5639 }
5640 #endif /* ATH_ENABLE_11N */
5641
5642 /*
5643 * This is called by the beacon parsing routine in the receive
5644 * path to update the current quiet time information provided by
5645 * an AP.
5646 *
5647 * This is STA specific, it doesn't take the AP TBTT/beacon slot
5648 * offset into account.
5649 *
5650 * The quiet IE doesn't control the /now/ beacon interval - it
5651 * controls the upcoming beacon interval. So, when tbtt=1,
5652 * the quiet element programming shall be for the next beacon
5653 * interval. There's no tbtt=0 behaviour defined, so don't.
5654 *
5655 * Since we're programming the next quiet interval, we have
5656 * to keep in mind what we will see when the next beacon
5657 * is received with potentially a quiet IE. For example, if
5658 * quiet_period is 1, then we are always getting a quiet interval
5659 * each TBTT - so if we just program it in upon each beacon received,
5660 * it will constantly reflect the "next" TBTT and we will never
5661 * let the counter stay programmed correctly.
5662 *
5663 * So:
5664 * + the first time we see the quiet IE, program it and store
5665 * the details somewhere;
5666 * + if the quiet parameters don't change (ie, period/duration/offset)
5667 * then just leave the programming enabled;
5668 * + (we can "skip" beacons, so don't try to enforce tbttcount unless
5669 * you're willing to also do the skipped beacon math);
5670 * + if the quiet IE is removed, then halt quiet time.
5671 */
5672 static int
ath_set_quiet_ie(struct ieee80211_node * ni,uint8_t * ie)5673 ath_set_quiet_ie(struct ieee80211_node *ni, uint8_t *ie)
5674 {
5675 struct ieee80211_quiet_ie *q;
5676 struct ieee80211vap *vap = ni->ni_vap;
5677 struct ath_vap *avp = ATH_VAP(vap);
5678 struct ieee80211com *ic = vap->iv_ic;
5679 struct ath_softc *sc = ic->ic_softc;
5680
5681 if (vap->iv_opmode != IEEE80211_M_STA)
5682 return (0);
5683
5684 /* Verify we have a quiet time IE */
5685 if (ie == NULL) {
5686 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5687 "%s: called; NULL IE, disabling\n", __func__);
5688
5689 ath_hal_set_quiet(sc->sc_ah, 0, 0, 0, HAL_QUIET_DISABLE);
5690 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));
5691 return (0);
5692 }
5693
5694 /* If we do, verify it's actually legit */
5695 if (ie[0] != IEEE80211_ELEMID_QUIET)
5696 return 0;
5697 if (ie[1] != 6)
5698 return 0;
5699
5700 /* Note: this belongs in net80211, parsed out and everything */
5701 q = (void *) ie;
5702
5703 /*
5704 * Compare what we have stored to what we last saw.
5705 * If they're the same then don't program in anything.
5706 */
5707 if ((q->period == avp->quiet_ie.period) &&
5708 (le16dec(&q->duration) == le16dec(&avp->quiet_ie.duration)) &&
5709 (le16dec(&q->offset) == le16dec(&avp->quiet_ie.offset)))
5710 return (0);
5711
5712 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5713 "%s: called; tbttcount=%d, period=%d, duration=%d, offset=%d\n",
5714 __func__,
5715 (int) q->tbttcount,
5716 (int) q->period,
5717 (int) le16dec(&q->duration),
5718 (int) le16dec(&q->offset));
5719
5720 /*
5721 * Don't program in garbage values.
5722 */
5723 if ((le16dec(&q->duration) == 0) ||
5724 (le16dec(&q->duration) >= ni->ni_intval)) {
5725 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5726 "%s: invalid duration (%d)\n", __func__,
5727 le16dec(&q->duration));
5728 return (0);
5729 }
5730 /*
5731 * Can have a 0 offset, but not a duration - so just check
5732 * they don't exceed the intval.
5733 */
5734 if (le16dec(&q->duration) + le16dec(&q->offset) >= ni->ni_intval) {
5735 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5736 "%s: invalid duration + offset (%d+%d)\n", __func__,
5737 le16dec(&q->duration),
5738 le16dec(&q->offset));
5739 return (0);
5740 }
5741 if (q->tbttcount == 0) {
5742 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5743 "%s: invalid tbttcount (0)\n", __func__);
5744 return (0);
5745 }
5746 if (q->period == 0) {
5747 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5748 "%s: invalid period (0)\n", __func__);
5749 return (0);
5750 }
5751
5752 /*
5753 * This is a new quiet time IE config, so wait until tbttcount
5754 * is equal to 1, and program it in.
5755 */
5756 if (q->tbttcount == 1) {
5757 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5758 "%s: programming\n", __func__);
5759 ath_hal_set_quiet(sc->sc_ah,
5760 q->period * ni->ni_intval, /* convert to TU */
5761 le16dec(&q->duration), /* already in TU */
5762 le16dec(&q->offset) + ni->ni_intval,
5763 HAL_QUIET_ENABLE | HAL_QUIET_ADD_CURRENT_TSF);
5764 /*
5765 * Note: no HAL_QUIET_ADD_SWBA_RESP_TIME; as this is for
5766 * STA mode
5767 */
5768
5769 /* Update local state */
5770 memcpy(&avp->quiet_ie, ie, sizeof(struct ieee80211_quiet_ie));
5771 }
5772
5773 return (0);
5774 }
5775
5776 static void
ath_set_channel(struct ieee80211com * ic)5777 ath_set_channel(struct ieee80211com *ic)
5778 {
5779 struct ath_softc *sc = ic->ic_softc;
5780
5781 ATH_LOCK(sc);
5782 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5783 ATH_UNLOCK(sc);
5784
5785 (void) ath_chan_set(sc, ic->ic_curchan);
5786 /*
5787 * If we are returning to our bss channel then mark state
5788 * so the next recv'd beacon's tsf will be used to sync the
5789 * beacon timers. Note that since we only hear beacons in
5790 * sta/ibss mode this has no effect in other operating modes.
5791 */
5792 ATH_LOCK(sc);
5793 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5794 sc->sc_syncbeacon = 1;
5795 ath_power_restore_power_state(sc);
5796 ATH_UNLOCK(sc);
5797 }
5798
5799 /*
5800 * Walk the vap list and check if there any vap's in RUN state.
5801 */
5802 static int
ath_isanyrunningvaps(struct ieee80211vap * this)5803 ath_isanyrunningvaps(struct ieee80211vap *this)
5804 {
5805 struct ieee80211com *ic = this->iv_ic;
5806 struct ieee80211vap *vap;
5807
5808 IEEE80211_LOCK_ASSERT(ic);
5809
5810 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5811 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
5812 return 1;
5813 }
5814 return 0;
5815 }
5816
5817 static int
ath_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)5818 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5819 {
5820 struct ieee80211com *ic = vap->iv_ic;
5821 struct ath_softc *sc = ic->ic_softc;
5822 struct ath_vap *avp = ATH_VAP(vap);
5823 struct ath_hal *ah = sc->sc_ah;
5824 struct ieee80211_node *ni = NULL;
5825 int i, error, stamode;
5826 u_int32_t rfilt;
5827 int csa_run_transition = 0;
5828 enum ieee80211_state ostate = vap->iv_state;
5829
5830 static const HAL_LED_STATE leds[] = {
5831 HAL_LED_INIT, /* IEEE80211_S_INIT */
5832 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5833 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5834 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5835 HAL_LED_RUN, /* IEEE80211_S_CAC */
5836 HAL_LED_RUN, /* IEEE80211_S_RUN */
5837 HAL_LED_RUN, /* IEEE80211_S_CSA */
5838 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5839 };
5840
5841 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5842 ieee80211_state_name[ostate],
5843 ieee80211_state_name[nstate]);
5844
5845 /*
5846 * net80211 _should_ have the comlock asserted at this point.
5847 * There are some comments around the calls to vap->iv_newstate
5848 * which indicate that it (newstate) may end up dropping the
5849 * lock. This and the subsequent lock assert check after newstate
5850 * are an attempt to catch these and figure out how/why.
5851 */
5852 IEEE80211_LOCK_ASSERT(ic);
5853
5854 /* Before we touch the hardware - wake it up */
5855 ATH_LOCK(sc);
5856 /*
5857 * If the NIC is in anything other than SLEEP state,
5858 * we need to ensure that self-generated frames are
5859 * set for PWRMGT=0. Otherwise we may end up with
5860 * strange situations.
5861 *
5862 * XXX TODO: is this actually the case? :-)
5863 */
5864 if (nstate != IEEE80211_S_SLEEP)
5865 ath_power_setselfgen(sc, HAL_PM_AWAKE);
5866
5867 /*
5868 * Now, wake the thing up.
5869 */
5870 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5871
5872 /*
5873 * And stop the calibration callout whilst we have
5874 * ATH_LOCK held.
5875 */
5876 callout_stop(&sc->sc_cal_ch);
5877 ATH_UNLOCK(sc);
5878
5879 if (ostate == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN)
5880 csa_run_transition = 1;
5881
5882 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
5883
5884 if (nstate == IEEE80211_S_SCAN) {
5885 /*
5886 * Scanning: turn off beacon miss and don't beacon.
5887 * Mark beacon state so when we reach RUN state we'll
5888 * [re]setup beacons. Unblock the task q thread so
5889 * deferred interrupt processing is done.
5890 */
5891
5892 /* Ensure we stay awake during scan */
5893 ATH_LOCK(sc);
5894 ath_power_setselfgen(sc, HAL_PM_AWAKE);
5895 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
5896 ATH_UNLOCK(sc);
5897
5898 ath_hal_intrset(ah,
5899 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5900 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5901 sc->sc_beacons = 0;
5902 taskqueue_unblock(sc->sc_tq);
5903 }
5904
5905 ni = ieee80211_ref_node(vap->iv_bss);
5906 rfilt = ath_calcrxfilter(sc);
5907 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
5908 vap->iv_opmode == IEEE80211_M_AHDEMO ||
5909 vap->iv_opmode == IEEE80211_M_IBSS);
5910
5911 /*
5912 * XXX Dont need to do this (and others) if we've transitioned
5913 * from SLEEP->RUN.
5914 */
5915 if (stamode && nstate == IEEE80211_S_RUN) {
5916 sc->sc_curaid = ni->ni_associd;
5917 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5918 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5919 }
5920 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5921 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5922 ath_hal_setrxfilter(ah, rfilt);
5923
5924 /* XXX is this to restore keycache on resume? */
5925 if (vap->iv_opmode != IEEE80211_M_STA &&
5926 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
5927 for (i = 0; i < IEEE80211_WEP_NKID; i++)
5928 if (ath_hal_keyisvalid(ah, i))
5929 ath_hal_keysetmac(ah, i, ni->ni_bssid);
5930 }
5931
5932 /*
5933 * Invoke the parent method to do net80211 work.
5934 */
5935 error = avp->av_newstate(vap, nstate, arg);
5936 if (error != 0)
5937 goto bad;
5938
5939 /*
5940 * See above: ensure av_newstate() doesn't drop the lock
5941 * on us.
5942 */
5943 IEEE80211_LOCK_ASSERT(ic);
5944
5945 /*
5946 * XXX TODO: if nstate is _S_CAC, then we should disable
5947 * ACK processing until CAC is completed.
5948 */
5949
5950 /*
5951 * XXX TODO: if we're on a passive channel, then we should
5952 * not allow any ACKs or self-generated frames until we hear
5953 * a beacon. Unfortunately there isn't a notification from
5954 * net80211 so perhaps we could slot that particular check
5955 * into the mgmt receive path and just ensure that we clear
5956 * it on RX of beacons in passive mode (and only clear it
5957 * once, obviously.)
5958 */
5959
5960 /*
5961 * XXX TODO: net80211 should be tracking whether channels
5962 * have heard beacons and are thus considered "OK" for
5963 * transmitting - and then inform the driver about this
5964 * state change. That way if we hear an AP go quiet
5965 * (and nothing else is beaconing on a channel) the
5966 * channel can go back to being passive until another
5967 * beacon is heard.
5968 */
5969
5970 /*
5971 * XXX TODO: if nstate is _S_CAC, then we should disable
5972 * ACK processing until CAC is completed.
5973 */
5974
5975 /*
5976 * XXX TODO: if we're on a passive channel, then we should
5977 * not allow any ACKs or self-generated frames until we hear
5978 * a beacon. Unfortunately there isn't a notification from
5979 * net80211 so perhaps we could slot that particular check
5980 * into the mgmt receive path and just ensure that we clear
5981 * it on RX of beacons in passive mode (and only clear it
5982 * once, obviously.)
5983 */
5984
5985 /*
5986 * XXX TODO: net80211 should be tracking whether channels
5987 * have heard beacons and are thus considered "OK" for
5988 * transmitting - and then inform the driver about this
5989 * state change. That way if we hear an AP go quiet
5990 * (and nothing else is beaconing on a channel) the
5991 * channel can go back to being passive until another
5992 * beacon is heard.
5993 */
5994
5995 if (nstate == IEEE80211_S_RUN) {
5996 /* NB: collect bss node again, it may have changed */
5997 ieee80211_free_node(ni);
5998 ni = ieee80211_ref_node(vap->iv_bss);
5999
6000 DPRINTF(sc, ATH_DEBUG_STATE,
6001 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
6002 "capinfo 0x%04x chan %d\n", __func__,
6003 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
6004 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
6005
6006 switch (vap->iv_opmode) {
6007 #ifdef IEEE80211_SUPPORT_TDMA
6008 case IEEE80211_M_AHDEMO:
6009 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
6010 break;
6011 /* fall thru... */
6012 #endif
6013 case IEEE80211_M_HOSTAP:
6014 case IEEE80211_M_IBSS:
6015 case IEEE80211_M_MBSS:
6016
6017 /*
6018 * TODO: Enable ACK processing (ie, clear AR_DIAG_ACK_DIS.)
6019 * For channels that are in CAC, we may have disabled
6020 * this during CAC to ensure we don't ACK frames
6021 * sent to us.
6022 */
6023
6024 /*
6025 * Allocate and setup the beacon frame.
6026 *
6027 * Stop any previous beacon DMA. This may be
6028 * necessary, for example, when an ibss merge
6029 * causes reconfiguration; there will be a state
6030 * transition from RUN->RUN that means we may
6031 * be called with beacon transmission active.
6032 */
6033 ath_hal_stoptxdma(ah, sc->sc_bhalq);
6034
6035 error = ath_beacon_alloc(sc, ni);
6036 if (error != 0)
6037 goto bad;
6038 /*
6039 * If joining an adhoc network defer beacon timer
6040 * configuration to the next beacon frame so we
6041 * have a current TSF to use. Otherwise we're
6042 * starting an ibss/bss so there's no need to delay;
6043 * if this is the first vap moving to RUN state, then
6044 * beacon state needs to be [re]configured.
6045 */
6046 if (vap->iv_opmode == IEEE80211_M_IBSS &&
6047 ni->ni_tstamp.tsf != 0) {
6048 sc->sc_syncbeacon = 1;
6049 } else if (!sc->sc_beacons) {
6050 #ifdef IEEE80211_SUPPORT_TDMA
6051 if (vap->iv_caps & IEEE80211_C_TDMA)
6052 ath_tdma_config(sc, vap);
6053 else
6054 #endif
6055 ath_beacon_config(sc, vap);
6056 sc->sc_beacons = 1;
6057 }
6058 break;
6059 case IEEE80211_M_STA:
6060 /*
6061 * Defer beacon timer configuration to the next
6062 * beacon frame so we have a current TSF to use
6063 * (any TSF collected when scanning is likely old).
6064 * However if it's due to a CSA -> RUN transition,
6065 * force a beacon update so we pick up a lack of
6066 * beacons from an AP in CAC and thus force a
6067 * scan.
6068 *
6069 * And, there's also corner cases here where
6070 * after a scan, the AP may have disappeared.
6071 * In that case, we may not receive an actual
6072 * beacon to update the beacon timer and thus we
6073 * won't get notified of the missing beacons.
6074 *
6075 * Also, don't do any of this if we're not running
6076 * with hardware beacon support, as that'll interfere
6077 * with an AP VAP.
6078 */
6079 if (ostate != IEEE80211_S_RUN &&
6080 ostate != IEEE80211_S_SLEEP) {
6081
6082 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
6083 DPRINTF(sc, ATH_DEBUG_BEACON,
6084 "%s: STA; syncbeacon=1\n", __func__);
6085 sc->sc_syncbeacon = 1;
6086 if (csa_run_transition)
6087 ath_beacon_config(sc, vap);
6088 }
6089
6090 /* Quiet time handling - ensure we resync */
6091 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));
6092
6093 /*
6094 * PR: kern/175227
6095 *
6096 * Reconfigure beacons during reset; as otherwise
6097 * we won't get the beacon timers reprogrammed
6098 * after a reset and thus we won't pick up a
6099 * beacon miss interrupt.
6100 *
6101 * Hopefully we'll see a beacon before the BMISS
6102 * timer fires (too often), leading to a STA
6103 * disassociation.
6104 */
6105 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
6106 sc->sc_beacons = 1;
6107 }
6108 }
6109 break;
6110 case IEEE80211_M_MONITOR:
6111 /*
6112 * Monitor mode vaps have only INIT->RUN and RUN->RUN
6113 * transitions so we must re-enable interrupts here to
6114 * handle the case of a single monitor mode vap.
6115 */
6116 ath_hal_intrset(ah, sc->sc_imask);
6117 break;
6118 case IEEE80211_M_WDS:
6119 break;
6120 default:
6121 break;
6122 }
6123 /*
6124 * Let the hal process statistics collected during a
6125 * scan so it can provide calibrated noise floor data.
6126 */
6127 ath_hal_process_noisefloor(ah);
6128 /*
6129 * Reset rssi stats; maybe not the best place...
6130 */
6131 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
6132 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
6133 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
6134
6135 /*
6136 * Force awake for RUN mode.
6137 */
6138 ATH_LOCK(sc);
6139 ath_power_setselfgen(sc, HAL_PM_AWAKE);
6140 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
6141
6142 /*
6143 * Finally, start any timers and the task q thread
6144 * (in case we didn't go through SCAN state).
6145 */
6146 if (ath_longcalinterval != 0) {
6147 /* start periodic recalibration timer */
6148 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
6149 } else {
6150 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
6151 "%s: calibration disabled\n", __func__);
6152 }
6153 ATH_UNLOCK(sc);
6154
6155 taskqueue_unblock(sc->sc_tq);
6156 } else if (nstate == IEEE80211_S_INIT) {
6157 /* Quiet time handling - ensure we resync */
6158 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));
6159
6160 /*
6161 * If there are no vaps left in RUN state then
6162 * shutdown host/driver operation:
6163 * o disable interrupts
6164 * o disable the task queue thread
6165 * o mark beacon processing as stopped
6166 */
6167 if (!ath_isanyrunningvaps(vap)) {
6168 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
6169 /* disable interrupts */
6170 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
6171 taskqueue_block(sc->sc_tq);
6172 sc->sc_beacons = 0;
6173 }
6174
6175 /*
6176 * For at least STA mode we likely should clear the ANI
6177 * and NF calibration state and allow the NIC/HAL to figure
6178 * out optimal parameters at runtime. Otherwise if we
6179 * disassociate due to interference / deafness it may persist
6180 * when we reconnect.
6181 *
6182 * Note: may need to do this for other states too, not just
6183 * _S_INIT.
6184 */
6185 #ifdef IEEE80211_SUPPORT_TDMA
6186 ath_hal_setcca(ah, AH_TRUE);
6187 #endif
6188 } else if (nstate == IEEE80211_S_SLEEP) {
6189 /* We're going to sleep, so transition appropriately */
6190 /* For now, only do this if we're a single STA vap */
6191 if (sc->sc_nvaps == 1 &&
6192 vap->iv_opmode == IEEE80211_M_STA) {
6193 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: syncbeacon=%d\n", __func__, sc->sc_syncbeacon);
6194 ATH_LOCK(sc);
6195 /*
6196 * Always at least set the self-generated
6197 * frame config to set PWRMGT=1.
6198 */
6199 ath_power_setselfgen(sc, HAL_PM_NETWORK_SLEEP);
6200
6201 /*
6202 * If we're not syncing beacons, transition
6203 * to NETWORK_SLEEP.
6204 *
6205 * We stay awake if syncbeacon > 0 in case
6206 * we need to listen for some beacons otherwise
6207 * our beacon timer config may be wrong.
6208 */
6209 if (sc->sc_syncbeacon == 0) {
6210 ath_power_setpower(sc, HAL_PM_NETWORK_SLEEP, 1);
6211 }
6212 ATH_UNLOCK(sc);
6213 }
6214
6215 /*
6216 * Note - the ANI/calibration timer isn't re-enabled during
6217 * network sleep for now. One unfortunate side-effect is that
6218 * the PHY/airtime statistics aren't gathered on the channel
6219 * but I haven't yet tested to see if reading those registers
6220 * CAN occur during network sleep.
6221 *
6222 * This should be revisited in a future commit, even if it's
6223 * just to split out the airtime polling from ANI/calibration.
6224 */
6225 } else if (nstate == IEEE80211_S_SCAN) {
6226 /* Quiet time handling - ensure we resync */
6227 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));
6228
6229 /*
6230 * If we're in scan mode then startpcureceive() is
6231 * hopefully being called with "reset ANI" for this channel;
6232 * but once we attempt to reassociate we program in the previous
6233 * ANI values and.. not do any calibration until we're running.
6234 * This may mean we stay deaf unless we can associate successfully.
6235 *
6236 * So do kick off the cal timer to get NF/ANI going.
6237 */
6238 ATH_LOCK(sc);
6239 if (ath_longcalinterval != 0) {
6240 /* start periodic recalibration timer */
6241 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
6242 } else {
6243 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
6244 "%s: calibration disabled\n", __func__);
6245 }
6246 ATH_UNLOCK(sc);
6247 }
6248 bad:
6249 ieee80211_free_node(ni);
6250
6251 /*
6252 * Restore the power state - either to what it was, or
6253 * to network_sleep if it's alright.
6254 */
6255 ATH_LOCK(sc);
6256 ath_power_restore_power_state(sc);
6257 ATH_UNLOCK(sc);
6258 return error;
6259 }
6260
6261 /*
6262 * Allocate a key cache slot to the station so we can
6263 * setup a mapping from key index to node. The key cache
6264 * slot is needed for managing antenna state and for
6265 * compression when stations do not use crypto. We do
6266 * it uniliaterally here; if crypto is employed this slot
6267 * will be reassigned.
6268 */
6269 static void
ath_setup_stationkey(struct ieee80211_node * ni)6270 ath_setup_stationkey(struct ieee80211_node *ni)
6271 {
6272 struct ieee80211vap *vap = ni->ni_vap;
6273 struct ath_softc *sc = vap->iv_ic->ic_softc;
6274 ieee80211_keyix keyix, rxkeyix;
6275
6276 /* XXX should take a locked ref to vap->iv_bss */
6277 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
6278 /*
6279 * Key cache is full; we'll fall back to doing
6280 * the more expensive lookup in software. Note
6281 * this also means no h/w compression.
6282 */
6283 /* XXX msg+statistic */
6284 } else {
6285 /* XXX locking? */
6286 ni->ni_ucastkey.wk_keyix = keyix;
6287 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
6288 /* NB: must mark device key to get called back on delete */
6289 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
6290 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
6291 /* NB: this will create a pass-thru key entry */
6292 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss);
6293 }
6294 }
6295
6296 /*
6297 * Setup driver-specific state for a newly associated node.
6298 * Note that we're called also on a re-associate, the isnew
6299 * param tells us if this is the first time or not.
6300 */
6301 static void
ath_newassoc(struct ieee80211_node * ni,int isnew)6302 ath_newassoc(struct ieee80211_node *ni, int isnew)
6303 {
6304 struct ath_node *an = ATH_NODE(ni);
6305 struct ieee80211vap *vap = ni->ni_vap;
6306 struct ath_softc *sc = vap->iv_ic->ic_softc;
6307 const struct ieee80211_txparam *tp = ni->ni_txparms;
6308
6309 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
6310 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
6311
6312 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: reassoc; isnew=%d, is_powersave=%d\n",
6313 __func__,
6314 ni->ni_macaddr,
6315 ":",
6316 isnew,
6317 an->an_is_powersave);
6318
6319 ATH_NODE_LOCK(an);
6320 ath_rate_newassoc(sc, an, isnew);
6321 ATH_NODE_UNLOCK(an);
6322
6323 if (isnew &&
6324 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
6325 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
6326 ath_setup_stationkey(ni);
6327
6328 /*
6329 * If we're reassociating, make sure that any paused queues
6330 * get unpaused.
6331 *
6332 * Now, we may have frames in the hardware queue for this node.
6333 * So if we are reassociating and there are frames in the queue,
6334 * we need to go through the cleanup path to ensure that they're
6335 * marked as non-aggregate.
6336 */
6337 if (! isnew) {
6338 DPRINTF(sc, ATH_DEBUG_NODE,
6339 "%s: %6D: reassoc; is_powersave=%d\n",
6340 __func__,
6341 ni->ni_macaddr,
6342 ":",
6343 an->an_is_powersave);
6344
6345 /* XXX for now, we can't hold the lock across assoc */
6346 ath_tx_node_reassoc(sc, an);
6347
6348 /* XXX for now, we can't hold the lock across wakeup */
6349 if (an->an_is_powersave)
6350 ath_tx_node_wakeup(sc, an);
6351 }
6352 }
6353
6354 static int
ath_setregdomain(struct ieee80211com * ic,struct ieee80211_regdomain * reg,int nchans,struct ieee80211_channel chans[])6355 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
6356 int nchans, struct ieee80211_channel chans[])
6357 {
6358 struct ath_softc *sc = ic->ic_softc;
6359 struct ath_hal *ah = sc->sc_ah;
6360 HAL_STATUS status;
6361
6362 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6363 "%s: rd %u cc %u location %c%s\n",
6364 __func__, reg->regdomain, reg->country, reg->location,
6365 reg->ecm ? " ecm" : "");
6366
6367 status = ath_hal_set_channels(ah, chans, nchans,
6368 reg->country, reg->regdomain);
6369 if (status != HAL_OK) {
6370 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
6371 __func__, status);
6372 return EINVAL; /* XXX */
6373 }
6374
6375 return 0;
6376 }
6377
6378 static void
ath_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])6379 ath_getradiocaps(struct ieee80211com *ic,
6380 int maxchans, int *nchans, struct ieee80211_channel chans[])
6381 {
6382 struct ath_softc *sc = ic->ic_softc;
6383 struct ath_hal *ah = sc->sc_ah;
6384
6385 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
6386 __func__, SKU_DEBUG, CTRY_DEFAULT);
6387
6388 /* XXX check return */
6389 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
6390 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
6391
6392 }
6393
6394 static int
ath_getchannels(struct ath_softc * sc)6395 ath_getchannels(struct ath_softc *sc)
6396 {
6397 struct ieee80211com *ic = &sc->sc_ic;
6398 struct ath_hal *ah = sc->sc_ah;
6399 HAL_STATUS status;
6400
6401 /*
6402 * Collect channel set based on EEPROM contents.
6403 */
6404 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
6405 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
6406 if (status != HAL_OK) {
6407 device_printf(sc->sc_dev,
6408 "%s: unable to collect channel list from hal, status %d\n",
6409 __func__, status);
6410 return EINVAL;
6411 }
6412 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
6413 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
6414 /* XXX map Atheros sku's to net80211 SKU's */
6415 /* XXX net80211 types too small */
6416 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
6417 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
6418 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
6419 ic->ic_regdomain.isocc[1] = ' ';
6420
6421 ic->ic_regdomain.ecm = 1;
6422 ic->ic_regdomain.location = 'I';
6423
6424 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6425 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
6426 __func__, sc->sc_eerd, sc->sc_eecc,
6427 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
6428 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
6429 return 0;
6430 }
6431
6432 static int
ath_rate_setup(struct ath_softc * sc,u_int mode)6433 ath_rate_setup(struct ath_softc *sc, u_int mode)
6434 {
6435 struct ath_hal *ah = sc->sc_ah;
6436 const HAL_RATE_TABLE *rt;
6437
6438 switch (mode) {
6439 case IEEE80211_MODE_11A:
6440 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
6441 break;
6442 case IEEE80211_MODE_HALF:
6443 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
6444 break;
6445 case IEEE80211_MODE_QUARTER:
6446 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
6447 break;
6448 case IEEE80211_MODE_11B:
6449 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
6450 break;
6451 case IEEE80211_MODE_11G:
6452 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
6453 break;
6454 case IEEE80211_MODE_TURBO_A:
6455 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
6456 break;
6457 case IEEE80211_MODE_TURBO_G:
6458 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
6459 break;
6460 case IEEE80211_MODE_STURBO_A:
6461 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
6462 break;
6463 case IEEE80211_MODE_11NA:
6464 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
6465 break;
6466 case IEEE80211_MODE_11NG:
6467 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
6468 break;
6469 default:
6470 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
6471 __func__, mode);
6472 return 0;
6473 }
6474 sc->sc_rates[mode] = rt;
6475 return (rt != NULL);
6476 }
6477
6478 static void
ath_setcurmode(struct ath_softc * sc,enum ieee80211_phymode mode)6479 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
6480 {
6481 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
6482 static const struct {
6483 u_int rate; /* tx/rx 802.11 rate */
6484 u_int16_t timeOn; /* LED on time (ms) */
6485 u_int16_t timeOff; /* LED off time (ms) */
6486 } blinkrates[] = {
6487 { 108, 40, 10 },
6488 { 96, 44, 11 },
6489 { 72, 50, 13 },
6490 { 48, 57, 14 },
6491 { 36, 67, 16 },
6492 { 24, 80, 20 },
6493 { 22, 100, 25 },
6494 { 18, 133, 34 },
6495 { 12, 160, 40 },
6496 { 10, 200, 50 },
6497 { 6, 240, 58 },
6498 { 4, 267, 66 },
6499 { 2, 400, 100 },
6500 { 0, 500, 130 },
6501 /* XXX half/quarter rates */
6502 };
6503 const HAL_RATE_TABLE *rt;
6504 int i, j;
6505
6506 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
6507 rt = sc->sc_rates[mode];
6508 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
6509 for (i = 0; i < rt->rateCount; i++) {
6510 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6511 if (rt->info[i].phy != IEEE80211_T_HT)
6512 sc->sc_rixmap[ieeerate] = i;
6513 else
6514 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
6515 }
6516 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
6517 for (i = 0; i < nitems(sc->sc_hwmap); i++) {
6518 if (i >= rt->rateCount) {
6519 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
6520 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
6521 continue;
6522 }
6523 sc->sc_hwmap[i].ieeerate =
6524 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6525 if (rt->info[i].phy == IEEE80211_T_HT)
6526 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
6527 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
6528 if (rt->info[i].shortPreamble ||
6529 rt->info[i].phy == IEEE80211_T_OFDM)
6530 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6531 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
6532 for (j = 0; j < nitems(blinkrates)-1; j++)
6533 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
6534 break;
6535 /* NB: this uses the last entry if the rate isn't found */
6536 /* XXX beware of overlow */
6537 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
6538 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
6539 }
6540 sc->sc_currates = rt;
6541 sc->sc_curmode = mode;
6542 /*
6543 * All protection frames are transmitted at 2Mb/s for
6544 * 11g, otherwise at 1Mb/s.
6545 */
6546 if (mode == IEEE80211_MODE_11G)
6547 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
6548 else
6549 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
6550 /* NB: caller is responsible for resetting rate control state */
6551 }
6552
6553 static void
ath_watchdog(void * arg)6554 ath_watchdog(void *arg)
6555 {
6556 struct ath_softc *sc = arg;
6557 struct ieee80211com *ic = &sc->sc_ic;
6558 int do_reset = 0;
6559
6560 ATH_LOCK_ASSERT(sc);
6561
6562 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
6563 uint32_t hangs;
6564
6565 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6566
6567 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
6568 hangs != 0) {
6569 device_printf(sc->sc_dev, "%s hang detected (0x%x)\n",
6570 hangs & 0xff ? "bb" : "mac", hangs);
6571 } else
6572 device_printf(sc->sc_dev, "device timeout\n");
6573 do_reset = 1;
6574 counter_u64_add(ic->ic_oerrors, 1);
6575 sc->sc_stats.ast_watchdog++;
6576
6577 ath_power_restore_power_state(sc);
6578 }
6579
6580 /*
6581 * We can't hold the lock across the ath_reset() call.
6582 *
6583 * And since this routine can't hold a lock and sleep,
6584 * do the reset deferred.
6585 */
6586 if (do_reset) {
6587 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
6588 }
6589
6590 callout_schedule(&sc->sc_wd_ch, hz);
6591 }
6592
6593 static void
ath_parent(struct ieee80211com * ic)6594 ath_parent(struct ieee80211com *ic)
6595 {
6596 struct ath_softc *sc = ic->ic_softc;
6597 int error = EDOOFUS;
6598
6599 ATH_LOCK(sc);
6600 if (ic->ic_nrunning > 0) {
6601 /*
6602 * To avoid rescanning another access point,
6603 * do not call ath_init() here. Instead,
6604 * only reflect promisc mode settings.
6605 */
6606 if (sc->sc_running) {
6607 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6608 ath_mode_init(sc);
6609 ath_power_restore_power_state(sc);
6610 } else if (!sc->sc_invalid) {
6611 /*
6612 * Beware of being called during attach/detach
6613 * to reset promiscuous mode. In that case we
6614 * will still be marked UP but not RUNNING.
6615 * However trying to re-init the interface
6616 * is the wrong thing to do as we've already
6617 * torn down much of our state. There's
6618 * probably a better way to deal with this.
6619 */
6620 error = ath_init(sc);
6621 }
6622 } else {
6623 ath_stop(sc);
6624 if (!sc->sc_invalid)
6625 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1);
6626 }
6627 ATH_UNLOCK(sc);
6628
6629 if (error == 0) {
6630 #ifdef ATH_TX99_DIAG
6631 if (sc->sc_tx99 != NULL)
6632 sc->sc_tx99->start(sc->sc_tx99);
6633 else
6634 #endif
6635 ieee80211_start_all(ic);
6636 }
6637 }
6638
6639 /*
6640 * Announce various information on device/driver attach.
6641 */
6642 static void
ath_announce(struct ath_softc * sc)6643 ath_announce(struct ath_softc *sc)
6644 {
6645 struct ath_hal *ah = sc->sc_ah;
6646
6647 device_printf(sc->sc_dev, "%s mac %d.%d RF%s phy %d.%d\n",
6648 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
6649 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
6650 device_printf(sc->sc_dev, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
6651 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);
6652 if (bootverbose) {
6653 int i;
6654 for (i = 0; i <= WME_AC_VO; i++) {
6655 struct ath_txq *txq = sc->sc_ac2q[i];
6656 device_printf(sc->sc_dev,
6657 "Use hw queue %u for %s traffic\n",
6658 txq->axq_qnum, ieee80211_wme_acnames[i]);
6659 }
6660 device_printf(sc->sc_dev, "Use hw queue %u for CAB traffic\n",
6661 sc->sc_cabq->axq_qnum);
6662 device_printf(sc->sc_dev, "Use hw queue %u for beacons\n",
6663 sc->sc_bhalq);
6664 }
6665 if (ath_rxbuf != ATH_RXBUF)
6666 device_printf(sc->sc_dev, "using %u rx buffers\n", ath_rxbuf);
6667 if (ath_txbuf != ATH_TXBUF)
6668 device_printf(sc->sc_dev, "using %u tx buffers\n", ath_txbuf);
6669 if (sc->sc_mcastkey && bootverbose)
6670 device_printf(sc->sc_dev, "using multicast key search\n");
6671 }
6672
6673 static void
ath_dfs_tasklet(void * p,int npending)6674 ath_dfs_tasklet(void *p, int npending)
6675 {
6676 struct ath_softc *sc = (struct ath_softc *) p;
6677 struct ieee80211com *ic = &sc->sc_ic;
6678
6679 /*
6680 * If previous processing has found a radar event,
6681 * signal this to the net80211 layer to begin DFS
6682 * processing.
6683 */
6684 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) {
6685 /* DFS event found, initiate channel change */
6686
6687 /*
6688 * XXX TODO: immediately disable ACK processing
6689 * on the current channel. This would be done
6690 * by setting AR_DIAG_ACK_DIS (AR5212; may be
6691 * different for others) until we are out of
6692 * CAC.
6693 */
6694
6695 /*
6696 * XXX doesn't currently tell us whether the event
6697 * XXX was found in the primary or extension
6698 * XXX channel!
6699 */
6700 IEEE80211_LOCK(ic);
6701 ieee80211_dfs_notify_radar(ic, sc->sc_curchan);
6702 IEEE80211_UNLOCK(ic);
6703 }
6704 }
6705
6706 /*
6707 * Enable/disable power save. This must be called with
6708 * no TX driver locks currently held, so it should only
6709 * be called from the RX path (which doesn't hold any
6710 * TX driver locks.)
6711 */
6712 static void
ath_node_powersave(struct ieee80211_node * ni,int enable)6713 ath_node_powersave(struct ieee80211_node *ni, int enable)
6714 {
6715 #ifdef ATH_SW_PSQ
6716 struct ath_node *an = ATH_NODE(ni);
6717 struct ieee80211com *ic = ni->ni_ic;
6718 struct ath_softc *sc = ic->ic_softc;
6719 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6720
6721 /* XXX and no TXQ locks should be held here */
6722
6723 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: %6D: enable=%d\n",
6724 __func__,
6725 ni->ni_macaddr,
6726 ":",
6727 !! enable);
6728
6729 /* Suspend or resume software queue handling */
6730 if (enable)
6731 ath_tx_node_sleep(sc, an);
6732 else
6733 ath_tx_node_wakeup(sc, an);
6734
6735 /* Update net80211 state */
6736 avp->av_node_ps(ni, enable);
6737 #else
6738 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6739
6740 /* Update net80211 state */
6741 avp->av_node_ps(ni, enable);
6742 #endif/* ATH_SW_PSQ */
6743 }
6744
6745 /*
6746 * Notification from net80211 that the powersave queue state has
6747 * changed.
6748 *
6749 * Since the software queue also may have some frames:
6750 *
6751 * + if the node software queue has frames and the TID state
6752 * is 0, we set the TIM;
6753 * + if the node and the stack are both empty, we clear the TIM bit.
6754 * + If the stack tries to set the bit, always set it.
6755 * + If the stack tries to clear the bit, only clear it if the
6756 * software queue in question is also cleared.
6757 *
6758 * TODO: this is called during node teardown; so let's ensure this
6759 * is all correctly handled and that the TIM bit is cleared.
6760 * It may be that the node flush is called _AFTER_ the net80211
6761 * stack clears the TIM.
6762 *
6763 * Here is the racy part. Since it's possible >1 concurrent,
6764 * overlapping TXes will appear complete with a TX completion in
6765 * another thread, it's possible that the concurrent TIM calls will
6766 * clash. We can't hold the node lock here because setting the
6767 * TIM grabs the net80211 comlock and this may cause a LOR.
6768 * The solution is either to totally serialise _everything_ at
6769 * this point (ie, all TX, completion and any reset/flush go into
6770 * one taskqueue) or a new "ath TIM lock" needs to be created that
6771 * just wraps the driver state change and this call to avp->av_set_tim().
6772 *
6773 * The same race exists in the net80211 power save queue handling
6774 * as well. Since multiple transmitting threads may queue frames
6775 * into the driver, as well as ps-poll and the driver transmitting
6776 * frames (and thus clearing the psq), it's quite possible that
6777 * a packet entering the PSQ and a ps-poll being handled will
6778 * race, causing the TIM to be cleared and not re-set.
6779 */
6780 static int
ath_node_set_tim(struct ieee80211_node * ni,int enable)6781 ath_node_set_tim(struct ieee80211_node *ni, int enable)
6782 {
6783 #ifdef ATH_SW_PSQ
6784 struct ieee80211com *ic = ni->ni_ic;
6785 struct ath_softc *sc = ic->ic_softc;
6786 struct ath_node *an = ATH_NODE(ni);
6787 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6788 int changed = 0;
6789
6790 ATH_TX_LOCK(sc);
6791 an->an_stack_psq = enable;
6792
6793 /*
6794 * This will get called for all operating modes,
6795 * even if avp->av_set_tim is unset.
6796 * It's currently set for hostap/ibss modes; but
6797 * the same infrastructure is used for both STA
6798 * and AP/IBSS node power save.
6799 */
6800 if (avp->av_set_tim == NULL) {
6801 ATH_TX_UNLOCK(sc);
6802 return (0);
6803 }
6804
6805 /*
6806 * If setting the bit, always set it here.
6807 * If clearing the bit, only clear it if the
6808 * software queue is also empty.
6809 *
6810 * If the node has left power save, just clear the TIM
6811 * bit regardless of the state of the power save queue.
6812 *
6813 * XXX TODO: although atomics are used, it's quite possible
6814 * that a race will occur between this and setting/clearing
6815 * in another thread. TX completion will occur always in
6816 * one thread, however setting/clearing the TIM bit can come
6817 * from a variety of different process contexts!
6818 */
6819 if (enable && an->an_tim_set == 1) {
6820 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6821 "%s: %6D: enable=%d, tim_set=1, ignoring\n",
6822 __func__,
6823 ni->ni_macaddr,
6824 ":",
6825 enable);
6826 ATH_TX_UNLOCK(sc);
6827 } else if (enable) {
6828 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6829 "%s: %6D: enable=%d, enabling TIM\n",
6830 __func__,
6831 ni->ni_macaddr,
6832 ":",
6833 enable);
6834 an->an_tim_set = 1;
6835 ATH_TX_UNLOCK(sc);
6836 changed = avp->av_set_tim(ni, enable);
6837 } else if (an->an_swq_depth == 0) {
6838 /* disable */
6839 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6840 "%s: %6D: enable=%d, an_swq_depth == 0, disabling\n",
6841 __func__,
6842 ni->ni_macaddr,
6843 ":",
6844 enable);
6845 an->an_tim_set = 0;
6846 ATH_TX_UNLOCK(sc);
6847 changed = avp->av_set_tim(ni, enable);
6848 } else if (! an->an_is_powersave) {
6849 /*
6850 * disable regardless; the node isn't in powersave now
6851 */
6852 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6853 "%s: %6D: enable=%d, an_pwrsave=0, disabling\n",
6854 __func__,
6855 ni->ni_macaddr,
6856 ":",
6857 enable);
6858 an->an_tim_set = 0;
6859 ATH_TX_UNLOCK(sc);
6860 changed = avp->av_set_tim(ni, enable);
6861 } else {
6862 /*
6863 * psq disable, node is currently in powersave, node
6864 * software queue isn't empty, so don't clear the TIM bit
6865 * for now.
6866 */
6867 ATH_TX_UNLOCK(sc);
6868 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6869 "%s: %6D: enable=%d, an_swq_depth > 0, ignoring\n",
6870 __func__,
6871 ni->ni_macaddr,
6872 ":",
6873 enable);
6874 changed = 0;
6875 }
6876
6877 return (changed);
6878 #else
6879 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6880
6881 /*
6882 * Some operating modes don't set av_set_tim(), so don't
6883 * update it here.
6884 */
6885 if (avp->av_set_tim == NULL)
6886 return (0);
6887
6888 return (avp->av_set_tim(ni, enable));
6889 #endif /* ATH_SW_PSQ */
6890 }
6891
6892 /*
6893 * Set or update the TIM from the software queue.
6894 *
6895 * Check the software queue depth before attempting to do lock
6896 * anything; that avoids trying to obtain the lock. Then,
6897 * re-check afterwards to ensure nothing has changed in the
6898 * meantime.
6899 *
6900 * set: This is designed to be called from the TX path, after
6901 * a frame has been queued; to see if the swq > 0.
6902 *
6903 * clear: This is designed to be called from the buffer completion point
6904 * (right now it's ath_tx_default_comp()) where the state of
6905 * a software queue has changed.
6906 *
6907 * It makes sense to place it at buffer free / completion rather
6908 * than after each software queue operation, as there's no real
6909 * point in churning the TIM bit as the last frames in the software
6910 * queue are transmitted. If they fail and we retry them, we'd
6911 * just be setting the TIM bit again anyway.
6912 */
6913 void
ath_tx_update_tim(struct ath_softc * sc,struct ieee80211_node * ni,int enable)6914 ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni,
6915 int enable)
6916 {
6917 #ifdef ATH_SW_PSQ
6918 struct ath_node *an;
6919 struct ath_vap *avp;
6920
6921 /* Don't do this for broadcast/etc frames */
6922 if (ni == NULL)
6923 return;
6924
6925 an = ATH_NODE(ni);
6926 avp = ATH_VAP(ni->ni_vap);
6927
6928 /*
6929 * And for operating modes without the TIM handler set, let's
6930 * just skip those.
6931 */
6932 if (avp->av_set_tim == NULL)
6933 return;
6934
6935 ATH_TX_LOCK_ASSERT(sc);
6936
6937 if (enable) {
6938 if (an->an_is_powersave &&
6939 an->an_tim_set == 0 &&
6940 an->an_swq_depth != 0) {
6941 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6942 "%s: %6D: swq_depth>0, tim_set=0, set!\n",
6943 __func__,
6944 ni->ni_macaddr,
6945 ":");
6946 an->an_tim_set = 1;
6947 (void) avp->av_set_tim(ni, 1);
6948 }
6949 } else {
6950 /*
6951 * Don't bother grabbing the lock unless the queue is empty.
6952 */
6953 if (an->an_swq_depth != 0)
6954 return;
6955
6956 if (an->an_is_powersave &&
6957 an->an_stack_psq == 0 &&
6958 an->an_tim_set == 1 &&
6959 an->an_swq_depth == 0) {
6960 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6961 "%s: %6D: swq_depth=0, tim_set=1, psq_set=0,"
6962 " clear!\n",
6963 __func__,
6964 ni->ni_macaddr,
6965 ":");
6966 an->an_tim_set = 0;
6967 (void) avp->av_set_tim(ni, 0);
6968 }
6969 }
6970 #else
6971 return;
6972 #endif /* ATH_SW_PSQ */
6973 }
6974
6975 /*
6976 * Received a ps-poll frame from net80211.
6977 *
6978 * Here we get a chance to serve out a software-queued frame ourselves
6979 * before we punt it to net80211 to transmit us one itself - either
6980 * because there's traffic in the net80211 psq, or a NULL frame to
6981 * indicate there's nothing else.
6982 */
6983 static void
ath_node_recv_pspoll(struct ieee80211_node * ni,struct mbuf * m)6984 ath_node_recv_pspoll(struct ieee80211_node *ni, struct mbuf *m)
6985 {
6986 #ifdef ATH_SW_PSQ
6987 struct ath_node *an;
6988 struct ath_vap *avp;
6989 struct ieee80211com *ic = ni->ni_ic;
6990 struct ath_softc *sc = ic->ic_softc;
6991 int tid;
6992
6993 /* Just paranoia */
6994 if (ni == NULL)
6995 return;
6996
6997 /*
6998 * Unassociated (temporary node) station.
6999 */
7000 if (ni->ni_associd == 0)
7001 return;
7002
7003 /*
7004 * We do have an active node, so let's begin looking into it.
7005 */
7006 an = ATH_NODE(ni);
7007 avp = ATH_VAP(ni->ni_vap);
7008
7009 /*
7010 * For now, we just call the original ps-poll method.
7011 * Once we're ready to flip this on:
7012 *
7013 * + Set leak to 1, as no matter what we're going to have
7014 * to send a frame;
7015 * + Check the software queue and if there's something in it,
7016 * schedule the highest TID thas has traffic from this node.
7017 * Then make sure we schedule the software scheduler to
7018 * run so it picks up said frame.
7019 *
7020 * That way whatever happens, we'll at least send _a_ frame
7021 * to the given node.
7022 *
7023 * Again, yes, it's crappy QoS if the node has multiple
7024 * TIDs worth of traffic - but let's get it working first
7025 * before we optimise it.
7026 *
7027 * Also yes, there's definitely latency here - we're not
7028 * direct dispatching to the hardware in this path (and
7029 * we're likely being called from the packet receive path,
7030 * so going back into TX may be a little hairy!) but again
7031 * I'd like to get this working first before optimising
7032 * turn-around time.
7033 */
7034
7035 ATH_TX_LOCK(sc);
7036
7037 /*
7038 * Legacy - we're called and the node isn't asleep.
7039 * Immediately punt.
7040 */
7041 if (! an->an_is_powersave) {
7042 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7043 "%s: %6D: not in powersave?\n",
7044 __func__,
7045 ni->ni_macaddr,
7046 ":");
7047 ATH_TX_UNLOCK(sc);
7048 avp->av_recv_pspoll(ni, m);
7049 return;
7050 }
7051
7052 /*
7053 * We're in powersave.
7054 *
7055 * Leak a frame.
7056 */
7057 an->an_leak_count = 1;
7058
7059 /*
7060 * Now, if there's no frames in the node, just punt to
7061 * recv_pspoll.
7062 *
7063 * Don't bother checking if the TIM bit is set, we really
7064 * only care if there are any frames here!
7065 */
7066 if (an->an_swq_depth == 0) {
7067 ATH_TX_UNLOCK(sc);
7068 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7069 "%s: %6D: SWQ empty; punting to net80211\n",
7070 __func__,
7071 ni->ni_macaddr,
7072 ":");
7073 avp->av_recv_pspoll(ni, m);
7074 return;
7075 }
7076
7077 /*
7078 * Ok, let's schedule the highest TID that has traffic
7079 * and then schedule something.
7080 */
7081 for (tid = IEEE80211_TID_SIZE - 1; tid >= 0; tid--) {
7082 struct ath_tid *atid = &an->an_tid[tid];
7083 /*
7084 * No frames? Skip.
7085 */
7086 if (atid->axq_depth == 0)
7087 continue;
7088 ath_tx_tid_sched(sc, atid);
7089 /*
7090 * XXX we could do a direct call to the TXQ
7091 * scheduler code here to optimise latency
7092 * at the expense of a REALLY deep callstack.
7093 */
7094 ATH_TX_UNLOCK(sc);
7095 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
7096 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7097 "%s: %6D: leaking frame to TID %d\n",
7098 __func__,
7099 ni->ni_macaddr,
7100 ":",
7101 tid);
7102 return;
7103 }
7104
7105 ATH_TX_UNLOCK(sc);
7106
7107 /*
7108 * XXX nothing in the TIDs at this point? Eek.
7109 */
7110 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7111 "%s: %6D: TIDs empty, but ath_node showed traffic?!\n",
7112 __func__,
7113 ni->ni_macaddr,
7114 ":");
7115 avp->av_recv_pspoll(ni, m);
7116 #else
7117 avp->av_recv_pspoll(ni, m);
7118 #endif /* ATH_SW_PSQ */
7119 }
7120
7121 MODULE_VERSION(ath_main, 1);
7122 MODULE_DEPEND(ath_main, wlan, 1, 1, 1); /* 802.11 media layer */
7123 MODULE_DEPEND(ath_main, ath_rate, 1, 1, 1);
7124 MODULE_DEPEND(ath_main, ath_dfs, 1, 1, 1);
7125 MODULE_DEPEND(ath_main, ath_hal, 1, 1, 1);
7126 #if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ) || defined(ATH_DEBUG_ALQ)
7127 MODULE_DEPEND(ath_main, alq, 1, 1, 1);
7128 #endif
7129