1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <crypto/hash.h>
8 #include "core.h"
9 #include "dp_tx.h"
10 #include "hal_tx.h"
11 #include "hif.h"
12 #include "debug.h"
13 #include "dp_rx.h"
14 #include "peer.h"
15 #include "dp_mon.h"
16
17 enum ath12k_dp_desc_type {
18 ATH12K_DP_TX_DESC,
19 ATH12K_DP_RX_DESC,
20 };
21
ath12k_dp_htt_htc_tx_complete(struct ath12k_base * ab,struct sk_buff * skb)22 static void ath12k_dp_htt_htc_tx_complete(struct ath12k_base *ab,
23 struct sk_buff *skb)
24 {
25 dev_kfree_skb_any(skb);
26 }
27
ath12k_dp_peer_cleanup(struct ath12k * ar,int vdev_id,const u8 * addr)28 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr)
29 {
30 struct ath12k_base *ab = ar->ab;
31 struct ath12k_peer *peer;
32
33 /* TODO: Any other peer specific DP cleanup */
34
35 spin_lock_bh(&ab->base_lock);
36 peer = ath12k_peer_find(ab, vdev_id, addr);
37 if (!peer) {
38 ath12k_warn(ab, "failed to lookup peer %pM on vdev %d\n",
39 addr, vdev_id);
40 spin_unlock_bh(&ab->base_lock);
41 return;
42 }
43
44 if (!peer->primary_link) {
45 spin_unlock_bh(&ab->base_lock);
46 return;
47 }
48
49 ath12k_dp_rx_peer_tid_cleanup(ar, peer);
50 crypto_free_shash(peer->tfm_mmic);
51 peer->dp_setup_done = false;
52 spin_unlock_bh(&ab->base_lock);
53 }
54
ath12k_dp_peer_setup(struct ath12k * ar,int vdev_id,const u8 * addr)55 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr)
56 {
57 struct ath12k_base *ab = ar->ab;
58 struct ath12k_peer *peer;
59 u32 reo_dest;
60 int ret = 0, tid;
61
62 /* NOTE: reo_dest ring id starts from 1 unlike mac_id which starts from 0 */
63 reo_dest = ar->dp.mac_id + 1;
64 ret = ath12k_wmi_set_peer_param(ar, addr, vdev_id,
65 WMI_PEER_SET_DEFAULT_ROUTING,
66 DP_RX_HASH_ENABLE | (reo_dest << 1));
67
68 if (ret) {
69 ath12k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n",
70 ret, addr, vdev_id);
71 return ret;
72 }
73
74 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
75 ret = ath12k_dp_rx_peer_tid_setup(ar, addr, vdev_id, tid, 1, 0,
76 HAL_PN_TYPE_NONE);
77 if (ret) {
78 ath12k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n",
79 tid, ret);
80 goto peer_clean;
81 }
82 }
83
84 ret = ath12k_dp_rx_peer_frag_setup(ar, addr, vdev_id);
85 if (ret) {
86 ath12k_warn(ab, "failed to setup rx defrag context\n");
87 goto peer_clean;
88 }
89
90 /* TODO: Setup other peer specific resource used in data path */
91
92 return 0;
93
94 peer_clean:
95 spin_lock_bh(&ab->base_lock);
96
97 peer = ath12k_peer_find(ab, vdev_id, addr);
98 if (!peer) {
99 ath12k_warn(ab, "failed to find the peer to del rx tid\n");
100 spin_unlock_bh(&ab->base_lock);
101 return -ENOENT;
102 }
103
104 for (tid--; tid >= 0; tid--)
105 ath12k_dp_rx_peer_tid_delete(ar, peer, tid);
106
107 spin_unlock_bh(&ab->base_lock);
108
109 return ret;
110 }
111
ath12k_dp_srng_cleanup(struct ath12k_base * ab,struct dp_srng * ring)112 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring)
113 {
114 if (!ring->vaddr_unaligned)
115 return;
116
117 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned,
118 ring->paddr_unaligned);
119
120 ring->vaddr_unaligned = NULL;
121 }
122
ath12k_dp_srng_find_ring_in_mask(int ring_num,const u8 * grp_mask)123 static int ath12k_dp_srng_find_ring_in_mask(int ring_num, const u8 *grp_mask)
124 {
125 int ext_group_num;
126 u8 mask = 1 << ring_num;
127
128 for (ext_group_num = 0; ext_group_num < ATH12K_EXT_IRQ_GRP_NUM_MAX;
129 ext_group_num++) {
130 if (mask & grp_mask[ext_group_num])
131 return ext_group_num;
132 }
133
134 return -ENOENT;
135 }
136
ath12k_dp_srng_calculate_msi_group(struct ath12k_base * ab,enum hal_ring_type type,int ring_num)137 static int ath12k_dp_srng_calculate_msi_group(struct ath12k_base *ab,
138 enum hal_ring_type type, int ring_num)
139 {
140 const struct ath12k_hal_tcl_to_wbm_rbm_map *map;
141 const u8 *grp_mask;
142 int i;
143
144 switch (type) {
145 case HAL_WBM2SW_RELEASE:
146 if (ring_num == HAL_WBM2SW_REL_ERR_RING_NUM) {
147 grp_mask = &ab->hw_params->ring_mask->rx_wbm_rel[0];
148 ring_num = 0;
149 } else {
150 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map;
151 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
152 if (ring_num == map[i].wbm_ring_num) {
153 ring_num = i;
154 break;
155 }
156 }
157
158 grp_mask = &ab->hw_params->ring_mask->tx[0];
159 }
160 break;
161 case HAL_REO_EXCEPTION:
162 grp_mask = &ab->hw_params->ring_mask->rx_err[0];
163 break;
164 case HAL_REO_DST:
165 grp_mask = &ab->hw_params->ring_mask->rx[0];
166 break;
167 case HAL_REO_STATUS:
168 grp_mask = &ab->hw_params->ring_mask->reo_status[0];
169 break;
170 case HAL_RXDMA_MONITOR_STATUS:
171 grp_mask = &ab->hw_params->ring_mask->rx_mon_status[0];
172 break;
173 case HAL_RXDMA_MONITOR_DST:
174 grp_mask = &ab->hw_params->ring_mask->rx_mon_dest[0];
175 break;
176 case HAL_TX_MONITOR_DST:
177 grp_mask = &ab->hw_params->ring_mask->tx_mon_dest[0];
178 break;
179 case HAL_RXDMA_BUF:
180 grp_mask = &ab->hw_params->ring_mask->host2rxdma[0];
181 break;
182 case HAL_RXDMA_MONITOR_BUF:
183 case HAL_TCL_DATA:
184 case HAL_TCL_CMD:
185 case HAL_REO_CMD:
186 case HAL_SW2WBM_RELEASE:
187 case HAL_WBM_IDLE_LINK:
188 case HAL_TCL_STATUS:
189 case HAL_REO_REINJECT:
190 case HAL_CE_SRC:
191 case HAL_CE_DST:
192 case HAL_CE_DST_STATUS:
193 default:
194 return -ENOENT;
195 }
196
197 return ath12k_dp_srng_find_ring_in_mask(ring_num, grp_mask);
198 }
199
ath12k_dp_srng_msi_setup(struct ath12k_base * ab,struct hal_srng_params * ring_params,enum hal_ring_type type,int ring_num)200 static void ath12k_dp_srng_msi_setup(struct ath12k_base *ab,
201 struct hal_srng_params *ring_params,
202 enum hal_ring_type type, int ring_num)
203 {
204 int msi_group_number, msi_data_count;
205 u32 msi_data_start, msi_irq_start, addr_lo, addr_hi;
206 int ret;
207
208 ret = ath12k_hif_get_user_msi_vector(ab, "DP",
209 &msi_data_count, &msi_data_start,
210 &msi_irq_start);
211 if (ret)
212 return;
213
214 msi_group_number = ath12k_dp_srng_calculate_msi_group(ab, type,
215 ring_num);
216 if (msi_group_number < 0) {
217 ath12k_dbg(ab, ATH12K_DBG_PCI,
218 "ring not part of an ext_group; ring_type: %d,ring_num %d",
219 type, ring_num);
220 ring_params->msi_addr = 0;
221 ring_params->msi_data = 0;
222 return;
223 }
224
225 if (msi_group_number > msi_data_count) {
226 ath12k_dbg(ab, ATH12K_DBG_PCI,
227 "multiple msi_groups share one msi, msi_group_num %d",
228 msi_group_number);
229 }
230
231 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi);
232
233 ring_params->msi_addr = addr_lo;
234 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32);
235 ring_params->msi_data = (msi_group_number % msi_data_count)
236 + msi_data_start;
237 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR;
238 }
239
ath12k_dp_srng_setup(struct ath12k_base * ab,struct dp_srng * ring,enum hal_ring_type type,int ring_num,int mac_id,int num_entries)240 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,
241 enum hal_ring_type type, int ring_num,
242 int mac_id, int num_entries)
243 {
244 struct hal_srng_params params = {};
245 int entry_sz = ath12k_hal_srng_get_entrysize(ab, type);
246 int max_entries = ath12k_hal_srng_get_max_entries(ab, type);
247 int ret;
248
249 if (max_entries < 0 || entry_sz < 0)
250 return -EINVAL;
251
252 if (num_entries > max_entries)
253 num_entries = max_entries;
254
255 ring->size = (num_entries * entry_sz) + HAL_RING_BASE_ALIGN - 1;
256 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size,
257 &ring->paddr_unaligned,
258 GFP_KERNEL);
259 if (!ring->vaddr_unaligned)
260 return -ENOMEM;
261
262 ring->vaddr = PTR_ALIGN(ring->vaddr_unaligned, HAL_RING_BASE_ALIGN);
263 ring->paddr = ring->paddr_unaligned + ((unsigned long)ring->vaddr -
264 (unsigned long)ring->vaddr_unaligned);
265
266 params.ring_base_vaddr = ring->vaddr;
267 params.ring_base_paddr = ring->paddr;
268 params.num_entries = num_entries;
269 ath12k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id);
270
271 switch (type) {
272 case HAL_REO_DST:
273 params.intr_batch_cntr_thres_entries =
274 HAL_SRNG_INT_BATCH_THRESHOLD_RX;
275 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
276 break;
277 case HAL_RXDMA_BUF:
278 case HAL_RXDMA_MONITOR_BUF:
279 params.low_threshold = num_entries >> 3;
280 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
281 params.intr_batch_cntr_thres_entries = 0;
282 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
283 break;
284 case HAL_RXDMA_MONITOR_STATUS:
285 params.low_threshold = num_entries >> 3;
286 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
287 params.intr_batch_cntr_thres_entries = 1;
288 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
289 break;
290 case HAL_TX_MONITOR_DST:
291 params.low_threshold = DP_TX_MONITOR_BUF_SIZE_MAX >> 3;
292 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
293 params.intr_batch_cntr_thres_entries = 0;
294 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX;
295 break;
296 case HAL_WBM2SW_RELEASE:
297 if (ab->hw_params->hw_ops->dp_srng_is_tx_comp_ring(ring_num)) {
298 params.intr_batch_cntr_thres_entries =
299 HAL_SRNG_INT_BATCH_THRESHOLD_TX;
300 params.intr_timer_thres_us =
301 HAL_SRNG_INT_TIMER_THRESHOLD_TX;
302 break;
303 }
304 /* follow through when ring_num != HAL_WBM2SW_REL_ERR_RING_NUM */
305 fallthrough;
306 case HAL_REO_EXCEPTION:
307 case HAL_REO_REINJECT:
308 case HAL_REO_CMD:
309 case HAL_REO_STATUS:
310 case HAL_TCL_DATA:
311 case HAL_TCL_CMD:
312 case HAL_TCL_STATUS:
313 case HAL_WBM_IDLE_LINK:
314 case HAL_SW2WBM_RELEASE:
315 case HAL_RXDMA_DST:
316 case HAL_RXDMA_MONITOR_DST:
317 case HAL_RXDMA_MONITOR_DESC:
318 params.intr_batch_cntr_thres_entries =
319 HAL_SRNG_INT_BATCH_THRESHOLD_OTHER;
320 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_OTHER;
321 break;
322 case HAL_RXDMA_DIR_BUF:
323 break;
324 default:
325 ath12k_warn(ab, "Not a valid ring type in dp :%d\n", type);
326 return -EINVAL;
327 }
328
329 ret = ath12k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms);
330 if (ret < 0) {
331 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n",
332 ret, ring_num);
333 return ret;
334 }
335
336 ring->ring_id = ret;
337
338 return 0;
339 }
340
341 static
ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base * ab,struct ath12k_link_vif * arvif)342 u32 ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base *ab,
343 struct ath12k_link_vif *arvif)
344 {
345 u32 bank_config = 0;
346 struct ath12k_vif *ahvif = arvif->ahvif;
347
348 /* Only valid for raw frames with HW crypto enabled.
349 * With SW crypto, mac80211 sets key per packet
350 */
351 if (ahvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW &&
352 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags))
353 bank_config |=
354 u32_encode_bits(ath12k_dp_tx_get_encrypt_type(ahvif->key_cipher),
355 HAL_TX_BANK_CONFIG_ENCRYPT_TYPE);
356
357 bank_config |= u32_encode_bits(ahvif->tx_encap_type,
358 HAL_TX_BANK_CONFIG_ENCAP_TYPE);
359 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP) |
360 u32_encode_bits(0, HAL_TX_BANK_CONFIG_LINK_META_SWAP) |
361 u32_encode_bits(0, HAL_TX_BANK_CONFIG_EPD);
362
363 /* only valid if idx_lookup_override is not set in tcl_data_cmd */
364 if (ahvif->vdev_type == WMI_VDEV_TYPE_STA)
365 bank_config |= u32_encode_bits(1, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN);
366 else
367 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN);
368
369 bank_config |= u32_encode_bits(arvif->hal_addr_search_flags & HAL_TX_ADDRX_EN,
370 HAL_TX_BANK_CONFIG_ADDRX_EN) |
371 u32_encode_bits(!!(arvif->hal_addr_search_flags &
372 HAL_TX_ADDRY_EN),
373 HAL_TX_BANK_CONFIG_ADDRY_EN);
374
375 bank_config |= u32_encode_bits(ieee80211_vif_is_mesh(ahvif->vif) ? 3 : 0,
376 HAL_TX_BANK_CONFIG_MESH_EN) |
377 u32_encode_bits(arvif->vdev_id_check_en,
378 HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN);
379
380 bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID);
381
382 return bank_config;
383 }
384
ath12k_dp_tx_get_bank_profile(struct ath12k_base * ab,struct ath12k_link_vif * arvif,struct ath12k_dp * dp)385 static int ath12k_dp_tx_get_bank_profile(struct ath12k_base *ab,
386 struct ath12k_link_vif *arvif,
387 struct ath12k_dp *dp)
388 {
389 int bank_id = DP_INVALID_BANK_ID;
390 int i;
391 u32 bank_config;
392 bool configure_register = false;
393
394 /* convert vdev params into hal_tx_bank_config */
395 bank_config = ath12k_dp_tx_get_vdev_bank_config(ab, arvif);
396
397 spin_lock_bh(&dp->tx_bank_lock);
398 /* TODO: implement using idr kernel framework*/
399 for (i = 0; i < dp->num_bank_profiles; i++) {
400 if (dp->bank_profiles[i].is_configured &&
401 (dp->bank_profiles[i].bank_config ^ bank_config) == 0) {
402 bank_id = i;
403 goto inc_ref_and_return;
404 }
405 if (!dp->bank_profiles[i].is_configured ||
406 !dp->bank_profiles[i].num_users) {
407 bank_id = i;
408 goto configure_and_return;
409 }
410 }
411
412 if (bank_id == DP_INVALID_BANK_ID) {
413 spin_unlock_bh(&dp->tx_bank_lock);
414 ath12k_err(ab, "unable to find TX bank!");
415 return bank_id;
416 }
417
418 configure_and_return:
419 dp->bank_profiles[bank_id].is_configured = true;
420 dp->bank_profiles[bank_id].bank_config = bank_config;
421 configure_register = true;
422 inc_ref_and_return:
423 dp->bank_profiles[bank_id].num_users++;
424 spin_unlock_bh(&dp->tx_bank_lock);
425
426 if (configure_register)
427 ath12k_hal_tx_configure_bank_register(ab, bank_config, bank_id);
428
429 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt tcl bank_id %d input 0x%x match 0x%x num_users %u",
430 bank_id, bank_config, dp->bank_profiles[bank_id].bank_config,
431 dp->bank_profiles[bank_id].num_users);
432
433 return bank_id;
434 }
435
ath12k_dp_tx_put_bank_profile(struct ath12k_dp * dp,u8 bank_id)436 void ath12k_dp_tx_put_bank_profile(struct ath12k_dp *dp, u8 bank_id)
437 {
438 spin_lock_bh(&dp->tx_bank_lock);
439 dp->bank_profiles[bank_id].num_users--;
440 spin_unlock_bh(&dp->tx_bank_lock);
441 }
442
ath12k_dp_deinit_bank_profiles(struct ath12k_base * ab)443 static void ath12k_dp_deinit_bank_profiles(struct ath12k_base *ab)
444 {
445 struct ath12k_dp *dp = &ab->dp;
446
447 kfree(dp->bank_profiles);
448 dp->bank_profiles = NULL;
449 }
450
ath12k_dp_init_bank_profiles(struct ath12k_base * ab)451 static int ath12k_dp_init_bank_profiles(struct ath12k_base *ab)
452 {
453 struct ath12k_dp *dp = &ab->dp;
454 u32 num_tcl_banks = ab->hw_params->num_tcl_banks;
455 int i;
456
457 dp->num_bank_profiles = num_tcl_banks;
458 dp->bank_profiles = kmalloc_array(num_tcl_banks,
459 sizeof(struct ath12k_dp_tx_bank_profile),
460 GFP_KERNEL);
461 if (!dp->bank_profiles)
462 return -ENOMEM;
463
464 spin_lock_init(&dp->tx_bank_lock);
465
466 for (i = 0; i < num_tcl_banks; i++) {
467 dp->bank_profiles[i].is_configured = false;
468 dp->bank_profiles[i].num_users = 0;
469 }
470
471 return 0;
472 }
473
ath12k_dp_srng_common_cleanup(struct ath12k_base * ab)474 static void ath12k_dp_srng_common_cleanup(struct ath12k_base *ab)
475 {
476 struct ath12k_dp *dp = &ab->dp;
477 int i;
478
479 ath12k_dp_srng_cleanup(ab, &dp->reo_status_ring);
480 ath12k_dp_srng_cleanup(ab, &dp->reo_cmd_ring);
481 ath12k_dp_srng_cleanup(ab, &dp->reo_except_ring);
482 ath12k_dp_srng_cleanup(ab, &dp->rx_rel_ring);
483 ath12k_dp_srng_cleanup(ab, &dp->reo_reinject_ring);
484 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
485 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring);
486 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring);
487 }
488 ath12k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring);
489 }
490
ath12k_dp_srng_common_setup(struct ath12k_base * ab)491 static int ath12k_dp_srng_common_setup(struct ath12k_base *ab)
492 {
493 struct ath12k_dp *dp = &ab->dp;
494 const struct ath12k_hal_tcl_to_wbm_rbm_map *map;
495 struct hal_srng *srng;
496 int i, ret, tx_comp_ring_num;
497 u32 ring_hash_map;
498
499 ret = ath12k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring,
500 HAL_SW2WBM_RELEASE, 0, 0,
501 DP_WBM_RELEASE_RING_SIZE);
502 if (ret) {
503 ath12k_warn(ab, "failed to set up wbm2sw_release ring :%d\n",
504 ret);
505 goto err;
506 }
507
508 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
509 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map;
510 tx_comp_ring_num = map[i].wbm_ring_num;
511
512 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring,
513 HAL_TCL_DATA, i, 0,
514 DP_TCL_DATA_RING_SIZE);
515 if (ret) {
516 ath12k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n",
517 i, ret);
518 goto err;
519 }
520
521 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring,
522 HAL_WBM2SW_RELEASE, tx_comp_ring_num, 0,
523 DP_TX_COMP_RING_SIZE(ab));
524 if (ret) {
525 ath12k_warn(ab, "failed to set up tcl_comp ring (%d) :%d\n",
526 tx_comp_ring_num, ret);
527 goto err;
528 }
529 }
530
531 ret = ath12k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT,
532 0, 0, DP_REO_REINJECT_RING_SIZE);
533 if (ret) {
534 ath12k_warn(ab, "failed to set up reo_reinject ring :%d\n",
535 ret);
536 goto err;
537 }
538
539 ret = ath12k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE,
540 HAL_WBM2SW_REL_ERR_RING_NUM, 0,
541 DP_RX_RELEASE_RING_SIZE);
542 if (ret) {
543 ath12k_warn(ab, "failed to set up rx_rel ring :%d\n", ret);
544 goto err;
545 }
546
547 ret = ath12k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION,
548 0, 0, DP_REO_EXCEPTION_RING_SIZE);
549 if (ret) {
550 ath12k_warn(ab, "failed to set up reo_exception ring :%d\n",
551 ret);
552 goto err;
553 }
554
555 ret = ath12k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD,
556 0, 0, DP_REO_CMD_RING_SIZE);
557 if (ret) {
558 ath12k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret);
559 goto err;
560 }
561
562 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
563 ath12k_hal_reo_init_cmd_ring(ab, srng);
564
565 ret = ath12k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS,
566 0, 0, DP_REO_STATUS_RING_SIZE);
567 if (ret) {
568 ath12k_warn(ab, "failed to set up reo_status ring :%d\n", ret);
569 goto err;
570 }
571
572 /* When hash based routing of rx packet is enabled, 32 entries to map
573 * the hash values to the ring will be configured. Each hash entry uses
574 * four bits to map to a particular ring. The ring mapping will be
575 * 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:SW5
576 * 8:SW6, 9:SW7, 10:SW8, 11:Not used.
577 */
578 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 |
579 HAL_HASH_ROUTING_RING_SW2 << 4 |
580 HAL_HASH_ROUTING_RING_SW3 << 8 |
581 HAL_HASH_ROUTING_RING_SW4 << 12 |
582 HAL_HASH_ROUTING_RING_SW1 << 16 |
583 HAL_HASH_ROUTING_RING_SW2 << 20 |
584 HAL_HASH_ROUTING_RING_SW3 << 24 |
585 HAL_HASH_ROUTING_RING_SW4 << 28;
586
587 ath12k_hal_reo_hw_setup(ab, ring_hash_map);
588
589 return 0;
590
591 err:
592 ath12k_dp_srng_common_cleanup(ab);
593
594 return ret;
595 }
596
ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base * ab)597 static void ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base *ab)
598 {
599 struct ath12k_dp *dp = &ab->dp;
600 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list;
601 int i;
602
603 for (i = 0; i < DP_IDLE_SCATTER_BUFS_MAX; i++) {
604 if (!slist[i].vaddr)
605 continue;
606
607 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX,
608 slist[i].vaddr, slist[i].paddr);
609 slist[i].vaddr = NULL;
610 }
611 }
612
ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base * ab,int size,u32 n_link_desc_bank,u32 n_link_desc,u32 last_bank_sz)613 static int ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base *ab,
614 int size,
615 u32 n_link_desc_bank,
616 u32 n_link_desc,
617 u32 last_bank_sz)
618 {
619 struct ath12k_dp *dp = &ab->dp;
620 struct dp_link_desc_bank *link_desc_banks = dp->link_desc_banks;
621 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list;
622 u32 n_entries_per_buf;
623 int num_scatter_buf, scatter_idx;
624 struct hal_wbm_link_desc *scatter_buf;
625 int align_bytes, n_entries;
626 dma_addr_t paddr;
627 int rem_entries;
628 int i;
629 int ret = 0;
630 u32 end_offset, cookie;
631 enum hal_rx_buf_return_buf_manager rbm = dp->idle_link_rbm;
632
633 n_entries_per_buf = HAL_WBM_IDLE_SCATTER_BUF_SIZE /
634 ath12k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK);
635 num_scatter_buf = DIV_ROUND_UP(size, HAL_WBM_IDLE_SCATTER_BUF_SIZE);
636
637 if (num_scatter_buf > DP_IDLE_SCATTER_BUFS_MAX)
638 return -EINVAL;
639
640 for (i = 0; i < num_scatter_buf; i++) {
641 slist[i].vaddr = dma_alloc_coherent(ab->dev,
642 HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX,
643 &slist[i].paddr, GFP_KERNEL);
644 if (!slist[i].vaddr) {
645 ret = -ENOMEM;
646 goto err;
647 }
648 }
649
650 scatter_idx = 0;
651 scatter_buf = slist[scatter_idx].vaddr;
652 rem_entries = n_entries_per_buf;
653
654 for (i = 0; i < n_link_desc_bank; i++) {
655 #if defined(__linux__)
656 align_bytes = link_desc_banks[i].vaddr -
657 link_desc_banks[i].vaddr_unaligned;
658 #elif defined(__FreeBSD__)
659 align_bytes = (uintptr_t)link_desc_banks[i].vaddr -
660 (uintptr_t)link_desc_banks[i].vaddr_unaligned;
661 #endif
662 n_entries = (DP_LINK_DESC_ALLOC_SIZE_THRESH - align_bytes) /
663 HAL_LINK_DESC_SIZE;
664 paddr = link_desc_banks[i].paddr;
665 while (n_entries) {
666 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i);
667 ath12k_hal_set_link_desc_addr(scatter_buf, cookie,
668 paddr, rbm);
669 n_entries--;
670 paddr += HAL_LINK_DESC_SIZE;
671 if (rem_entries) {
672 rem_entries--;
673 scatter_buf++;
674 continue;
675 }
676
677 rem_entries = n_entries_per_buf;
678 scatter_idx++;
679 scatter_buf = slist[scatter_idx].vaddr;
680 }
681 }
682
683 end_offset = (scatter_buf - slist[scatter_idx].vaddr) *
684 sizeof(struct hal_wbm_link_desc);
685 ath12k_hal_setup_link_idle_list(ab, slist, num_scatter_buf,
686 n_link_desc, end_offset);
687
688 return 0;
689
690 err:
691 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
692
693 return ret;
694 }
695
696 static void
ath12k_dp_link_desc_bank_free(struct ath12k_base * ab,struct dp_link_desc_bank * link_desc_banks)697 ath12k_dp_link_desc_bank_free(struct ath12k_base *ab,
698 struct dp_link_desc_bank *link_desc_banks)
699 {
700 int i;
701
702 for (i = 0; i < DP_LINK_DESC_BANKS_MAX; i++) {
703 if (link_desc_banks[i].vaddr_unaligned) {
704 dma_free_coherent(ab->dev,
705 link_desc_banks[i].size,
706 link_desc_banks[i].vaddr_unaligned,
707 link_desc_banks[i].paddr_unaligned);
708 link_desc_banks[i].vaddr_unaligned = NULL;
709 }
710 }
711 }
712
ath12k_dp_link_desc_bank_alloc(struct ath12k_base * ab,struct dp_link_desc_bank * desc_bank,int n_link_desc_bank,int last_bank_sz)713 static int ath12k_dp_link_desc_bank_alloc(struct ath12k_base *ab,
714 struct dp_link_desc_bank *desc_bank,
715 int n_link_desc_bank,
716 int last_bank_sz)
717 {
718 struct ath12k_dp *dp = &ab->dp;
719 int i;
720 int ret = 0;
721 int desc_sz = DP_LINK_DESC_ALLOC_SIZE_THRESH;
722
723 for (i = 0; i < n_link_desc_bank; i++) {
724 if (i == (n_link_desc_bank - 1) && last_bank_sz)
725 desc_sz = last_bank_sz;
726
727 desc_bank[i].vaddr_unaligned =
728 dma_alloc_coherent(ab->dev, desc_sz,
729 &desc_bank[i].paddr_unaligned,
730 GFP_KERNEL);
731 if (!desc_bank[i].vaddr_unaligned) {
732 ret = -ENOMEM;
733 goto err;
734 }
735
736 desc_bank[i].vaddr = PTR_ALIGN(desc_bank[i].vaddr_unaligned,
737 HAL_LINK_DESC_ALIGN);
738 desc_bank[i].paddr = desc_bank[i].paddr_unaligned +
739 ((unsigned long)desc_bank[i].vaddr -
740 (unsigned long)desc_bank[i].vaddr_unaligned);
741 desc_bank[i].size = desc_sz;
742 }
743
744 return 0;
745
746 err:
747 ath12k_dp_link_desc_bank_free(ab, dp->link_desc_banks);
748
749 return ret;
750 }
751
ath12k_dp_link_desc_cleanup(struct ath12k_base * ab,struct dp_link_desc_bank * desc_bank,u32 ring_type,struct dp_srng * ring)752 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,
753 struct dp_link_desc_bank *desc_bank,
754 u32 ring_type, struct dp_srng *ring)
755 {
756 ath12k_dp_link_desc_bank_free(ab, desc_bank);
757
758 if (ring_type != HAL_RXDMA_MONITOR_DESC) {
759 ath12k_dp_srng_cleanup(ab, ring);
760 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
761 }
762 }
763
ath12k_wbm_idle_ring_setup(struct ath12k_base * ab,u32 * n_link_desc)764 static int ath12k_wbm_idle_ring_setup(struct ath12k_base *ab, u32 *n_link_desc)
765 {
766 struct ath12k_dp *dp = &ab->dp;
767 u32 n_mpdu_link_desc, n_mpdu_queue_desc;
768 u32 n_tx_msdu_link_desc, n_rx_msdu_link_desc;
769 int ret = 0;
770
771 n_mpdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX) /
772 HAL_NUM_MPDUS_PER_LINK_DESC;
773
774 n_mpdu_queue_desc = n_mpdu_link_desc /
775 HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC;
776
777 n_tx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_FLOWS_PER_TID *
778 DP_AVG_MSDUS_PER_FLOW) /
779 HAL_NUM_TX_MSDUS_PER_LINK_DESC;
780
781 n_rx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX *
782 DP_AVG_MSDUS_PER_MPDU) /
783 HAL_NUM_RX_MSDUS_PER_LINK_DESC;
784
785 *n_link_desc = n_mpdu_link_desc + n_mpdu_queue_desc +
786 n_tx_msdu_link_desc + n_rx_msdu_link_desc;
787
788 if (*n_link_desc & (*n_link_desc - 1))
789 *n_link_desc = 1 << fls(*n_link_desc);
790
791 ret = ath12k_dp_srng_setup(ab, &dp->wbm_idle_ring,
792 HAL_WBM_IDLE_LINK, 0, 0, *n_link_desc);
793 if (ret) {
794 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
795 return ret;
796 }
797 return ret;
798 }
799
ath12k_dp_link_desc_setup(struct ath12k_base * ab,struct dp_link_desc_bank * link_desc_banks,u32 ring_type,struct hal_srng * srng,u32 n_link_desc)800 int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
801 struct dp_link_desc_bank *link_desc_banks,
802 u32 ring_type, struct hal_srng *srng,
803 u32 n_link_desc)
804 {
805 u32 tot_mem_sz;
806 u32 n_link_desc_bank, last_bank_sz;
807 u32 entry_sz, align_bytes, n_entries;
808 struct hal_wbm_link_desc *desc;
809 u32 paddr;
810 int i, ret;
811 u32 cookie;
812 enum hal_rx_buf_return_buf_manager rbm = ab->dp.idle_link_rbm;
813
814 tot_mem_sz = n_link_desc * HAL_LINK_DESC_SIZE;
815 tot_mem_sz += HAL_LINK_DESC_ALIGN;
816
817 if (tot_mem_sz <= DP_LINK_DESC_ALLOC_SIZE_THRESH) {
818 n_link_desc_bank = 1;
819 last_bank_sz = tot_mem_sz;
820 } else {
821 n_link_desc_bank = tot_mem_sz /
822 (DP_LINK_DESC_ALLOC_SIZE_THRESH -
823 HAL_LINK_DESC_ALIGN);
824 last_bank_sz = tot_mem_sz %
825 (DP_LINK_DESC_ALLOC_SIZE_THRESH -
826 HAL_LINK_DESC_ALIGN);
827
828 if (last_bank_sz)
829 n_link_desc_bank += 1;
830 }
831
832 if (n_link_desc_bank > DP_LINK_DESC_BANKS_MAX)
833 return -EINVAL;
834
835 ret = ath12k_dp_link_desc_bank_alloc(ab, link_desc_banks,
836 n_link_desc_bank, last_bank_sz);
837 if (ret)
838 return ret;
839
840 /* Setup link desc idle list for HW internal usage */
841 entry_sz = ath12k_hal_srng_get_entrysize(ab, ring_type);
842 tot_mem_sz = entry_sz * n_link_desc;
843
844 /* Setup scatter desc list when the total memory requirement is more */
845 if (tot_mem_sz > DP_LINK_DESC_ALLOC_SIZE_THRESH &&
846 ring_type != HAL_RXDMA_MONITOR_DESC) {
847 ret = ath12k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz,
848 n_link_desc_bank,
849 n_link_desc,
850 last_bank_sz);
851 if (ret) {
852 ath12k_warn(ab, "failed to setup scatting idle list descriptor :%d\n",
853 ret);
854 goto fail_desc_bank_free;
855 }
856
857 return 0;
858 }
859
860 spin_lock_bh(&srng->lock);
861
862 ath12k_hal_srng_access_begin(ab, srng);
863
864 for (i = 0; i < n_link_desc_bank; i++) {
865 #if defined(__linux__)
866 align_bytes = link_desc_banks[i].vaddr -
867 link_desc_banks[i].vaddr_unaligned;
868 #elif defined(__FreeBSD__)
869 align_bytes = (uintptr_t)link_desc_banks[i].vaddr -
870 (uintptr_t)link_desc_banks[i].vaddr_unaligned;
871 #endif
872 n_entries = (link_desc_banks[i].size - align_bytes) /
873 HAL_LINK_DESC_SIZE;
874 paddr = link_desc_banks[i].paddr;
875 while (n_entries &&
876 (desc = ath12k_hal_srng_src_get_next_entry(ab, srng))) {
877 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i);
878 ath12k_hal_set_link_desc_addr(desc, cookie, paddr, rbm);
879 n_entries--;
880 paddr += HAL_LINK_DESC_SIZE;
881 }
882 }
883
884 ath12k_hal_srng_access_end(ab, srng);
885
886 spin_unlock_bh(&srng->lock);
887
888 return 0;
889
890 fail_desc_bank_free:
891 ath12k_dp_link_desc_bank_free(ab, link_desc_banks);
892
893 return ret;
894 }
895
ath12k_dp_service_srng(struct ath12k_base * ab,struct ath12k_ext_irq_grp * irq_grp,int budget)896 int ath12k_dp_service_srng(struct ath12k_base *ab,
897 struct ath12k_ext_irq_grp *irq_grp,
898 int budget)
899 {
900 struct napi_struct *napi = &irq_grp->napi;
901 int grp_id = irq_grp->grp_id;
902 int work_done = 0;
903 int i = 0, j;
904 int tot_work_done = 0;
905 enum dp_monitor_mode monitor_mode;
906 u8 ring_mask;
907
908 if (ab->hw_params->ring_mask->tx[grp_id]) {
909 i = fls(ab->hw_params->ring_mask->tx[grp_id]) - 1;
910 ath12k_dp_tx_completion_handler(ab, i);
911 }
912
913 if (ab->hw_params->ring_mask->rx_err[grp_id]) {
914 work_done = ath12k_dp_rx_process_err(ab, napi, budget);
915 budget -= work_done;
916 tot_work_done += work_done;
917 if (budget <= 0)
918 goto done;
919 }
920
921 if (ab->hw_params->ring_mask->rx_wbm_rel[grp_id]) {
922 work_done = ath12k_dp_rx_process_wbm_err(ab,
923 napi,
924 budget);
925 budget -= work_done;
926 tot_work_done += work_done;
927
928 if (budget <= 0)
929 goto done;
930 }
931
932 if (ab->hw_params->ring_mask->rx[grp_id]) {
933 i = fls(ab->hw_params->ring_mask->rx[grp_id]) - 1;
934 work_done = ath12k_dp_rx_process(ab, i, napi,
935 budget);
936 budget -= work_done;
937 tot_work_done += work_done;
938 if (budget <= 0)
939 goto done;
940 }
941
942 if (ab->hw_params->ring_mask->rx_mon_status[grp_id]) {
943 ring_mask = ab->hw_params->ring_mask->rx_mon_status[grp_id];
944 for (i = 0; i < ab->num_radios; i++) {
945 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) {
946 int id = i * ab->hw_params->num_rxdma_per_pdev + j;
947
948 if (ring_mask & BIT(id)) {
949 work_done =
950 ath12k_dp_mon_process_ring(ab, id, napi, budget,
951 0);
952 budget -= work_done;
953 tot_work_done += work_done;
954 if (budget <= 0)
955 goto done;
956 }
957 }
958 }
959 }
960
961 if (ab->hw_params->ring_mask->rx_mon_dest[grp_id]) {
962 monitor_mode = ATH12K_DP_RX_MONITOR_MODE;
963 ring_mask = ab->hw_params->ring_mask->rx_mon_dest[grp_id];
964 for (i = 0; i < ab->num_radios; i++) {
965 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) {
966 int id = i * ab->hw_params->num_rxdma_per_pdev + j;
967
968 if (ring_mask & BIT(id)) {
969 work_done =
970 ath12k_dp_mon_process_ring(ab, id, napi, budget,
971 monitor_mode);
972 budget -= work_done;
973 tot_work_done += work_done;
974
975 if (budget <= 0)
976 goto done;
977 }
978 }
979 }
980 }
981
982 if (ab->hw_params->ring_mask->tx_mon_dest[grp_id]) {
983 monitor_mode = ATH12K_DP_TX_MONITOR_MODE;
984 ring_mask = ab->hw_params->ring_mask->tx_mon_dest[grp_id];
985 for (i = 0; i < ab->num_radios; i++) {
986 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) {
987 int id = i * ab->hw_params->num_rxdma_per_pdev + j;
988
989 if (ring_mask & BIT(id)) {
990 work_done =
991 ath12k_dp_mon_process_ring(ab, id, napi, budget,
992 monitor_mode);
993 budget -= work_done;
994 tot_work_done += work_done;
995
996 if (budget <= 0)
997 goto done;
998 }
999 }
1000 }
1001 }
1002
1003 if (ab->hw_params->ring_mask->reo_status[grp_id])
1004 ath12k_dp_rx_process_reo_status(ab);
1005
1006 if (ab->hw_params->ring_mask->host2rxdma[grp_id]) {
1007 struct ath12k_dp *dp = &ab->dp;
1008 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
1009 LIST_HEAD(list);
1010
1011 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0);
1012 }
1013
1014 /* TODO: Implement handler for other interrupts */
1015
1016 done:
1017 return tot_work_done;
1018 }
1019
ath12k_dp_pdev_free(struct ath12k_base * ab)1020 void ath12k_dp_pdev_free(struct ath12k_base *ab)
1021 {
1022 int i;
1023
1024 for (i = 0; i < ab->num_radios; i++)
1025 ath12k_dp_rx_pdev_free(ab, i);
1026 }
1027
ath12k_dp_pdev_pre_alloc(struct ath12k * ar)1028 void ath12k_dp_pdev_pre_alloc(struct ath12k *ar)
1029 {
1030 struct ath12k_pdev_dp *dp = &ar->dp;
1031
1032 dp->mac_id = ar->pdev_idx;
1033 atomic_set(&dp->num_tx_pending, 0);
1034 init_waitqueue_head(&dp->tx_empty_waitq);
1035 /* TODO: Add any RXDMA setup required per pdev */
1036 }
1037
ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base * ab)1038 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab)
1039 {
1040 if (test_bit(WMI_TLV_SERVICE_WMSK_COMPACTION_RX_TLVS, ab->wmi_ab.svc_map) &&
1041 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start &&
1042 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end &&
1043 ab->hw_params->hal_ops->get_hal_rx_compact_ops) {
1044 return true;
1045 }
1046 return false;
1047 }
1048
ath12k_dp_hal_rx_desc_init(struct ath12k_base * ab)1049 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab)
1050 {
1051 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) {
1052 /* RX TLVS compaction is supported, hence change the hal_rx_ops
1053 * to compact hal_rx_ops.
1054 */
1055 ab->hal_rx_ops = ab->hw_params->hal_ops->get_hal_rx_compact_ops();
1056 }
1057 ab->hal.hal_desc_sz =
1058 ab->hal_rx_ops->rx_desc_get_desc_size();
1059 }
1060
ath12k_dp_pdev_alloc(struct ath12k_base * ab)1061 int ath12k_dp_pdev_alloc(struct ath12k_base *ab)
1062 {
1063 struct ath12k *ar;
1064 int ret;
1065 int i;
1066
1067 ret = ath12k_dp_rx_htt_setup(ab);
1068 if (ret)
1069 goto out;
1070
1071 /* TODO: Per-pdev rx ring unlike tx ring which is mapped to different AC's */
1072 for (i = 0; i < ab->num_radios; i++) {
1073 ar = ab->pdevs[i].ar;
1074 ret = ath12k_dp_rx_pdev_alloc(ab, i);
1075 if (ret) {
1076 ath12k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n",
1077 i);
1078 goto err;
1079 }
1080 ret = ath12k_dp_rx_pdev_mon_attach(ar);
1081 if (ret) {
1082 ath12k_warn(ab, "failed to initialize mon pdev %d\n", i);
1083 goto err;
1084 }
1085 }
1086
1087 return 0;
1088 err:
1089 ath12k_dp_pdev_free(ab);
1090 out:
1091 return ret;
1092 }
1093
ath12k_dp_htt_connect(struct ath12k_dp * dp)1094 int ath12k_dp_htt_connect(struct ath12k_dp *dp)
1095 {
1096 struct ath12k_htc_svc_conn_req conn_req = {};
1097 struct ath12k_htc_svc_conn_resp conn_resp = {};
1098 int status;
1099
1100 conn_req.ep_ops.ep_tx_complete = ath12k_dp_htt_htc_tx_complete;
1101 conn_req.ep_ops.ep_rx_complete = ath12k_dp_htt_htc_t2h_msg_handler;
1102
1103 /* connect to control service */
1104 conn_req.service_id = ATH12K_HTC_SVC_ID_HTT_DATA_MSG;
1105
1106 status = ath12k_htc_connect_service(&dp->ab->htc, &conn_req,
1107 &conn_resp);
1108
1109 if (status)
1110 return status;
1111
1112 dp->eid = conn_resp.eid;
1113
1114 return 0;
1115 }
1116
ath12k_dp_update_vdev_search(struct ath12k_link_vif * arvif)1117 static void ath12k_dp_update_vdev_search(struct ath12k_link_vif *arvif)
1118 {
1119 switch (arvif->ahvif->vdev_type) {
1120 case WMI_VDEV_TYPE_STA:
1121 arvif->hal_addr_search_flags = HAL_TX_ADDRY_EN;
1122 arvif->search_type = HAL_TX_ADDR_SEARCH_INDEX;
1123 break;
1124 case WMI_VDEV_TYPE_AP:
1125 case WMI_VDEV_TYPE_IBSS:
1126 arvif->hal_addr_search_flags = HAL_TX_ADDRX_EN;
1127 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
1128 break;
1129 case WMI_VDEV_TYPE_MONITOR:
1130 default:
1131 return;
1132 }
1133 }
1134
ath12k_dp_vdev_tx_attach(struct ath12k * ar,struct ath12k_link_vif * arvif)1135 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif)
1136 {
1137 struct ath12k_base *ab = ar->ab;
1138
1139 arvif->tcl_metadata |= u32_encode_bits(1, HTT_TCL_META_DATA_TYPE) |
1140 u32_encode_bits(arvif->vdev_id,
1141 HTT_TCL_META_DATA_VDEV_ID) |
1142 u32_encode_bits(ar->pdev->pdev_id,
1143 HTT_TCL_META_DATA_PDEV_ID);
1144
1145 /* set HTT extension valid bit to 0 by default */
1146 arvif->tcl_metadata &= ~HTT_TCL_META_DATA_VALID_HTT;
1147
1148 ath12k_dp_update_vdev_search(arvif);
1149 arvif->vdev_id_check_en = true;
1150 arvif->bank_id = ath12k_dp_tx_get_bank_profile(ab, arvif, &ab->dp);
1151
1152 /* TODO: error path for bank id failure */
1153 if (arvif->bank_id == DP_INVALID_BANK_ID) {
1154 ath12k_err(ar->ab, "Failed to initialize DP TX Banks");
1155 return;
1156 }
1157 }
1158
ath12k_dp_cc_cleanup(struct ath12k_base * ab)1159 static void ath12k_dp_cc_cleanup(struct ath12k_base *ab)
1160 {
1161 struct ath12k_rx_desc_info *desc_info;
1162 struct ath12k_tx_desc_info *tx_desc_info, *tmp1;
1163 struct ath12k_dp *dp = &ab->dp;
1164 struct ath12k_skb_cb *skb_cb;
1165 struct sk_buff *skb;
1166 struct ath12k *ar;
1167 int i, j;
1168 u32 pool_id, tx_spt_page;
1169
1170 if (!dp->spt_info)
1171 return;
1172
1173 /* RX Descriptor cleanup */
1174 spin_lock_bh(&dp->rx_desc_lock);
1175
1176 if (dp->rxbaddr) {
1177 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES(ab); i++) {
1178 if (!dp->rxbaddr[i])
1179 continue;
1180
1181 desc_info = dp->rxbaddr[i];
1182
1183 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) {
1184 if (!desc_info[j].in_use) {
1185 list_del(&desc_info[j].list);
1186 continue;
1187 }
1188
1189 skb = desc_info[j].skb;
1190 if (!skb)
1191 continue;
1192
1193 dma_unmap_single(ab->dev,
1194 ATH12K_SKB_RXCB(skb)->paddr,
1195 skb->len + skb_tailroom(skb),
1196 DMA_FROM_DEVICE);
1197 dev_kfree_skb_any(skb);
1198 }
1199
1200 kfree(dp->rxbaddr[i]);
1201 dp->rxbaddr[i] = NULL;
1202 }
1203
1204 kfree(dp->rxbaddr);
1205 dp->rxbaddr = NULL;
1206 }
1207
1208 spin_unlock_bh(&dp->rx_desc_lock);
1209
1210 /* TX Descriptor cleanup */
1211 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) {
1212 spin_lock_bh(&dp->tx_desc_lock[i]);
1213
1214 list_for_each_entry_safe(tx_desc_info, tmp1,
1215 &dp->tx_desc_used_list[i], list) {
1216 list_del(&tx_desc_info->list);
1217 skb = tx_desc_info->skb;
1218
1219 if (!skb)
1220 continue;
1221
1222 skb_cb = ATH12K_SKB_CB(skb);
1223 if (skb_cb->paddr_ext_desc) {
1224 dma_unmap_single(ab->dev,
1225 skb_cb->paddr_ext_desc,
1226 tx_desc_info->skb_ext_desc->len,
1227 DMA_TO_DEVICE);
1228 dev_kfree_skb_any(tx_desc_info->skb_ext_desc);
1229 }
1230
1231 /* if we are unregistering, hw would've been destroyed and
1232 * ar is no longer valid.
1233 */
1234 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) {
1235 ar = skb_cb->ar;
1236
1237 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
1238 wake_up(&ar->dp.tx_empty_waitq);
1239 }
1240
1241 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr,
1242 skb->len, DMA_TO_DEVICE);
1243 dev_kfree_skb_any(skb);
1244 }
1245
1246 spin_unlock_bh(&dp->tx_desc_lock[i]);
1247 }
1248
1249 if (dp->txbaddr) {
1250 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) {
1251 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
1252
1253 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL(ab); i++) {
1254 tx_spt_page = i + pool_id *
1255 ATH12K_TX_SPT_PAGES_PER_POOL(ab);
1256 if (!dp->txbaddr[tx_spt_page])
1257 continue;
1258
1259 kfree(dp->txbaddr[tx_spt_page]);
1260 dp->txbaddr[tx_spt_page] = NULL;
1261 }
1262
1263 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1264 }
1265
1266 kfree(dp->txbaddr);
1267 dp->txbaddr = NULL;
1268 }
1269
1270 /* unmap SPT pages */
1271 for (i = 0; i < dp->num_spt_pages; i++) {
1272 if (!dp->spt_info[i].vaddr)
1273 continue;
1274
1275 dma_free_coherent(ab->dev, ATH12K_PAGE_SIZE,
1276 dp->spt_info[i].vaddr, dp->spt_info[i].paddr);
1277 dp->spt_info[i].vaddr = NULL;
1278 }
1279
1280 kfree(dp->spt_info);
1281 dp->spt_info = NULL;
1282 }
1283
ath12k_dp_reoq_lut_cleanup(struct ath12k_base * ab)1284 static void ath12k_dp_reoq_lut_cleanup(struct ath12k_base *ab)
1285 {
1286 struct ath12k_dp *dp = &ab->dp;
1287
1288 if (!ab->hw_params->reoq_lut_support)
1289 return;
1290
1291 if (dp->reoq_lut.vaddr_unaligned) {
1292 ath12k_hif_write32(ab,
1293 HAL_SEQ_WCSS_UMAC_REO_REG +
1294 HAL_REO1_QDESC_LUT_BASE0(ab), 0);
1295 dma_free_coherent(ab->dev, dp->reoq_lut.size,
1296 dp->reoq_lut.vaddr_unaligned,
1297 dp->reoq_lut.paddr_unaligned);
1298 dp->reoq_lut.vaddr_unaligned = NULL;
1299 }
1300
1301 if (dp->ml_reoq_lut.vaddr_unaligned) {
1302 ath12k_hif_write32(ab,
1303 HAL_SEQ_WCSS_UMAC_REO_REG +
1304 HAL_REO1_QDESC_LUT_BASE1(ab), 0);
1305 dma_free_coherent(ab->dev, dp->ml_reoq_lut.size,
1306 dp->ml_reoq_lut.vaddr_unaligned,
1307 dp->ml_reoq_lut.paddr_unaligned);
1308 dp->ml_reoq_lut.vaddr_unaligned = NULL;
1309 }
1310 }
1311
ath12k_dp_free(struct ath12k_base * ab)1312 void ath12k_dp_free(struct ath12k_base *ab)
1313 {
1314 struct ath12k_dp *dp = &ab->dp;
1315 int i;
1316
1317 if (!dp->ab)
1318 return;
1319
1320 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1321 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring);
1322
1323 ath12k_dp_cc_cleanup(ab);
1324 ath12k_dp_reoq_lut_cleanup(ab);
1325 ath12k_dp_deinit_bank_profiles(ab);
1326 ath12k_dp_srng_common_cleanup(ab);
1327
1328 ath12k_dp_rx_reo_cmd_list_cleanup(ab);
1329
1330 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
1331 kfree(dp->tx_ring[i].tx_status);
1332 dp->tx_ring[i].tx_status = NULL;
1333 }
1334
1335 ath12k_dp_rx_free(ab);
1336 /* Deinit any SOC level resource */
1337 dp->ab = NULL;
1338 }
1339
ath12k_dp_cc_config(struct ath12k_base * ab)1340 void ath12k_dp_cc_config(struct ath12k_base *ab)
1341 {
1342 u32 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1343 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
1344 u32 wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG;
1345 u32 val = 0;
1346
1347 if (ath12k_ftm_mode)
1348 return;
1349
1350 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(ab), cmem_base);
1351
1352 val |= u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
1353 HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
1354 u32_encode_bits(ATH12K_CC_PPT_MSB,
1355 HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
1356 u32_encode_bits(ATH12K_CC_SPT_MSB,
1357 HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
1358 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ALIGN) |
1359 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ENABLE) |
1360 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE);
1361
1362 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(ab), val);
1363
1364 /* Enable HW CC for WBM */
1365 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base);
1366
1367 val = u32_encode_bits(ATH12K_CMEM_ADDR_MSB,
1368 HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) |
1369 u32_encode_bits(ATH12K_CC_PPT_MSB,
1370 HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB) |
1371 u32_encode_bits(ATH12K_CC_SPT_MSB,
1372 HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB) |
1373 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ALIGN);
1374
1375 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val);
1376
1377 /* Enable conversion complete indication */
1378 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2);
1379 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN) |
1380 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN) |
1381 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN);
1382
1383 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val);
1384
1385 /* Enable Cookie conversion for WBM2SW Rings */
1386 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG);
1387 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN) |
1388 ab->hw_params->hal_params->wbm2sw_cc_enable;
1389
1390 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val);
1391 }
1392
ath12k_dp_cc_cookie_gen(u16 ppt_idx,u16 spt_idx)1393 static u32 ath12k_dp_cc_cookie_gen(u16 ppt_idx, u16 spt_idx)
1394 {
1395 return (u32)ppt_idx << ATH12K_CC_PPT_SHIFT | spt_idx;
1396 }
1397
ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base * ab,u16 ppt_idx,u16 spt_idx)1398 static inline void *ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base *ab,
1399 u16 ppt_idx, u16 spt_idx)
1400 {
1401 struct ath12k_dp *dp = &ab->dp;
1402
1403 return dp->spt_info[ppt_idx].vaddr + spt_idx;
1404 }
1405
ath12k_dp_get_rx_desc(struct ath12k_base * ab,u32 cookie)1406 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,
1407 u32 cookie)
1408 {
1409 struct ath12k_dp *dp = &ab->dp;
1410 struct ath12k_rx_desc_info **desc_addr_ptr;
1411 u16 start_ppt_idx, end_ppt_idx, ppt_idx, spt_idx;
1412
1413 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT);
1414 spt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_SPT);
1415
1416 start_ppt_idx = dp->rx_ppt_base + ATH12K_RX_SPT_PAGE_OFFSET(ab);
1417 end_ppt_idx = start_ppt_idx + ATH12K_NUM_RX_SPT_PAGES(ab);
1418
1419 if (ppt_idx < start_ppt_idx ||
1420 ppt_idx >= end_ppt_idx ||
1421 spt_idx > ATH12K_MAX_SPT_ENTRIES)
1422 return NULL;
1423
1424 ppt_idx = ppt_idx - dp->rx_ppt_base;
1425 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1426
1427 return *desc_addr_ptr;
1428 }
1429
ath12k_dp_get_tx_desc(struct ath12k_base * ab,u32 cookie)1430 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,
1431 u32 cookie)
1432 {
1433 struct ath12k_tx_desc_info **desc_addr_ptr;
1434 u16 start_ppt_idx, end_ppt_idx, ppt_idx, spt_idx;
1435
1436 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT);
1437 spt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_SPT);
1438
1439 start_ppt_idx = ATH12K_TX_SPT_PAGE_OFFSET;
1440 end_ppt_idx = start_ppt_idx +
1441 (ATH12K_TX_SPT_PAGES_PER_POOL(ab) * ATH12K_HW_MAX_QUEUES);
1442
1443 if (ppt_idx < start_ppt_idx ||
1444 ppt_idx >= end_ppt_idx ||
1445 spt_idx > ATH12K_MAX_SPT_ENTRIES)
1446 return NULL;
1447
1448 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1449
1450 return *desc_addr_ptr;
1451 }
1452
ath12k_dp_cc_desc_init(struct ath12k_base * ab)1453 static int ath12k_dp_cc_desc_init(struct ath12k_base *ab)
1454 {
1455 struct ath12k_dp *dp = &ab->dp;
1456 struct ath12k_rx_desc_info *rx_descs, **rx_desc_addr;
1457 struct ath12k_tx_desc_info *tx_descs, **tx_desc_addr;
1458 u32 num_rx_spt_pages = ATH12K_NUM_RX_SPT_PAGES(ab);
1459 u32 i, j, pool_id, tx_spt_page;
1460 u32 ppt_idx, cookie_ppt_idx;
1461
1462 spin_lock_bh(&dp->rx_desc_lock);
1463
1464 dp->rxbaddr = kcalloc(num_rx_spt_pages,
1465 sizeof(struct ath12k_rx_desc_info *), GFP_ATOMIC);
1466
1467 if (!dp->rxbaddr) {
1468 spin_unlock_bh(&dp->rx_desc_lock);
1469 return -ENOMEM;
1470 }
1471
1472 /* First ATH12K_NUM_RX_SPT_PAGES(ab) of allocated SPT pages are used for
1473 * RX
1474 */
1475 for (i = 0; i < num_rx_spt_pages; i++) {
1476 rx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*rx_descs),
1477 GFP_ATOMIC);
1478
1479 if (!rx_descs) {
1480 spin_unlock_bh(&dp->rx_desc_lock);
1481 return -ENOMEM;
1482 }
1483
1484 ppt_idx = ATH12K_RX_SPT_PAGE_OFFSET(ab) + i;
1485 cookie_ppt_idx = dp->rx_ppt_base + ppt_idx;
1486 dp->rxbaddr[i] = &rx_descs[0];
1487
1488 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) {
1489 rx_descs[j].cookie = ath12k_dp_cc_cookie_gen(cookie_ppt_idx, j);
1490 rx_descs[j].magic = ATH12K_DP_RX_DESC_MAGIC;
1491 rx_descs[j].device_id = ab->device_id;
1492 list_add_tail(&rx_descs[j].list, &dp->rx_desc_free_list);
1493
1494 /* Update descriptor VA in SPT */
1495 rx_desc_addr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j);
1496 *rx_desc_addr = &rx_descs[j];
1497 }
1498 }
1499
1500 spin_unlock_bh(&dp->rx_desc_lock);
1501
1502 dp->txbaddr = kcalloc(ATH12K_NUM_TX_SPT_PAGES(ab),
1503 sizeof(struct ath12k_tx_desc_info *), GFP_ATOMIC);
1504
1505 if (!dp->txbaddr)
1506 return -ENOMEM;
1507
1508 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) {
1509 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
1510 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL(ab); i++) {
1511 tx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*tx_descs),
1512 GFP_ATOMIC);
1513
1514 if (!tx_descs) {
1515 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1516 /* Caller takes care of TX pending and RX desc cleanup */
1517 return -ENOMEM;
1518 }
1519
1520 tx_spt_page = i + pool_id *
1521 ATH12K_TX_SPT_PAGES_PER_POOL(ab);
1522 ppt_idx = ATH12K_TX_SPT_PAGE_OFFSET + tx_spt_page;
1523
1524 dp->txbaddr[tx_spt_page] = &tx_descs[0];
1525
1526 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) {
1527 tx_descs[j].desc_id = ath12k_dp_cc_cookie_gen(ppt_idx, j);
1528 tx_descs[j].pool_id = pool_id;
1529 list_add_tail(&tx_descs[j].list,
1530 &dp->tx_desc_free_list[pool_id]);
1531
1532 /* Update descriptor VA in SPT */
1533 tx_desc_addr =
1534 ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j);
1535 *tx_desc_addr = &tx_descs[j];
1536 }
1537 }
1538 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
1539 }
1540 return 0;
1541 }
1542
ath12k_dp_cmem_init(struct ath12k_base * ab,struct ath12k_dp * dp,enum ath12k_dp_desc_type type)1543 static int ath12k_dp_cmem_init(struct ath12k_base *ab,
1544 struct ath12k_dp *dp,
1545 enum ath12k_dp_desc_type type)
1546 {
1547 u32 cmem_base;
1548 int i, start, end;
1549
1550 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1551
1552 switch (type) {
1553 case ATH12K_DP_TX_DESC:
1554 start = ATH12K_TX_SPT_PAGE_OFFSET;
1555 end = start + ATH12K_NUM_TX_SPT_PAGES(ab);
1556 break;
1557 case ATH12K_DP_RX_DESC:
1558 cmem_base += ATH12K_PPT_ADDR_OFFSET(dp->rx_ppt_base);
1559 start = ATH12K_RX_SPT_PAGE_OFFSET(ab);
1560 end = start + ATH12K_NUM_RX_SPT_PAGES(ab);
1561 break;
1562 default:
1563 ath12k_err(ab, "invalid descriptor type %d in cmem init\n", type);
1564 return -EINVAL;
1565 }
1566
1567 /* Write to PPT in CMEM */
1568 for (i = start; i < end; i++)
1569 ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i),
1570 dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET);
1571
1572 return 0;
1573 }
1574
ath12k_dp_partner_cc_init(struct ath12k_base * ab)1575 void ath12k_dp_partner_cc_init(struct ath12k_base *ab)
1576 {
1577 struct ath12k_hw_group *ag = ab->ag;
1578 int i;
1579
1580 for (i = 0; i < ag->num_devices; i++) {
1581 if (ag->ab[i] == ab)
1582 continue;
1583
1584 ath12k_dp_cmem_init(ab, &ag->ab[i]->dp, ATH12K_DP_RX_DESC);
1585 }
1586 }
1587
ath12k_dp_get_num_spt_pages(struct ath12k_base * ab)1588 static u32 ath12k_dp_get_num_spt_pages(struct ath12k_base *ab)
1589 {
1590 return ATH12K_NUM_RX_SPT_PAGES(ab) + ATH12K_NUM_TX_SPT_PAGES(ab);
1591 }
1592
ath12k_dp_cc_init(struct ath12k_base * ab)1593 static int ath12k_dp_cc_init(struct ath12k_base *ab)
1594 {
1595 struct ath12k_dp *dp = &ab->dp;
1596 int i, ret = 0;
1597
1598 INIT_LIST_HEAD(&dp->rx_desc_free_list);
1599 spin_lock_init(&dp->rx_desc_lock);
1600
1601 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) {
1602 INIT_LIST_HEAD(&dp->tx_desc_free_list[i]);
1603 INIT_LIST_HEAD(&dp->tx_desc_used_list[i]);
1604 spin_lock_init(&dp->tx_desc_lock[i]);
1605 }
1606
1607 dp->num_spt_pages = ath12k_dp_get_num_spt_pages(ab);
1608 if (dp->num_spt_pages > ATH12K_MAX_PPT_ENTRIES)
1609 dp->num_spt_pages = ATH12K_MAX_PPT_ENTRIES;
1610
1611 dp->spt_info = kcalloc(dp->num_spt_pages, sizeof(struct ath12k_spt_info),
1612 GFP_KERNEL);
1613
1614 if (!dp->spt_info) {
1615 ath12k_warn(ab, "SPT page allocation failure");
1616 return -ENOMEM;
1617 }
1618
1619 dp->rx_ppt_base = ab->device_id * ATH12K_NUM_RX_SPT_PAGES(ab);
1620
1621 for (i = 0; i < dp->num_spt_pages; i++) {
1622 dp->spt_info[i].vaddr = dma_alloc_coherent(ab->dev,
1623 ATH12K_PAGE_SIZE,
1624 &dp->spt_info[i].paddr,
1625 GFP_KERNEL);
1626
1627 if (!dp->spt_info[i].vaddr) {
1628 ret = -ENOMEM;
1629 goto free;
1630 }
1631
1632 if (dp->spt_info[i].paddr & ATH12K_SPT_4K_ALIGN_CHECK) {
1633 ath12k_warn(ab, "SPT allocated memory is not 4K aligned");
1634 ret = -EINVAL;
1635 goto free;
1636 }
1637 }
1638
1639 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_TX_DESC);
1640 if (ret) {
1641 ath12k_warn(ab, "HW CC Tx cmem init failed %d", ret);
1642 goto free;
1643 }
1644
1645 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_RX_DESC);
1646 if (ret) {
1647 ath12k_warn(ab, "HW CC Rx cmem init failed %d", ret);
1648 goto free;
1649 }
1650
1651 ret = ath12k_dp_cc_desc_init(ab);
1652 if (ret) {
1653 ath12k_warn(ab, "HW CC desc init failed %d", ret);
1654 goto free;
1655 }
1656
1657 return 0;
1658 free:
1659 ath12k_dp_cc_cleanup(ab);
1660 return ret;
1661 }
1662
ath12k_dp_alloc_reoq_lut(struct ath12k_base * ab,struct ath12k_reo_q_addr_lut * lut)1663 static int ath12k_dp_alloc_reoq_lut(struct ath12k_base *ab,
1664 struct ath12k_reo_q_addr_lut *lut)
1665 {
1666 lut->size = DP_REOQ_LUT_SIZE + HAL_REO_QLUT_ADDR_ALIGN - 1;
1667 lut->vaddr_unaligned = dma_alloc_coherent(ab->dev, lut->size,
1668 &lut->paddr_unaligned,
1669 GFP_KERNEL | __GFP_ZERO);
1670 if (!lut->vaddr_unaligned)
1671 return -ENOMEM;
1672
1673 lut->vaddr = PTR_ALIGN(lut->vaddr_unaligned, HAL_REO_QLUT_ADDR_ALIGN);
1674 lut->paddr = lut->paddr_unaligned +
1675 ((unsigned long)lut->vaddr - (unsigned long)lut->vaddr_unaligned);
1676 return 0;
1677 }
1678
ath12k_dp_reoq_lut_setup(struct ath12k_base * ab)1679 static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab)
1680 {
1681 struct ath12k_dp *dp = &ab->dp;
1682 u32 val;
1683 int ret;
1684
1685 if (!ab->hw_params->reoq_lut_support)
1686 return 0;
1687
1688 ret = ath12k_dp_alloc_reoq_lut(ab, &dp->reoq_lut);
1689 if (ret) {
1690 ath12k_warn(ab, "failed to allocate memory for reoq table");
1691 return ret;
1692 }
1693
1694 ret = ath12k_dp_alloc_reoq_lut(ab, &dp->ml_reoq_lut);
1695 if (ret) {
1696 ath12k_warn(ab, "failed to allocate memory for ML reoq table");
1697 dma_free_coherent(ab->dev, dp->reoq_lut.size,
1698 dp->reoq_lut.vaddr_unaligned,
1699 dp->reoq_lut.paddr_unaligned);
1700 dp->reoq_lut.vaddr_unaligned = NULL;
1701 return ret;
1702 }
1703
1704 /* Bits in the register have address [39:8] LUT base address to be
1705 * allocated such that LSBs are assumed to be zero. Also, current
1706 * design supports paddr up to 4 GB max hence it fits in 32 bit
1707 * register only
1708 */
1709
1710 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab),
1711 dp->reoq_lut.paddr >> 8);
1712
1713 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE1(ab),
1714 dp->ml_reoq_lut.paddr >> 8);
1715
1716 val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR(ab));
1717
1718 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR(ab),
1719 val | HAL_REO_QDESC_ADDR_READ_LUT_ENABLE);
1720
1721 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_MAX_PEERID(ab),
1722 HAL_REO_QDESC_MAX_PEERID);
1723
1724 return 0;
1725 }
1726
1727 static enum hal_rx_buf_return_buf_manager
ath12k_dp_get_idle_link_rbm(struct ath12k_base * ab)1728 ath12k_dp_get_idle_link_rbm(struct ath12k_base *ab)
1729 {
1730 switch (ab->device_id) {
1731 case 0:
1732 return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST;
1733 case 1:
1734 return HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST;
1735 case 2:
1736 return HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST;
1737 default:
1738 ath12k_warn(ab, "invalid %d device id, so choose default rbm\n",
1739 ab->device_id);
1740 WARN_ON(1);
1741 return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST;
1742 }
1743 }
1744
ath12k_dp_alloc(struct ath12k_base * ab)1745 int ath12k_dp_alloc(struct ath12k_base *ab)
1746 {
1747 struct ath12k_dp *dp = &ab->dp;
1748 struct hal_srng *srng = NULL;
1749 size_t size = 0;
1750 u32 n_link_desc = 0;
1751 int ret;
1752 int i;
1753
1754 dp->ab = ab;
1755
1756 INIT_LIST_HEAD(&dp->reo_cmd_list);
1757 INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list);
1758 INIT_LIST_HEAD(&dp->reo_cmd_update_rx_queue_list);
1759 spin_lock_init(&dp->reo_cmd_lock);
1760 spin_lock_init(&dp->reo_rxq_flush_lock);
1761
1762 dp->reo_cmd_cache_flush_count = 0;
1763 dp->idle_link_rbm = ath12k_dp_get_idle_link_rbm(ab);
1764
1765 ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc);
1766 if (ret) {
1767 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
1768 return ret;
1769 }
1770
1771 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id];
1772
1773 ret = ath12k_dp_link_desc_setup(ab, dp->link_desc_banks,
1774 HAL_WBM_IDLE_LINK, srng, n_link_desc);
1775 if (ret) {
1776 ath12k_warn(ab, "failed to setup link desc: %d\n", ret);
1777 return ret;
1778 }
1779
1780 ret = ath12k_dp_cc_init(ab);
1781
1782 if (ret) {
1783 ath12k_warn(ab, "failed to setup cookie converter %d\n", ret);
1784 goto fail_link_desc_cleanup;
1785 }
1786 ret = ath12k_dp_init_bank_profiles(ab);
1787 if (ret) {
1788 ath12k_warn(ab, "failed to setup bank profiles %d\n", ret);
1789 goto fail_hw_cc_cleanup;
1790 }
1791
1792 ret = ath12k_dp_srng_common_setup(ab);
1793 if (ret)
1794 goto fail_dp_bank_profiles_cleanup;
1795
1796 size = sizeof(struct hal_wbm_release_ring_tx) *
1797 DP_TX_COMP_RING_SIZE(ab);
1798
1799 ret = ath12k_dp_reoq_lut_setup(ab);
1800 if (ret) {
1801 ath12k_warn(ab, "failed to setup reoq table %d\n", ret);
1802 goto fail_cmn_srng_cleanup;
1803 }
1804
1805 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
1806 dp->tx_ring[i].tcl_data_ring_id = i;
1807
1808 dp->tx_ring[i].tx_status_head = 0;
1809 dp->tx_ring[i].tx_status_tail = DP_TX_COMP_RING_SIZE(ab) - 1;
1810 dp->tx_ring[i].tx_status = kmalloc(size, GFP_KERNEL);
1811 if (!dp->tx_ring[i].tx_status) {
1812 ret = -ENOMEM;
1813 /* FIXME: The allocated tx status is not freed
1814 * properly here
1815 */
1816 goto fail_cmn_reoq_cleanup;
1817 }
1818 }
1819
1820 for (i = 0; i < HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX; i++)
1821 ath12k_hal_tx_set_dscp_tid_map(ab, i);
1822
1823 ret = ath12k_dp_rx_alloc(ab);
1824 if (ret)
1825 goto fail_dp_rx_free;
1826
1827 /* Init any SOC level resource for DP */
1828
1829 return 0;
1830
1831 fail_dp_rx_free:
1832 ath12k_dp_rx_free(ab);
1833
1834 fail_cmn_reoq_cleanup:
1835 ath12k_dp_reoq_lut_cleanup(ab);
1836
1837 fail_cmn_srng_cleanup:
1838 ath12k_dp_srng_common_cleanup(ab);
1839
1840 fail_dp_bank_profiles_cleanup:
1841 ath12k_dp_deinit_bank_profiles(ab);
1842
1843 fail_hw_cc_cleanup:
1844 ath12k_dp_cc_cleanup(ab);
1845
1846 fail_link_desc_cleanup:
1847 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1848 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring);
1849
1850 return ret;
1851 }
1852