1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "dp_mon.h"
8 #include "debug.h"
9 #include "dp_rx.h"
10 #include "dp_tx.h"
11 #include "peer.h"
12
13 #define ATH12K_LE32_DEC_ENC(value, dec_bits, enc_bits) \
14 u32_encode_bits(le32_get_bits(value, dec_bits), enc_bits)
15
16 #define ATH12K_LE64_DEC_ENC(value, dec_bits, enc_bits) \
17 u32_encode_bits(le64_get_bits(value, dec_bits), enc_bits)
18
19 static void
ath12k_dp_mon_rx_handle_ofdma_info(const struct hal_rx_ppdu_end_user_stats * ppdu_end_user,struct hal_rx_user_status * rx_user_status)20 ath12k_dp_mon_rx_handle_ofdma_info(const struct hal_rx_ppdu_end_user_stats *ppdu_end_user,
21 struct hal_rx_user_status *rx_user_status)
22 {
23 rx_user_status->ul_ofdma_user_v0_word0 =
24 __le32_to_cpu(ppdu_end_user->usr_resp_ref);
25 rx_user_status->ul_ofdma_user_v0_word1 =
26 __le32_to_cpu(ppdu_end_user->usr_resp_ref_ext);
27 }
28
29 static void
ath12k_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats * stats,void * ppduinfo,struct hal_rx_user_status * rx_user_status)30 ath12k_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats *stats,
31 void *ppduinfo,
32 struct hal_rx_user_status *rx_user_status)
33 {
34 rx_user_status->mpdu_ok_byte_count =
35 le32_get_bits(stats->info7,
36 HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT);
37 rx_user_status->mpdu_err_byte_count =
38 le32_get_bits(stats->info8,
39 HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT);
40 }
41
42 static void
ath12k_dp_mon_rx_populate_mu_user_info(const struct hal_rx_ppdu_end_user_stats * rx_tlv,struct hal_rx_mon_ppdu_info * ppdu_info,struct hal_rx_user_status * rx_user_status)43 ath12k_dp_mon_rx_populate_mu_user_info(const struct hal_rx_ppdu_end_user_stats *rx_tlv,
44 struct hal_rx_mon_ppdu_info *ppdu_info,
45 struct hal_rx_user_status *rx_user_status)
46 {
47 rx_user_status->ast_index = ppdu_info->ast_index;
48 rx_user_status->tid = ppdu_info->tid;
49 rx_user_status->tcp_ack_msdu_count =
50 ppdu_info->tcp_ack_msdu_count;
51 rx_user_status->tcp_msdu_count =
52 ppdu_info->tcp_msdu_count;
53 rx_user_status->udp_msdu_count =
54 ppdu_info->udp_msdu_count;
55 rx_user_status->other_msdu_count =
56 ppdu_info->other_msdu_count;
57 rx_user_status->frame_control = ppdu_info->frame_control;
58 rx_user_status->frame_control_info_valid =
59 ppdu_info->frame_control_info_valid;
60 rx_user_status->data_sequence_control_info_valid =
61 ppdu_info->data_sequence_control_info_valid;
62 rx_user_status->first_data_seq_ctrl =
63 ppdu_info->first_data_seq_ctrl;
64 rx_user_status->preamble_type = ppdu_info->preamble_type;
65 rx_user_status->ht_flags = ppdu_info->ht_flags;
66 rx_user_status->vht_flags = ppdu_info->vht_flags;
67 rx_user_status->he_flags = ppdu_info->he_flags;
68 rx_user_status->rs_flags = ppdu_info->rs_flags;
69
70 rx_user_status->mpdu_cnt_fcs_ok =
71 ppdu_info->num_mpdu_fcs_ok;
72 rx_user_status->mpdu_cnt_fcs_err =
73 ppdu_info->num_mpdu_fcs_err;
74 memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0],
75 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
76 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
77
78 ath12k_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status);
79 }
80
ath12k_dp_mon_parse_vht_sig_a(const struct hal_rx_vht_sig_a_info * vht_sig,struct hal_rx_mon_ppdu_info * ppdu_info)81 static void ath12k_dp_mon_parse_vht_sig_a(const struct hal_rx_vht_sig_a_info *vht_sig,
82 struct hal_rx_mon_ppdu_info *ppdu_info)
83 {
84 u32 nsts, info0, info1;
85 u8 gi_setting;
86
87 info0 = __le32_to_cpu(vht_sig->info0);
88 info1 = __le32_to_cpu(vht_sig->info1);
89
90 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
91 ppdu_info->mcs = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_MCS);
92 gi_setting = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING);
93 switch (gi_setting) {
94 case HAL_RX_VHT_SIG_A_NORMAL_GI:
95 ppdu_info->gi = HAL_RX_GI_0_8_US;
96 break;
97 case HAL_RX_VHT_SIG_A_SHORT_GI:
98 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY:
99 ppdu_info->gi = HAL_RX_GI_0_4_US;
100 break;
101 }
102
103 ppdu_info->is_stbc = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_STBC);
104 nsts = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS);
105 if (ppdu_info->is_stbc && nsts > 0)
106 nsts = ((nsts + 1) >> 1) - 1;
107
108 ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK);
109 ppdu_info->bw = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_BW);
110 ppdu_info->beamformed = u32_get_bits(info1,
111 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED);
112 ppdu_info->vht_flag_values5 = u32_get_bits(info0,
113 HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID);
114 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) |
115 ppdu_info->nss);
116 ppdu_info->vht_flag_values2 = ppdu_info->bw;
117 ppdu_info->vht_flag_values4 =
118 u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
119 }
120
ath12k_dp_mon_parse_ht_sig(const struct hal_rx_ht_sig_info * ht_sig,struct hal_rx_mon_ppdu_info * ppdu_info)121 static void ath12k_dp_mon_parse_ht_sig(const struct hal_rx_ht_sig_info *ht_sig,
122 struct hal_rx_mon_ppdu_info *ppdu_info)
123 {
124 u32 info0 = __le32_to_cpu(ht_sig->info0);
125 u32 info1 = __le32_to_cpu(ht_sig->info1);
126
127 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_MCS);
128 ppdu_info->bw = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_BW);
129 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_STBC);
130 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING);
131 ppdu_info->gi = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_GI);
132 ppdu_info->nss = (ppdu_info->mcs >> 3);
133 }
134
ath12k_dp_mon_parse_l_sig_b(const struct hal_rx_lsig_b_info * lsigb,struct hal_rx_mon_ppdu_info * ppdu_info)135 static void ath12k_dp_mon_parse_l_sig_b(const struct hal_rx_lsig_b_info *lsigb,
136 struct hal_rx_mon_ppdu_info *ppdu_info)
137 {
138 u32 info0 = __le32_to_cpu(lsigb->info0);
139 u8 rate;
140
141 rate = u32_get_bits(info0, HAL_RX_LSIG_B_INFO_INFO0_RATE);
142 switch (rate) {
143 case 1:
144 rate = HAL_RX_LEGACY_RATE_1_MBPS;
145 break;
146 case 2:
147 case 5:
148 rate = HAL_RX_LEGACY_RATE_2_MBPS;
149 break;
150 case 3:
151 case 6:
152 rate = HAL_RX_LEGACY_RATE_5_5_MBPS;
153 break;
154 case 4:
155 case 7:
156 rate = HAL_RX_LEGACY_RATE_11_MBPS;
157 break;
158 default:
159 rate = HAL_RX_LEGACY_RATE_INVALID;
160 }
161
162 ppdu_info->rate = rate;
163 ppdu_info->cck_flag = 1;
164 }
165
ath12k_dp_mon_parse_l_sig_a(const struct hal_rx_lsig_a_info * lsiga,struct hal_rx_mon_ppdu_info * ppdu_info)166 static void ath12k_dp_mon_parse_l_sig_a(const struct hal_rx_lsig_a_info *lsiga,
167 struct hal_rx_mon_ppdu_info *ppdu_info)
168 {
169 u32 info0 = __le32_to_cpu(lsiga->info0);
170 u8 rate;
171
172 rate = u32_get_bits(info0, HAL_RX_LSIG_A_INFO_INFO0_RATE);
173 switch (rate) {
174 case 8:
175 rate = HAL_RX_LEGACY_RATE_48_MBPS;
176 break;
177 case 9:
178 rate = HAL_RX_LEGACY_RATE_24_MBPS;
179 break;
180 case 10:
181 rate = HAL_RX_LEGACY_RATE_12_MBPS;
182 break;
183 case 11:
184 rate = HAL_RX_LEGACY_RATE_6_MBPS;
185 break;
186 case 12:
187 rate = HAL_RX_LEGACY_RATE_54_MBPS;
188 break;
189 case 13:
190 rate = HAL_RX_LEGACY_RATE_36_MBPS;
191 break;
192 case 14:
193 rate = HAL_RX_LEGACY_RATE_18_MBPS;
194 break;
195 case 15:
196 rate = HAL_RX_LEGACY_RATE_9_MBPS;
197 break;
198 default:
199 rate = HAL_RX_LEGACY_RATE_INVALID;
200 }
201
202 ppdu_info->rate = rate;
203 }
204
205 static void
ath12k_dp_mon_parse_he_sig_b2_ofdma(const struct hal_rx_he_sig_b2_ofdma_info * ofdma,struct hal_rx_mon_ppdu_info * ppdu_info)206 ath12k_dp_mon_parse_he_sig_b2_ofdma(const struct hal_rx_he_sig_b2_ofdma_info *ofdma,
207 struct hal_rx_mon_ppdu_info *ppdu_info)
208 {
209 u32 info0, value;
210
211 info0 = __le32_to_cpu(ofdma->info0);
212
213 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_DCM_KNOWN | HE_CODING_KNOWN;
214
215 /* HE-data2 */
216 ppdu_info->he_data2 |= HE_TXBF_KNOWN;
217
218 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS);
219 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
220 ppdu_info->he_data3 |= value;
221
222 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM);
223 value = value << HE_DCM_SHIFT;
224 ppdu_info->he_data3 |= value;
225
226 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING);
227 ppdu_info->ldpc = value;
228 value = value << HE_CODING_SHIFT;
229 ppdu_info->he_data3 |= value;
230
231 /* HE-data4 */
232 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID);
233 value = value << HE_STA_ID_SHIFT;
234 ppdu_info->he_data4 |= value;
235
236 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS);
237 ppdu_info->beamformed = u32_get_bits(info0,
238 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF);
239 }
240
241 static void
ath12k_dp_mon_parse_he_sig_b2_mu(const struct hal_rx_he_sig_b2_mu_info * he_sig_b2_mu,struct hal_rx_mon_ppdu_info * ppdu_info)242 ath12k_dp_mon_parse_he_sig_b2_mu(const struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu,
243 struct hal_rx_mon_ppdu_info *ppdu_info)
244 {
245 u32 info0, value;
246
247 info0 = __le32_to_cpu(he_sig_b2_mu->info0);
248
249 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_CODING_KNOWN;
250
251 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS);
252 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
253 ppdu_info->he_data3 |= value;
254
255 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING);
256 ppdu_info->ldpc = value;
257 value = value << HE_CODING_SHIFT;
258 ppdu_info->he_data3 |= value;
259
260 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID);
261 value = value << HE_STA_ID_SHIFT;
262 ppdu_info->he_data4 |= value;
263
264 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS);
265 }
266
267 static void
ath12k_dp_mon_parse_he_sig_b1_mu(const struct hal_rx_he_sig_b1_mu_info * he_sig_b1_mu,struct hal_rx_mon_ppdu_info * ppdu_info)268 ath12k_dp_mon_parse_he_sig_b1_mu(const struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu,
269 struct hal_rx_mon_ppdu_info *ppdu_info)
270 {
271 u32 info0 = __le32_to_cpu(he_sig_b1_mu->info0);
272 u16 ru_tones;
273
274 ru_tones = u32_get_bits(info0,
275 HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION);
276 ppdu_info->ru_alloc = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
277 ppdu_info->he_RU[0] = ru_tones;
278 }
279
280 static void
ath12k_dp_mon_parse_he_sig_mu(const struct hal_rx_he_sig_a_mu_dl_info * he_sig_a_mu_dl,struct hal_rx_mon_ppdu_info * ppdu_info)281 ath12k_dp_mon_parse_he_sig_mu(const struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl,
282 struct hal_rx_mon_ppdu_info *ppdu_info)
283 {
284 u32 info0, info1, value;
285 u16 he_gi = 0, he_ltf = 0;
286
287 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0);
288 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1);
289
290 ppdu_info->he_mu_flags = 1;
291
292 ppdu_info->he_data1 = HE_MU_FORMAT_TYPE;
293 ppdu_info->he_data1 |=
294 HE_BSS_COLOR_KNOWN |
295 HE_DL_UL_KNOWN |
296 HE_LDPC_EXTRA_SYMBOL_KNOWN |
297 HE_STBC_KNOWN |
298 HE_DATA_BW_RU_KNOWN |
299 HE_DOPPLER_KNOWN;
300
301 ppdu_info->he_data2 =
302 HE_GI_KNOWN |
303 HE_LTF_SYMBOLS_KNOWN |
304 HE_PRE_FEC_PADDING_KNOWN |
305 HE_PE_DISAMBIGUITY_KNOWN |
306 HE_TXOP_KNOWN |
307 HE_MIDABLE_PERIODICITY_KNOWN;
308
309 /* data3 */
310 ppdu_info->he_data3 = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR);
311 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG);
312 value = value << HE_DL_UL_SHIFT;
313 ppdu_info->he_data3 |= value;
314
315 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA);
316 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
317 ppdu_info->he_data3 |= value;
318
319 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC);
320 value = value << HE_STBC_SHIFT;
321 ppdu_info->he_data3 |= value;
322
323 /* data4 */
324 ppdu_info->he_data4 = u32_get_bits(info0,
325 HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE);
326 ppdu_info->he_data4 = value;
327
328 /* data5 */
329 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
330 ppdu_info->he_data5 = value;
331 ppdu_info->bw = value;
332
333 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE);
334 switch (value) {
335 case 0:
336 he_gi = HE_GI_0_8;
337 he_ltf = HE_LTF_4_X;
338 break;
339 case 1:
340 he_gi = HE_GI_0_8;
341 he_ltf = HE_LTF_2_X;
342 break;
343 case 2:
344 he_gi = HE_GI_1_6;
345 he_ltf = HE_LTF_2_X;
346 break;
347 case 3:
348 he_gi = HE_GI_3_2;
349 he_ltf = HE_LTF_4_X;
350 break;
351 }
352
353 ppdu_info->gi = he_gi;
354 value = he_gi << HE_GI_SHIFT;
355 ppdu_info->he_data5 |= value;
356
357 value = he_ltf << HE_LTF_SIZE_SHIFT;
358 ppdu_info->he_data5 |= value;
359
360 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB);
361 value = (value << HE_LTF_SYM_SHIFT);
362 ppdu_info->he_data5 |= value;
363
364 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR);
365 value = value << HE_PRE_FEC_PAD_SHIFT;
366 ppdu_info->he_data5 |= value;
367
368 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM);
369 value = value << HE_PE_DISAMBIGUITY_SHIFT;
370 ppdu_info->he_data5 |= value;
371
372 /*data6*/
373 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION);
374 value = value << HE_DOPPLER_SHIFT;
375 ppdu_info->he_data6 |= value;
376
377 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION);
378 value = value << HE_TXOP_SHIFT;
379 ppdu_info->he_data6 |= value;
380
381 /* HE-MU Flags */
382 /* HE-MU-flags1 */
383 ppdu_info->he_flags1 =
384 HE_SIG_B_MCS_KNOWN |
385 HE_SIG_B_DCM_KNOWN |
386 HE_SIG_B_COMPRESSION_FLAG_1_KNOWN |
387 HE_SIG_B_SYM_NUM_KNOWN |
388 HE_RU_0_KNOWN;
389
390 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB);
391 ppdu_info->he_flags1 |= value;
392 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB);
393 value = value << HE_DCM_FLAG_1_SHIFT;
394 ppdu_info->he_flags1 |= value;
395
396 /* HE-MU-flags2 */
397 ppdu_info->he_flags2 = HE_BW_KNOWN;
398
399 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
400 ppdu_info->he_flags2 |= value;
401 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB);
402 value = value << HE_SIG_B_COMPRESSION_FLAG_2_SHIFT;
403 ppdu_info->he_flags2 |= value;
404 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB);
405 value = value - 1;
406 value = value << HE_NUM_SIG_B_SYMBOLS_SHIFT;
407 ppdu_info->he_flags2 |= value;
408
409 ppdu_info->is_stbc = info1 &
410 HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC;
411 }
412
ath12k_dp_mon_parse_he_sig_su(const struct hal_rx_he_sig_a_su_info * he_sig_a,struct hal_rx_mon_ppdu_info * ppdu_info)413 static void ath12k_dp_mon_parse_he_sig_su(const struct hal_rx_he_sig_a_su_info *he_sig_a,
414 struct hal_rx_mon_ppdu_info *ppdu_info)
415 {
416 u32 info0, info1, value;
417 u32 dcm;
418 u8 he_dcm = 0, he_stbc = 0;
419 u16 he_gi = 0, he_ltf = 0;
420
421 ppdu_info->he_flags = 1;
422
423 info0 = __le32_to_cpu(he_sig_a->info0);
424 info1 = __le32_to_cpu(he_sig_a->info1);
425
426 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND);
427 if (value == 0)
428 ppdu_info->he_data1 = HE_TRIG_FORMAT_TYPE;
429 else
430 ppdu_info->he_data1 = HE_SU_FORMAT_TYPE;
431
432 ppdu_info->he_data1 |=
433 HE_BSS_COLOR_KNOWN |
434 HE_BEAM_CHANGE_KNOWN |
435 HE_DL_UL_KNOWN |
436 HE_MCS_KNOWN |
437 HE_DCM_KNOWN |
438 HE_CODING_KNOWN |
439 HE_LDPC_EXTRA_SYMBOL_KNOWN |
440 HE_STBC_KNOWN |
441 HE_DATA_BW_RU_KNOWN |
442 HE_DOPPLER_KNOWN;
443
444 ppdu_info->he_data2 |=
445 HE_GI_KNOWN |
446 HE_TXBF_KNOWN |
447 HE_PE_DISAMBIGUITY_KNOWN |
448 HE_TXOP_KNOWN |
449 HE_LTF_SYMBOLS_KNOWN |
450 HE_PRE_FEC_PADDING_KNOWN |
451 HE_MIDABLE_PERIODICITY_KNOWN;
452
453 ppdu_info->he_data3 = u32_get_bits(info0,
454 HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR);
455 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE);
456 value = value << HE_BEAM_CHANGE_SHIFT;
457 ppdu_info->he_data3 |= value;
458 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG);
459 value = value << HE_DL_UL_SHIFT;
460 ppdu_info->he_data3 |= value;
461
462 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
463 ppdu_info->mcs = value;
464 value = value << HE_TRANSMIT_MCS_SHIFT;
465 ppdu_info->he_data3 |= value;
466
467 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
468 he_dcm = value;
469 value = value << HE_DCM_SHIFT;
470 ppdu_info->he_data3 |= value;
471 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
472 value = value << HE_CODING_SHIFT;
473 ppdu_info->he_data3 |= value;
474 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA);
475 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
476 ppdu_info->he_data3 |= value;
477 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
478 he_stbc = value;
479 value = value << HE_STBC_SHIFT;
480 ppdu_info->he_data3 |= value;
481
482 /* data4 */
483 ppdu_info->he_data4 = u32_get_bits(info0,
484 HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE);
485
486 /* data5 */
487 value = u32_get_bits(info0,
488 HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
489 ppdu_info->he_data5 = value;
490 ppdu_info->bw = value;
491 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE);
492 switch (value) {
493 case 0:
494 he_gi = HE_GI_0_8;
495 he_ltf = HE_LTF_1_X;
496 break;
497 case 1:
498 he_gi = HE_GI_0_8;
499 he_ltf = HE_LTF_2_X;
500 break;
501 case 2:
502 he_gi = HE_GI_1_6;
503 he_ltf = HE_LTF_2_X;
504 break;
505 case 3:
506 if (he_dcm && he_stbc) {
507 he_gi = HE_GI_0_8;
508 he_ltf = HE_LTF_4_X;
509 } else {
510 he_gi = HE_GI_3_2;
511 he_ltf = HE_LTF_4_X;
512 }
513 break;
514 }
515 ppdu_info->gi = he_gi;
516 value = he_gi << HE_GI_SHIFT;
517 ppdu_info->he_data5 |= value;
518 value = he_ltf << HE_LTF_SIZE_SHIFT;
519 ppdu_info->ltf_size = he_ltf;
520 ppdu_info->he_data5 |= value;
521
522 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
523 value = (value << HE_LTF_SYM_SHIFT);
524 ppdu_info->he_data5 |= value;
525
526 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR);
527 value = value << HE_PRE_FEC_PAD_SHIFT;
528 ppdu_info->he_data5 |= value;
529
530 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
531 value = value << HE_TXBF_SHIFT;
532 ppdu_info->he_data5 |= value;
533 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM);
534 value = value << HE_PE_DISAMBIGUITY_SHIFT;
535 ppdu_info->he_data5 |= value;
536
537 /* data6 */
538 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
539 value++;
540 ppdu_info->he_data6 = value;
541 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND);
542 value = value << HE_DOPPLER_SHIFT;
543 ppdu_info->he_data6 |= value;
544 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION);
545 value = value << HE_TXOP_SHIFT;
546 ppdu_info->he_data6 |= value;
547
548 ppdu_info->mcs =
549 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
550 ppdu_info->bw =
551 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
552 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
553 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
554 ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
555 dcm = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
556 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
557 ppdu_info->dcm = dcm;
558 }
559
560 static void
ath12k_dp_mon_hal_rx_parse_u_sig_cmn(const struct hal_mon_usig_cmn * cmn,struct hal_rx_mon_ppdu_info * ppdu_info)561 ath12k_dp_mon_hal_rx_parse_u_sig_cmn(const struct hal_mon_usig_cmn *cmn,
562 struct hal_rx_mon_ppdu_info *ppdu_info)
563 {
564 u32 common;
565
566 ppdu_info->u_sig_info.bw = le32_get_bits(cmn->info0,
567 HAL_RX_USIG_CMN_INFO0_BW);
568 ppdu_info->u_sig_info.ul_dl = le32_get_bits(cmn->info0,
569 HAL_RX_USIG_CMN_INFO0_UL_DL);
570
571 common = __le32_to_cpu(ppdu_info->u_sig_info.usig.common);
572 common |= IEEE80211_RADIOTAP_EHT_USIG_COMMON_PHY_VER_KNOWN |
573 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN |
574 IEEE80211_RADIOTAP_EHT_USIG_COMMON_UL_DL_KNOWN |
575 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BSS_COLOR_KNOWN |
576 IEEE80211_RADIOTAP_EHT_USIG_COMMON_TXOP_KNOWN |
577 ATH12K_LE32_DEC_ENC(cmn->info0,
578 HAL_RX_USIG_CMN_INFO0_PHY_VERSION,
579 IEEE80211_RADIOTAP_EHT_USIG_COMMON_PHY_VER) |
580 u32_encode_bits(ppdu_info->u_sig_info.bw,
581 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW) |
582 u32_encode_bits(ppdu_info->u_sig_info.ul_dl,
583 IEEE80211_RADIOTAP_EHT_USIG_COMMON_UL_DL) |
584 ATH12K_LE32_DEC_ENC(cmn->info0,
585 HAL_RX_USIG_CMN_INFO0_BSS_COLOR,
586 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BSS_COLOR) |
587 ATH12K_LE32_DEC_ENC(cmn->info0,
588 HAL_RX_USIG_CMN_INFO0_TXOP,
589 IEEE80211_RADIOTAP_EHT_USIG_COMMON_TXOP);
590 ppdu_info->u_sig_info.usig.common = cpu_to_le32(common);
591
592 switch (ppdu_info->u_sig_info.bw) {
593 default:
594 fallthrough;
595 case HAL_EHT_BW_20:
596 ppdu_info->bw = HAL_RX_BW_20MHZ;
597 break;
598 case HAL_EHT_BW_40:
599 ppdu_info->bw = HAL_RX_BW_40MHZ;
600 break;
601 case HAL_EHT_BW_80:
602 ppdu_info->bw = HAL_RX_BW_80MHZ;
603 break;
604 case HAL_EHT_BW_160:
605 ppdu_info->bw = HAL_RX_BW_160MHZ;
606 break;
607 case HAL_EHT_BW_320_1:
608 case HAL_EHT_BW_320_2:
609 ppdu_info->bw = HAL_RX_BW_320MHZ;
610 break;
611 }
612 }
613
614 static void
ath12k_dp_mon_hal_rx_parse_u_sig_tb(const struct hal_mon_usig_tb * usig_tb,struct hal_rx_mon_ppdu_info * ppdu_info)615 ath12k_dp_mon_hal_rx_parse_u_sig_tb(const struct hal_mon_usig_tb *usig_tb,
616 struct hal_rx_mon_ppdu_info *ppdu_info)
617 {
618 struct ieee80211_radiotap_eht_usig *usig = &ppdu_info->u_sig_info.usig;
619 enum ieee80211_radiotap_eht_usig_tb spatial_reuse1, spatial_reuse2;
620 u32 common, value, mask;
621
622 spatial_reuse1 = IEEE80211_RADIOTAP_EHT_USIG2_TB_B3_B6_SPATIAL_REUSE_1;
623 spatial_reuse2 = IEEE80211_RADIOTAP_EHT_USIG2_TB_B7_B10_SPATIAL_REUSE_2;
624
625 common = __le32_to_cpu(usig->common);
626 value = __le32_to_cpu(usig->value);
627 mask = __le32_to_cpu(usig->mask);
628
629 ppdu_info->u_sig_info.ppdu_type_comp_mode =
630 le32_get_bits(usig_tb->info0,
631 HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE);
632
633 common |= ATH12K_LE32_DEC_ENC(usig_tb->info0,
634 HAL_RX_USIG_TB_INFO0_RX_INTEG_CHECK_PASS,
635 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BAD_USIG_CRC);
636
637 value |= IEEE80211_RADIOTAP_EHT_USIG1_TB_B20_B25_DISREGARD |
638 u32_encode_bits(ppdu_info->u_sig_info.ppdu_type_comp_mode,
639 IEEE80211_RADIOTAP_EHT_USIG2_TB_B0_B1_PPDU_TYPE) |
640 IEEE80211_RADIOTAP_EHT_USIG2_TB_B2_VALIDATE |
641 ATH12K_LE32_DEC_ENC(usig_tb->info0,
642 HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_1,
643 spatial_reuse1) |
644 ATH12K_LE32_DEC_ENC(usig_tb->info0,
645 HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_2,
646 spatial_reuse2) |
647 IEEE80211_RADIOTAP_EHT_USIG2_TB_B11_B15_DISREGARD |
648 ATH12K_LE32_DEC_ENC(usig_tb->info0,
649 HAL_RX_USIG_TB_INFO0_CRC,
650 IEEE80211_RADIOTAP_EHT_USIG2_TB_B16_B19_CRC) |
651 ATH12K_LE32_DEC_ENC(usig_tb->info0,
652 HAL_RX_USIG_TB_INFO0_TAIL,
653 IEEE80211_RADIOTAP_EHT_USIG2_TB_B20_B25_TAIL);
654
655 mask |= IEEE80211_RADIOTAP_EHT_USIG1_TB_B20_B25_DISREGARD |
656 IEEE80211_RADIOTAP_EHT_USIG2_TB_B0_B1_PPDU_TYPE |
657 IEEE80211_RADIOTAP_EHT_USIG2_TB_B2_VALIDATE |
658 spatial_reuse1 | spatial_reuse2 |
659 IEEE80211_RADIOTAP_EHT_USIG2_TB_B11_B15_DISREGARD |
660 IEEE80211_RADIOTAP_EHT_USIG2_TB_B16_B19_CRC |
661 IEEE80211_RADIOTAP_EHT_USIG2_TB_B20_B25_TAIL;
662
663 usig->common = cpu_to_le32(common);
664 usig->value = cpu_to_le32(value);
665 usig->mask = cpu_to_le32(mask);
666 }
667
668 static void
ath12k_dp_mon_hal_rx_parse_u_sig_mu(const struct hal_mon_usig_mu * usig_mu,struct hal_rx_mon_ppdu_info * ppdu_info)669 ath12k_dp_mon_hal_rx_parse_u_sig_mu(const struct hal_mon_usig_mu *usig_mu,
670 struct hal_rx_mon_ppdu_info *ppdu_info)
671 {
672 struct ieee80211_radiotap_eht_usig *usig = &ppdu_info->u_sig_info.usig;
673 enum ieee80211_radiotap_eht_usig_mu sig_symb, punc;
674 u32 common, value, mask;
675
676 sig_symb = IEEE80211_RADIOTAP_EHT_USIG2_MU_B11_B15_EHT_SIG_SYMBOLS;
677 punc = IEEE80211_RADIOTAP_EHT_USIG2_MU_B3_B7_PUNCTURED_INFO;
678
679 common = __le32_to_cpu(usig->common);
680 value = __le32_to_cpu(usig->value);
681 mask = __le32_to_cpu(usig->mask);
682
683 ppdu_info->u_sig_info.ppdu_type_comp_mode =
684 le32_get_bits(usig_mu->info0,
685 HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE);
686 ppdu_info->u_sig_info.eht_sig_mcs =
687 le32_get_bits(usig_mu->info0,
688 HAL_RX_USIG_MU_INFO0_EHT_SIG_MCS);
689 ppdu_info->u_sig_info.num_eht_sig_sym =
690 le32_get_bits(usig_mu->info0,
691 HAL_RX_USIG_MU_INFO0_NUM_EHT_SIG_SYM);
692
693 common |= ATH12K_LE32_DEC_ENC(usig_mu->info0,
694 HAL_RX_USIG_MU_INFO0_RX_INTEG_CHECK_PASS,
695 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BAD_USIG_CRC);
696
697 value |= IEEE80211_RADIOTAP_EHT_USIG1_MU_B20_B24_DISREGARD |
698 IEEE80211_RADIOTAP_EHT_USIG1_MU_B25_VALIDATE |
699 u32_encode_bits(ppdu_info->u_sig_info.ppdu_type_comp_mode,
700 IEEE80211_RADIOTAP_EHT_USIG2_MU_B0_B1_PPDU_TYPE) |
701 IEEE80211_RADIOTAP_EHT_USIG2_MU_B2_VALIDATE |
702 ATH12K_LE32_DEC_ENC(usig_mu->info0,
703 HAL_RX_USIG_MU_INFO0_PUNC_CH_INFO,
704 punc) |
705 IEEE80211_RADIOTAP_EHT_USIG2_MU_B8_VALIDATE |
706 u32_encode_bits(ppdu_info->u_sig_info.eht_sig_mcs,
707 IEEE80211_RADIOTAP_EHT_USIG2_MU_B9_B10_SIG_MCS) |
708 u32_encode_bits(ppdu_info->u_sig_info.num_eht_sig_sym,
709 sig_symb) |
710 ATH12K_LE32_DEC_ENC(usig_mu->info0,
711 HAL_RX_USIG_MU_INFO0_CRC,
712 IEEE80211_RADIOTAP_EHT_USIG2_MU_B16_B19_CRC) |
713 ATH12K_LE32_DEC_ENC(usig_mu->info0,
714 HAL_RX_USIG_MU_INFO0_TAIL,
715 IEEE80211_RADIOTAP_EHT_USIG2_MU_B20_B25_TAIL);
716
717 mask |= IEEE80211_RADIOTAP_EHT_USIG1_MU_B20_B24_DISREGARD |
718 IEEE80211_RADIOTAP_EHT_USIG1_MU_B25_VALIDATE |
719 IEEE80211_RADIOTAP_EHT_USIG2_MU_B0_B1_PPDU_TYPE |
720 IEEE80211_RADIOTAP_EHT_USIG2_MU_B2_VALIDATE |
721 punc |
722 IEEE80211_RADIOTAP_EHT_USIG2_MU_B8_VALIDATE |
723 IEEE80211_RADIOTAP_EHT_USIG2_MU_B9_B10_SIG_MCS |
724 sig_symb |
725 IEEE80211_RADIOTAP_EHT_USIG2_MU_B16_B19_CRC |
726 IEEE80211_RADIOTAP_EHT_USIG2_MU_B20_B25_TAIL;
727
728 usig->common = cpu_to_le32(common);
729 usig->value = cpu_to_le32(value);
730 usig->mask = cpu_to_le32(mask);
731 }
732
733 static void
ath12k_dp_mon_hal_rx_parse_u_sig_hdr(const struct hal_mon_usig_hdr * usig,struct hal_rx_mon_ppdu_info * ppdu_info)734 ath12k_dp_mon_hal_rx_parse_u_sig_hdr(const struct hal_mon_usig_hdr *usig,
735 struct hal_rx_mon_ppdu_info *ppdu_info)
736 {
737 u8 comp_mode;
738
739 ppdu_info->eht_usig = true;
740
741 ath12k_dp_mon_hal_rx_parse_u_sig_cmn(&usig->cmn, ppdu_info);
742
743 comp_mode = le32_get_bits(usig->non_cmn.mu.info0,
744 HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE);
745
746 if (comp_mode == 0 && ppdu_info->u_sig_info.ul_dl)
747 ath12k_dp_mon_hal_rx_parse_u_sig_tb(&usig->non_cmn.tb, ppdu_info);
748 else
749 ath12k_dp_mon_hal_rx_parse_u_sig_mu(&usig->non_cmn.mu, ppdu_info);
750 }
751
752 static void
ath12k_dp_mon_hal_aggr_tlv(struct hal_rx_mon_ppdu_info * ppdu_info,u16 tlv_len,const void * tlv_data)753 ath12k_dp_mon_hal_aggr_tlv(struct hal_rx_mon_ppdu_info *ppdu_info,
754 u16 tlv_len, const void *tlv_data)
755 {
756 if (tlv_len <= HAL_RX_MON_MAX_AGGR_SIZE - ppdu_info->tlv_aggr.cur_len) {
757 memcpy(ppdu_info->tlv_aggr.buf + ppdu_info->tlv_aggr.cur_len,
758 tlv_data, tlv_len);
759 ppdu_info->tlv_aggr.cur_len += tlv_len;
760 }
761 }
762
763 static inline bool
ath12k_dp_mon_hal_rx_is_frame_type_ndp(const struct hal_rx_u_sig_info * usig_info)764 ath12k_dp_mon_hal_rx_is_frame_type_ndp(const struct hal_rx_u_sig_info *usig_info)
765 {
766 if (usig_info->ppdu_type_comp_mode == 1 &&
767 usig_info->eht_sig_mcs == 0 &&
768 usig_info->num_eht_sig_sym == 0)
769 return true;
770
771 return false;
772 }
773
774 static inline bool
ath12k_dp_mon_hal_rx_is_non_ofdma(const struct hal_rx_u_sig_info * usig_info)775 ath12k_dp_mon_hal_rx_is_non_ofdma(const struct hal_rx_u_sig_info *usig_info)
776 {
777 u32 ppdu_type_comp_mode = usig_info->ppdu_type_comp_mode;
778 u32 ul_dl = usig_info->ul_dl;
779
780 if ((ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_MIMO && ul_dl == 0) ||
781 (ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_OFDMA && ul_dl == 0) ||
782 (ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_MIMO && ul_dl == 1))
783 return true;
784
785 return false;
786 }
787
788 static inline bool
ath12k_dp_mon_hal_rx_is_ofdma(const struct hal_rx_u_sig_info * usig_info)789 ath12k_dp_mon_hal_rx_is_ofdma(const struct hal_rx_u_sig_info *usig_info)
790 {
791 if (usig_info->ppdu_type_comp_mode == 0 && usig_info->ul_dl == 0)
792 return true;
793
794 return false;
795 }
796
797 static void
ath12k_dp_mon_hal_rx_parse_eht_sig_ndp(const struct hal_eht_sig_ndp_cmn_eb * eht_sig_ndp,struct hal_rx_mon_ppdu_info * ppdu_info)798 ath12k_dp_mon_hal_rx_parse_eht_sig_ndp(const struct hal_eht_sig_ndp_cmn_eb *eht_sig_ndp,
799 struct hal_rx_mon_ppdu_info *ppdu_info)
800 {
801 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;
802 u32 known, data;
803
804 known = __le32_to_cpu(eht->known);
805 known |= IEEE80211_RADIOTAP_EHT_KNOWN_SPATIAL_REUSE |
806 IEEE80211_RADIOTAP_EHT_KNOWN_EHT_LTF |
807 IEEE80211_RADIOTAP_EHT_KNOWN_NSS_S |
808 IEEE80211_RADIOTAP_EHT_KNOWN_BEAMFORMED_S |
809 IEEE80211_RADIOTAP_EHT_KNOWN_DISREGARD_S |
810 IEEE80211_RADIOTAP_EHT_KNOWN_CRC1 |
811 IEEE80211_RADIOTAP_EHT_KNOWN_TAIL1;
812 eht->known = cpu_to_le32(known);
813
814 data = __le32_to_cpu(eht->data[0]);
815 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
816 HAL_RX_EHT_SIG_NDP_CMN_INFO0_SPATIAL_REUSE,
817 IEEE80211_RADIOTAP_EHT_DATA0_SPATIAL_REUSE);
818 /* GI and LTF size are separately indicated in radiotap header
819 * and hence will be parsed from other TLV
820 */
821 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
822 HAL_RX_EHT_SIG_NDP_CMN_INFO0_NUM_LTF_SYM,
823 IEEE80211_RADIOTAP_EHT_DATA0_EHT_LTF);
824
825 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
826 HAL_RX_EHT_SIG_NDP_CMN_INFO0_CRC,
827 IEEE80211_RADIOTAP_EHT_DATA0_CRC1_O);
828
829 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
830 HAL_RX_EHT_SIG_NDP_CMN_INFO0_DISREGARD,
831 IEEE80211_RADIOTAP_EHT_DATA0_DISREGARD_S);
832 eht->data[0] = cpu_to_le32(data);
833
834 data = __le32_to_cpu(eht->data[7]);
835 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
836 HAL_RX_EHT_SIG_NDP_CMN_INFO0_NSS,
837 IEEE80211_RADIOTAP_EHT_DATA7_NSS_S);
838
839 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
840 HAL_RX_EHT_SIG_NDP_CMN_INFO0_BEAMFORMED,
841 IEEE80211_RADIOTAP_EHT_DATA7_BEAMFORMED_S);
842 eht->data[7] = cpu_to_le32(data);
843 }
844
845 static void
ath12k_dp_mon_hal_rx_parse_usig_overflow(const struct hal_eht_sig_usig_overflow * ovflow,struct hal_rx_mon_ppdu_info * ppdu_info)846 ath12k_dp_mon_hal_rx_parse_usig_overflow(const struct hal_eht_sig_usig_overflow *ovflow,
847 struct hal_rx_mon_ppdu_info *ppdu_info)
848 {
849 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;
850 u32 known, data;
851
852 known = __le32_to_cpu(eht->known);
853 known |= IEEE80211_RADIOTAP_EHT_KNOWN_SPATIAL_REUSE |
854 IEEE80211_RADIOTAP_EHT_KNOWN_EHT_LTF |
855 IEEE80211_RADIOTAP_EHT_KNOWN_LDPC_EXTRA_SYM_OM |
856 IEEE80211_RADIOTAP_EHT_KNOWN_PRE_PADD_FACOR_OM |
857 IEEE80211_RADIOTAP_EHT_KNOWN_PE_DISAMBIGUITY_OM |
858 IEEE80211_RADIOTAP_EHT_KNOWN_DISREGARD_O;
859 eht->known = cpu_to_le32(known);
860
861 data = __le32_to_cpu(eht->data[0]);
862 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
863 HAL_RX_EHT_SIG_OVERFLOW_INFO0_SPATIAL_REUSE,
864 IEEE80211_RADIOTAP_EHT_DATA0_SPATIAL_REUSE);
865
866 /* GI and LTF size are separately indicated in radiotap header
867 * and hence will be parsed from other TLV
868 */
869 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
870 HAL_RX_EHT_SIG_OVERFLOW_INFO0_NUM_LTF_SYM,
871 IEEE80211_RADIOTAP_EHT_DATA0_EHT_LTF);
872
873 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
874 HAL_RX_EHT_SIG_OVERFLOW_INFO0_LDPC_EXTA_SYM,
875 IEEE80211_RADIOTAP_EHT_DATA0_LDPC_EXTRA_SYM_OM);
876
877 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
878 HAL_RX_EHT_SIG_OVERFLOW_INFO0_PRE_FEC_PAD_FACTOR,
879 IEEE80211_RADIOTAP_EHT_DATA0_PRE_PADD_FACOR_OM);
880
881 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
882 HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISAMBIGUITY,
883 IEEE80211_RADIOTAP_EHT_DATA0_PE_DISAMBIGUITY_OM);
884
885 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
886 HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISREGARD,
887 IEEE80211_RADIOTAP_EHT_DATA0_DISREGARD_O);
888 eht->data[0] = cpu_to_le32(data);
889 }
890
891 static void
ath12k_dp_mon_hal_rx_parse_non_ofdma_users(const struct hal_eht_sig_non_ofdma_cmn_eb * eb,struct hal_rx_mon_ppdu_info * ppdu_info)892 ath12k_dp_mon_hal_rx_parse_non_ofdma_users(const struct hal_eht_sig_non_ofdma_cmn_eb *eb,
893 struct hal_rx_mon_ppdu_info *ppdu_info)
894 {
895 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;
896 u32 known, data;
897
898 known = __le32_to_cpu(eht->known);
899 known |= IEEE80211_RADIOTAP_EHT_KNOWN_NR_NON_OFDMA_USERS_M;
900 eht->known = cpu_to_le32(known);
901
902 data = __le32_to_cpu(eht->data[7]);
903 data |= ATH12K_LE32_DEC_ENC(eb->info0,
904 HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_USERS,
905 IEEE80211_RADIOTAP_EHT_DATA7_NUM_OF_NON_OFDMA_USERS);
906 eht->data[7] = cpu_to_le32(data);
907 }
908
909 static void
ath12k_dp_mon_hal_rx_parse_eht_mumimo_user(const struct hal_eht_sig_mu_mimo * user,struct hal_rx_mon_ppdu_info * ppdu_info)910 ath12k_dp_mon_hal_rx_parse_eht_mumimo_user(const struct hal_eht_sig_mu_mimo *user,
911 struct hal_rx_mon_ppdu_info *ppdu_info)
912 {
913 struct hal_rx_eht_info *eht_info = &ppdu_info->eht_info;
914 u32 user_idx;
915
916 if (eht_info->num_user_info >= ARRAY_SIZE(eht_info->user_info))
917 return;
918
919 user_idx = eht_info->num_user_info++;
920
921 eht_info->user_info[user_idx] |=
922 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID_KNOWN |
923 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
924 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN |
925 IEEE80211_RADIOTAP_EHT_USER_INFO_SPATIAL_CONFIG_KNOWN_M |
926 ATH12K_LE32_DEC_ENC(user->info0,
927 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_STA_ID,
928 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID) |
929 ATH12K_LE32_DEC_ENC(user->info0,
930 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CODING,
931 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING) |
932 ATH12K_LE32_DEC_ENC(user->info0,
933 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS,
934 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
935 ATH12K_LE32_DEC_ENC(user->info0,
936 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_SPATIAL_CODING,
937 IEEE80211_RADIOTAP_EHT_USER_INFO_SPATIAL_CONFIG_M);
938
939 ppdu_info->mcs = le32_get_bits(user->info0,
940 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS);
941 }
942
943 static void
ath12k_dp_mon_hal_rx_parse_eht_non_mumimo_user(const struct hal_eht_sig_non_mu_mimo * user,struct hal_rx_mon_ppdu_info * ppdu_info)944 ath12k_dp_mon_hal_rx_parse_eht_non_mumimo_user(const struct hal_eht_sig_non_mu_mimo *user,
945 struct hal_rx_mon_ppdu_info *ppdu_info)
946 {
947 struct hal_rx_eht_info *eht_info = &ppdu_info->eht_info;
948 u32 user_idx;
949
950 if (eht_info->num_user_info >= ARRAY_SIZE(eht_info->user_info))
951 return;
952
953 user_idx = eht_info->num_user_info++;
954
955 eht_info->user_info[user_idx] |=
956 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID_KNOWN |
957 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
958 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN |
959 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O |
960 IEEE80211_RADIOTAP_EHT_USER_INFO_BEAMFORMING_KNOWN_O |
961 ATH12K_LE32_DEC_ENC(user->info0,
962 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_STA_ID,
963 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID) |
964 ATH12K_LE32_DEC_ENC(user->info0,
965 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CODING,
966 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING) |
967 ATH12K_LE32_DEC_ENC(user->info0,
968 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS,
969 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
970 ATH12K_LE32_DEC_ENC(user->info0,
971 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS,
972 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O) |
973 ATH12K_LE32_DEC_ENC(user->info0,
974 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_BEAMFORMED,
975 IEEE80211_RADIOTAP_EHT_USER_INFO_BEAMFORMING_O);
976
977 ppdu_info->mcs = le32_get_bits(user->info0,
978 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS);
979
980 ppdu_info->nss = le32_get_bits(user->info0,
981 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS) + 1;
982 }
983
984 static inline bool
ath12k_dp_mon_hal_rx_is_mu_mimo_user(const struct hal_rx_u_sig_info * usig_info)985 ath12k_dp_mon_hal_rx_is_mu_mimo_user(const struct hal_rx_u_sig_info *usig_info)
986 {
987 if (usig_info->ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_SU &&
988 usig_info->ul_dl == 1)
989 return true;
990
991 return false;
992 }
993
994 static void
ath12k_dp_mon_hal_rx_parse_eht_sig_non_ofdma(const void * tlv,struct hal_rx_mon_ppdu_info * ppdu_info)995 ath12k_dp_mon_hal_rx_parse_eht_sig_non_ofdma(const void *tlv,
996 struct hal_rx_mon_ppdu_info *ppdu_info)
997 {
998 const struct hal_eht_sig_non_ofdma_cmn_eb *eb = tlv;
999
1000 ath12k_dp_mon_hal_rx_parse_usig_overflow(tlv, ppdu_info);
1001 ath12k_dp_mon_hal_rx_parse_non_ofdma_users(eb, ppdu_info);
1002
1003 if (ath12k_dp_mon_hal_rx_is_mu_mimo_user(&ppdu_info->u_sig_info))
1004 ath12k_dp_mon_hal_rx_parse_eht_mumimo_user(&eb->user_field.mu_mimo,
1005 ppdu_info);
1006 else
1007 ath12k_dp_mon_hal_rx_parse_eht_non_mumimo_user(&eb->user_field.n_mu_mimo,
1008 ppdu_info);
1009 }
1010
1011 static void
ath12k_dp_mon_hal_rx_parse_ru_allocation(const struct hal_eht_sig_ofdma_cmn_eb * eb,struct hal_rx_mon_ppdu_info * ppdu_info)1012 ath12k_dp_mon_hal_rx_parse_ru_allocation(const struct hal_eht_sig_ofdma_cmn_eb *eb,
1013 struct hal_rx_mon_ppdu_info *ppdu_info)
1014 {
1015 const struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cmn_eb1 = &eb->eb1;
1016 const struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cmn_eb2 = &eb->eb2;
1017 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;
1018 enum ieee80211_radiotap_eht_data ru_123, ru_124, ru_125, ru_126;
1019 enum ieee80211_radiotap_eht_data ru_121, ru_122, ru_112, ru_111;
1020 u32 data;
1021
1022 ru_123 = IEEE80211_RADIOTAP_EHT_DATA4_RU_ALLOC_CC_1_2_3;
1023 ru_124 = IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_4;
1024 ru_125 = IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_5;
1025 ru_126 = IEEE80211_RADIOTAP_EHT_DATA6_RU_ALLOC_CC_1_2_6;
1026 ru_121 = IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_1;
1027 ru_122 = IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_2;
1028 ru_112 = IEEE80211_RADIOTAP_EHT_DATA2_RU_ALLOC_CC_1_1_2;
1029 ru_111 = IEEE80211_RADIOTAP_EHT_DATA1_RU_ALLOC_CC_1_1_1;
1030
1031 switch (ppdu_info->u_sig_info.bw) {
1032 case HAL_EHT_BW_320_2:
1033 case HAL_EHT_BW_320_1:
1034 data = __le32_to_cpu(eht->data[4]);
1035 /* CC1 2::3 */
1036 data |= IEEE80211_RADIOTAP_EHT_DATA4_RU_ALLOC_CC_1_2_3_KNOWN |
1037 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1038 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_3,
1039 ru_123);
1040 eht->data[4] = cpu_to_le32(data);
1041
1042 data = __le32_to_cpu(eht->data[5]);
1043 /* CC1 2::4 */
1044 data |= IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_4_KNOWN |
1045 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1046 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_4,
1047 ru_124);
1048
1049 /* CC1 2::5 */
1050 data |= IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_5_KNOWN |
1051 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1052 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_5,
1053 ru_125);
1054 eht->data[5] = cpu_to_le32(data);
1055
1056 data = __le32_to_cpu(eht->data[6]);
1057 /* CC1 2::6 */
1058 data |= IEEE80211_RADIOTAP_EHT_DATA6_RU_ALLOC_CC_1_2_6_KNOWN |
1059 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1060 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_6,
1061 ru_126);
1062 eht->data[6] = cpu_to_le32(data);
1063
1064 fallthrough;
1065 case HAL_EHT_BW_160:
1066 data = __le32_to_cpu(eht->data[3]);
1067 /* CC1 2::1 */
1068 data |= IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_1_KNOWN |
1069 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1070 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_1,
1071 ru_121);
1072 /* CC1 2::2 */
1073 data |= IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_2_KNOWN |
1074 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1075 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_2,
1076 ru_122);
1077 eht->data[3] = cpu_to_le32(data);
1078
1079 fallthrough;
1080 case HAL_EHT_BW_80:
1081 data = __le32_to_cpu(eht->data[2]);
1082 /* CC1 1::2 */
1083 data |= IEEE80211_RADIOTAP_EHT_DATA2_RU_ALLOC_CC_1_1_2_KNOWN |
1084 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb1->info0,
1085 HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_2,
1086 ru_112);
1087 eht->data[2] = cpu_to_le32(data);
1088
1089 fallthrough;
1090 case HAL_EHT_BW_40:
1091 fallthrough;
1092 case HAL_EHT_BW_20:
1093 data = __le32_to_cpu(eht->data[1]);
1094 /* CC1 1::1 */
1095 data |= IEEE80211_RADIOTAP_EHT_DATA1_RU_ALLOC_CC_1_1_1_KNOWN |
1096 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb1->info0,
1097 HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_1,
1098 ru_111);
1099 eht->data[1] = cpu_to_le32(data);
1100 break;
1101 default:
1102 break;
1103 }
1104 }
1105
1106 static void
ath12k_dp_mon_hal_rx_parse_eht_sig_ofdma(const void * tlv,struct hal_rx_mon_ppdu_info * ppdu_info)1107 ath12k_dp_mon_hal_rx_parse_eht_sig_ofdma(const void *tlv,
1108 struct hal_rx_mon_ppdu_info *ppdu_info)
1109 {
1110 const struct hal_eht_sig_ofdma_cmn_eb *ofdma = tlv;
1111
1112 ath12k_dp_mon_hal_rx_parse_usig_overflow(tlv, ppdu_info);
1113 ath12k_dp_mon_hal_rx_parse_ru_allocation(ofdma, ppdu_info);
1114
1115 ath12k_dp_mon_hal_rx_parse_eht_non_mumimo_user(&ofdma->user_field.n_mu_mimo,
1116 ppdu_info);
1117 }
1118
1119 static void
ath12k_dp_mon_parse_eht_sig_hdr(struct hal_rx_mon_ppdu_info * ppdu_info,const void * tlv_data)1120 ath12k_dp_mon_parse_eht_sig_hdr(struct hal_rx_mon_ppdu_info *ppdu_info,
1121 const void *tlv_data)
1122 {
1123 ppdu_info->is_eht = true;
1124
1125 if (ath12k_dp_mon_hal_rx_is_frame_type_ndp(&ppdu_info->u_sig_info))
1126 ath12k_dp_mon_hal_rx_parse_eht_sig_ndp(tlv_data, ppdu_info);
1127 else if (ath12k_dp_mon_hal_rx_is_non_ofdma(&ppdu_info->u_sig_info))
1128 ath12k_dp_mon_hal_rx_parse_eht_sig_non_ofdma(tlv_data, ppdu_info);
1129 else if (ath12k_dp_mon_hal_rx_is_ofdma(&ppdu_info->u_sig_info))
1130 ath12k_dp_mon_hal_rx_parse_eht_sig_ofdma(tlv_data, ppdu_info);
1131 }
1132
1133 static inline enum ath12k_eht_ru_size
hal_rx_mon_hal_ru_size_to_ath12k_ru_size(u32 hal_ru_size)1134 hal_rx_mon_hal_ru_size_to_ath12k_ru_size(u32 hal_ru_size)
1135 {
1136 switch (hal_ru_size) {
1137 case HAL_EHT_RU_26:
1138 return ATH12K_EHT_RU_26;
1139 case HAL_EHT_RU_52:
1140 return ATH12K_EHT_RU_52;
1141 case HAL_EHT_RU_78:
1142 return ATH12K_EHT_RU_52_26;
1143 case HAL_EHT_RU_106:
1144 return ATH12K_EHT_RU_106;
1145 case HAL_EHT_RU_132:
1146 return ATH12K_EHT_RU_106_26;
1147 case HAL_EHT_RU_242:
1148 return ATH12K_EHT_RU_242;
1149 case HAL_EHT_RU_484:
1150 return ATH12K_EHT_RU_484;
1151 case HAL_EHT_RU_726:
1152 return ATH12K_EHT_RU_484_242;
1153 case HAL_EHT_RU_996:
1154 return ATH12K_EHT_RU_996;
1155 case HAL_EHT_RU_996x2:
1156 return ATH12K_EHT_RU_996x2;
1157 case HAL_EHT_RU_996x3:
1158 return ATH12K_EHT_RU_996x3;
1159 case HAL_EHT_RU_996x4:
1160 return ATH12K_EHT_RU_996x4;
1161 case HAL_EHT_RU_NONE:
1162 return ATH12K_EHT_RU_INVALID;
1163 case HAL_EHT_RU_996_484:
1164 return ATH12K_EHT_RU_996_484;
1165 case HAL_EHT_RU_996x2_484:
1166 return ATH12K_EHT_RU_996x2_484;
1167 case HAL_EHT_RU_996x3_484:
1168 return ATH12K_EHT_RU_996x3_484;
1169 case HAL_EHT_RU_996_484_242:
1170 return ATH12K_EHT_RU_996_484_242;
1171 default:
1172 return ATH12K_EHT_RU_INVALID;
1173 }
1174 }
1175
1176 static inline u32
hal_rx_ul_ofdma_ru_size_to_width(enum ath12k_eht_ru_size ru_size)1177 hal_rx_ul_ofdma_ru_size_to_width(enum ath12k_eht_ru_size ru_size)
1178 {
1179 switch (ru_size) {
1180 case ATH12K_EHT_RU_26:
1181 return RU_26;
1182 case ATH12K_EHT_RU_52:
1183 return RU_52;
1184 case ATH12K_EHT_RU_52_26:
1185 return RU_52_26;
1186 case ATH12K_EHT_RU_106:
1187 return RU_106;
1188 case ATH12K_EHT_RU_106_26:
1189 return RU_106_26;
1190 case ATH12K_EHT_RU_242:
1191 return RU_242;
1192 case ATH12K_EHT_RU_484:
1193 return RU_484;
1194 case ATH12K_EHT_RU_484_242:
1195 return RU_484_242;
1196 case ATH12K_EHT_RU_996:
1197 return RU_996;
1198 case ATH12K_EHT_RU_996_484:
1199 return RU_996_484;
1200 case ATH12K_EHT_RU_996_484_242:
1201 return RU_996_484_242;
1202 case ATH12K_EHT_RU_996x2:
1203 return RU_2X996;
1204 case ATH12K_EHT_RU_996x2_484:
1205 return RU_2X996_484;
1206 case ATH12K_EHT_RU_996x3:
1207 return RU_3X996;
1208 case ATH12K_EHT_RU_996x3_484:
1209 return RU_3X996_484;
1210 case ATH12K_EHT_RU_996x4:
1211 return RU_4X996;
1212 default:
1213 return RU_INVALID;
1214 }
1215 }
1216
1217 static void
ath12k_dp_mon_hal_rx_parse_user_info(const struct hal_receive_user_info * rx_usr_info,u16 user_id,struct hal_rx_mon_ppdu_info * ppdu_info)1218 ath12k_dp_mon_hal_rx_parse_user_info(const struct hal_receive_user_info *rx_usr_info,
1219 u16 user_id,
1220 struct hal_rx_mon_ppdu_info *ppdu_info)
1221 {
1222 struct hal_rx_user_status *mon_rx_user_status = NULL;
1223 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;
1224 enum ath12k_eht_ru_size rtap_ru_size = ATH12K_EHT_RU_INVALID;
1225 u32 ru_width, reception_type, ru_index = HAL_EHT_RU_INVALID;
1226 u32 ru_type_80_0, ru_start_index_80_0;
1227 u32 ru_type_80_1, ru_start_index_80_1;
1228 u32 ru_type_80_2, ru_start_index_80_2;
1229 u32 ru_type_80_3, ru_start_index_80_3;
1230 u32 ru_size = 0, num_80mhz_with_ru = 0;
1231 u64 ru_index_320mhz = 0;
1232 u32 ru_index_per80mhz;
1233
1234 reception_type = le32_get_bits(rx_usr_info->info0,
1235 HAL_RX_USR_INFO0_RECEPTION_TYPE);
1236
1237 switch (reception_type) {
1238 case HAL_RECEPTION_TYPE_SU:
1239 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
1240 break;
1241 case HAL_RECEPTION_TYPE_DL_MU_MIMO:
1242 case HAL_RECEPTION_TYPE_UL_MU_MIMO:
1243 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
1244 break;
1245 case HAL_RECEPTION_TYPE_DL_MU_OFMA:
1246 case HAL_RECEPTION_TYPE_UL_MU_OFDMA:
1247 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
1248 break;
1249 case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO:
1250 case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO:
1251 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO;
1252 }
1253
1254 ppdu_info->is_stbc = le32_get_bits(rx_usr_info->info0, HAL_RX_USR_INFO0_STBC);
1255 ppdu_info->ldpc = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_LDPC);
1256 ppdu_info->dcm = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_STA_DCM);
1257 ppdu_info->bw = le32_get_bits(rx_usr_info->info1, HAL_RX_USR_INFO1_RX_BW);
1258 ppdu_info->mcs = le32_get_bits(rx_usr_info->info1, HAL_RX_USR_INFO1_MCS);
1259 ppdu_info->nss = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_NSS) + 1;
1260
1261 if (user_id < HAL_MAX_UL_MU_USERS) {
1262 mon_rx_user_status = &ppdu_info->userstats[user_id];
1263 mon_rx_user_status->mcs = ppdu_info->mcs;
1264 mon_rx_user_status->nss = ppdu_info->nss;
1265 }
1266
1267 if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO ||
1268 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
1269 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO))
1270 return;
1271
1272 /* RU allocation present only for OFDMA reception */
1273 ru_type_80_0 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_0);
1274 ru_start_index_80_0 = le32_get_bits(rx_usr_info->info3,
1275 HAL_RX_USR_INFO3_RU_START_IDX_80_0);
1276 if (ru_type_80_0 != HAL_EHT_RU_NONE) {
1277 ru_size += ru_type_80_0;
1278 ru_index_per80mhz = ru_start_index_80_0;
1279 ru_index = ru_index_per80mhz;
1280 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_0, 0, ru_index_per80mhz);
1281 num_80mhz_with_ru++;
1282 }
1283
1284 ru_type_80_1 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_1);
1285 ru_start_index_80_1 = le32_get_bits(rx_usr_info->info3,
1286 HAL_RX_USR_INFO3_RU_START_IDX_80_1);
1287 if (ru_type_80_1 != HAL_EHT_RU_NONE) {
1288 ru_size += ru_type_80_1;
1289 ru_index_per80mhz = ru_start_index_80_1;
1290 ru_index = ru_index_per80mhz;
1291 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_1, 1, ru_index_per80mhz);
1292 num_80mhz_with_ru++;
1293 }
1294
1295 ru_type_80_2 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_2);
1296 ru_start_index_80_2 = le32_get_bits(rx_usr_info->info3,
1297 HAL_RX_USR_INFO3_RU_START_IDX_80_2);
1298 if (ru_type_80_2 != HAL_EHT_RU_NONE) {
1299 ru_size += ru_type_80_2;
1300 ru_index_per80mhz = ru_start_index_80_2;
1301 ru_index = ru_index_per80mhz;
1302 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_2, 2, ru_index_per80mhz);
1303 num_80mhz_with_ru++;
1304 }
1305
1306 ru_type_80_3 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_3);
1307 ru_start_index_80_3 = le32_get_bits(rx_usr_info->info2,
1308 HAL_RX_USR_INFO3_RU_START_IDX_80_3);
1309 if (ru_type_80_3 != HAL_EHT_RU_NONE) {
1310 ru_size += ru_type_80_3;
1311 ru_index_per80mhz = ru_start_index_80_3;
1312 ru_index = ru_index_per80mhz;
1313 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_3, 3, ru_index_per80mhz);
1314 num_80mhz_with_ru++;
1315 }
1316
1317 if (num_80mhz_with_ru > 1) {
1318 /* Calculate the MRU index */
1319 switch (ru_index_320mhz) {
1320 case HAL_EHT_RU_996_484_0:
1321 case HAL_EHT_RU_996x2_484_0:
1322 case HAL_EHT_RU_996x3_484_0:
1323 ru_index = 0;
1324 break;
1325 case HAL_EHT_RU_996_484_1:
1326 case HAL_EHT_RU_996x2_484_1:
1327 case HAL_EHT_RU_996x3_484_1:
1328 ru_index = 1;
1329 break;
1330 case HAL_EHT_RU_996_484_2:
1331 case HAL_EHT_RU_996x2_484_2:
1332 case HAL_EHT_RU_996x3_484_2:
1333 ru_index = 2;
1334 break;
1335 case HAL_EHT_RU_996_484_3:
1336 case HAL_EHT_RU_996x2_484_3:
1337 case HAL_EHT_RU_996x3_484_3:
1338 ru_index = 3;
1339 break;
1340 case HAL_EHT_RU_996_484_4:
1341 case HAL_EHT_RU_996x2_484_4:
1342 case HAL_EHT_RU_996x3_484_4:
1343 ru_index = 4;
1344 break;
1345 case HAL_EHT_RU_996_484_5:
1346 case HAL_EHT_RU_996x2_484_5:
1347 case HAL_EHT_RU_996x3_484_5:
1348 ru_index = 5;
1349 break;
1350 case HAL_EHT_RU_996_484_6:
1351 case HAL_EHT_RU_996x2_484_6:
1352 case HAL_EHT_RU_996x3_484_6:
1353 ru_index = 6;
1354 break;
1355 case HAL_EHT_RU_996_484_7:
1356 case HAL_EHT_RU_996x2_484_7:
1357 case HAL_EHT_RU_996x3_484_7:
1358 ru_index = 7;
1359 break;
1360 case HAL_EHT_RU_996x2_484_8:
1361 ru_index = 8;
1362 break;
1363 case HAL_EHT_RU_996x2_484_9:
1364 ru_index = 9;
1365 break;
1366 case HAL_EHT_RU_996x2_484_10:
1367 ru_index = 10;
1368 break;
1369 case HAL_EHT_RU_996x2_484_11:
1370 ru_index = 11;
1371 break;
1372 default:
1373 ru_index = HAL_EHT_RU_INVALID;
1374 break;
1375 }
1376
1377 ru_size += 4;
1378 }
1379
1380 rtap_ru_size = hal_rx_mon_hal_ru_size_to_ath12k_ru_size(ru_size);
1381 if (rtap_ru_size != ATH12K_EHT_RU_INVALID) {
1382 u32 known, data;
1383
1384 known = __le32_to_cpu(eht->known);
1385 known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_SIZE_OM;
1386 eht->known = cpu_to_le32(known);
1387
1388 data = __le32_to_cpu(eht->data[1]);
1389 data |= u32_encode_bits(rtap_ru_size,
1390 IEEE80211_RADIOTAP_EHT_DATA1_RU_SIZE);
1391 eht->data[1] = cpu_to_le32(data);
1392 }
1393
1394 if (ru_index != HAL_EHT_RU_INVALID) {
1395 u32 known, data;
1396
1397 known = __le32_to_cpu(eht->known);
1398 known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_INDEX_OM;
1399 eht->known = cpu_to_le32(known);
1400
1401 data = __le32_to_cpu(eht->data[1]);
1402 data |= u32_encode_bits(rtap_ru_size,
1403 IEEE80211_RADIOTAP_EHT_DATA1_RU_INDEX);
1404 eht->data[1] = cpu_to_le32(data);
1405 }
1406
1407 if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID &&
1408 rtap_ru_size != ATH12K_EHT_RU_INVALID) {
1409 mon_rx_user_status->ul_ofdma_ru_start_index = ru_index;
1410 mon_rx_user_status->ul_ofdma_ru_size = rtap_ru_size;
1411
1412 ru_width = hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size);
1413
1414 mon_rx_user_status->ul_ofdma_ru_width = ru_width;
1415 mon_rx_user_status->ofdma_info_valid = 1;
1416 }
1417 }
1418
1419 static enum hal_rx_mon_status
ath12k_dp_mon_rx_parse_status_tlv(struct ath12k * ar,struct ath12k_mon_data * pmon,const struct hal_tlv_64_hdr * tlv)1420 ath12k_dp_mon_rx_parse_status_tlv(struct ath12k *ar,
1421 struct ath12k_mon_data *pmon,
1422 const struct hal_tlv_64_hdr *tlv)
1423 {
1424 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
1425 const void *tlv_data = tlv->value;
1426 u32 info[7], userid;
1427 u16 tlv_tag, tlv_len;
1428
1429 tlv_tag = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_TAG);
1430 tlv_len = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_LEN);
1431 userid = le64_get_bits(tlv->tl, HAL_TLV_64_USR_ID);
1432
1433 if (ppdu_info->tlv_aggr.in_progress && ppdu_info->tlv_aggr.tlv_tag != tlv_tag) {
1434 ath12k_dp_mon_parse_eht_sig_hdr(ppdu_info, ppdu_info->tlv_aggr.buf);
1435
1436 ppdu_info->tlv_aggr.in_progress = false;
1437 ppdu_info->tlv_aggr.cur_len = 0;
1438 }
1439
1440 switch (tlv_tag) {
1441 case HAL_RX_PPDU_START: {
1442 const struct hal_rx_ppdu_start *ppdu_start = tlv_data;
1443
1444 u64 ppdu_ts = ath12k_le32hilo_to_u64(ppdu_start->ppdu_start_ts_63_32,
1445 ppdu_start->ppdu_start_ts_31_0);
1446
1447 info[0] = __le32_to_cpu(ppdu_start->info0);
1448
1449 ppdu_info->ppdu_id = u32_get_bits(info[0],
1450 HAL_RX_PPDU_START_INFO0_PPDU_ID);
1451
1452 info[1] = __le32_to_cpu(ppdu_start->info1);
1453 ppdu_info->chan_num = u32_get_bits(info[1],
1454 HAL_RX_PPDU_START_INFO1_CHAN_NUM);
1455 ppdu_info->freq = u32_get_bits(info[1],
1456 HAL_RX_PPDU_START_INFO1_CHAN_FREQ);
1457 ppdu_info->ppdu_ts = ppdu_ts;
1458
1459 if (ppdu_info->ppdu_id != ppdu_info->last_ppdu_id) {
1460 ppdu_info->last_ppdu_id = ppdu_info->ppdu_id;
1461 ppdu_info->num_users = 0;
1462 memset(&ppdu_info->mpdu_fcs_ok_bitmap, 0,
1463 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
1464 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
1465 }
1466 break;
1467 }
1468 case HAL_RX_PPDU_END_USER_STATS: {
1469 const struct hal_rx_ppdu_end_user_stats *eu_stats = tlv_data;
1470 u32 tid_bitmap;
1471
1472 info[0] = __le32_to_cpu(eu_stats->info0);
1473 info[1] = __le32_to_cpu(eu_stats->info1);
1474 info[2] = __le32_to_cpu(eu_stats->info2);
1475 info[4] = __le32_to_cpu(eu_stats->info4);
1476 info[5] = __le32_to_cpu(eu_stats->info5);
1477 info[6] = __le32_to_cpu(eu_stats->info6);
1478
1479 ppdu_info->ast_index =
1480 u32_get_bits(info[2], HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX);
1481 ppdu_info->fc_valid =
1482 u32_get_bits(info[1], HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID);
1483 tid_bitmap = u32_get_bits(info[6],
1484 HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP);
1485 ppdu_info->tid = ffs(tid_bitmap) - 1;
1486 ppdu_info->tcp_msdu_count =
1487 u32_get_bits(info[4],
1488 HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT);
1489 ppdu_info->udp_msdu_count =
1490 u32_get_bits(info[4],
1491 HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT);
1492 ppdu_info->other_msdu_count =
1493 u32_get_bits(info[5],
1494 HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT);
1495 ppdu_info->tcp_ack_msdu_count =
1496 u32_get_bits(info[5],
1497 HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT);
1498 ppdu_info->preamble_type =
1499 u32_get_bits(info[1],
1500 HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE);
1501 ppdu_info->num_mpdu_fcs_ok =
1502 u32_get_bits(info[1],
1503 HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK);
1504 ppdu_info->num_mpdu_fcs_err =
1505 u32_get_bits(info[0],
1506 HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR);
1507 ppdu_info->peer_id =
1508 u32_get_bits(info[0], HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID);
1509
1510 switch (ppdu_info->preamble_type) {
1511 case HAL_RX_PREAMBLE_11N:
1512 ppdu_info->ht_flags = 1;
1513 break;
1514 case HAL_RX_PREAMBLE_11AC:
1515 ppdu_info->vht_flags = 1;
1516 break;
1517 case HAL_RX_PREAMBLE_11AX:
1518 ppdu_info->he_flags = 1;
1519 break;
1520 case HAL_RX_PREAMBLE_11BE:
1521 ppdu_info->is_eht = true;
1522 break;
1523 default:
1524 break;
1525 }
1526
1527 if (userid < HAL_MAX_UL_MU_USERS) {
1528 struct hal_rx_user_status *rxuser_stats =
1529 &ppdu_info->userstats[userid];
1530
1531 if (ppdu_info->num_mpdu_fcs_ok > 1 ||
1532 ppdu_info->num_mpdu_fcs_err > 1)
1533 ppdu_info->userstats[userid].ampdu_present = true;
1534
1535 ppdu_info->num_users += 1;
1536
1537 ath12k_dp_mon_rx_handle_ofdma_info(eu_stats, rxuser_stats);
1538 ath12k_dp_mon_rx_populate_mu_user_info(eu_stats, ppdu_info,
1539 rxuser_stats);
1540 }
1541 ppdu_info->mpdu_fcs_ok_bitmap[0] = __le32_to_cpu(eu_stats->rsvd1[0]);
1542 ppdu_info->mpdu_fcs_ok_bitmap[1] = __le32_to_cpu(eu_stats->rsvd1[1]);
1543 break;
1544 }
1545 case HAL_RX_PPDU_END_USER_STATS_EXT: {
1546 const struct hal_rx_ppdu_end_user_stats_ext *eu_stats = tlv_data;
1547
1548 ppdu_info->mpdu_fcs_ok_bitmap[2] = __le32_to_cpu(eu_stats->info1);
1549 ppdu_info->mpdu_fcs_ok_bitmap[3] = __le32_to_cpu(eu_stats->info2);
1550 ppdu_info->mpdu_fcs_ok_bitmap[4] = __le32_to_cpu(eu_stats->info3);
1551 ppdu_info->mpdu_fcs_ok_bitmap[5] = __le32_to_cpu(eu_stats->info4);
1552 ppdu_info->mpdu_fcs_ok_bitmap[6] = __le32_to_cpu(eu_stats->info5);
1553 ppdu_info->mpdu_fcs_ok_bitmap[7] = __le32_to_cpu(eu_stats->info6);
1554 break;
1555 }
1556 case HAL_PHYRX_HT_SIG:
1557 ath12k_dp_mon_parse_ht_sig(tlv_data, ppdu_info);
1558 break;
1559
1560 case HAL_PHYRX_L_SIG_B:
1561 ath12k_dp_mon_parse_l_sig_b(tlv_data, ppdu_info);
1562 break;
1563
1564 case HAL_PHYRX_L_SIG_A:
1565 ath12k_dp_mon_parse_l_sig_a(tlv_data, ppdu_info);
1566 break;
1567
1568 case HAL_PHYRX_VHT_SIG_A:
1569 ath12k_dp_mon_parse_vht_sig_a(tlv_data, ppdu_info);
1570 break;
1571
1572 case HAL_PHYRX_HE_SIG_A_SU:
1573 ath12k_dp_mon_parse_he_sig_su(tlv_data, ppdu_info);
1574 break;
1575
1576 case HAL_PHYRX_HE_SIG_A_MU_DL:
1577 ath12k_dp_mon_parse_he_sig_mu(tlv_data, ppdu_info);
1578 break;
1579
1580 case HAL_PHYRX_HE_SIG_B1_MU:
1581 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, ppdu_info);
1582 break;
1583
1584 case HAL_PHYRX_HE_SIG_B2_MU:
1585 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, ppdu_info);
1586 break;
1587
1588 case HAL_PHYRX_HE_SIG_B2_OFDMA:
1589 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, ppdu_info);
1590 break;
1591
1592 case HAL_PHYRX_RSSI_LEGACY: {
1593 const struct hal_rx_phyrx_rssi_legacy_info *rssi = tlv_data;
1594
1595 info[0] = __le32_to_cpu(rssi->info0);
1596 info[1] = __le32_to_cpu(rssi->info1);
1597
1598 /* TODO: Please note that the combined rssi will not be accurate
1599 * in MU case. Rssi in MU needs to be retrieved from
1600 * PHYRX_OTHER_RECEIVE_INFO TLV.
1601 */
1602 ppdu_info->rssi_comb =
1603 u32_get_bits(info[1],
1604 HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB);
1605
1606 ppdu_info->bw = u32_get_bits(info[0],
1607 HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW);
1608 break;
1609 }
1610 case HAL_PHYRX_OTHER_RECEIVE_INFO: {
1611 const struct hal_phyrx_common_user_info *cmn_usr_info = tlv_data;
1612
1613 ppdu_info->gi = le32_get_bits(cmn_usr_info->info0,
1614 HAL_RX_PHY_CMN_USER_INFO0_GI);
1615 break;
1616 }
1617 case HAL_RX_PPDU_START_USER_INFO:
1618 ath12k_dp_mon_hal_rx_parse_user_info(tlv_data, userid, ppdu_info);
1619 break;
1620
1621 case HAL_RXPCU_PPDU_END_INFO: {
1622 const struct hal_rx_ppdu_end_duration *ppdu_rx_duration = tlv_data;
1623
1624 info[0] = __le32_to_cpu(ppdu_rx_duration->info0);
1625 ppdu_info->rx_duration =
1626 u32_get_bits(info[0], HAL_RX_PPDU_END_DURATION);
1627 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]);
1628 ppdu_info->tsft = (ppdu_info->tsft << 32) |
1629 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]);
1630 break;
1631 }
1632 case HAL_RX_MPDU_START: {
1633 const struct hal_rx_mpdu_start *mpdu_start = tlv_data;
1634 u16 peer_id;
1635
1636 info[1] = __le32_to_cpu(mpdu_start->info1);
1637 peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID);
1638 if (peer_id)
1639 ppdu_info->peer_id = peer_id;
1640
1641 ppdu_info->mpdu_len += u32_get_bits(info[1],
1642 HAL_RX_MPDU_START_INFO2_MPDU_LEN);
1643 if (userid < HAL_MAX_UL_MU_USERS) {
1644 info[0] = __le32_to_cpu(mpdu_start->info0);
1645 ppdu_info->userid = userid;
1646 ppdu_info->userstats[userid].ampdu_id =
1647 u32_get_bits(info[0], HAL_RX_MPDU_START_INFO0_PPDU_ID);
1648 }
1649
1650 break;
1651 }
1652 case HAL_RX_MSDU_START:
1653 /* TODO: add msdu start parsing logic */
1654 break;
1655 case HAL_MON_BUF_ADDR:
1656 return HAL_RX_MON_STATUS_BUF_ADDR;
1657 case HAL_RX_MSDU_END:
1658 return HAL_RX_MON_STATUS_MSDU_END;
1659 case HAL_RX_MPDU_END:
1660 return HAL_RX_MON_STATUS_MPDU_END;
1661 case HAL_PHYRX_GENERIC_U_SIG:
1662 ath12k_dp_mon_hal_rx_parse_u_sig_hdr(tlv_data, ppdu_info);
1663 break;
1664 case HAL_PHYRX_GENERIC_EHT_SIG:
1665 /* Handle the case where aggregation is in progress
1666 * or the current TLV is one of the TLVs which should be
1667 * aggregated
1668 */
1669 if (!ppdu_info->tlv_aggr.in_progress) {
1670 ppdu_info->tlv_aggr.in_progress = true;
1671 ppdu_info->tlv_aggr.tlv_tag = tlv_tag;
1672 ppdu_info->tlv_aggr.cur_len = 0;
1673 }
1674
1675 ppdu_info->is_eht = true;
1676
1677 ath12k_dp_mon_hal_aggr_tlv(ppdu_info, tlv_len, tlv_data);
1678 break;
1679 case HAL_DUMMY:
1680 return HAL_RX_MON_STATUS_BUF_DONE;
1681 case HAL_RX_PPDU_END_STATUS_DONE:
1682 case 0:
1683 return HAL_RX_MON_STATUS_PPDU_DONE;
1684 default:
1685 break;
1686 }
1687
1688 return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
1689 }
1690
ath12k_dp_mon_rx_msdus_set_payload(struct ath12k * ar,struct sk_buff * head_msdu,struct sk_buff * tail_msdu)1691 static void ath12k_dp_mon_rx_msdus_set_payload(struct ath12k *ar,
1692 struct sk_buff *head_msdu,
1693 struct sk_buff *tail_msdu)
1694 {
1695 u32 rx_pkt_offset, l2_hdr_offset;
1696
1697 rx_pkt_offset = ar->ab->hal.hal_desc_sz;
1698 l2_hdr_offset =
1699 ath12k_dp_rx_h_l3pad(ar->ab, (struct hal_rx_desc *)tail_msdu->data);
1700 skb_pull(head_msdu, rx_pkt_offset + l2_hdr_offset);
1701 }
1702
1703 static struct sk_buff *
ath12k_dp_mon_rx_merg_msdus(struct ath12k * ar,struct sk_buff * head_msdu,struct sk_buff * tail_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)1704 ath12k_dp_mon_rx_merg_msdus(struct ath12k *ar,
1705 struct sk_buff *head_msdu, struct sk_buff *tail_msdu,
1706 struct ieee80211_rx_status *rxs, bool *fcs_err)
1707 {
1708 struct ath12k_base *ab = ar->ab;
1709 struct sk_buff *msdu, *mpdu_buf, *prev_buf, *head_frag_list;
1710 struct hal_rx_desc *rx_desc, *tail_rx_desc;
1711 u8 *hdr_desc, *dest, decap_format;
1712 struct ieee80211_hdr_3addr *wh;
1713 u32 err_bitmap, frag_list_sum_len = 0;
1714
1715 mpdu_buf = NULL;
1716
1717 if (!head_msdu)
1718 goto err_merge_fail;
1719
1720 rx_desc = (struct hal_rx_desc *)head_msdu->data;
1721 tail_rx_desc = (struct hal_rx_desc *)tail_msdu->data;
1722
1723 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, tail_rx_desc);
1724 if (err_bitmap & HAL_RX_MPDU_ERR_FCS)
1725 *fcs_err = true;
1726
1727 decap_format = ath12k_dp_rx_h_decap_type(ab, tail_rx_desc);
1728
1729 ath12k_dp_rx_h_ppdu(ar, tail_rx_desc, rxs);
1730
1731 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
1732 ath12k_dp_mon_rx_msdus_set_payload(ar, head_msdu, tail_msdu);
1733
1734 prev_buf = head_msdu;
1735 msdu = head_msdu->next;
1736 head_frag_list = NULL;
1737
1738 while (msdu) {
1739 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu, tail_msdu);
1740
1741 if (!head_frag_list)
1742 head_frag_list = msdu;
1743
1744 frag_list_sum_len += msdu->len;
1745 prev_buf = msdu;
1746 msdu = msdu->next;
1747 }
1748
1749 prev_buf->next = NULL;
1750
1751 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
1752 if (head_frag_list) {
1753 skb_shinfo(head_msdu)->frag_list = head_frag_list;
1754 head_msdu->data_len = frag_list_sum_len;
1755 head_msdu->len += head_msdu->data_len;
1756 head_msdu->next = NULL;
1757 }
1758 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
1759 u8 qos_pkt = 0;
1760
1761 rx_desc = (struct hal_rx_desc *)head_msdu->data;
1762 hdr_desc =
1763 ab->hal_rx_ops->rx_desc_get_msdu_payload(rx_desc);
1764
1765 /* Base size */
1766 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
1767
1768 if (ieee80211_is_data_qos(wh->frame_control))
1769 qos_pkt = 1;
1770
1771 msdu = head_msdu;
1772
1773 while (msdu) {
1774 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu, tail_msdu);
1775 if (qos_pkt) {
1776 dest = skb_push(msdu, sizeof(__le16));
1777 if (!dest)
1778 goto err_merge_fail;
1779 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
1780 }
1781 prev_buf = msdu;
1782 msdu = msdu->next;
1783 }
1784 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
1785 if (!dest)
1786 goto err_merge_fail;
1787
1788 ath12k_dbg(ab, ATH12K_DBG_DATA,
1789 "mpdu_buf %p mpdu_buf->len %u",
1790 prev_buf, prev_buf->len);
1791 } else {
1792 ath12k_dbg(ab, ATH12K_DBG_DATA,
1793 "decap format %d is not supported!\n",
1794 decap_format);
1795 goto err_merge_fail;
1796 }
1797
1798 return head_msdu;
1799
1800 err_merge_fail:
1801 if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) {
1802 ath12k_dbg(ab, ATH12K_DBG_DATA,
1803 "err_merge_fail mpdu_buf %p", mpdu_buf);
1804 /* Free the head buffer */
1805 dev_kfree_skb_any(mpdu_buf);
1806 }
1807 return NULL;
1808 }
1809
1810 static void
ath12k_dp_mon_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)1811 ath12k_dp_mon_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
1812 u8 *rtap_buf)
1813 {
1814 u32 rtap_len = 0;
1815
1816 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
1817 rtap_len += 2;
1818
1819 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
1820 rtap_len += 2;
1821
1822 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
1823 rtap_len += 2;
1824
1825 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
1826 rtap_len += 2;
1827
1828 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
1829 rtap_len += 2;
1830
1831 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
1832 }
1833
1834 static void
ath12k_dp_mon_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)1835 ath12k_dp_mon_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
1836 u8 *rtap_buf)
1837 {
1838 u32 rtap_len = 0;
1839
1840 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
1841 rtap_len += 2;
1842
1843 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
1844 rtap_len += 2;
1845
1846 rtap_buf[rtap_len] = rx_status->he_RU[0];
1847 rtap_len += 1;
1848
1849 rtap_buf[rtap_len] = rx_status->he_RU[1];
1850 rtap_len += 1;
1851
1852 rtap_buf[rtap_len] = rx_status->he_RU[2];
1853 rtap_len += 1;
1854
1855 rtap_buf[rtap_len] = rx_status->he_RU[3];
1856 }
1857
ath12k_dp_mon_update_radiotap(struct ath12k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)1858 static void ath12k_dp_mon_update_radiotap(struct ath12k *ar,
1859 struct hal_rx_mon_ppdu_info *ppduinfo,
1860 struct sk_buff *mon_skb,
1861 struct ieee80211_rx_status *rxs)
1862 {
1863 struct ieee80211_supported_band *sband;
1864 u8 *ptr = NULL;
1865
1866 rxs->flag |= RX_FLAG_MACTIME_START;
1867 rxs->signal = ppduinfo->rssi_comb + ATH12K_DEFAULT_NOISE_FLOOR;
1868 rxs->nss = ppduinfo->nss + 1;
1869
1870 if (ppduinfo->userstats[ppduinfo->userid].ampdu_present) {
1871 rxs->flag |= RX_FLAG_AMPDU_DETAILS;
1872 rxs->ampdu_reference = ppduinfo->userstats[ppduinfo->userid].ampdu_id;
1873 }
1874
1875 if (ppduinfo->is_eht || ppduinfo->eht_usig) {
1876 struct ieee80211_radiotap_tlv *tlv;
1877 struct ieee80211_radiotap_eht *eht;
1878 struct ieee80211_radiotap_eht_usig *usig;
1879 u16 len = 0, i, eht_len, usig_len;
1880 u8 user;
1881
1882 if (ppduinfo->is_eht) {
1883 eht_len = struct_size(eht,
1884 user_info,
1885 ppduinfo->eht_info.num_user_info);
1886 len += sizeof(*tlv) + eht_len;
1887 }
1888
1889 if (ppduinfo->eht_usig) {
1890 usig_len = sizeof(*usig);
1891 len += sizeof(*tlv) + usig_len;
1892 }
1893
1894 rxs->flag |= RX_FLAG_RADIOTAP_TLV_AT_END;
1895 rxs->encoding = RX_ENC_EHT;
1896
1897 skb_reset_mac_header(mon_skb);
1898
1899 tlv = skb_push(mon_skb, len);
1900
1901 if (ppduinfo->is_eht) {
1902 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT);
1903 tlv->len = cpu_to_le16(eht_len);
1904
1905 eht = (struct ieee80211_radiotap_eht *)tlv->data;
1906 eht->known = ppduinfo->eht_info.eht.known;
1907
1908 for (i = 0;
1909 i < ARRAY_SIZE(eht->data) &&
1910 i < ARRAY_SIZE(ppduinfo->eht_info.eht.data);
1911 i++)
1912 eht->data[i] = ppduinfo->eht_info.eht.data[i];
1913
1914 for (user = 0; user < ppduinfo->eht_info.num_user_info; user++)
1915 put_unaligned_le32(ppduinfo->eht_info.user_info[user],
1916 &eht->user_info[user]);
1917
1918 tlv = (struct ieee80211_radiotap_tlv *)&tlv->data[eht_len];
1919 }
1920
1921 if (ppduinfo->eht_usig) {
1922 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG);
1923 tlv->len = cpu_to_le16(usig_len);
1924
1925 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data;
1926 *usig = ppduinfo->u_sig_info.usig;
1927 }
1928 } else if (ppduinfo->he_mu_flags) {
1929 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
1930 rxs->encoding = RX_ENC_HE;
1931 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
1932 ath12k_dp_mon_rx_update_radiotap_he_mu(ppduinfo, ptr);
1933 } else if (ppduinfo->he_flags) {
1934 rxs->flag |= RX_FLAG_RADIOTAP_HE;
1935 rxs->encoding = RX_ENC_HE;
1936 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
1937 ath12k_dp_mon_rx_update_radiotap_he(ppduinfo, ptr);
1938 rxs->rate_idx = ppduinfo->rate;
1939 } else if (ppduinfo->vht_flags) {
1940 rxs->encoding = RX_ENC_VHT;
1941 rxs->rate_idx = ppduinfo->rate;
1942 } else if (ppduinfo->ht_flags) {
1943 rxs->encoding = RX_ENC_HT;
1944 rxs->rate_idx = ppduinfo->rate;
1945 } else {
1946 rxs->encoding = RX_ENC_LEGACY;
1947 sband = &ar->mac.sbands[rxs->band];
1948 rxs->rate_idx = ath12k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
1949 ppduinfo->cck_flag);
1950 }
1951
1952 rxs->mactime = ppduinfo->tsft;
1953 }
1954
ath12k_dp_mon_rx_deliver_msdu(struct ath12k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)1955 static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi,
1956 struct sk_buff *msdu,
1957 struct ieee80211_rx_status *status)
1958 {
1959 static const struct ieee80211_radiotap_he known = {
1960 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1961 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
1962 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
1963 };
1964 struct ieee80211_rx_status *rx_status;
1965 struct ieee80211_radiotap_he *he = NULL;
1966 struct ieee80211_sta *pubsta = NULL;
1967 struct ath12k_peer *peer;
1968 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
1969 u8 decap = DP_RX_DECAP_TYPE_RAW;
1970 bool is_mcbc = rxcb->is_mcbc;
1971 bool is_eapol_tkip = rxcb->is_eapol;
1972
1973 if ((status->encoding == RX_ENC_HE) && !(status->flag & RX_FLAG_RADIOTAP_HE) &&
1974 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
1975 he = skb_push(msdu, sizeof(known));
1976 memcpy(he, &known, sizeof(known));
1977 status->flag |= RX_FLAG_RADIOTAP_HE;
1978 }
1979
1980 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
1981 decap = ath12k_dp_rx_h_decap_type(ar->ab, rxcb->rx_desc);
1982 spin_lock_bh(&ar->ab->base_lock);
1983 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu);
1984 if (peer && peer->sta) {
1985 pubsta = peer->sta;
1986 if (pubsta->valid_links) {
1987 status->link_valid = 1;
1988 status->link_id = peer->link_id;
1989 }
1990 }
1991
1992 spin_unlock_bh(&ar->ab->base_lock);
1993
1994 ath12k_dbg(ar->ab, ATH12K_DBG_DATA,
1995 "rx skb %p len %u peer %pM %u %s %s%s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
1996 msdu,
1997 msdu->len,
1998 peer ? peer->addr : NULL,
1999 rxcb->tid,
2000 (is_mcbc) ? "mcast" : "ucast",
2001 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2002 (status->encoding == RX_ENC_HT) ? "ht" : "",
2003 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2004 (status->encoding == RX_ENC_HE) ? "he" : "",
2005 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2006 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2007 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2008 (status->bw == RATE_INFO_BW_320) ? "320" : "",
2009 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2010 status->rate_idx,
2011 status->nss,
2012 status->freq,
2013 status->band, status->flag,
2014 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2015 !!(status->flag & RX_FLAG_MMIC_ERROR),
2016 !!(status->flag & RX_FLAG_AMSDU_MORE));
2017
2018 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ",
2019 msdu->data, msdu->len);
2020 rx_status = IEEE80211_SKB_RXCB(msdu);
2021 *rx_status = *status;
2022
2023 /* TODO: trace rx packet */
2024
2025 /* PN for multicast packets are not validate in HW,
2026 * so skip 802.3 rx path
2027 * Also, fast_rx expects the STA to be authorized, hence
2028 * eapol packets are sent in slow path.
2029 */
2030 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol_tkip &&
2031 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2032 rx_status->flag |= RX_FLAG_8023;
2033
2034 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi);
2035 }
2036
ath12k_dp_mon_rx_deliver(struct ath12k * ar,struct sk_buff * head_msdu,struct sk_buff * tail_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct napi_struct * napi)2037 static int ath12k_dp_mon_rx_deliver(struct ath12k *ar,
2038 struct sk_buff *head_msdu, struct sk_buff *tail_msdu,
2039 struct hal_rx_mon_ppdu_info *ppduinfo,
2040 struct napi_struct *napi)
2041 {
2042 struct ath12k_pdev_dp *dp = &ar->dp;
2043 struct sk_buff *mon_skb, *skb_next, *header;
2044 struct ieee80211_rx_status *rxs = &dp->rx_status;
2045 bool fcs_err = false;
2046
2047 mon_skb = ath12k_dp_mon_rx_merg_msdus(ar,
2048 head_msdu, tail_msdu,
2049 rxs, &fcs_err);
2050 if (!mon_skb)
2051 goto mon_deliver_fail;
2052
2053 header = mon_skb;
2054 rxs->flag = 0;
2055
2056 if (fcs_err)
2057 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
2058
2059 do {
2060 skb_next = mon_skb->next;
2061 if (!skb_next)
2062 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
2063 else
2064 rxs->flag |= RX_FLAG_AMSDU_MORE;
2065
2066 if (mon_skb == header) {
2067 header = NULL;
2068 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
2069 } else {
2070 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
2071 }
2072 rxs->flag |= RX_FLAG_ONLY_MONITOR;
2073 ath12k_dp_mon_update_radiotap(ar, ppduinfo, mon_skb, rxs);
2074 ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, rxs);
2075 mon_skb = skb_next;
2076 } while (mon_skb);
2077 rxs->flag = 0;
2078
2079 return 0;
2080
2081 mon_deliver_fail:
2082 mon_skb = head_msdu;
2083 while (mon_skb) {
2084 skb_next = mon_skb->next;
2085 dev_kfree_skb_any(mon_skb);
2086 mon_skb = skb_next;
2087 }
2088 return -EINVAL;
2089 }
2090
2091 static enum hal_rx_mon_status
ath12k_dp_mon_parse_rx_dest(struct ath12k * ar,struct ath12k_mon_data * pmon,struct sk_buff * skb)2092 ath12k_dp_mon_parse_rx_dest(struct ath12k *ar, struct ath12k_mon_data *pmon,
2093 struct sk_buff *skb)
2094 {
2095 struct hal_tlv_64_hdr *tlv;
2096 struct ath12k_skb_rxcb *rxcb;
2097 enum hal_rx_mon_status hal_status;
2098 u16 tlv_tag, tlv_len;
2099 u8 *ptr = skb->data;
2100
2101 do {
2102 tlv = (struct hal_tlv_64_hdr *)ptr;
2103 tlv_tag = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_TAG);
2104
2105 /* The actual length of PPDU_END is the combined length of many PHY
2106 * TLVs that follow. Skip the TLV header and
2107 * rx_rxpcu_classification_overview that follows the header to get to
2108 * next TLV.
2109 */
2110
2111 if (tlv_tag == HAL_RX_PPDU_END)
2112 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview);
2113 else
2114 tlv_len = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_LEN);
2115
2116 hal_status = ath12k_dp_mon_rx_parse_status_tlv(ar, pmon, tlv);
2117 ptr += sizeof(*tlv) + tlv_len;
2118 ptr = PTR_ALIGN(ptr, HAL_TLV_64_ALIGN);
2119
2120 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE)
2121 break;
2122
2123 } while ((hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE) ||
2124 (hal_status == HAL_RX_MON_STATUS_BUF_ADDR) ||
2125 (hal_status == HAL_RX_MON_STATUS_MPDU_END) ||
2126 (hal_status == HAL_RX_MON_STATUS_MSDU_END));
2127
2128 rxcb = ATH12K_SKB_RXCB(skb);
2129 if (rxcb->is_end_of_ppdu)
2130 hal_status = HAL_RX_MON_STATUS_PPDU_DONE;
2131
2132 return hal_status;
2133 }
2134
2135 enum hal_rx_mon_status
ath12k_dp_mon_rx_parse_mon_status(struct ath12k * ar,struct ath12k_mon_data * pmon,struct sk_buff * skb,struct napi_struct * napi)2136 ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar,
2137 struct ath12k_mon_data *pmon,
2138 struct sk_buff *skb,
2139 struct napi_struct *napi)
2140 {
2141 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
2142 struct dp_mon_mpdu *tmp;
2143 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
2144 struct sk_buff *head_msdu, *tail_msdu;
2145 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE;
2146
2147 ath12k_dp_mon_parse_rx_dest(ar, pmon, skb);
2148
2149 list_for_each_entry_safe(mon_mpdu, tmp, &pmon->dp_rx_mon_mpdu_list, list) {
2150 list_del(&mon_mpdu->list);
2151 head_msdu = mon_mpdu->head;
2152 tail_msdu = mon_mpdu->tail;
2153
2154 if (head_msdu && tail_msdu) {
2155 ath12k_dp_mon_rx_deliver(ar, head_msdu,
2156 tail_msdu, ppdu_info, napi);
2157 }
2158
2159 kfree(mon_mpdu);
2160 }
2161 return hal_status;
2162 }
2163
ath12k_dp_mon_buf_replenish(struct ath12k_base * ab,struct dp_rxdma_mon_ring * buf_ring,int req_entries)2164 int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab,
2165 struct dp_rxdma_mon_ring *buf_ring,
2166 int req_entries)
2167 {
2168 struct hal_mon_buf_ring *mon_buf;
2169 struct sk_buff *skb;
2170 struct hal_srng *srng;
2171 dma_addr_t paddr;
2172 u32 cookie;
2173 int buf_id;
2174
2175 srng = &ab->hal.srng_list[buf_ring->refill_buf_ring.ring_id];
2176 spin_lock_bh(&srng->lock);
2177 ath12k_hal_srng_access_begin(ab, srng);
2178
2179 while (req_entries > 0) {
2180 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + DP_RX_BUFFER_ALIGN_SIZE);
2181 if (unlikely(!skb))
2182 goto fail_alloc_skb;
2183
2184 if (!IS_ALIGNED((unsigned long)skb->data, DP_RX_BUFFER_ALIGN_SIZE)) {
2185 skb_pull(skb,
2186 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2187 skb->data);
2188 }
2189
2190 paddr = dma_map_single(ab->dev, skb->data,
2191 skb->len + skb_tailroom(skb),
2192 DMA_FROM_DEVICE);
2193
2194 if (unlikely(dma_mapping_error(ab->dev, paddr)))
2195 goto fail_free_skb;
2196
2197 spin_lock_bh(&buf_ring->idr_lock);
2198 buf_id = idr_alloc(&buf_ring->bufs_idr, skb, 0,
2199 buf_ring->bufs_max * 3, GFP_ATOMIC);
2200 spin_unlock_bh(&buf_ring->idr_lock);
2201
2202 if (unlikely(buf_id < 0))
2203 goto fail_dma_unmap;
2204
2205 mon_buf = ath12k_hal_srng_src_get_next_entry(ab, srng);
2206 if (unlikely(!mon_buf))
2207 goto fail_idr_remove;
2208
2209 ATH12K_SKB_RXCB(skb)->paddr = paddr;
2210
2211 cookie = u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID);
2212
2213 mon_buf->paddr_lo = cpu_to_le32(lower_32_bits(paddr));
2214 mon_buf->paddr_hi = cpu_to_le32(upper_32_bits(paddr));
2215 mon_buf->cookie = cpu_to_le64(cookie);
2216
2217 req_entries--;
2218 }
2219
2220 ath12k_hal_srng_access_end(ab, srng);
2221 spin_unlock_bh(&srng->lock);
2222 return 0;
2223
2224 fail_idr_remove:
2225 spin_lock_bh(&buf_ring->idr_lock);
2226 idr_remove(&buf_ring->bufs_idr, buf_id);
2227 spin_unlock_bh(&buf_ring->idr_lock);
2228 fail_dma_unmap:
2229 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2230 DMA_FROM_DEVICE);
2231 fail_free_skb:
2232 dev_kfree_skb_any(skb);
2233 fail_alloc_skb:
2234 ath12k_hal_srng_access_end(ab, srng);
2235 spin_unlock_bh(&srng->lock);
2236 return -ENOMEM;
2237 }
2238
2239 static struct dp_mon_tx_ppdu_info *
ath12k_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data * pmon,unsigned int ppdu_id,enum dp_mon_tx_ppdu_info_type type)2240 ath12k_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data *pmon,
2241 unsigned int ppdu_id,
2242 enum dp_mon_tx_ppdu_info_type type)
2243 {
2244 struct dp_mon_tx_ppdu_info *tx_ppdu_info;
2245
2246 if (type == DP_MON_TX_PROT_PPDU_INFO) {
2247 tx_ppdu_info = pmon->tx_prot_ppdu_info;
2248
2249 if (tx_ppdu_info && !tx_ppdu_info->is_used)
2250 return tx_ppdu_info;
2251 kfree(tx_ppdu_info);
2252 } else {
2253 tx_ppdu_info = pmon->tx_data_ppdu_info;
2254
2255 if (tx_ppdu_info && !tx_ppdu_info->is_used)
2256 return tx_ppdu_info;
2257 kfree(tx_ppdu_info);
2258 }
2259
2260 /* allocate new tx_ppdu_info */
2261 tx_ppdu_info = kzalloc(sizeof(*tx_ppdu_info), GFP_ATOMIC);
2262 if (!tx_ppdu_info)
2263 return NULL;
2264
2265 tx_ppdu_info->is_used = 0;
2266 tx_ppdu_info->ppdu_id = ppdu_id;
2267
2268 if (type == DP_MON_TX_PROT_PPDU_INFO)
2269 pmon->tx_prot_ppdu_info = tx_ppdu_info;
2270 else
2271 pmon->tx_data_ppdu_info = tx_ppdu_info;
2272
2273 return tx_ppdu_info;
2274 }
2275
2276 static struct dp_mon_tx_ppdu_info *
ath12k_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data * pmon,u16 tlv_tag)2277 ath12k_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data *pmon,
2278 u16 tlv_tag)
2279 {
2280 switch (tlv_tag) {
2281 case HAL_TX_FES_SETUP:
2282 case HAL_TX_FLUSH:
2283 case HAL_PCU_PPDU_SETUP_INIT:
2284 case HAL_TX_PEER_ENTRY:
2285 case HAL_TX_QUEUE_EXTENSION:
2286 case HAL_TX_MPDU_START:
2287 case HAL_TX_MSDU_START:
2288 case HAL_TX_DATA:
2289 case HAL_MON_BUF_ADDR:
2290 case HAL_TX_MPDU_END:
2291 case HAL_TX_LAST_MPDU_FETCHED:
2292 case HAL_TX_LAST_MPDU_END:
2293 case HAL_COEX_TX_REQ:
2294 case HAL_TX_RAW_OR_NATIVE_FRAME_SETUP:
2295 case HAL_SCH_CRITICAL_TLV_REFERENCE:
2296 case HAL_TX_FES_SETUP_COMPLETE:
2297 case HAL_TQM_MPDU_GLOBAL_START:
2298 case HAL_SCHEDULER_END:
2299 case HAL_TX_FES_STATUS_USER_PPDU:
2300 break;
2301 case HAL_TX_FES_STATUS_PROT: {
2302 if (!pmon->tx_prot_ppdu_info->is_used)
2303 pmon->tx_prot_ppdu_info->is_used = true;
2304
2305 return pmon->tx_prot_ppdu_info;
2306 }
2307 }
2308
2309 if (!pmon->tx_data_ppdu_info->is_used)
2310 pmon->tx_data_ppdu_info->is_used = true;
2311
2312 return pmon->tx_data_ppdu_info;
2313 }
2314
2315 #define MAX_MONITOR_HEADER 512
2316 #define MAX_DUMMY_FRM_BODY 128
2317
ath12k_dp_mon_tx_alloc_skb(void)2318 struct sk_buff *ath12k_dp_mon_tx_alloc_skb(void)
2319 {
2320 struct sk_buff *skb;
2321
2322 skb = dev_alloc_skb(MAX_MONITOR_HEADER + MAX_DUMMY_FRM_BODY);
2323 if (!skb)
2324 return NULL;
2325
2326 skb_reserve(skb, MAX_MONITOR_HEADER);
2327
2328 if (!IS_ALIGNED((unsigned long)skb->data, 4))
2329 skb_pull(skb, PTR_ALIGN(skb->data, 4) - skb->data);
2330
2331 return skb;
2332 }
2333
2334 static int
ath12k_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)2335 ath12k_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
2336 {
2337 struct sk_buff *skb;
2338 struct ieee80211_cts *cts;
2339
2340 skb = ath12k_dp_mon_tx_alloc_skb();
2341 if (!skb)
2342 return -ENOMEM;
2343
2344 cts = (struct ieee80211_cts *)skb->data;
2345 memset(cts, 0, MAX_DUMMY_FRM_BODY);
2346 cts->frame_control =
2347 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CTS);
2348 cts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
2349 memcpy(cts->ra, tx_ppdu_info->rx_status.addr1, sizeof(cts->ra));
2350
2351 skb_put(skb, sizeof(*cts));
2352 tx_ppdu_info->tx_mon_mpdu->head = skb;
2353 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
2354 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
2355 &tx_ppdu_info->dp_tx_mon_mpdu_list);
2356
2357 return 0;
2358 }
2359
2360 static int
ath12k_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)2361 ath12k_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
2362 {
2363 struct sk_buff *skb;
2364 struct ieee80211_rts *rts;
2365
2366 skb = ath12k_dp_mon_tx_alloc_skb();
2367 if (!skb)
2368 return -ENOMEM;
2369
2370 rts = (struct ieee80211_rts *)skb->data;
2371 memset(rts, 0, MAX_DUMMY_FRM_BODY);
2372 rts->frame_control =
2373 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS);
2374 rts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
2375 memcpy(rts->ra, tx_ppdu_info->rx_status.addr1, sizeof(rts->ra));
2376 memcpy(rts->ta, tx_ppdu_info->rx_status.addr2, sizeof(rts->ta));
2377
2378 skb_put(skb, sizeof(*rts));
2379 tx_ppdu_info->tx_mon_mpdu->head = skb;
2380 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
2381 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
2382 &tx_ppdu_info->dp_tx_mon_mpdu_list);
2383
2384 return 0;
2385 }
2386
2387 static int
ath12k_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)2388 ath12k_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
2389 {
2390 struct sk_buff *skb;
2391 struct ieee80211_qos_hdr *qhdr;
2392
2393 skb = ath12k_dp_mon_tx_alloc_skb();
2394 if (!skb)
2395 return -ENOMEM;
2396
2397 qhdr = (struct ieee80211_qos_hdr *)skb->data;
2398 memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
2399 qhdr->frame_control =
2400 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
2401 qhdr->duration_id = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
2402 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
2403 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
2404 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
2405
2406 skb_put(skb, sizeof(*qhdr));
2407 tx_ppdu_info->tx_mon_mpdu->head = skb;
2408 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
2409 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
2410 &tx_ppdu_info->dp_tx_mon_mpdu_list);
2411
2412 return 0;
2413 }
2414
2415 static int
ath12k_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)2416 ath12k_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
2417 {
2418 struct sk_buff *skb;
2419 struct dp_mon_qosframe_addr4 *qhdr;
2420
2421 skb = ath12k_dp_mon_tx_alloc_skb();
2422 if (!skb)
2423 return -ENOMEM;
2424
2425 qhdr = (struct dp_mon_qosframe_addr4 *)skb->data;
2426 memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
2427 qhdr->frame_control =
2428 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
2429 qhdr->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
2430 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
2431 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
2432 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
2433 memcpy(qhdr->addr4, tx_ppdu_info->rx_status.addr4, ETH_ALEN);
2434
2435 skb_put(skb, sizeof(*qhdr));
2436 tx_ppdu_info->tx_mon_mpdu->head = skb;
2437 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
2438 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
2439 &tx_ppdu_info->dp_tx_mon_mpdu_list);
2440
2441 return 0;
2442 }
2443
2444 static int
ath12k_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)2445 ath12k_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
2446 {
2447 struct sk_buff *skb;
2448 struct dp_mon_frame_min_one *fbmhdr;
2449
2450 skb = ath12k_dp_mon_tx_alloc_skb();
2451 if (!skb)
2452 return -ENOMEM;
2453
2454 fbmhdr = (struct dp_mon_frame_min_one *)skb->data;
2455 memset(fbmhdr, 0, MAX_DUMMY_FRM_BODY);
2456 fbmhdr->frame_control =
2457 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_CFACK);
2458 memcpy(fbmhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
2459
2460 /* set duration zero for ack frame */
2461 fbmhdr->duration = 0;
2462
2463 skb_put(skb, sizeof(*fbmhdr));
2464 tx_ppdu_info->tx_mon_mpdu->head = skb;
2465 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
2466 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
2467 &tx_ppdu_info->dp_tx_mon_mpdu_list);
2468
2469 return 0;
2470 }
2471
2472 static int
ath12k_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)2473 ath12k_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
2474 {
2475 int ret = 0;
2476
2477 switch (tx_ppdu_info->rx_status.medium_prot_type) {
2478 case DP_MON_TX_MEDIUM_RTS_LEGACY:
2479 case DP_MON_TX_MEDIUM_RTS_11AC_STATIC_BW:
2480 case DP_MON_TX_MEDIUM_RTS_11AC_DYNAMIC_BW:
2481 ret = ath12k_dp_mon_tx_gen_rts_frame(tx_ppdu_info);
2482 break;
2483 case DP_MON_TX_MEDIUM_CTS2SELF:
2484 ret = ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
2485 break;
2486 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_3ADDR:
2487 ret = ath12k_dp_mon_tx_gen_3addr_qos_null_frame(tx_ppdu_info);
2488 break;
2489 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_4ADDR:
2490 ret = ath12k_dp_mon_tx_gen_4addr_qos_null_frame(tx_ppdu_info);
2491 break;
2492 }
2493
2494 return ret;
2495 }
2496
2497 static enum dp_mon_tx_tlv_status
ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base * ab,struct ath12k_mon_data * pmon,u16 tlv_tag,const void * tlv_data,u32 userid)2498 ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base *ab,
2499 struct ath12k_mon_data *pmon,
2500 u16 tlv_tag, const void *tlv_data, u32 userid)
2501 {
2502 struct dp_mon_tx_ppdu_info *tx_ppdu_info;
2503 enum dp_mon_tx_tlv_status status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
2504 u32 info[7];
2505
2506 tx_ppdu_info = ath12k_dp_mon_hal_tx_ppdu_info(pmon, tlv_tag);
2507
2508 switch (tlv_tag) {
2509 case HAL_TX_FES_SETUP: {
2510 const struct hal_tx_fes_setup *tx_fes_setup = tlv_data;
2511
2512 info[0] = __le32_to_cpu(tx_fes_setup->info0);
2513 tx_ppdu_info->ppdu_id = __le32_to_cpu(tx_fes_setup->schedule_id);
2514 tx_ppdu_info->num_users =
2515 u32_get_bits(info[0], HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
2516 status = DP_MON_TX_FES_SETUP;
2517 break;
2518 }
2519
2520 case HAL_TX_FES_STATUS_END: {
2521 const struct hal_tx_fes_status_end *tx_fes_status_end = tlv_data;
2522 u32 tst_15_0, tst_31_16;
2523
2524 info[0] = __le32_to_cpu(tx_fes_status_end->info0);
2525 tst_15_0 =
2526 u32_get_bits(info[0],
2527 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0);
2528 tst_31_16 =
2529 u32_get_bits(info[0],
2530 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16);
2531
2532 tx_ppdu_info->rx_status.ppdu_ts = (tst_15_0 | (tst_31_16 << 16));
2533 status = DP_MON_TX_FES_STATUS_END;
2534 break;
2535 }
2536
2537 case HAL_RX_RESPONSE_REQUIRED_INFO: {
2538 const struct hal_rx_resp_req_info *rx_resp_req_info = tlv_data;
2539 u32 addr_32;
2540 u16 addr_16;
2541
2542 info[0] = __le32_to_cpu(rx_resp_req_info->info0);
2543 info[1] = __le32_to_cpu(rx_resp_req_info->info1);
2544 info[2] = __le32_to_cpu(rx_resp_req_info->info2);
2545 info[3] = __le32_to_cpu(rx_resp_req_info->info3);
2546 info[4] = __le32_to_cpu(rx_resp_req_info->info4);
2547 info[5] = __le32_to_cpu(rx_resp_req_info->info5);
2548
2549 tx_ppdu_info->rx_status.ppdu_id =
2550 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_PPDU_ID);
2551 tx_ppdu_info->rx_status.reception_type =
2552 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE);
2553 tx_ppdu_info->rx_status.rx_duration =
2554 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_DURATION);
2555 tx_ppdu_info->rx_status.mcs =
2556 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_RATE_MCS);
2557 tx_ppdu_info->rx_status.sgi =
2558 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_SGI);
2559 tx_ppdu_info->rx_status.is_stbc =
2560 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_STBC);
2561 tx_ppdu_info->rx_status.ldpc =
2562 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_LDPC);
2563 tx_ppdu_info->rx_status.is_ampdu =
2564 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_IS_AMPDU);
2565 tx_ppdu_info->rx_status.num_users =
2566 u32_get_bits(info[2], HAL_RX_RESP_REQ_INFO2_NUM_USER);
2567
2568 addr_32 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO3_ADDR1_31_0);
2569 addr_16 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO4_ADDR1_47_32);
2570 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
2571
2572 addr_16 = u32_get_bits(info[4], HAL_RX_RESP_REQ_INFO4_ADDR1_15_0);
2573 addr_32 = u32_get_bits(info[5], HAL_RX_RESP_REQ_INFO5_ADDR1_47_16);
2574 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
2575
2576 if (tx_ppdu_info->rx_status.reception_type == 0)
2577 ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
2578 status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
2579 break;
2580 }
2581
2582 case HAL_PCU_PPDU_SETUP_INIT: {
2583 const struct hal_tx_pcu_ppdu_setup_init *ppdu_setup = tlv_data;
2584 u32 addr_32;
2585 u16 addr_16;
2586
2587 info[0] = __le32_to_cpu(ppdu_setup->info0);
2588 info[1] = __le32_to_cpu(ppdu_setup->info1);
2589 info[2] = __le32_to_cpu(ppdu_setup->info2);
2590 info[3] = __le32_to_cpu(ppdu_setup->info3);
2591 info[4] = __le32_to_cpu(ppdu_setup->info4);
2592 info[5] = __le32_to_cpu(ppdu_setup->info5);
2593 info[6] = __le32_to_cpu(ppdu_setup->info6);
2594
2595 /* protection frame address 1 */
2596 addr_32 = u32_get_bits(info[1],
2597 HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0);
2598 addr_16 = u32_get_bits(info[2],
2599 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32);
2600 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
2601
2602 /* protection frame address 2 */
2603 addr_16 = u32_get_bits(info[2],
2604 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0);
2605 addr_32 = u32_get_bits(info[3],
2606 HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16);
2607 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
2608
2609 /* protection frame address 3 */
2610 addr_32 = u32_get_bits(info[4],
2611 HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0);
2612 addr_16 = u32_get_bits(info[5],
2613 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32);
2614 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr3);
2615
2616 /* protection frame address 4 */
2617 addr_16 = u32_get_bits(info[5],
2618 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0);
2619 addr_32 = u32_get_bits(info[6],
2620 HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16);
2621 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr4);
2622
2623 status = u32_get_bits(info[0],
2624 HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE);
2625 break;
2626 }
2627
2628 case HAL_TX_QUEUE_EXTENSION: {
2629 const struct hal_tx_queue_exten *tx_q_exten = tlv_data;
2630
2631 info[0] = __le32_to_cpu(tx_q_exten->info0);
2632
2633 tx_ppdu_info->rx_status.frame_control =
2634 u32_get_bits(info[0],
2635 HAL_TX_Q_EXT_INFO0_FRAME_CTRL);
2636 tx_ppdu_info->rx_status.fc_valid = true;
2637 break;
2638 }
2639
2640 case HAL_TX_FES_STATUS_START: {
2641 const struct hal_tx_fes_status_start *tx_fes_start = tlv_data;
2642
2643 info[0] = __le32_to_cpu(tx_fes_start->info0);
2644
2645 tx_ppdu_info->rx_status.medium_prot_type =
2646 u32_get_bits(info[0],
2647 HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE);
2648 break;
2649 }
2650
2651 case HAL_TX_FES_STATUS_PROT: {
2652 const struct hal_tx_fes_status_prot *tx_fes_status = tlv_data;
2653 u32 start_timestamp;
2654 u32 end_timestamp;
2655
2656 info[0] = __le32_to_cpu(tx_fes_status->info0);
2657 info[1] = __le32_to_cpu(tx_fes_status->info1);
2658
2659 start_timestamp =
2660 u32_get_bits(info[0],
2661 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0);
2662 start_timestamp |=
2663 u32_get_bits(info[0],
2664 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16) << 15;
2665 end_timestamp =
2666 u32_get_bits(info[1],
2667 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0);
2668 end_timestamp |=
2669 u32_get_bits(info[1],
2670 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16) << 15;
2671 tx_ppdu_info->rx_status.rx_duration = end_timestamp - start_timestamp;
2672
2673 ath12k_dp_mon_tx_gen_prot_frame(tx_ppdu_info);
2674 break;
2675 }
2676
2677 case HAL_TX_FES_STATUS_START_PPDU:
2678 case HAL_TX_FES_STATUS_START_PROT: {
2679 const struct hal_tx_fes_status_start_prot *tx_fes_stat_start = tlv_data;
2680 u64 ppdu_ts;
2681
2682 info[0] = __le32_to_cpu(tx_fes_stat_start->info0);
2683
2684 tx_ppdu_info->rx_status.ppdu_ts =
2685 u32_get_bits(info[0],
2686 HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32);
2687 ppdu_ts = (u32_get_bits(info[1],
2688 HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32));
2689 tx_ppdu_info->rx_status.ppdu_ts |= ppdu_ts << 32;
2690 break;
2691 }
2692
2693 case HAL_TX_FES_STATUS_USER_PPDU: {
2694 const struct hal_tx_fes_status_user_ppdu *tx_fes_usr_ppdu = tlv_data;
2695
2696 info[0] = __le32_to_cpu(tx_fes_usr_ppdu->info0);
2697
2698 tx_ppdu_info->rx_status.rx_duration =
2699 u32_get_bits(info[0],
2700 HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION);
2701 break;
2702 }
2703
2704 case HAL_MACTX_HE_SIG_A_SU:
2705 ath12k_dp_mon_parse_he_sig_su(tlv_data, &tx_ppdu_info->rx_status);
2706 break;
2707
2708 case HAL_MACTX_HE_SIG_A_MU_DL:
2709 ath12k_dp_mon_parse_he_sig_mu(tlv_data, &tx_ppdu_info->rx_status);
2710 break;
2711
2712 case HAL_MACTX_HE_SIG_B1_MU:
2713 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, &tx_ppdu_info->rx_status);
2714 break;
2715
2716 case HAL_MACTX_HE_SIG_B2_MU:
2717 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, &tx_ppdu_info->rx_status);
2718 break;
2719
2720 case HAL_MACTX_HE_SIG_B2_OFDMA:
2721 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, &tx_ppdu_info->rx_status);
2722 break;
2723
2724 case HAL_MACTX_VHT_SIG_A:
2725 ath12k_dp_mon_parse_vht_sig_a(tlv_data, &tx_ppdu_info->rx_status);
2726 break;
2727
2728 case HAL_MACTX_L_SIG_A:
2729 ath12k_dp_mon_parse_l_sig_a(tlv_data, &tx_ppdu_info->rx_status);
2730 break;
2731
2732 case HAL_MACTX_L_SIG_B:
2733 ath12k_dp_mon_parse_l_sig_b(tlv_data, &tx_ppdu_info->rx_status);
2734 break;
2735
2736 case HAL_RX_FRAME_BITMAP_ACK: {
2737 const struct hal_rx_frame_bitmap_ack *fbm_ack = tlv_data;
2738 u32 addr_32;
2739 u16 addr_16;
2740
2741 info[0] = __le32_to_cpu(fbm_ack->info0);
2742 info[1] = __le32_to_cpu(fbm_ack->info1);
2743
2744 addr_32 = u32_get_bits(info[0],
2745 HAL_RX_FBM_ACK_INFO0_ADDR1_31_0);
2746 addr_16 = u32_get_bits(info[1],
2747 HAL_RX_FBM_ACK_INFO1_ADDR1_47_32);
2748 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
2749
2750 ath12k_dp_mon_tx_gen_ack_frame(tx_ppdu_info);
2751 break;
2752 }
2753
2754 case HAL_MACTX_PHY_DESC: {
2755 const struct hal_tx_phy_desc *tx_phy_desc = tlv_data;
2756
2757 info[0] = __le32_to_cpu(tx_phy_desc->info0);
2758 info[1] = __le32_to_cpu(tx_phy_desc->info1);
2759 info[2] = __le32_to_cpu(tx_phy_desc->info2);
2760 info[3] = __le32_to_cpu(tx_phy_desc->info3);
2761
2762 tx_ppdu_info->rx_status.beamformed =
2763 u32_get_bits(info[0],
2764 HAL_TX_PHY_DESC_INFO0_BF_TYPE);
2765 tx_ppdu_info->rx_status.preamble_type =
2766 u32_get_bits(info[0],
2767 HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B);
2768 tx_ppdu_info->rx_status.mcs =
2769 u32_get_bits(info[1],
2770 HAL_TX_PHY_DESC_INFO1_MCS);
2771 tx_ppdu_info->rx_status.ltf_size =
2772 u32_get_bits(info[3],
2773 HAL_TX_PHY_DESC_INFO3_LTF_SIZE);
2774 tx_ppdu_info->rx_status.nss =
2775 u32_get_bits(info[2],
2776 HAL_TX_PHY_DESC_INFO2_NSS);
2777 tx_ppdu_info->rx_status.chan_num =
2778 u32_get_bits(info[3],
2779 HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL);
2780 tx_ppdu_info->rx_status.bw =
2781 u32_get_bits(info[0],
2782 HAL_TX_PHY_DESC_INFO0_BANDWIDTH);
2783 break;
2784 }
2785
2786 case HAL_TX_MPDU_START: {
2787 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu;
2788
2789 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
2790 if (!mon_mpdu)
2791 return DP_MON_TX_STATUS_PPDU_NOT_DONE;
2792 status = DP_MON_TX_MPDU_START;
2793 break;
2794 }
2795
2796 case HAL_TX_MPDU_END:
2797 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
2798 &tx_ppdu_info->dp_tx_mon_mpdu_list);
2799 break;
2800 }
2801
2802 return status;
2803 }
2804
2805 enum dp_mon_tx_tlv_status
ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag,struct hal_tlv_hdr * tx_tlv,u8 * num_users)2806 ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag,
2807 struct hal_tlv_hdr *tx_tlv,
2808 u8 *num_users)
2809 {
2810 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
2811 u32 info0;
2812
2813 switch (tlv_tag) {
2814 case HAL_TX_FES_SETUP: {
2815 struct hal_tx_fes_setup *tx_fes_setup =
2816 (struct hal_tx_fes_setup *)tx_tlv;
2817
2818 info0 = __le32_to_cpu(tx_fes_setup->info0);
2819
2820 *num_users = u32_get_bits(info0, HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
2821 tlv_status = DP_MON_TX_FES_SETUP;
2822 break;
2823 }
2824
2825 case HAL_RX_RESPONSE_REQUIRED_INFO: {
2826 /* TODO: need to update *num_users */
2827 tlv_status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
2828 break;
2829 }
2830 }
2831
2832 return tlv_status;
2833 }
2834
2835 static void
ath12k_dp_mon_tx_process_ppdu_info(struct ath12k * ar,struct napi_struct * napi,struct dp_mon_tx_ppdu_info * tx_ppdu_info)2836 ath12k_dp_mon_tx_process_ppdu_info(struct ath12k *ar,
2837 struct napi_struct *napi,
2838 struct dp_mon_tx_ppdu_info *tx_ppdu_info)
2839 {
2840 struct dp_mon_mpdu *tmp, *mon_mpdu;
2841 struct sk_buff *head_msdu, *tail_msdu;
2842
2843 list_for_each_entry_safe(mon_mpdu, tmp,
2844 &tx_ppdu_info->dp_tx_mon_mpdu_list, list) {
2845 list_del(&mon_mpdu->list);
2846 head_msdu = mon_mpdu->head;
2847 tail_msdu = mon_mpdu->tail;
2848
2849 if (head_msdu)
2850 ath12k_dp_mon_rx_deliver(ar, head_msdu, tail_msdu,
2851 &tx_ppdu_info->rx_status, napi);
2852
2853 kfree(mon_mpdu);
2854 }
2855 }
2856
2857 enum hal_rx_mon_status
ath12k_dp_mon_tx_parse_mon_status(struct ath12k * ar,struct ath12k_mon_data * pmon,struct sk_buff * skb,struct napi_struct * napi,u32 ppdu_id)2858 ath12k_dp_mon_tx_parse_mon_status(struct ath12k *ar,
2859 struct ath12k_mon_data *pmon,
2860 struct sk_buff *skb,
2861 struct napi_struct *napi,
2862 u32 ppdu_id)
2863 {
2864 struct ath12k_base *ab = ar->ab;
2865 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info, *tx_data_ppdu_info;
2866 struct hal_tlv_hdr *tlv;
2867 u8 *ptr = skb->data;
2868 u16 tlv_tag;
2869 u16 tlv_len;
2870 u32 tlv_userid = 0;
2871 u8 num_user;
2872 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
2873
2874 tx_prot_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
2875 DP_MON_TX_PROT_PPDU_INFO);
2876 if (!tx_prot_ppdu_info)
2877 return -ENOMEM;
2878
2879 tlv = (struct hal_tlv_hdr *)ptr;
2880 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
2881
2882 tlv_status = ath12k_dp_mon_tx_status_get_num_user(tlv_tag, tlv, &num_user);
2883 if (tlv_status == DP_MON_TX_STATUS_PPDU_NOT_DONE || !num_user)
2884 return -EINVAL;
2885
2886 tx_data_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
2887 DP_MON_TX_DATA_PPDU_INFO);
2888 if (!tx_data_ppdu_info)
2889 return -ENOMEM;
2890
2891 do {
2892 tlv = (struct hal_tlv_hdr *)ptr;
2893 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
2894 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN);
2895 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID);
2896
2897 tlv_status = ath12k_dp_mon_tx_parse_status_tlv(ab, pmon,
2898 tlv_tag, ptr,
2899 tlv_userid);
2900 ptr += tlv_len;
2901 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
2902 if ((ptr - skb->data) >= DP_TX_MONITOR_BUF_SIZE)
2903 break;
2904 } while (tlv_status != DP_MON_TX_FES_STATUS_END);
2905
2906 ath12k_dp_mon_tx_process_ppdu_info(ar, napi, tx_data_ppdu_info);
2907 ath12k_dp_mon_tx_process_ppdu_info(ar, napi, tx_prot_ppdu_info);
2908
2909 return tlv_status;
2910 }
2911
2912 static void
ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats * rx_stats,struct hal_rx_mon_ppdu_info * ppdu_info,struct hal_rx_user_status * user_stats,u32 num_msdu)2913 ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats *rx_stats,
2914 struct hal_rx_mon_ppdu_info *ppdu_info,
2915 struct hal_rx_user_status *user_stats,
2916 u32 num_msdu)
2917 {
2918 struct ath12k_rx_peer_rate_stats *stats;
2919 u32 mcs_idx = (user_stats) ? user_stats->mcs : ppdu_info->mcs;
2920 u32 nss_idx = (user_stats) ? user_stats->nss - 1 : ppdu_info->nss - 1;
2921 u32 bw_idx = ppdu_info->bw;
2922 u32 gi_idx = ppdu_info->gi;
2923 u32 len;
2924
2925 if (mcs_idx > HAL_RX_MAX_MCS_HT || nss_idx >= HAL_RX_MAX_NSS ||
2926 bw_idx >= HAL_RX_BW_MAX || gi_idx >= HAL_RX_GI_MAX) {
2927 return;
2928 }
2929
2930 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX ||
2931 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11BE)
2932 gi_idx = ath12k_he_gi_to_nl80211_he_gi(ppdu_info->gi);
2933
2934 rx_stats->pkt_stats.rx_rate[bw_idx][gi_idx][nss_idx][mcs_idx] += num_msdu;
2935 stats = &rx_stats->byte_stats;
2936
2937 if (user_stats)
2938 len = user_stats->mpdu_ok_byte_count;
2939 else
2940 len = ppdu_info->mpdu_len;
2941
2942 stats->rx_rate[bw_idx][gi_idx][nss_idx][mcs_idx] += len;
2943 }
2944
ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k * ar,struct ath12k_link_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2945 static void ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k *ar,
2946 struct ath12k_link_sta *arsta,
2947 struct hal_rx_mon_ppdu_info *ppdu_info)
2948 {
2949 struct ath12k_rx_peer_stats *rx_stats = arsta->rx_stats;
2950 u32 num_msdu;
2951
2952 if (!rx_stats)
2953 return;
2954
2955 arsta->rssi_comb = ppdu_info->rssi_comb;
2956 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
2957
2958 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2959 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2960
2961 rx_stats->num_msdu += num_msdu;
2962 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2963 ppdu_info->tcp_ack_msdu_count;
2964 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2965 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2966
2967 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2968 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2969 ppdu_info->nss = 1;
2970 ppdu_info->mcs = HAL_RX_MAX_MCS;
2971 ppdu_info->tid = IEEE80211_NUM_TIDS;
2972 }
2973
2974 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2975 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2976
2977 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2978 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2979
2980 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2981 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2982
2983 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2984 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2985
2986 if (ppdu_info->is_stbc)
2987 rx_stats->stbc_count += num_msdu;
2988
2989 if (ppdu_info->beamformed)
2990 rx_stats->beamformed_count += num_msdu;
2991
2992 if (ppdu_info->num_mpdu_fcs_ok > 1)
2993 rx_stats->ampdu_msdu_count += num_msdu;
2994 else
2995 rx_stats->non_ampdu_msdu_count += num_msdu;
2996
2997 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2998 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2999 rx_stats->dcm_count += ppdu_info->dcm;
3000
3001 rx_stats->rx_duration += ppdu_info->rx_duration;
3002 arsta->rx_duration = rx_stats->rx_duration;
3003
3004 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) {
3005 rx_stats->pkt_stats.nss_count[ppdu_info->nss - 1] += num_msdu;
3006 rx_stats->byte_stats.nss_count[ppdu_info->nss - 1] += ppdu_info->mpdu_len;
3007 }
3008
3009 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N &&
3010 ppdu_info->mcs <= HAL_RX_MAX_MCS_HT) {
3011 rx_stats->pkt_stats.ht_mcs_count[ppdu_info->mcs] += num_msdu;
3012 rx_stats->byte_stats.ht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
3013 /* To fit into rate table for HT packets */
3014 ppdu_info->mcs = ppdu_info->mcs % 8;
3015 }
3016
3017 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC &&
3018 ppdu_info->mcs <= HAL_RX_MAX_MCS_VHT) {
3019 rx_stats->pkt_stats.vht_mcs_count[ppdu_info->mcs] += num_msdu;
3020 rx_stats->byte_stats.vht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
3021 }
3022
3023 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX &&
3024 ppdu_info->mcs <= HAL_RX_MAX_MCS_HE) {
3025 rx_stats->pkt_stats.he_mcs_count[ppdu_info->mcs] += num_msdu;
3026 rx_stats->byte_stats.he_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
3027 }
3028
3029 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11BE &&
3030 ppdu_info->mcs <= HAL_RX_MAX_MCS_BE) {
3031 rx_stats->pkt_stats.be_mcs_count[ppdu_info->mcs] += num_msdu;
3032 rx_stats->byte_stats.be_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len;
3033 }
3034
3035 if ((ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
3036 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) &&
3037 ppdu_info->rate < HAL_RX_LEGACY_RATE_INVALID) {
3038 rx_stats->pkt_stats.legacy_count[ppdu_info->rate] += num_msdu;
3039 rx_stats->byte_stats.legacy_count[ppdu_info->rate] += ppdu_info->mpdu_len;
3040 }
3041
3042 if (ppdu_info->gi < HAL_RX_GI_MAX) {
3043 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu;
3044 rx_stats->byte_stats.gi_count[ppdu_info->gi] += ppdu_info->mpdu_len;
3045 }
3046
3047 if (ppdu_info->bw < HAL_RX_BW_MAX) {
3048 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu;
3049 rx_stats->byte_stats.bw_count[ppdu_info->bw] += ppdu_info->mpdu_len;
3050 }
3051
3052 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info,
3053 NULL, num_msdu);
3054 }
3055
ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info * ppdu_info)3056 void ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info *ppdu_info)
3057 {
3058 struct hal_rx_user_status *rx_user_status;
3059 u32 num_users, i, mu_ul_user_v0_word0, mu_ul_user_v0_word1, ru_size;
3060
3061 if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO ||
3062 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
3063 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO))
3064 return;
3065
3066 num_users = ppdu_info->num_users;
3067 if (num_users > HAL_MAX_UL_MU_USERS)
3068 num_users = HAL_MAX_UL_MU_USERS;
3069
3070 for (i = 0; i < num_users; i++) {
3071 rx_user_status = &ppdu_info->userstats[i];
3072 mu_ul_user_v0_word0 =
3073 rx_user_status->ul_ofdma_user_v0_word0;
3074 mu_ul_user_v0_word1 =
3075 rx_user_status->ul_ofdma_user_v0_word1;
3076
3077 if (u32_get_bits(mu_ul_user_v0_word0,
3078 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID) &&
3079 !u32_get_bits(mu_ul_user_v0_word0,
3080 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER)) {
3081 rx_user_status->mcs =
3082 u32_get_bits(mu_ul_user_v0_word1,
3083 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS);
3084 rx_user_status->nss =
3085 u32_get_bits(mu_ul_user_v0_word1,
3086 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS) + 1;
3087
3088 rx_user_status->ofdma_info_valid = 1;
3089 rx_user_status->ul_ofdma_ru_start_index =
3090 u32_get_bits(mu_ul_user_v0_word1,
3091 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START);
3092
3093 ru_size = u32_get_bits(mu_ul_user_v0_word1,
3094 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE);
3095 rx_user_status->ul_ofdma_ru_width = ru_size;
3096 rx_user_status->ul_ofdma_ru_size = ru_size;
3097 }
3098 rx_user_status->ldpc = u32_get_bits(mu_ul_user_v0_word1,
3099 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC);
3100 }
3101 ppdu_info->ldpc = 1;
3102 }
3103
3104 static void
ath12k_dp_mon_rx_update_user_stats(struct ath12k * ar,struct hal_rx_mon_ppdu_info * ppdu_info,u32 uid)3105 ath12k_dp_mon_rx_update_user_stats(struct ath12k *ar,
3106 struct hal_rx_mon_ppdu_info *ppdu_info,
3107 u32 uid)
3108 {
3109 struct ath12k_sta *ahsta;
3110 struct ath12k_link_sta *arsta;
3111 struct ath12k_rx_peer_stats *rx_stats = NULL;
3112 struct hal_rx_user_status *user_stats = &ppdu_info->userstats[uid];
3113 struct ath12k_peer *peer;
3114 u32 num_msdu;
3115
3116 if (user_stats->ast_index == 0 || user_stats->ast_index == 0xFFFF)
3117 return;
3118
3119 peer = ath12k_peer_find_by_ast(ar->ab, user_stats->ast_index);
3120
3121 if (!peer) {
3122 ath12k_warn(ar->ab, "peer ast idx %d can't be found\n",
3123 user_stats->ast_index);
3124 return;
3125 }
3126
3127 ahsta = ath12k_sta_to_ahsta(peer->sta);
3128 arsta = &ahsta->deflink;
3129 rx_stats = arsta->rx_stats;
3130
3131 if (!rx_stats)
3132 return;
3133
3134 arsta->rssi_comb = ppdu_info->rssi_comb;
3135 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
3136
3137 num_msdu = user_stats->tcp_msdu_count + user_stats->tcp_ack_msdu_count +
3138 user_stats->udp_msdu_count + user_stats->other_msdu_count;
3139
3140 rx_stats->num_msdu += num_msdu;
3141 rx_stats->tcp_msdu_count += user_stats->tcp_msdu_count +
3142 user_stats->tcp_ack_msdu_count;
3143 rx_stats->udp_msdu_count += user_stats->udp_msdu_count;
3144 rx_stats->other_msdu_count += user_stats->other_msdu_count;
3145
3146 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
3147 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
3148
3149 if (user_stats->tid <= IEEE80211_NUM_TIDS)
3150 rx_stats->tid_count[user_stats->tid] += num_msdu;
3151
3152 if (user_stats->preamble_type < HAL_RX_PREAMBLE_MAX)
3153 rx_stats->pream_cnt[user_stats->preamble_type] += num_msdu;
3154
3155 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
3156 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
3157
3158 if (ppdu_info->is_stbc)
3159 rx_stats->stbc_count += num_msdu;
3160
3161 if (ppdu_info->beamformed)
3162 rx_stats->beamformed_count += num_msdu;
3163
3164 if (user_stats->mpdu_cnt_fcs_ok > 1)
3165 rx_stats->ampdu_msdu_count += num_msdu;
3166 else
3167 rx_stats->non_ampdu_msdu_count += num_msdu;
3168
3169 rx_stats->num_mpdu_fcs_ok += user_stats->mpdu_cnt_fcs_ok;
3170 rx_stats->num_mpdu_fcs_err += user_stats->mpdu_cnt_fcs_err;
3171 rx_stats->dcm_count += ppdu_info->dcm;
3172 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
3173 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO)
3174 rx_stats->ru_alloc_cnt[user_stats->ul_ofdma_ru_size] += num_msdu;
3175
3176 rx_stats->rx_duration += ppdu_info->rx_duration;
3177 arsta->rx_duration = rx_stats->rx_duration;
3178
3179 if (user_stats->nss > 0 && user_stats->nss <= HAL_RX_MAX_NSS) {
3180 rx_stats->pkt_stats.nss_count[user_stats->nss - 1] += num_msdu;
3181 rx_stats->byte_stats.nss_count[user_stats->nss - 1] +=
3182 user_stats->mpdu_ok_byte_count;
3183 }
3184
3185 if (user_stats->preamble_type == HAL_RX_PREAMBLE_11AX &&
3186 user_stats->mcs <= HAL_RX_MAX_MCS_HE) {
3187 rx_stats->pkt_stats.he_mcs_count[user_stats->mcs] += num_msdu;
3188 rx_stats->byte_stats.he_mcs_count[user_stats->mcs] +=
3189 user_stats->mpdu_ok_byte_count;
3190 }
3191
3192 if (ppdu_info->gi < HAL_RX_GI_MAX) {
3193 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu;
3194 rx_stats->byte_stats.gi_count[ppdu_info->gi] +=
3195 user_stats->mpdu_ok_byte_count;
3196 }
3197
3198 if (ppdu_info->bw < HAL_RX_BW_MAX) {
3199 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu;
3200 rx_stats->byte_stats.bw_count[ppdu_info->bw] +=
3201 user_stats->mpdu_ok_byte_count;
3202 }
3203
3204 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info,
3205 user_stats, num_msdu);
3206 }
3207
3208 static void
ath12k_dp_mon_rx_update_peer_mu_stats(struct ath12k * ar,struct hal_rx_mon_ppdu_info * ppdu_info)3209 ath12k_dp_mon_rx_update_peer_mu_stats(struct ath12k *ar,
3210 struct hal_rx_mon_ppdu_info *ppdu_info)
3211 {
3212 u32 num_users, i;
3213
3214 num_users = ppdu_info->num_users;
3215 if (num_users > HAL_MAX_UL_MU_USERS)
3216 num_users = HAL_MAX_UL_MU_USERS;
3217
3218 for (i = 0; i < num_users; i++)
3219 ath12k_dp_mon_rx_update_user_stats(ar, ppdu_info, i);
3220 }
3221
3222 static void
ath12k_dp_mon_rx_memset_ppdu_info(struct hal_rx_mon_ppdu_info * ppdu_info)3223 ath12k_dp_mon_rx_memset_ppdu_info(struct hal_rx_mon_ppdu_info *ppdu_info)
3224 {
3225 memset(ppdu_info, 0, sizeof(*ppdu_info));
3226 ppdu_info->peer_id = HAL_INVALID_PEERID;
3227 }
3228
ath12k_dp_mon_srng_process(struct ath12k * ar,int * budget,struct napi_struct * napi)3229 int ath12k_dp_mon_srng_process(struct ath12k *ar, int *budget,
3230 struct napi_struct *napi)
3231 {
3232 struct ath12k_base *ab = ar->ab;
3233 struct ath12k_pdev_dp *pdev_dp = &ar->dp;
3234 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data;
3235 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
3236 struct ath12k_dp *dp = &ab->dp;
3237 struct hal_mon_dest_desc *mon_dst_desc;
3238 struct sk_buff *skb;
3239 struct ath12k_skb_rxcb *rxcb;
3240 struct dp_srng *mon_dst_ring;
3241 struct hal_srng *srng;
3242 struct dp_rxdma_mon_ring *buf_ring;
3243 struct ath12k_sta *ahsta = NULL;
3244 struct ath12k_link_sta *arsta;
3245 struct ath12k_peer *peer;
3246 struct sk_buff_head skb_list;
3247 u64 cookie;
3248 int num_buffs_reaped = 0, srng_id, buf_id;
3249 u32 hal_status, end_offset, info0, end_reason;
3250 u8 pdev_idx = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, ar->pdev_idx);
3251
3252 __skb_queue_head_init(&skb_list);
3253 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, pdev_idx);
3254 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id];
3255 buf_ring = &dp->rxdma_mon_buf_ring;
3256
3257 srng = &ab->hal.srng_list[mon_dst_ring->ring_id];
3258 spin_lock_bh(&srng->lock);
3259 ath12k_hal_srng_access_begin(ab, srng);
3260
3261 while (likely(*budget)) {
3262 *budget -= 1;
3263 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng);
3264 if (unlikely(!mon_dst_desc))
3265 break;
3266
3267 /* In case of empty descriptor, the cookie in the ring descriptor
3268 * is invalid. Therefore, this entry is skipped, and ring processing
3269 * continues.
3270 */
3271 info0 = le32_to_cpu(mon_dst_desc->info0);
3272 if (u32_get_bits(info0, HAL_MON_DEST_INFO0_EMPTY_DESC))
3273 goto move_next;
3274
3275 cookie = le32_to_cpu(mon_dst_desc->cookie);
3276 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
3277
3278 spin_lock_bh(&buf_ring->idr_lock);
3279 skb = idr_remove(&buf_ring->bufs_idr, buf_id);
3280 spin_unlock_bh(&buf_ring->idr_lock);
3281
3282 if (unlikely(!skb)) {
3283 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
3284 buf_id);
3285 goto move_next;
3286 }
3287
3288 rxcb = ATH12K_SKB_RXCB(skb);
3289 dma_unmap_single(ab->dev, rxcb->paddr,
3290 skb->len + skb_tailroom(skb),
3291 DMA_FROM_DEVICE);
3292
3293 end_reason = u32_get_bits(info0, HAL_MON_DEST_INFO0_END_REASON);
3294
3295 /* HAL_MON_FLUSH_DETECTED implies that an rx flush received at the end of
3296 * rx PPDU and HAL_MON_PPDU_TRUNCATED implies that the PPDU got
3297 * truncated due to a system level error. In both the cases, buffer data
3298 * can be discarded
3299 */
3300 if ((end_reason == HAL_MON_FLUSH_DETECTED) ||
3301 (end_reason == HAL_MON_PPDU_TRUNCATED)) {
3302 ath12k_dbg(ab, ATH12K_DBG_DATA,
3303 "Monitor dest descriptor end reason %d", end_reason);
3304 dev_kfree_skb_any(skb);
3305 goto move_next;
3306 }
3307
3308 /* Calculate the budget when the ring descriptor with the
3309 * HAL_MON_END_OF_PPDU to ensure that one PPDU worth of data is always
3310 * reaped. This helps to efficiently utilize the NAPI budget.
3311 */
3312 if (end_reason == HAL_MON_END_OF_PPDU) {
3313 *budget -= 1;
3314 rxcb->is_end_of_ppdu = true;
3315 }
3316
3317 end_offset = u32_get_bits(info0, HAL_MON_DEST_INFO0_END_OFFSET);
3318 if (likely(end_offset <= DP_RX_BUFFER_SIZE)) {
3319 skb_put(skb, end_offset);
3320 } else {
3321 ath12k_warn(ab,
3322 "invalid offset on mon stats destination %u\n",
3323 end_offset);
3324 skb_put(skb, DP_RX_BUFFER_SIZE);
3325 }
3326
3327 __skb_queue_tail(&skb_list, skb);
3328
3329 move_next:
3330 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
3331 ath12k_hal_srng_dst_get_next_entry(ab, srng);
3332 num_buffs_reaped++;
3333 }
3334
3335 ath12k_hal_srng_access_end(ab, srng);
3336 spin_unlock_bh(&srng->lock);
3337
3338 if (!num_buffs_reaped)
3339 return 0;
3340
3341 /* In some cases, one PPDU worth of data can be spread across multiple NAPI
3342 * schedules, To avoid losing existing parsed ppdu_info information, skip
3343 * the memset of the ppdu_info structure and continue processing it.
3344 */
3345 if (!ppdu_info->ppdu_continuation)
3346 ath12k_dp_mon_rx_memset_ppdu_info(ppdu_info);
3347
3348 while ((skb = __skb_dequeue(&skb_list))) {
3349 hal_status = ath12k_dp_mon_parse_rx_dest(ar, pmon, skb);
3350 if (hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
3351 ppdu_info->ppdu_continuation = true;
3352 dev_kfree_skb_any(skb);
3353 continue;
3354 }
3355
3356 if (ppdu_info->peer_id == HAL_INVALID_PEERID)
3357 goto free_skb;
3358
3359 rcu_read_lock();
3360 spin_lock_bh(&ab->base_lock);
3361 peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id);
3362 if (!peer || !peer->sta) {
3363 ath12k_dbg(ab, ATH12K_DBG_DATA,
3364 "failed to find the peer with monitor peer_id %d\n",
3365 ppdu_info->peer_id);
3366 goto next_skb;
3367 }
3368
3369 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) {
3370 ahsta = ath12k_sta_to_ahsta(peer->sta);
3371 arsta = &ahsta->deflink;
3372 ath12k_dp_mon_rx_update_peer_su_stats(ar, arsta,
3373 ppdu_info);
3374 } else if ((ppdu_info->fc_valid) &&
3375 (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) {
3376 ath12k_dp_mon_rx_process_ulofdma(ppdu_info);
3377 ath12k_dp_mon_rx_update_peer_mu_stats(ar, ppdu_info);
3378 }
3379
3380 next_skb:
3381 spin_unlock_bh(&ab->base_lock);
3382 rcu_read_unlock();
3383 free_skb:
3384 dev_kfree_skb_any(skb);
3385 ath12k_dp_mon_rx_memset_ppdu_info(ppdu_info);
3386 }
3387
3388 return num_buffs_reaped;
3389 }
3390
ath12k_dp_mon_process_ring(struct ath12k_base * ab,int mac_id,struct napi_struct * napi,int budget,enum dp_monitor_mode monitor_mode)3391 int ath12k_dp_mon_process_ring(struct ath12k_base *ab, int mac_id,
3392 struct napi_struct *napi, int budget,
3393 enum dp_monitor_mode monitor_mode)
3394 {
3395 struct ath12k *ar = ath12k_ab_to_ar(ab, mac_id);
3396 int num_buffs_reaped = 0;
3397
3398 if (ab->hw_params->rxdma1_enable) {
3399 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE)
3400 num_buffs_reaped = ath12k_dp_mon_srng_process(ar, &budget, napi);
3401 }
3402
3403 return num_buffs_reaped;
3404 }
3405