1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include "opt_acpi.h"
30 #include "opt_iommu.h"
31 #include "opt_isa.h"
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/kernel.h>
37 #include <sys/lock.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <sys/rman.h>
42 #include <sys/sysctl.h>
43
44 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pcivar.h>
46
47 #include <vm/vm.h>
48 #include <vm/pmap.h>
49
50 #include <x86/apicreg.h>
51 #include <machine/frame.h>
52 #include <machine/intr_machdep.h>
53 #include <x86/apicvar.h>
54 #include <machine/resource.h>
55 #include <machine/segments.h>
56 #include <x86/iommu/iommu_intrmap.h>
57
58 #define IOAPIC_ISA_INTS 16
59 #define IOAPIC_MEM_REGION 32
60 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
61 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
62
63 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
64
65 /*
66 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
67 * as laid out in the ACPI System Interrupt number model where each I/O
68 * APIC has a contiguous chunk of the System Interrupt address space.
69 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
70 * IRQs behave as PCI IRQs by default. We also assume that the pin for
71 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the
72 * configuration of individual pins as indicated by their tables.
73 *
74 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
75 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
76 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
77 */
78
79 struct ioapic_intsrc {
80 struct intsrc io_intsrc;
81 int io_irq;
82 u_int io_intpin:8;
83 u_int io_vector:8;
84 u_int io_cpu;
85 u_int io_activehi:1;
86 u_int io_edgetrigger:1;
87 u_int io_masked:1;
88 u_int io_valid:1;
89 int io_bus:4;
90 uint32_t io_lowreg;
91 u_int io_remap_cookie;
92 };
93
94 struct ioapic {
95 struct pic io_pic;
96 u_int io_id:8; /* logical ID */
97 u_int io_apic_id:8; /* Id as enumerated by MADT */
98 u_int io_hw_apic_id:8; /* Content of APIC ID register */
99 u_int io_intbase:8; /* System Interrupt base */
100 u_int io_numintr:8;
101 u_int io_haseoi:1;
102 volatile ioapic_t *io_addr; /* XXX: should use bus_space */
103 vm_paddr_t io_paddr;
104 STAILQ_ENTRY(ioapic) io_next;
105 device_t pci_dev; /* matched pci device, if found */
106 struct resource *pci_wnd; /* BAR 0, should be same or alias to
107 io_paddr */
108 struct ioapic_intsrc io_pins[0];
109 };
110
111 static u_int ioapic_read(volatile ioapic_t *apic, int reg);
112 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
113 static const char *ioapic_bus_string(int bus_type);
114 static void ioapic_print_irq(struct ioapic_intsrc *intpin);
115 static void ioapic_register_sources(struct pic *pic);
116 static void ioapic_enable_source(struct intsrc *isrc);
117 static void ioapic_disable_source(struct intsrc *isrc, int eoi);
118 static void ioapic_eoi_source(struct intsrc *isrc);
119 static void ioapic_enable_intr(struct intsrc *isrc);
120 static void ioapic_disable_intr(struct intsrc *isrc);
121 static int ioapic_vector(struct intsrc *isrc);
122 static int ioapic_source_pending(struct intsrc *isrc);
123 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
124 enum intr_polarity pol);
125 static void ioapic_resume(struct pic *pic, bool suspend_cancelled);
126 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id);
127 static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
128 static void ioapic_reprogram_intpin(struct intsrc *isrc);
129
130 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
131 struct pic ioapic_template = {
132 .pic_register_sources = ioapic_register_sources,
133 .pic_enable_source = ioapic_enable_source,
134 .pic_disable_source = ioapic_disable_source,
135 .pic_eoi_source = ioapic_eoi_source,
136 .pic_enable_intr = ioapic_enable_intr,
137 .pic_disable_intr = ioapic_disable_intr,
138 .pic_vector = ioapic_vector,
139 .pic_source_pending = ioapic_source_pending,
140 .pic_suspend = NULL,
141 .pic_resume = ioapic_resume,
142 .pic_config_intr = ioapic_config_intr,
143 .pic_assign_cpu = ioapic_assign_cpu,
144 .pic_reprogram_pin = ioapic_reprogram_intpin,
145 };
146
147 static u_int next_ioapic_base;
148 static u_int next_id;
149
150 static int enable_extint;
151 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0,
152 "Enable the ExtINT pin in the first I/O APIC");
153
154 static void
_ioapic_eoi_source(struct intsrc * isrc,int locked)155 _ioapic_eoi_source(struct intsrc *isrc, int locked)
156 {
157 struct ioapic_intsrc *src;
158 struct ioapic *io;
159 volatile uint32_t *apic_eoi;
160 uint32_t low1;
161
162 lapic_eoi();
163 if (!lapic_eoi_suppression)
164 return;
165 src = (struct ioapic_intsrc *)isrc;
166 if (src->io_edgetrigger)
167 return;
168 io = (struct ioapic *)isrc->is_pic;
169
170 /*
171 * Handle targeted EOI for level-triggered pins, if broadcast
172 * EOI suppression is supported by LAPICs.
173 */
174 if (io->io_haseoi) {
175 /*
176 * If IOAPIC has EOI Register, simply write vector
177 * number into the reg.
178 */
179 apic_eoi = (volatile uint32_t *)((volatile char *)
180 io->io_addr + IOAPIC_EOIR);
181 *apic_eoi = src->io_vector;
182 } else {
183 /*
184 * Otherwise, if IO-APIC is too old to provide EOIR,
185 * do what Intel did for the Linux kernel. Temporary
186 * switch the pin to edge-trigger and back, masking
187 * the pin during the trick.
188 */
189 if (!locked)
190 mtx_lock_spin(&icu_lock);
191 low1 = src->io_lowreg;
192 low1 &= ~IOART_TRGRLVL;
193 low1 |= IOART_TRGREDG | IOART_INTMSET;
194 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
195 low1);
196 low1 = src->io_lowreg;
197 if (src->io_masked != 0 || src->io_valid == 0)
198 low1 |= IOART_INTMSET;
199 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
200 low1);
201 if (!locked)
202 mtx_unlock_spin(&icu_lock);
203 }
204 }
205
206 static u_int
ioapic_read(volatile ioapic_t * apic,int reg)207 ioapic_read(volatile ioapic_t *apic, int reg)
208 {
209
210 mtx_assert(&icu_lock, MA_OWNED);
211 apic->ioregsel = reg;
212 return (apic->iowin);
213 }
214
215 static void
ioapic_write(volatile ioapic_t * apic,int reg,u_int val)216 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
217 {
218
219 mtx_assert(&icu_lock, MA_OWNED);
220 apic->ioregsel = reg;
221 apic->iowin = val;
222 }
223
224 static const char *
ioapic_bus_string(int bus_type)225 ioapic_bus_string(int bus_type)
226 {
227
228 switch (bus_type) {
229 case APIC_BUS_ISA:
230 return ("ISA");
231 case APIC_BUS_EISA:
232 return ("EISA");
233 case APIC_BUS_PCI:
234 return ("PCI");
235 default:
236 return ("unknown");
237 }
238 }
239
240 static void
ioapic_print_irq(struct ioapic_intsrc * intpin)241 ioapic_print_irq(struct ioapic_intsrc *intpin)
242 {
243
244 switch (intpin->io_irq) {
245 case IRQ_DISABLED:
246 printf("disabled");
247 break;
248 case IRQ_EXTINT:
249 printf("ExtINT");
250 break;
251 case IRQ_NMI:
252 printf("NMI");
253 break;
254 case IRQ_SMI:
255 printf("SMI");
256 break;
257 default:
258 printf("%s IRQ %d", ioapic_bus_string(intpin->io_bus),
259 intpin->io_irq);
260 }
261 }
262
263 static void
ioapic_enable_source(struct intsrc * isrc)264 ioapic_enable_source(struct intsrc *isrc)
265 {
266 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
267 struct ioapic *io = (struct ioapic *)isrc->is_pic;
268 uint32_t flags;
269
270 mtx_lock_spin(&icu_lock);
271 if (intpin->io_masked) {
272 flags = intpin->io_lowreg;
273 if (intpin->io_valid)
274 flags &= ~IOART_INTMASK;
275 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
276 flags);
277 intpin->io_masked = 0;
278 }
279 mtx_unlock_spin(&icu_lock);
280 }
281
282 static void
ioapic_disable_source(struct intsrc * isrc,int eoi)283 ioapic_disable_source(struct intsrc *isrc, int eoi)
284 {
285 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
286 struct ioapic *io = (struct ioapic *)isrc->is_pic;
287 uint32_t flags;
288
289 mtx_lock_spin(&icu_lock);
290 if (!intpin->io_masked && !intpin->io_edgetrigger) {
291 flags = intpin->io_lowreg | IOART_INTMSET;
292 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
293 flags);
294 intpin->io_masked = 1;
295 }
296
297 if (eoi == PIC_EOI)
298 _ioapic_eoi_source(isrc, 1);
299
300 mtx_unlock_spin(&icu_lock);
301 }
302
303 static void
ioapic_eoi_source(struct intsrc * isrc)304 ioapic_eoi_source(struct intsrc *isrc)
305 {
306
307 _ioapic_eoi_source(isrc, 0);
308 }
309
310 /*
311 * Completely program an intpin based on the data in its interrupt source
312 * structure.
313 */
314 static void
ioapic_program_intpin(struct ioapic_intsrc * intpin)315 ioapic_program_intpin(struct ioapic_intsrc *intpin)
316 {
317 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
318 uint32_t low, high;
319 #ifdef IOMMU
320 int error;
321 #endif
322
323 /*
324 * If a pin is completely invalid or if it is valid but hasn't
325 * been enabled yet, just ensure that the pin is masked.
326 */
327 mtx_assert(&icu_lock, MA_OWNED);
328 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq >= 0 &&
329 intpin->io_vector == 0)) {
330 low = ioapic_read(io->io_addr,
331 IOAPIC_REDTBL_LO(intpin->io_intpin));
332 if ((low & IOART_INTMASK) == IOART_INTMCLR)
333 ioapic_write(io->io_addr,
334 IOAPIC_REDTBL_LO(intpin->io_intpin),
335 low | IOART_INTMSET);
336 #ifdef IOMMU
337 mtx_unlock_spin(&icu_lock);
338 iommu_unmap_ioapic_intr(io->io_apic_id,
339 &intpin->io_remap_cookie);
340 mtx_lock_spin(&icu_lock);
341 #endif
342 return;
343 }
344
345 #ifdef IOMMU
346 mtx_unlock_spin(&icu_lock);
347 error = iommu_map_ioapic_intr(io->io_apic_id,
348 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
349 intpin->io_activehi, intpin->io_irq, &intpin->io_remap_cookie,
350 &high, &low);
351 mtx_lock_spin(&icu_lock);
352 if (error == 0) {
353 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin),
354 high);
355 intpin->io_lowreg = low;
356 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
357 low);
358 return;
359 } else if (error != EOPNOTSUPP) {
360 return;
361 }
362 #endif
363
364 /*
365 * Set the destination. Note that with Intel interrupt remapping,
366 * the previously reserved bits 55:48 now have a purpose so ensure
367 * these are zero. If the CPU number (in fact, APIC ID) is too
368 * large, mark the interrupt as invalid, and target CPU #0.
369 */
370 if (intpin->io_cpu <= IOAPIC_MAX_ID) {
371 low = IOART_DESTPHY;
372 high = intpin->io_cpu << APIC_ID_SHIFT;
373 intpin->io_valid = 1;
374 } else if (intpin->io_cpu <= IOAPIC_MAX_EXT_ID &&
375 apic_ext_dest_id == 1) {
376 low = IOART_DESTPHY;
377 high = intpin->io_cpu << APIC_ID_SHIFT & APIC_ID_MASK;
378 high |= (intpin->io_cpu >> 8) << APIC_EXT_ID_SHIFT
379 & APIC_EXT_ID_MASK;
380 intpin->io_valid = 1;
381 } else {
382 printf("%s: unsupported destination APIC ID %u for pin %u\n",
383 __func__, intpin->io_cpu, intpin->io_intpin);
384 low = IOART_DESTPHY;
385 high = 0 << APIC_ID_SHIFT;
386 intpin->io_valid = 0;
387 }
388
389 /* Program the rest of the low word. */
390 if (intpin->io_edgetrigger)
391 low |= IOART_TRGREDG;
392 else
393 low |= IOART_TRGRLVL;
394 if (intpin->io_activehi)
395 low |= IOART_INTAHI;
396 else
397 low |= IOART_INTALO;
398 if (intpin->io_masked || !intpin->io_valid)
399 low |= IOART_INTMSET;
400 switch (intpin->io_irq) {
401 case IRQ_EXTINT:
402 KASSERT(intpin->io_edgetrigger,
403 ("ExtINT not edge triggered"));
404 low |= IOART_DELEXINT;
405 break;
406 case IRQ_NMI:
407 KASSERT(intpin->io_edgetrigger,
408 ("NMI not edge triggered"));
409 low |= IOART_DELNMI;
410 break;
411 case IRQ_SMI:
412 KASSERT(intpin->io_edgetrigger,
413 ("SMI not edge triggered"));
414 low |= IOART_DELSMI;
415 break;
416 default:
417 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
418 intpin->io_irq));
419 low |= IOART_DELFIXED | intpin->io_vector;
420 }
421
422 /* Write the values to the APIC. */
423 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), high);
424 intpin->io_lowreg = low;
425 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
426 }
427
428 static void
ioapic_reprogram_intpin(struct intsrc * isrc)429 ioapic_reprogram_intpin(struct intsrc *isrc)
430 {
431
432 mtx_lock_spin(&icu_lock);
433 ioapic_program_intpin((struct ioapic_intsrc *)isrc);
434 mtx_unlock_spin(&icu_lock);
435 }
436
437 static int
ioapic_assign_cpu(struct intsrc * isrc,u_int apic_id)438 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id)
439 {
440 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
441 struct ioapic *io = (struct ioapic *)isrc->is_pic;
442 u_int old_vector, new_vector;
443 u_int old_id;
444
445 /*
446 * On Hyper-V:
447 * - Stick to the first cpu for all I/O APIC pins.
448 * - And don't allow destination cpu changes.
449 */
450 if (vm_guest == VM_GUEST_HV) {
451 if (intpin->io_vector)
452 return (EINVAL);
453 else
454 apic_id = 0;
455 }
456
457 /*
458 * keep 1st core as the destination for NMI
459 */
460 if (intpin->io_irq == IRQ_NMI)
461 apic_id = 0;
462
463 /*
464 * Set us up to free the old irq.
465 */
466 old_vector = intpin->io_vector;
467 old_id = intpin->io_cpu;
468 if (old_vector && apic_id == old_id)
469 return (0);
470
471 /*
472 * Allocate an APIC vector for this interrupt pin. Once
473 * we have a vector we program the interrupt pin.
474 */
475 new_vector = apic_alloc_vector(apic_id, intpin->io_irq);
476 if (new_vector == 0)
477 return (ENOSPC);
478
479 /*
480 * Mask the old intpin if it is enabled while it is migrated.
481 *
482 * At least some level-triggered interrupts seem to need the
483 * extra DELAY() to avoid being stuck in a non-EOI'd state.
484 */
485 mtx_lock_spin(&icu_lock);
486 if (!intpin->io_masked && !intpin->io_edgetrigger) {
487 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
488 intpin->io_lowreg | IOART_INTMSET);
489 mtx_unlock_spin(&icu_lock);
490 DELAY(100);
491 mtx_lock_spin(&icu_lock);
492 }
493
494 intpin->io_cpu = apic_id;
495 intpin->io_vector = new_vector;
496 if (isrc->is_handlers > 0)
497 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
498 if (bootverbose) {
499 printf("ioapic%u: routing intpin %u (", io->io_id,
500 intpin->io_intpin);
501 ioapic_print_irq(intpin);
502 printf(") to lapic %u vector %u\n", intpin->io_cpu,
503 intpin->io_vector);
504 }
505 ioapic_program_intpin(intpin);
506 mtx_unlock_spin(&icu_lock);
507
508 /*
509 * Free the old vector after the new one is established. This is done
510 * to prevent races where we could miss an interrupt.
511 */
512 if (old_vector) {
513 if (isrc->is_handlers > 0)
514 apic_disable_vector(old_id, old_vector);
515 apic_free_vector(old_id, old_vector, intpin->io_irq);
516 }
517 return (0);
518 }
519
520 static void
ioapic_enable_intr(struct intsrc * isrc)521 ioapic_enable_intr(struct intsrc *isrc)
522 {
523 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
524
525 if (intpin->io_vector == 0)
526 if (ioapic_assign_cpu(isrc, intr_next_cpu(isrc->is_domain)) != 0)
527 panic("Couldn't find an APIC vector for IRQ %d",
528 intpin->io_irq);
529 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
530 }
531
532 static void
ioapic_disable_intr(struct intsrc * isrc)533 ioapic_disable_intr(struct intsrc *isrc)
534 {
535 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
536 u_int vector;
537
538 if (intpin->io_vector != 0) {
539 /* Mask this interrupt pin and free its APIC vector. */
540 vector = intpin->io_vector;
541 apic_disable_vector(intpin->io_cpu, vector);
542 mtx_lock_spin(&icu_lock);
543 intpin->io_masked = 1;
544 intpin->io_vector = 0;
545 ioapic_program_intpin(intpin);
546 mtx_unlock_spin(&icu_lock);
547 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq);
548 }
549 }
550
551 static int
ioapic_vector(struct intsrc * isrc)552 ioapic_vector(struct intsrc *isrc)
553 {
554 struct ioapic_intsrc *pin;
555
556 pin = (struct ioapic_intsrc *)isrc;
557 return (pin->io_irq);
558 }
559
560 static int
ioapic_source_pending(struct intsrc * isrc)561 ioapic_source_pending(struct intsrc *isrc)
562 {
563 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
564
565 if (intpin->io_vector == 0)
566 return 0;
567 return (lapic_intr_pending(intpin->io_vector));
568 }
569
570 static int
ioapic_config_intr(struct intsrc * isrc,enum intr_trigger trig,enum intr_polarity pol)571 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
572 enum intr_polarity pol)
573 {
574 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
575 struct ioapic *io = (struct ioapic *)isrc->is_pic;
576 int changed;
577
578 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
579 ("%s: Conforming trigger or polarity\n", __func__));
580
581 /*
582 * EISA interrupts always use active high polarity, so don't allow
583 * them to be set to active low.
584 *
585 * XXX: Should we write to the ELCR if the trigger mode changes for
586 * an EISA IRQ or an ISA IRQ with the ELCR present?
587 */
588 mtx_lock_spin(&icu_lock);
589 if (intpin->io_bus == APIC_BUS_EISA)
590 pol = INTR_POLARITY_HIGH;
591 changed = 0;
592 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
593 if (bootverbose)
594 printf("ioapic%u: Changing trigger for pin %u to %s\n",
595 io->io_id, intpin->io_intpin,
596 trig == INTR_TRIGGER_EDGE ? "edge" : "level");
597 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
598 changed++;
599 }
600 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
601 if (bootverbose)
602 printf("ioapic%u: Changing polarity for pin %u to %s\n",
603 io->io_id, intpin->io_intpin,
604 pol == INTR_POLARITY_HIGH ? "high" : "low");
605 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
606 changed++;
607 }
608 if (changed)
609 ioapic_program_intpin(intpin);
610 mtx_unlock_spin(&icu_lock);
611 return (0);
612 }
613
614 static void
ioapic_resume(struct pic * pic,bool suspend_cancelled)615 ioapic_resume(struct pic *pic, bool suspend_cancelled)
616 {
617 struct ioapic *io = (struct ioapic *)pic;
618 int i;
619
620 mtx_lock_spin(&icu_lock);
621 for (i = 0; i < io->io_numintr; i++)
622 ioapic_program_intpin(&io->io_pins[i]);
623 mtx_unlock_spin(&icu_lock);
624 }
625
626 /*
627 * Create a plain I/O APIC object.
628 */
629 ioapic_drv_t
ioapic_create(vm_paddr_t addr,int32_t apic_id,int intbase)630 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase)
631 {
632 struct ioapic *io;
633 struct ioapic_intsrc *intpin;
634 ioapic_t *apic;
635 u_int numintr, i;
636 uint32_t value;
637
638 /* Map the register window so we can access the device. */
639 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION);
640 mtx_lock_spin(&icu_lock);
641 value = ioapic_read(apic, IOAPIC_VER);
642 mtx_unlock_spin(&icu_lock);
643
644 /* If it's version register doesn't seem to work, punt. */
645 if (value == 0xffffffff) {
646 pmap_unmapdev(apic, IOAPIC_MEM_REGION);
647 return (NULL);
648 }
649
650 /* Determine the number of vectors and set the APIC ID. */
651 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
652 io = malloc(sizeof(struct ioapic) +
653 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
654 io->io_pic = ioapic_template;
655 io->pci_dev = NULL;
656 io->pci_wnd = NULL;
657 mtx_lock_spin(&icu_lock);
658 io->io_id = next_id++;
659 io->io_hw_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
660 io->io_apic_id = apic_id == -1 ? io->io_hw_apic_id : apic_id;
661 mtx_unlock_spin(&icu_lock);
662 if (io->io_hw_apic_id != apic_id)
663 printf("ioapic%u: MADT APIC ID %d != hw id %d\n", io->io_id,
664 apic_id, io->io_hw_apic_id);
665 if (intbase == -1) {
666 intbase = next_ioapic_base;
667 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
668 intbase);
669 } else if (intbase != next_ioapic_base && bootverbose)
670 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
671 io->io_id, intbase, next_ioapic_base);
672 io->io_intbase = intbase;
673 next_ioapic_base = intbase + numintr;
674 if (next_ioapic_base > num_io_irqs)
675 num_io_irqs = next_ioapic_base;
676 io->io_numintr = numintr;
677 io->io_addr = apic;
678 io->io_paddr = addr;
679
680 if (bootverbose) {
681 printf("ioapic%u: ver 0x%02x maxredir 0x%02x\n", io->io_id,
682 (value & IOART_VER_VERSION), (value & IOART_VER_MAXREDIR)
683 >> MAXREDIRSHIFT);
684 }
685 /*
686 * The summary information about IO-APIC versions is taken from
687 * the Linux kernel source:
688 * 0Xh 82489DX
689 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
690 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
691 * 30h-FFh Reserved
692 * IO-APICs with version >= 0x20 have working EOIR register.
693 */
694 io->io_haseoi = (value & IOART_VER_VERSION) >= 0x20;
695
696 /*
697 * Initialize pins. Start off with interrupts disabled. Default
698 * to active-hi and edge-triggered for ISA interrupts and active-lo
699 * and level-triggered for all others.
700 */
701 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
702 mtx_lock_spin(&icu_lock);
703 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
704 intpin->io_intsrc.is_pic = (struct pic *)io;
705 intpin->io_intpin = i;
706 intpin->io_irq = intbase + i;
707
708 /*
709 * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
710 * Assume that pins 1-15 are ISA interrupts and that all
711 * other pins are PCI interrupts.
712 */
713 if (intpin->io_irq == 0)
714 ioapic_set_extint(io, i);
715 else if (intpin->io_irq < IOAPIC_ISA_INTS) {
716 intpin->io_bus = APIC_BUS_ISA;
717 intpin->io_activehi = 1;
718 intpin->io_edgetrigger = 1;
719 intpin->io_masked = 1;
720 intpin->io_valid = 1;
721 } else {
722 intpin->io_bus = APIC_BUS_PCI;
723 intpin->io_activehi = 0;
724 intpin->io_edgetrigger = 0;
725 intpin->io_masked = 1;
726 intpin->io_valid = 1;
727 }
728
729 /*
730 * Route interrupts to the BSP by default. Interrupts may
731 * be routed to other CPUs later after they are enabled.
732 */
733 intpin->io_cpu = PCPU_GET(apic_id);
734 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
735 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
736 #ifdef IOMMU
737 /* dummy, but sets cookie */
738 mtx_unlock_spin(&icu_lock);
739 iommu_map_ioapic_intr(io->io_apic_id,
740 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
741 intpin->io_activehi, intpin->io_irq,
742 &intpin->io_remap_cookie, NULL, NULL);
743 mtx_lock_spin(&icu_lock);
744 #endif
745 }
746 mtx_unlock_spin(&icu_lock);
747
748 return (io);
749 }
750
751 int
ioapic_get_vector(ioapic_drv_t io,u_int pin)752 ioapic_get_vector(ioapic_drv_t io, u_int pin)
753 {
754
755 if (pin >= io->io_numintr)
756 return (-1);
757 return (io->io_pins[pin].io_irq);
758 }
759
760 int
ioapic_disable_pin(ioapic_drv_t io,u_int pin)761 ioapic_disable_pin(ioapic_drv_t io, u_int pin)
762 {
763
764 if (pin >= io->io_numintr)
765 return (EINVAL);
766 if (io->io_pins[pin].io_irq == IRQ_DISABLED)
767 return (EINVAL);
768 io->io_pins[pin].io_irq = IRQ_DISABLED;
769 if (bootverbose)
770 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
771 return (0);
772 }
773
774 int
ioapic_remap_vector(ioapic_drv_t io,u_int pin,int vector)775 ioapic_remap_vector(ioapic_drv_t io, u_int pin, int vector)
776 {
777
778 if (pin >= io->io_numintr || vector < 0)
779 return (EINVAL);
780 if (io->io_pins[pin].io_irq < 0)
781 return (EINVAL);
782 io->io_pins[pin].io_irq = vector;
783 if (bootverbose)
784 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
785 vector, pin);
786 return (0);
787 }
788
789 int
ioapic_set_bus(ioapic_drv_t io,u_int pin,int bus_type)790 ioapic_set_bus(ioapic_drv_t io, u_int pin, int bus_type)
791 {
792
793 if (bus_type < 0 || bus_type > APIC_BUS_MAX)
794 return (EINVAL);
795 if (pin >= io->io_numintr)
796 return (EINVAL);
797 if (io->io_pins[pin].io_irq < 0)
798 return (EINVAL);
799 if (io->io_pins[pin].io_bus == bus_type)
800 return (0);
801 io->io_pins[pin].io_bus = bus_type;
802 if (bootverbose)
803 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
804 ioapic_bus_string(bus_type));
805 return (0);
806 }
807
808 int
ioapic_set_nmi(ioapic_drv_t io,u_int pin)809 ioapic_set_nmi(ioapic_drv_t io, u_int pin)
810 {
811
812 if (pin >= io->io_numintr)
813 return (EINVAL);
814 if (io->io_pins[pin].io_irq == IRQ_NMI)
815 return (0);
816 if (io->io_pins[pin].io_irq < 0)
817 return (EINVAL);
818 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
819 io->io_pins[pin].io_irq = IRQ_NMI;
820 io->io_pins[pin].io_masked = 0;
821 io->io_pins[pin].io_valid = 1;
822 io->io_pins[pin].io_edgetrigger = 1;
823 io->io_pins[pin].io_activehi = 1;
824 if (bootverbose)
825 printf("ioapic%u: Routing NMI -> intpin %d\n",
826 io->io_id, pin);
827 return (0);
828 }
829
830 int
ioapic_set_smi(ioapic_drv_t io,u_int pin)831 ioapic_set_smi(ioapic_drv_t io, u_int pin)
832 {
833
834 if (pin >= io->io_numintr)
835 return (EINVAL);
836 if (io->io_pins[pin].io_irq == IRQ_SMI)
837 return (0);
838 if (io->io_pins[pin].io_irq < 0)
839 return (EINVAL);
840 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
841 io->io_pins[pin].io_irq = IRQ_SMI;
842 io->io_pins[pin].io_masked = 0;
843 io->io_pins[pin].io_valid = 1;
844 io->io_pins[pin].io_edgetrigger = 1;
845 io->io_pins[pin].io_activehi = 1;
846 if (bootverbose)
847 printf("ioapic%u: Routing SMI -> intpin %d\n",
848 io->io_id, pin);
849 return (0);
850 }
851
852 int
ioapic_set_extint(ioapic_drv_t io,u_int pin)853 ioapic_set_extint(ioapic_drv_t io, u_int pin)
854 {
855
856 if (pin >= io->io_numintr)
857 return (EINVAL);
858 if (io->io_pins[pin].io_irq == IRQ_EXTINT)
859 return (0);
860 if (io->io_pins[pin].io_irq < 0)
861 return (EINVAL);
862 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
863 io->io_pins[pin].io_irq = IRQ_EXTINT;
864 if (enable_extint)
865 io->io_pins[pin].io_masked = 0;
866 else
867 io->io_pins[pin].io_masked = 1;
868 io->io_pins[pin].io_valid = 1;
869 io->io_pins[pin].io_edgetrigger = 1;
870 io->io_pins[pin].io_activehi = 1;
871 if (bootverbose)
872 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
873 io->io_id, pin);
874 return (0);
875 }
876
877 int
ioapic_set_polarity(ioapic_drv_t io,u_int pin,enum intr_polarity pol)878 ioapic_set_polarity(ioapic_drv_t io, u_int pin, enum intr_polarity pol)
879 {
880 int activehi;
881
882 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
883 return (EINVAL);
884 if (io->io_pins[pin].io_irq < 0)
885 return (EINVAL);
886 activehi = (pol == INTR_POLARITY_HIGH);
887 if (io->io_pins[pin].io_activehi == activehi)
888 return (0);
889 io->io_pins[pin].io_activehi = activehi;
890 if (bootverbose)
891 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
892 pol == INTR_POLARITY_HIGH ? "high" : "low");
893 return (0);
894 }
895
896 int
ioapic_set_triggermode(ioapic_drv_t io,u_int pin,enum intr_trigger trigger)897 ioapic_set_triggermode(ioapic_drv_t io, u_int pin, enum intr_trigger trigger)
898 {
899 int edgetrigger;
900
901 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
902 return (EINVAL);
903 if (io->io_pins[pin].io_irq < 0)
904 return (EINVAL);
905 edgetrigger = (trigger == INTR_TRIGGER_EDGE);
906 if (io->io_pins[pin].io_edgetrigger == edgetrigger)
907 return (0);
908 io->io_pins[pin].io_edgetrigger = edgetrigger;
909 if (bootverbose)
910 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
911 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
912 return (0);
913 }
914
915 /*
916 * Register a complete I/O APIC object with the interrupt subsystem.
917 */
918 void
ioapic_register(ioapic_drv_t io)919 ioapic_register(ioapic_drv_t io)
920 {
921 struct ioapic_intsrc *pin;
922 volatile ioapic_t *apic;
923 uint32_t flags;
924 int i;
925
926 apic = io->io_addr;
927 mtx_lock_spin(&icu_lock);
928 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
929 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
930 mtx_unlock_spin(&icu_lock);
931 printf("ioapic%u <Version %u.%u> irqs %u-%u\n",
932 io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
933 io->io_intbase + io->io_numintr - 1);
934
935 /*
936 * Reprogram pins to handle special case pins (such as NMI and
937 * SMI) and disable normal pins until a handler is registered.
938 */
939 intr_register_pic(&io->io_pic);
940 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++)
941 ioapic_reprogram_intpin(&pin->io_intsrc);
942 }
943
944 /*
945 * Add interrupt sources for I/O APIC interrupt pins.
946 */
947 static void
ioapic_register_sources(struct pic * pic)948 ioapic_register_sources(struct pic *pic)
949 {
950 struct ioapic_intsrc *pin;
951 struct ioapic *io;
952 int i;
953
954 io = (struct ioapic *)pic;
955 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
956 if (pin->io_irq >= 0)
957 intr_register_source(&pin->io_intsrc);
958 }
959 }
960
961 /* A simple new-bus driver to consume PCI I/O APIC devices. */
962 static int
ioapic_pci_probe(device_t dev)963 ioapic_pci_probe(device_t dev)
964 {
965
966 if (pci_get_class(dev) == PCIC_BASEPERIPH &&
967 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) {
968 switch (pci_get_progif(dev)) {
969 case PCIP_BASEPERIPH_PIC_IO_APIC:
970 device_set_desc(dev, "IO APIC");
971 break;
972 case PCIP_BASEPERIPH_PIC_IOX_APIC:
973 device_set_desc(dev, "IO(x) APIC");
974 break;
975 default:
976 return (ENXIO);
977 }
978 device_quiet(dev);
979 return (-10000);
980 }
981 return (ENXIO);
982 }
983
984 static int
ioapic_pci_attach(device_t dev)985 ioapic_pci_attach(device_t dev)
986 {
987 struct resource *res;
988 volatile ioapic_t *apic;
989 struct ioapic *io;
990 int rid;
991 u_int apic_id;
992
993 /*
994 * Try to match the enumerated ioapic. Match BAR start
995 * against io_paddr. Due to a fear that PCI window is not the
996 * same as the MADT reported io window, but an alias, read the
997 * APIC ID from the mapped BAR and match against it.
998 */
999 rid = PCIR_BAR(0);
1000 res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1001 RF_ACTIVE | RF_SHAREABLE);
1002 if (res == NULL) {
1003 if (bootverbose)
1004 device_printf(dev, "cannot activate BAR0\n");
1005 return (ENXIO);
1006 }
1007 apic = (volatile ioapic_t *)rman_get_virtual(res);
1008 if (rman_get_size(res) < IOAPIC_WND_SIZE) {
1009 if (bootverbose)
1010 device_printf(dev,
1011 "BAR0 too small (%jd) for IOAPIC window\n",
1012 (uintmax_t)rman_get_size(res));
1013 goto fail;
1014 }
1015 mtx_lock_spin(&icu_lock);
1016 apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
1017 /* First match by io window address */
1018 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1019 if (io->io_paddr == (vm_paddr_t)rman_get_start(res))
1020 goto found;
1021 }
1022 /* Then by apic id */
1023 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1024 if (io->io_hw_apic_id == apic_id)
1025 goto found;
1026 }
1027 mtx_unlock_spin(&icu_lock);
1028 if (bootverbose)
1029 device_printf(dev,
1030 "cannot match pci bar apic id %d against MADT, BAR0 %#jx\n",
1031 apic_id, (uintmax_t)rman_get_start(res));
1032 fail:
1033 bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
1034 return (ENXIO);
1035 found:
1036 KASSERT(io->pci_dev == NULL,
1037 ("ioapic %d pci_dev not NULL", io->io_id));
1038 KASSERT(io->pci_wnd == NULL,
1039 ("ioapic %d pci_wnd not NULL", io->io_id));
1040
1041 io->pci_dev = dev;
1042 io->pci_wnd = res;
1043 if (bootverbose && (io->io_paddr != (vm_paddr_t)rman_get_start(res) ||
1044 io->io_hw_apic_id != apic_id)) {
1045 device_printf(dev, "pci%d:%d:%d:%d pci BAR0@%jx id %d "
1046 "MADT id %d hw id %d paddr@%jx\n",
1047 pci_get_domain(dev), pci_get_bus(dev),
1048 pci_get_slot(dev), pci_get_function(dev),
1049 (uintmax_t)rman_get_start(res), apic_id,
1050 io->io_apic_id, io->io_hw_apic_id, (uintmax_t)io->io_paddr);
1051 }
1052 mtx_unlock_spin(&icu_lock);
1053 return (0);
1054 }
1055
1056 static device_method_t ioapic_pci_methods[] = {
1057 /* Device interface */
1058 DEVMETHOD(device_probe, ioapic_pci_probe),
1059 DEVMETHOD(device_attach, ioapic_pci_attach),
1060
1061 DEVMETHOD_END
1062 };
1063
1064 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0);
1065
1066 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, 0, 0);
1067
1068 int
ioapic_get_rid(u_int apic_id,uint16_t * ridp)1069 ioapic_get_rid(u_int apic_id, uint16_t *ridp)
1070 {
1071 struct ioapic *io;
1072 uintptr_t rid;
1073 int error;
1074
1075 mtx_lock_spin(&icu_lock);
1076 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1077 if (io->io_apic_id == apic_id)
1078 break;
1079 }
1080 mtx_unlock_spin(&icu_lock);
1081 if (io == NULL || io->pci_dev == NULL)
1082 return (EINVAL);
1083 error = pci_get_id(io->pci_dev, PCI_ID_RID, &rid);
1084 if (error != 0)
1085 return (error);
1086 *ridp = rid;
1087 return (0);
1088 }
1089
1090 device_t
ioapic_get_dev(u_int apic_id)1091 ioapic_get_dev(u_int apic_id)
1092 {
1093 struct ioapic *io;
1094
1095 mtx_lock_spin(&icu_lock);
1096 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1097 if (io->io_hw_apic_id == apic_id)
1098 break;
1099 }
1100 mtx_unlock_spin(&icu_lock);
1101 if (io != NULL)
1102 return (io->pci_dev);
1103 return (NULL);
1104 }
1105
1106 /*
1107 * A new-bus driver to consume the memory resources associated with
1108 * the APICs in the system. On some systems ACPI or PnPBIOS system
1109 * resource devices may already claim these resources. To keep from
1110 * breaking those devices, we attach ourself to the nexus device after
1111 * legacy0 and acpi0 and ignore any allocation failures.
1112 */
1113 static void
apic_identify(driver_t * driver,device_t parent)1114 apic_identify(driver_t *driver, device_t parent)
1115 {
1116
1117 /*
1118 * Add at order 12. acpi0 is probed at order 10 and legacy0
1119 * is probed at order 11.
1120 */
1121 if (lapic_paddr != 0)
1122 BUS_ADD_CHILD(parent, 12, "apic", 0);
1123 }
1124
1125 static int
apic_probe(device_t dev)1126 apic_probe(device_t dev)
1127 {
1128
1129 device_set_desc(dev, "APIC resources");
1130 device_quiet(dev);
1131 return (0);
1132 }
1133
1134 static void
apic_add_resource(device_t dev,int rid,vm_paddr_t base,size_t length)1135 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length)
1136 {
1137 int error;
1138
1139 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length);
1140 if (error)
1141 panic("apic_add_resource: resource %d failed set with %d", rid,
1142 error);
1143 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_SHAREABLE);
1144 }
1145
1146 static int
apic_attach(device_t dev)1147 apic_attach(device_t dev)
1148 {
1149 struct ioapic *io;
1150 int i;
1151
1152 /* Reserve the local APIC. */
1153 apic_add_resource(dev, 0, lapic_paddr, LAPIC_MEM_REGION);
1154 i = 1;
1155 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1156 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION);
1157 i++;
1158 }
1159 return (0);
1160 }
1161
1162 static device_method_t apic_methods[] = {
1163 /* Device interface */
1164 DEVMETHOD(device_identify, apic_identify),
1165 DEVMETHOD(device_probe, apic_probe),
1166 DEVMETHOD(device_attach, apic_attach),
1167
1168 DEVMETHOD_END
1169 };
1170
1171 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0);
1172
1173 DRIVER_MODULE(apic, nexus, apic_driver, 0, 0);
1174
1175 #include "opt_ddb.h"
1176
1177 #ifdef DDB
1178 #include <ddb/ddb.h>
1179
1180 static const char *
ioapic_delivery_mode(uint32_t mode)1181 ioapic_delivery_mode(uint32_t mode)
1182 {
1183
1184 switch (mode) {
1185 case IOART_DELFIXED:
1186 return ("fixed");
1187 case IOART_DELLOPRI:
1188 return ("lowestpri");
1189 case IOART_DELSMI:
1190 return ("SMI");
1191 case IOART_DELRSV1:
1192 return ("rsrvd1");
1193 case IOART_DELNMI:
1194 return ("NMI");
1195 case IOART_DELINIT:
1196 return ("INIT");
1197 case IOART_DELRSV2:
1198 return ("rsrvd2");
1199 case IOART_DELEXINT:
1200 return ("ExtINT");
1201 default:
1202 return ("");
1203 }
1204 }
1205
1206 static u_int
db_ioapic_read(volatile ioapic_t * apic,int reg)1207 db_ioapic_read(volatile ioapic_t *apic, int reg)
1208 {
1209
1210 apic->ioregsel = reg;
1211 return (apic->iowin);
1212 }
1213
1214 static void
db_show_ioapic_one(volatile ioapic_t * io_addr)1215 db_show_ioapic_one(volatile ioapic_t *io_addr)
1216 {
1217 uint32_t r, lo, hi;
1218 int mre, i;
1219
1220 r = db_ioapic_read(io_addr, IOAPIC_VER);
1221 mre = (r & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT;
1222 db_printf("Id 0x%08x Ver 0x%02x MRE %d\n",
1223 db_ioapic_read(io_addr, IOAPIC_ID), r & IOART_VER_VERSION, mre);
1224 for (i = 0; i < mre; i++) {
1225 lo = db_ioapic_read(io_addr, IOAPIC_REDTBL_LO(i));
1226 hi = db_ioapic_read(io_addr, IOAPIC_REDTBL_HI(i));
1227 db_printf(" pin %d Dest %s/%x %smasked Trig %s RemoteIRR %d "
1228 "Polarity %s Status %s DeliveryMode %s Vec %d\n", i,
1229 (lo & IOART_DESTMOD) == IOART_DESTLOG ? "log" : "phy",
1230 (hi & IOART_DEST) >> 24,
1231 (lo & IOART_INTMASK) == IOART_INTMSET ? "" : "not",
1232 (lo & IOART_TRGRMOD) == IOART_TRGRLVL ? "lvl" : "edge",
1233 (lo & IOART_REM_IRR) == IOART_REM_IRR ? 1 : 0,
1234 (lo & IOART_INTPOL) == IOART_INTALO ? "low" : "high",
1235 (lo & IOART_DELIVS) == IOART_DELIVS ? "pend" : "idle",
1236 ioapic_delivery_mode(lo & IOART_DELMOD),
1237 (lo & IOART_INTVEC));
1238 }
1239 }
1240
DB_SHOW_COMMAND(ioapic,db_show_ioapic)1241 DB_SHOW_COMMAND(ioapic, db_show_ioapic)
1242 {
1243 struct ioapic *ioapic;
1244 int idx, i;
1245
1246 if (!have_addr) {
1247 db_printf("usage: show ioapic index\n");
1248 return;
1249 }
1250
1251 idx = (int)addr;
1252 i = 0;
1253 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) {
1254 if (idx == i) {
1255 db_show_ioapic_one(ioapic->io_addr);
1256 break;
1257 }
1258 i++;
1259 }
1260 }
1261
DB_SHOW_ALL_COMMAND(ioapics,db_show_all_ioapics)1262 DB_SHOW_ALL_COMMAND(ioapics, db_show_all_ioapics)
1263 {
1264 struct ioapic *ioapic;
1265
1266 STAILQ_FOREACH(ioapic, &ioapic_list, io_next)
1267 db_show_ioapic_one(ioapic->io_addr);
1268 }
1269 #endif
1270