1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef __TEGRA_VI_H__ 7 #define __TEGRA_VI_H__ 8 9 #include <linux/host1x.h> 10 #include <linux/list.h> 11 12 #include <linux/mutex.h> 13 #include <linux/spinlock.h> 14 #include <linux/wait.h> 15 16 #include <media/media-entity.h> 17 #include <media/v4l2-async.h> 18 #include <media/v4l2-ctrls.h> 19 #include <media/v4l2-device.h> 20 #include <media/v4l2-dev.h> 21 #include <media/v4l2-subdev.h> 22 #include <media/videobuf2-v4l2.h> 23 24 #include "csi.h" 25 26 #define V4L2_CID_TEGRA_SYNCPT_TIMEOUT_RETRY (V4L2_CTRL_CLASS_CAMERA | 0x1001) 27 28 #define TEGRA_DEF_WIDTH 1920 29 #define TEGRA_DEF_HEIGHT 1080 30 #define TEGRA_IMAGE_FORMAT_DEF 32 31 32 #define MAX_FORMAT_NUM 64 33 34 enum tegra_vi_pg_mode { 35 TEGRA_VI_PG_DISABLED = 0, 36 TEGRA_VI_PG_DIRECT, 37 TEGRA_VI_PG_PATCH, 38 }; 39 40 struct tegra_vi; 41 struct tegra_vi_channel; 42 43 /** 44 * struct tegra_vi_ops - Tegra VI operations 45 * @vi_enable: soc-specific operations needed to enable/disable the VI peripheral 46 * @channel_host1x_syncpt_init: initialize synchronization points 47 * @channel_host1x_syncpt_free: free all synchronization points 48 * @vi_fmt_align: modify `pix` to fit the hardware alignment 49 * requirements and fill image geometry 50 * @channel_queue_setup: additional operations at the end of vb2_ops::queue_setup 51 * @vi_start_streaming: starts media pipeline, subdevice streaming, sets up 52 * VI for capture and runs capture start and capture finish 53 * kthreads for capturing frames to buffer and returns them back. 54 * @vi_stop_streaming: stops media pipeline and subdevice streaming and returns 55 * back any queued buffers. 56 */ 57 struct tegra_vi_ops { 58 int (*vi_enable)(struct tegra_vi *vi, bool on); 59 int (*channel_host1x_syncpt_init)(struct tegra_vi_channel *chan); 60 void (*channel_host1x_syncpt_free)(struct tegra_vi_channel *chan); 61 void (*vi_fmt_align)(struct v4l2_pix_format *pix, unsigned int bpp); 62 void (*channel_queue_setup)(struct tegra_vi_channel *chan); 63 int (*vi_start_streaming)(struct vb2_queue *vq, u32 count); 64 void (*vi_stop_streaming)(struct vb2_queue *vq); 65 }; 66 67 /** 68 * struct tegra_vi_soc - NVIDIA Tegra Video Input SoC structure 69 * 70 * @video_formats: supported video formats 71 * @nformats: total video formats 72 * @default_video_format: default video format (pointer to a @video_formats item) 73 * @ops: vi operations 74 * @hw_revision: VI hw_revision 75 * @vi_max_channels: supported max streaming channels 76 * @vi_max_clk_hz: VI clock max frequency 77 * @has_h_v_flip: the chip can do H and V flip, and the driver implements it 78 */ 79 struct tegra_vi_soc { 80 const struct tegra_video_format *video_formats; 81 const unsigned int nformats; 82 const struct tegra_video_format *default_video_format; 83 const struct tegra_vi_ops *ops; 84 u32 hw_revision; 85 unsigned int vi_max_channels; 86 unsigned int vi_max_clk_hz; 87 bool has_h_v_flip:1; 88 }; 89 90 /** 91 * struct tegra_vi - NVIDIA Tegra Video Input device structure 92 * 93 * @dev: device struct 94 * @client: host1x_client struct 95 * @iomem: register base 96 * @clk: main clock for VI block 97 * @soc: pointer to SoC data structure 98 * @ops: vi operations 99 * @vi_chans: list head for VI channels 100 */ 101 struct tegra_vi { 102 struct device *dev; 103 struct host1x_client client; 104 void __iomem *iomem; 105 struct clk *clk; 106 const struct tegra_vi_soc *soc; 107 const struct tegra_vi_ops *ops; 108 struct list_head vi_chans; 109 }; 110 111 /** 112 * struct tegra_vi_channel - Tegra video channel 113 * 114 * @list: list head for this entry 115 * @video: V4L2 video device associated with the video channel 116 * @video_lock: protects the @format and @queue fields 117 * @pad: media pad for the video device entity 118 * 119 * @vi: Tegra video input device structure 120 * @frame_start_sp: host1x syncpoint pointer to synchronize programmed capture 121 * start condition with hardware frame start events through host1x 122 * syncpoint counters. (Tegra210) 123 * @mw_ack_sp: host1x syncpoint pointer to synchronize programmed memory write 124 * ack trigger condition with hardware memory write done at end of 125 * frame through host1x syncpoint counters (On Tegra20 used for the 126 * OUT_1 syncpt) 127 * @sp_incr_lock: protects cpu syncpoint increment. 128 * 129 * @kthread_start_capture: kthread to start capture of single frame when 130 * vb buffer is available. This thread programs VI CSI hardware 131 * for single frame capture and waits for frame start event from 132 * the hardware. On receiving frame start event, it wakes up 133 * kthread_finish_capture thread to wait for finishing frame data 134 * write to the memory. In case of missing frame start event, this 135 * thread returns buffer back to vb with VB2_BUF_STATE_ERROR. 136 * @start_wait: waitqueue for starting frame capture when buffer is available. 137 * @kthread_finish_capture: kthread to finish the buffer capture and return to. 138 * This thread is woken up by kthread_start_capture on receiving 139 * frame start event from the hardware and this thread waits for 140 * MW_ACK_DONE event which indicates completion of writing frame 141 * data to the memory. On receiving MW_ACK_DONE event, buffer is 142 * returned back to vb with VB2_BUF_STATE_DONE and in case of 143 * missing MW_ACK_DONE event, buffer is returned back to vb with 144 * VB2_BUF_STATE_ERROR. 145 * @done_wait: waitqueue for finishing capture data writes to memory. 146 * 147 * @format: active V4L2 pixel format 148 * @fmtinfo: format information corresponding to the active @format 149 * @queue: vb2 buffers queue 150 * @sequence: V4L2 buffers sequence number 151 * 152 * @addr_offset_u: U plane base address, relative to buffer base address (only for planar) 153 * @addr_offset_v: V plane base address, relative to buffer base address (only for planar) 154 * @start_offset: 1st Y byte to write, relative to buffer base address (for H/V flip) 155 * @start_offset_u: 1st U byte to write, relative to buffer base address (for H/V flip) 156 * @start_offset_v: 1st V byte to write, relative to buffer base address (for H/V flip) 157 * 158 * @capture: list of queued buffers for capture 159 * @start_lock: protects the capture queued list 160 * @done: list of capture done queued buffers 161 * @done_lock: protects the capture done queue list 162 * 163 * @portnos: VI channel port numbers 164 * @totalports: total number of ports used for this channel 165 * @numgangports: number of ports combined together as a gang for capture 166 * @of_node: device node of VI channel 167 * 168 * @ctrl_handler: V4L2 control handler of this video channel 169 * @syncpt_timeout_retry: syncpt timeout retry count for the capture 170 * @fmts_bitmap: a bitmap for supported formats matching v4l2 subdev formats 171 * @tpg_fmts_bitmap: a bitmap for supported TPG formats 172 * @pg_mode: test pattern generator mode (disabled/direct/patch) 173 * @notifier: V4L2 asynchronous subdevs notifier 174 * 175 * @hflip: Horizontal flip is enabled 176 * @vflip: Vertical flip is enabled 177 */ 178 struct tegra_vi_channel { 179 struct list_head list; 180 struct video_device video; 181 /* protects the @format and @queue fields */ 182 struct mutex video_lock; 183 struct media_pad pad; 184 185 struct tegra_vi *vi; 186 struct host1x_syncpt *frame_start_sp[GANG_PORTS_MAX]; 187 struct host1x_syncpt *mw_ack_sp[GANG_PORTS_MAX]; 188 /* protects the cpu syncpoint increment */ 189 spinlock_t sp_incr_lock[GANG_PORTS_MAX]; 190 191 struct task_struct *kthread_start_capture; 192 wait_queue_head_t start_wait; 193 struct task_struct *kthread_finish_capture; 194 wait_queue_head_t done_wait; 195 196 struct v4l2_pix_format format; 197 const struct tegra_video_format *fmtinfo; 198 struct vb2_queue queue; 199 u32 sequence; 200 201 unsigned int addr_offset_u; 202 unsigned int addr_offset_v; 203 unsigned int start_offset; 204 unsigned int start_offset_u; 205 unsigned int start_offset_v; 206 207 struct list_head capture; 208 /* protects the capture queued list */ 209 spinlock_t start_lock; 210 struct list_head done; 211 /* protects the capture done queue list */ 212 spinlock_t done_lock; 213 214 unsigned char portnos[GANG_PORTS_MAX]; 215 u8 totalports; 216 u8 numgangports; 217 struct device_node *of_node; 218 219 struct v4l2_ctrl_handler ctrl_handler; 220 unsigned int syncpt_timeout_retry; 221 DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM); 222 DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM); 223 enum tegra_vi_pg_mode pg_mode; 224 225 struct v4l2_async_notifier notifier; 226 227 bool hflip:1; 228 bool vflip:1; 229 }; 230 231 /** 232 * struct tegra_channel_buffer - video channel buffer 233 * 234 * @buf: vb2 buffer base object 235 * @queue: buffer list entry in the channel queued buffers list 236 * @chan: channel that uses the buffer 237 * @addr: Tegra IOVA buffer address for VI output 238 * @mw_ack_sp_thresh: MW_ACK_DONE syncpoint threshold corresponding 239 * to the capture buffer. 240 */ 241 struct tegra_channel_buffer { 242 struct vb2_v4l2_buffer buf; 243 struct list_head queue; 244 struct tegra_vi_channel *chan; 245 dma_addr_t addr; 246 u32 mw_ack_sp_thresh[GANG_PORTS_MAX]; 247 }; 248 249 /* 250 * VI channel input data type enum. 251 * These data type enum value gets programmed into corresponding Tegra VI 252 * channel register bits. 253 */ 254 enum tegra_image_dt { 255 TEGRA_IMAGE_DT_YUV420_8 = 24, 256 TEGRA_IMAGE_DT_YUV420_10, 257 258 TEGRA_IMAGE_DT_YUV420CSPS_8 = 28, 259 TEGRA_IMAGE_DT_YUV420CSPS_10, 260 TEGRA_IMAGE_DT_YUV422_8, 261 TEGRA_IMAGE_DT_YUV422_10, 262 TEGRA_IMAGE_DT_RGB444, 263 TEGRA_IMAGE_DT_RGB555, 264 TEGRA_IMAGE_DT_RGB565, 265 TEGRA_IMAGE_DT_RGB666, 266 TEGRA_IMAGE_DT_RGB888, 267 268 TEGRA_IMAGE_DT_RAW6 = 40, 269 TEGRA_IMAGE_DT_RAW7, 270 TEGRA_IMAGE_DT_RAW8, 271 TEGRA_IMAGE_DT_RAW10, 272 TEGRA_IMAGE_DT_RAW12, 273 TEGRA_IMAGE_DT_RAW14, 274 }; 275 276 /** 277 * struct tegra_video_format - Tegra video format description 278 * 279 * @img_dt: MIPI CSI-2 data type (for CSI-2 only) 280 * @bit_width: format width in bits per component (for CSI/Tegra210 only) 281 * @code: media bus format code 282 * @bpp: bytes per pixel (when stored in memory) 283 * @img_fmt: image format (for CSI/Tegra210 only) 284 * @fourcc: V4L2 pixel format FCC identifier 285 */ 286 struct tegra_video_format { 287 enum tegra_image_dt img_dt; 288 unsigned int bit_width; 289 unsigned int code; 290 unsigned int bpp; 291 u32 img_fmt; 292 u32 fourcc; 293 }; 294 295 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC) 296 extern const struct tegra_vi_soc tegra20_vi_soc; 297 #endif 298 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 299 extern const struct tegra_vi_soc tegra210_vi_soc; 300 #endif 301 302 struct v4l2_subdev * 303 tegra_channel_get_remote_csi_subdev(struct tegra_vi_channel *chan); 304 struct v4l2_subdev * 305 tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan); 306 int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on); 307 void tegra_channel_release_buffers(struct tegra_vi_channel *chan, 308 enum vb2_buffer_state state); 309 void tegra_channels_cleanup(struct tegra_vi *vi); 310 #endif 311