1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Qualcomm PM8xxx PMIC XOADC driver
4 *
5 * These ADCs are known as HK/XO (house keeping / chrystal oscillator)
6 * "XO" in "XOADC" means Chrystal Oscillator. It's a bunch of
7 * specific-purpose and general purpose ADC converters and channels.
8 *
9 * Copyright (C) 2017 Linaro Ltd.
10 * Author: Linus Walleij <linus.walleij@linaro.org>
11 */
12
13 #include <linux/iio/adc/qcom-vadc-common.h>
14 #include <linux/iio/iio.h>
15 #include <linux/iio/sysfs.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/property.h>
19 #include <linux/regmap.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/regulator/consumer.h>
23
24 /*
25 * Definitions for the "user processor" registers lifted from the v3.4
26 * Qualcomm tree. Their kernel has two out-of-tree drivers for the ADC:
27 * drivers/misc/pmic8058-xoadc.c
28 * drivers/hwmon/pm8xxx-adc.c
29 * None of them contain any complete register specification, so this is
30 * a best effort of combining the information.
31 */
32
33 /* These appear to be "battery monitor" registers */
34 #define ADC_ARB_BTM_CNTRL1 0x17e
35 #define ADC_ARB_BTM_CNTRL1_EN_BTM BIT(0)
36 #define ADC_ARB_BTM_CNTRL1_SEL_OP_MODE BIT(1)
37 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL1 BIT(2)
38 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL2 BIT(3)
39 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL3 BIT(4)
40 #define ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL4 BIT(5)
41 #define ADC_ARB_BTM_CNTRL1_EOC BIT(6)
42 #define ADC_ARB_BTM_CNTRL1_REQ BIT(7)
43
44 #define ADC_ARB_BTM_AMUX_CNTRL 0x17f
45 #define ADC_ARB_BTM_ANA_PARAM 0x180
46 #define ADC_ARB_BTM_DIG_PARAM 0x181
47 #define ADC_ARB_BTM_RSV 0x182
48 #define ADC_ARB_BTM_DATA1 0x183
49 #define ADC_ARB_BTM_DATA0 0x184
50 #define ADC_ARB_BTM_BAT_COOL_THR1 0x185
51 #define ADC_ARB_BTM_BAT_COOL_THR0 0x186
52 #define ADC_ARB_BTM_BAT_WARM_THR1 0x187
53 #define ADC_ARB_BTM_BAT_WARM_THR0 0x188
54 #define ADC_ARB_BTM_CNTRL2 0x18c
55
56 /* Proper ADC registers */
57
58 #define ADC_ARB_USRP_CNTRL 0x197
59 #define ADC_ARB_USRP_CNTRL_EN_ARB BIT(0)
60 #define ADC_ARB_USRP_CNTRL_RSV1 BIT(1)
61 #define ADC_ARB_USRP_CNTRL_RSV2 BIT(2)
62 #define ADC_ARB_USRP_CNTRL_RSV3 BIT(3)
63 #define ADC_ARB_USRP_CNTRL_RSV4 BIT(4)
64 #define ADC_ARB_USRP_CNTRL_RSV5 BIT(5)
65 #define ADC_ARB_USRP_CNTRL_EOC BIT(6)
66 #define ADC_ARB_USRP_CNTRL_REQ BIT(7)
67
68 #define ADC_ARB_USRP_AMUX_CNTRL 0x198
69 /*
70 * The channel mask includes the bits selecting channel mux and prescaler
71 * on PM8058, or channel mux and premux on PM8921.
72 */
73 #define ADC_ARB_USRP_AMUX_CNTRL_CHAN_MASK 0xfc
74 #define ADC_ARB_USRP_AMUX_CNTRL_RSV0 BIT(0)
75 #define ADC_ARB_USRP_AMUX_CNTRL_RSV1 BIT(1)
76 /* On PM8058 this is prescaling, on PM8921 this is premux */
77 #define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX0 BIT(2)
78 #define ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX1 BIT(3)
79 #define ADC_ARB_USRP_AMUX_CNTRL_SEL0 BIT(4)
80 #define ADC_ARB_USRP_AMUX_CNTRL_SEL1 BIT(5)
81 #define ADC_ARB_USRP_AMUX_CNTRL_SEL2 BIT(6)
82 #define ADC_ARB_USRP_AMUX_CNTRL_SEL3 BIT(7)
83 #define ADC_AMUX_PREMUX_SHIFT 2
84 #define ADC_AMUX_SEL_SHIFT 4
85
86 /* We know very little about the bits in this register */
87 #define ADC_ARB_USRP_ANA_PARAM 0x199
88 #define ADC_ARB_USRP_ANA_PARAM_DIS 0xFE
89 #define ADC_ARB_USRP_ANA_PARAM_EN 0xFF
90
91 #define ADC_ARB_USRP_DIG_PARAM 0x19A
92 #define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 BIT(0)
93 #define ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 BIT(1)
94 #define ADC_ARB_USRP_DIG_PARAM_CLK_RATE0 BIT(2)
95 #define ADC_ARB_USRP_DIG_PARAM_CLK_RATE1 BIT(3)
96 #define ADC_ARB_USRP_DIG_PARAM_EOC BIT(4)
97 /*
98 * On a later ADC the decimation factors are defined as
99 * 00 = 512, 01 = 1024, 10 = 2048, 11 = 4096 so assume this
100 * holds also for this older XOADC.
101 */
102 #define ADC_ARB_USRP_DIG_PARAM_DEC_RATE0 BIT(5)
103 #define ADC_ARB_USRP_DIG_PARAM_DEC_RATE1 BIT(6)
104 #define ADC_ARB_USRP_DIG_PARAM_EN BIT(7)
105 #define ADC_DIG_PARAM_DEC_SHIFT 5
106
107 #define ADC_ARB_USRP_RSV 0x19B
108 #define ADC_ARB_USRP_RSV_RST BIT(0)
109 #define ADC_ARB_USRP_RSV_DTEST0 BIT(1)
110 #define ADC_ARB_USRP_RSV_DTEST1 BIT(2)
111 #define ADC_ARB_USRP_RSV_OP BIT(3)
112 #define ADC_ARB_USRP_RSV_IP_SEL0 BIT(4)
113 #define ADC_ARB_USRP_RSV_IP_SEL1 BIT(5)
114 #define ADC_ARB_USRP_RSV_IP_SEL2 BIT(6)
115 #define ADC_ARB_USRP_RSV_TRM BIT(7)
116 #define ADC_RSV_IP_SEL_SHIFT 4
117
118 #define ADC_ARB_USRP_DATA0 0x19D
119 #define ADC_ARB_USRP_DATA1 0x19C
120
121 /*
122 * Physical channels which MUST exist on all PM variants in order to provide
123 * proper reference points for calibration.
124 *
125 * @PM8XXX_CHANNEL_INTERNAL: 625mV reference channel
126 * @PM8XXX_CHANNEL_125V: 1250mV reference channel
127 * @PM8XXX_CHANNEL_INTERNAL_2: 325mV reference channel
128 * @PM8XXX_CHANNEL_MUXOFF: channel to reduce input load on mux, apparently also
129 * measures XO temperature
130 */
131 #define PM8XXX_CHANNEL_INTERNAL 0x0c
132 #define PM8XXX_CHANNEL_125V 0x0d
133 #define PM8XXX_CHANNEL_INTERNAL_2 0x0e
134 #define PM8XXX_CHANNEL_MUXOFF 0x0f
135
136 /*
137 * PM8058 AMUX premux scaling, two bits. This is done of the channel before
138 * reaching the AMUX.
139 */
140 #define PM8058_AMUX_PRESCALE_0 0x0 /* No scaling on the signal */
141 #define PM8058_AMUX_PRESCALE_1 0x1 /* Unity scaling selected by the user */
142 #define PM8058_AMUX_PRESCALE_1_DIV3 0x2 /* 1/3 prescaler on the input */
143
144 /* Defines reference voltage for the XOADC */
145 #define AMUX_RSV0 0x0 /* XO_IN/XOADC_GND, special selection to read XO temp */
146 #define AMUX_RSV1 0x1 /* PMIC_IN/XOADC_GND */
147 #define AMUX_RSV2 0x2 /* PMIC_IN/BMS_CSP */
148 #define AMUX_RSV3 0x3 /* not used */
149 #define AMUX_RSV4 0x4 /* XOADC_GND/XOADC_GND */
150 #define AMUX_RSV5 0x5 /* XOADC_VREF/XOADC_GND */
151 #define XOADC_RSV_MAX 5 /* 3 bits 0..7, 3 and 6,7 are invalid */
152
153 /**
154 * struct xoadc_channel - encodes channel properties and defaults
155 * @datasheet_name: the hardwarename of this channel
156 * @pre_scale_mux: prescale (PM8058) or premux (PM8921) for selecting
157 * this channel. Both this and the amux channel is needed to uniquely
158 * identify a channel. Values 0..3.
159 * @amux_channel: value of the ADC_ARB_USRP_AMUX_CNTRL register for this
160 * channel, bits 4..7, selects the amux, values 0..f
161 * @prescale: the channels have hard-coded prescale ratios defined
162 * by the hardware, this tells us what it is
163 * @type: corresponding IIO channel type, usually IIO_VOLTAGE or
164 * IIO_TEMP
165 * @scale_fn_type: the liner interpolation etc to convert the
166 * ADC code to the value that IIO expects, in uV or millicelsius
167 * etc. This scale function can be pretty elaborate if different
168 * thermistors are connected or other hardware characteristics are
169 * deployed.
170 * @amux_ip_rsv: ratiometric scale value used by the analog muxer: this
171 * selects the reference voltage for ratiometric scaling
172 */
173 struct xoadc_channel {
174 const char *datasheet_name;
175 u8 pre_scale_mux:2;
176 u8 amux_channel:4;
177 const struct u32_fract prescale;
178 enum iio_chan_type type;
179 enum vadc_scale_fn_type scale_fn_type;
180 u8 amux_ip_rsv:3;
181 };
182
183 /**
184 * struct xoadc_variant - encodes the XOADC variant characteristics
185 * @name: name of this PMIC variant
186 * @channels: the hardware channels and respective settings and defaults
187 * @broken_ratiometric: if the PMIC has broken ratiometric scaling (this
188 * is a known problem on PM8058)
189 * @prescaling: this variant uses AMUX bits 2 & 3 for prescaling (PM8058)
190 * @second_level_mux: this variant uses AMUX bits 2 & 3 for a second level
191 * mux
192 */
193 struct xoadc_variant {
194 const char name[16];
195 const struct xoadc_channel *channels;
196 bool broken_ratiometric;
197 bool prescaling;
198 bool second_level_mux;
199 };
200
201 /*
202 * XOADC_CHAN macro parameters:
203 * _dname: the name of the channel
204 * _presmux: prescaler (PM8058) or premux (PM8921) setting for this channel
205 * _amux: the value in bits 2..7 of the ADC_ARB_USRP_AMUX_CNTRL register
206 * for this channel. On some PMICs some of the bits select a prescaler, and
207 * on some PMICs some of the bits select various complex multiplex settings.
208 * _type: IIO channel type
209 * _prenum: prescaler numerator (dividend)
210 * _preden: prescaler denominator (divisor)
211 * _scale: scaling function type, this selects how the raw valued is mangled
212 * to output the actual processed measurement
213 * _amip: analog mux input parent when using ratiometric measurements
214 */
215 #define XOADC_CHAN(_dname, _presmux, _amux, _type, _prenum, _preden, _scale, _amip) \
216 { \
217 .datasheet_name = __stringify(_dname), \
218 .pre_scale_mux = _presmux, \
219 .amux_channel = _amux, \
220 .prescale = { \
221 .numerator = _prenum, .denominator = _preden, \
222 }, \
223 .type = _type, \
224 .scale_fn_type = _scale, \
225 .amux_ip_rsv = _amip, \
226 }
227
228 /*
229 * Taken from arch/arm/mach-msm/board-9615.c in the vendor tree:
230 * TODO: incomplete, needs testing.
231 */
232 static const struct xoadc_channel pm8018_xoadc_channels[] = {
233 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
234 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
235 XOADC_CHAN(VPH_PWR, 0x00, 0x02, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
236 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
237 /* Used for battery ID or battery temperature */
238 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV2),
239 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
240 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
241 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
242 { }, /* Sentinel */
243 };
244
245 /*
246 * Taken from arch/arm/mach-msm/board-8930-pmic.c in the vendor tree:
247 * TODO: needs testing.
248 */
249 static const struct xoadc_channel pm8038_xoadc_channels[] = {
250 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
251 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
252 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
253 XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
254 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
255 XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
256 XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
257 XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
258 /* AMUX8 used for battery temperature in most cases */
259 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV2),
260 XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
261 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1),
262 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
263 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
264 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
265 XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
266 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
267 { }, /* Sentinel */
268 };
269
270 /*
271 * This was created by cross-referencing the vendor tree
272 * arch/arm/mach-msm/board-msm8x60.c msm_adc_channels_data[]
273 * with the "channel types" (first field) to find the right
274 * configuration for these channels on an MSM8x60 i.e. PM8058
275 * setup.
276 */
277 static const struct xoadc_channel pm8058_xoadc_channels[] = {
278 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
279 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
280 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 10, SCALE_DEFAULT, AMUX_RSV1),
281 XOADC_CHAN(ICHG, 0x00, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
282 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
283 /*
284 * AMUX channels 5 thru 9 are referred to as MPP5 thru MPP9 in
285 * some code and documentation. But they are really just 5
286 * channels just like any other. They are connected to a switching
287 * matrix where they can be routed to any of the MPPs, not just
288 * 1-to-1 onto MPP5 thru 9, so naming them MPP5 thru MPP9 is
289 * very confusing.
290 */
291 XOADC_CHAN(AMUX5, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
292 XOADC_CHAN(AMUX6, 0x00, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
293 XOADC_CHAN(AMUX7, 0x00, 0x07, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
294 XOADC_CHAN(AMUX8, 0x00, 0x08, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
295 XOADC_CHAN(AMUX9, 0x00, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
296 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
297 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
298 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
299 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
300 XOADC_CHAN(INTERNAL_2, 0x00, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
301 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
302 /* There are also "unity" and divided by 3 channels (prescaler) but noone is using them */
303 { }, /* Sentinel */
304 };
305
306 /*
307 * The PM8921 has some pre-muxing on its channels, this comes from the vendor tree
308 * include/linux/mfd/pm8xxx/pm8xxx-adc.h
309 * board-flo-pmic.c (Nexus 7) and board-8064-pmic.c
310 */
311 static const struct xoadc_channel pm8921_xoadc_channels[] = {
312 XOADC_CHAN(VCOIN, 0x00, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
313 XOADC_CHAN(VBAT, 0x00, 0x01, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
314 XOADC_CHAN(DCIN, 0x00, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
315 /* channel "ICHG" is reserved and not used on PM8921 */
316 XOADC_CHAN(VPH_PWR, 0x00, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
317 XOADC_CHAN(IBAT, 0x00, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
318 /* CHAN 6 & 7 (MPP1 & MPP2) are reserved for MPP channels on PM8921 */
319 XOADC_CHAN(BATT_THERM, 0x00, 0x08, IIO_TEMP, 1, 1, SCALE_THERM_100K_PULLUP, AMUX_RSV1),
320 XOADC_CHAN(BATT_ID, 0x00, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
321 XOADC_CHAN(USB_VBUS, 0x00, 0x0a, IIO_VOLTAGE, 1, 4, SCALE_DEFAULT, AMUX_RSV1),
322 XOADC_CHAN(DIE_TEMP, 0x00, 0x0b, IIO_TEMP, 1, 1, SCALE_PMIC_THERM, AMUX_RSV1),
323 XOADC_CHAN(INTERNAL, 0x00, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
324 XOADC_CHAN(125V, 0x00, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
325 /* FIXME: look into the scaling of this temperature */
326 XOADC_CHAN(CHG_TEMP, 0x00, 0x0e, IIO_TEMP, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
327 XOADC_CHAN(MUXOFF, 0x00, 0x0f, IIO_TEMP, 1, 1, SCALE_XOTHERM, AMUX_RSV0),
328 /* The following channels have premux bit 0 set to 1 (all end in 4) */
329 XOADC_CHAN(ATEST_8, 0x01, 0x00, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
330 /* Set scaling to 1/2 based on the name for these two */
331 XOADC_CHAN(USB_SNS_DIV20, 0x01, 0x01, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
332 XOADC_CHAN(DCIN_SNS_DIV20, 0x01, 0x02, IIO_VOLTAGE, 1, 2, SCALE_DEFAULT, AMUX_RSV1),
333 XOADC_CHAN(AMUX3, 0x01, 0x03, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
334 XOADC_CHAN(AMUX4, 0x01, 0x04, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
335 XOADC_CHAN(AMUX5, 0x01, 0x05, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
336 XOADC_CHAN(AMUX6, 0x01, 0x06, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
337 XOADC_CHAN(AMUX7, 0x01, 0x07, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
338 XOADC_CHAN(AMUX8, 0x01, 0x08, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
339 /* Internal test signals, I think */
340 XOADC_CHAN(ATEST_1, 0x01, 0x09, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
341 XOADC_CHAN(ATEST_2, 0x01, 0x0a, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
342 XOADC_CHAN(ATEST_3, 0x01, 0x0b, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
343 XOADC_CHAN(ATEST_4, 0x01, 0x0c, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
344 XOADC_CHAN(ATEST_5, 0x01, 0x0d, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
345 XOADC_CHAN(ATEST_6, 0x01, 0x0e, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
346 XOADC_CHAN(ATEST_7, 0x01, 0x0f, IIO_VOLTAGE, 1, 1, SCALE_DEFAULT, AMUX_RSV1),
347 /* The following channels have premux bit 1 set to 1 (all end in 8) */
348 /* I guess even ATEST8 will be divided by 3 here */
349 XOADC_CHAN(ATEST_8, 0x02, 0x00, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
350 /* I guess div 2 div 3 becomes div 6 */
351 XOADC_CHAN(USB_SNS_DIV20_DIV3, 0x02, 0x01, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
352 XOADC_CHAN(DCIN_SNS_DIV20_DIV3, 0x02, 0x02, IIO_VOLTAGE, 1, 6, SCALE_DEFAULT, AMUX_RSV1),
353 XOADC_CHAN(AMUX3_DIV3, 0x02, 0x03, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
354 XOADC_CHAN(AMUX4_DIV3, 0x02, 0x04, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
355 XOADC_CHAN(AMUX5_DIV3, 0x02, 0x05, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
356 XOADC_CHAN(AMUX6_DIV3, 0x02, 0x06, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
357 XOADC_CHAN(AMUX7_DIV3, 0x02, 0x07, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
358 XOADC_CHAN(AMUX8_DIV3, 0x02, 0x08, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
359 XOADC_CHAN(ATEST_1_DIV3, 0x02, 0x09, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
360 XOADC_CHAN(ATEST_2_DIV3, 0x02, 0x0a, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
361 XOADC_CHAN(ATEST_3_DIV3, 0x02, 0x0b, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
362 XOADC_CHAN(ATEST_4_DIV3, 0x02, 0x0c, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
363 XOADC_CHAN(ATEST_5_DIV3, 0x02, 0x0d, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
364 XOADC_CHAN(ATEST_6_DIV3, 0x02, 0x0e, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
365 XOADC_CHAN(ATEST_7_DIV3, 0x02, 0x0f, IIO_VOLTAGE, 1, 3, SCALE_DEFAULT, AMUX_RSV1),
366 { }, /* Sentinel */
367 };
368
369 /**
370 * struct pm8xxx_chan_info - ADC channel information
371 * @label: label of this channel from device tree (defaults to datasheet name if not specified)
372 * @hwchan: pointer to hardware channel information (muxing & scaling settings)
373 * @calibration: whether to use absolute or ratiometric calibration
374 * @decimation: 0,1,2,3
375 * @amux_ip_rsv: ratiometric scale value if using ratiometric
376 * calibration: 0, 1, 2, 4, 5.
377 */
378 struct pm8xxx_chan_info {
379 const char *label;
380 const struct xoadc_channel *hwchan;
381 enum vadc_calibration calibration;
382 u8 decimation:2;
383 u8 amux_ip_rsv:3;
384 };
385
386 /**
387 * struct pm8xxx_xoadc - state container for the XOADC
388 * @dev: pointer to device
389 * @map: regmap to access registers
390 * @variant: XOADC variant characteristics
391 * @vref: reference voltage regulator
392 * characteristics of the channels, and sensible default settings
393 * @nchans: number of channels, configured by the device tree
394 * @chans: the channel information per-channel, configured by the device tree
395 * @iio_chans: IIO channel specifiers
396 * @graph: linear calibration parameters for absolute and
397 * ratiometric measurements
398 * @complete: completion to indicate end of conversion
399 * @lock: lock to restrict access to the hardware to one client at the time
400 */
401 struct pm8xxx_xoadc {
402 struct device *dev;
403 struct regmap *map;
404 const struct xoadc_variant *variant;
405 struct regulator *vref;
406 unsigned int nchans;
407 struct pm8xxx_chan_info *chans;
408 struct iio_chan_spec *iio_chans;
409 struct vadc_linear_graph graph[2];
410 struct completion complete;
411 struct mutex lock;
412 };
413
pm8xxx_eoc_irq(int irq,void * d)414 static irqreturn_t pm8xxx_eoc_irq(int irq, void *d)
415 {
416 struct iio_dev *indio_dev = d;
417 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
418
419 complete(&adc->complete);
420
421 return IRQ_HANDLED;
422 }
423
424 static struct pm8xxx_chan_info *
pm8xxx_get_channel(struct pm8xxx_xoadc * adc,u8 chan)425 pm8xxx_get_channel(struct pm8xxx_xoadc *adc, u8 chan)
426 {
427 int i;
428
429 for (i = 0; i < adc->nchans; i++) {
430 struct pm8xxx_chan_info *ch = &adc->chans[i];
431 if (ch->hwchan->amux_channel == chan)
432 return ch;
433 }
434 return NULL;
435 }
436
pm8xxx_read_channel_rsv(struct pm8xxx_xoadc * adc,const struct pm8xxx_chan_info * ch,u8 rsv,u16 * adc_code,bool force_ratiometric)437 static int pm8xxx_read_channel_rsv(struct pm8xxx_xoadc *adc,
438 const struct pm8xxx_chan_info *ch,
439 u8 rsv, u16 *adc_code,
440 bool force_ratiometric)
441 {
442 int ret;
443 unsigned int val;
444 u8 rsvmask, rsvval;
445 u8 lsb, msb;
446
447 dev_dbg(adc->dev, "read channel \"%s\", amux %d, prescale/mux: %d, rsv %d\n",
448 ch->label, ch->hwchan->amux_channel, ch->hwchan->pre_scale_mux, rsv);
449
450 mutex_lock(&adc->lock);
451
452 /* Mux in this channel */
453 val = ch->hwchan->amux_channel << ADC_AMUX_SEL_SHIFT;
454 val |= ch->hwchan->pre_scale_mux << ADC_AMUX_PREMUX_SHIFT;
455 ret = regmap_write(adc->map, ADC_ARB_USRP_AMUX_CNTRL, val);
456 if (ret)
457 goto unlock;
458
459 /* Set up ratiometric scale value, mask off all bits except these */
460 rsvmask = (ADC_ARB_USRP_RSV_RST | ADC_ARB_USRP_RSV_DTEST0 |
461 ADC_ARB_USRP_RSV_DTEST1 | ADC_ARB_USRP_RSV_OP);
462 if (adc->variant->broken_ratiometric && !force_ratiometric) {
463 /*
464 * Apparently the PM8058 has some kind of bug which is
465 * reflected in the vendor tree drivers/misc/pmix8058-xoadc.c
466 * which just hardcodes the RSV selector to SEL1 (0x20) for
467 * most cases and SEL0 (0x10) for the MUXOFF channel only.
468 * If we force ratiometric (currently only done when attempting
469 * to do ratiometric calibration) this doesn't seem to work
470 * very well and I suspect ratiometric conversion is simply
471 * broken or not supported on the PM8058.
472 *
473 * Maybe IO_SEL2 doesn't exist on PM8058 and bits 4 & 5 select
474 * the mode alone.
475 *
476 * Some PM8058 register documentation would be nice to get
477 * this right.
478 */
479 if (ch->hwchan->amux_channel == PM8XXX_CHANNEL_MUXOFF)
480 rsvval = ADC_ARB_USRP_RSV_IP_SEL0;
481 else
482 rsvval = ADC_ARB_USRP_RSV_IP_SEL1;
483 } else {
484 if (rsv == 0xff)
485 rsvval = (ch->amux_ip_rsv << ADC_RSV_IP_SEL_SHIFT) |
486 ADC_ARB_USRP_RSV_TRM;
487 else
488 rsvval = (rsv << ADC_RSV_IP_SEL_SHIFT) |
489 ADC_ARB_USRP_RSV_TRM;
490 }
491
492 ret = regmap_update_bits(adc->map,
493 ADC_ARB_USRP_RSV,
494 ~rsvmask,
495 rsvval);
496 if (ret)
497 goto unlock;
498
499 ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
500 ADC_ARB_USRP_ANA_PARAM_DIS);
501 if (ret)
502 goto unlock;
503
504 /* Decimation factor */
505 ret = regmap_write(adc->map, ADC_ARB_USRP_DIG_PARAM,
506 ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0 |
507 ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1 |
508 ch->decimation << ADC_DIG_PARAM_DEC_SHIFT);
509 if (ret)
510 goto unlock;
511
512 ret = regmap_write(adc->map, ADC_ARB_USRP_ANA_PARAM,
513 ADC_ARB_USRP_ANA_PARAM_EN);
514 if (ret)
515 goto unlock;
516
517 /* Enable the arbiter, the Qualcomm code does it twice like this */
518 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
519 ADC_ARB_USRP_CNTRL_EN_ARB);
520 if (ret)
521 goto unlock;
522 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
523 ADC_ARB_USRP_CNTRL_EN_ARB);
524 if (ret)
525 goto unlock;
526
527
528 /* Fire a request! */
529 reinit_completion(&adc->complete);
530 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL,
531 ADC_ARB_USRP_CNTRL_EN_ARB |
532 ADC_ARB_USRP_CNTRL_REQ);
533 if (ret)
534 goto unlock;
535
536 /* Next the interrupt occurs */
537 if (!wait_for_completion_timeout(&adc->complete, VADC_CONV_TIME_MAX_US)) {
538 ret = -ETIMEDOUT;
539 goto unlock;
540 }
541
542 ret = regmap_read(adc->map, ADC_ARB_USRP_DATA0, &val);
543 if (ret)
544 goto unlock;
545 lsb = val;
546 ret = regmap_read(adc->map, ADC_ARB_USRP_DATA1, &val);
547 if (ret)
548 goto unlock;
549 msb = val;
550 *adc_code = (msb << 8) | lsb;
551
552 /* Turn off the ADC by setting the arbiter to 0 twice */
553 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0);
554 if (ret)
555 goto unlock;
556 ret = regmap_write(adc->map, ADC_ARB_USRP_CNTRL, 0);
557 if (ret)
558 goto unlock;
559
560 unlock:
561 mutex_unlock(&adc->lock);
562 return ret;
563 }
564
pm8xxx_read_channel(struct pm8xxx_xoadc * adc,const struct pm8xxx_chan_info * ch,u16 * adc_code)565 static int pm8xxx_read_channel(struct pm8xxx_xoadc *adc,
566 const struct pm8xxx_chan_info *ch,
567 u16 *adc_code)
568 {
569 /*
570 * Normally we just use the ratiometric scale value (RSV) predefined
571 * for the channel, but during calibration we need to modify this
572 * so this wrapper is a helper hiding the more complex version.
573 */
574 return pm8xxx_read_channel_rsv(adc, ch, 0xff, adc_code, false);
575 }
576
pm8xxx_calibrate_device(struct pm8xxx_xoadc * adc)577 static int pm8xxx_calibrate_device(struct pm8xxx_xoadc *adc)
578 {
579 const struct pm8xxx_chan_info *ch;
580 u16 read_1250v;
581 u16 read_0625v;
582 u16 read_nomux_rsv5;
583 u16 read_nomux_rsv4;
584 int ret;
585
586 adc->graph[VADC_CALIB_ABSOLUTE].dx = VADC_ABSOLUTE_RANGE_UV;
587 adc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE;
588
589 /* Common reference channel calibration */
590 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V);
591 if (!ch)
592 return -ENODEV;
593 ret = pm8xxx_read_channel(adc, ch, &read_1250v);
594 if (ret) {
595 dev_err(adc->dev, "could not read 1.25V reference channel\n");
596 return -ENODEV;
597 }
598 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL);
599 if (!ch)
600 return -ENODEV;
601 ret = pm8xxx_read_channel(adc, ch, &read_0625v);
602 if (ret) {
603 dev_err(adc->dev, "could not read 0.625V reference channel\n");
604 return -ENODEV;
605 }
606 if (read_1250v == read_0625v) {
607 dev_err(adc->dev, "read same ADC code for 1.25V and 0.625V\n");
608 return -ENODEV;
609 }
610
611 adc->graph[VADC_CALIB_ABSOLUTE].dy = read_1250v - read_0625v;
612 adc->graph[VADC_CALIB_ABSOLUTE].gnd = read_0625v;
613
614 dev_info(adc->dev, "absolute calibration dx = %d uV, dy = %d units\n",
615 VADC_ABSOLUTE_RANGE_UV, adc->graph[VADC_CALIB_ABSOLUTE].dy);
616
617 /* Ratiometric calibration */
618 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF);
619 if (!ch)
620 return -ENODEV;
621 ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV5,
622 &read_nomux_rsv5, true);
623 if (ret) {
624 dev_err(adc->dev, "could not read MUXOFF reference channel\n");
625 return -ENODEV;
626 }
627 ret = pm8xxx_read_channel_rsv(adc, ch, AMUX_RSV4,
628 &read_nomux_rsv4, true);
629 if (ret) {
630 dev_err(adc->dev, "could not read MUXOFF reference channel\n");
631 return -ENODEV;
632 }
633 adc->graph[VADC_CALIB_RATIOMETRIC].dy =
634 read_nomux_rsv5 - read_nomux_rsv4;
635 adc->graph[VADC_CALIB_RATIOMETRIC].gnd = read_nomux_rsv4;
636
637 dev_info(adc->dev, "ratiometric calibration dx = %d, dy = %d units\n",
638 VADC_RATIOMETRIC_RANGE,
639 adc->graph[VADC_CALIB_RATIOMETRIC].dy);
640
641 return 0;
642 }
643
pm8xxx_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)644 static int pm8xxx_read_raw(struct iio_dev *indio_dev,
645 struct iio_chan_spec const *chan,
646 int *val, int *val2, long mask)
647 {
648 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
649 const struct pm8xxx_chan_info *ch;
650 u16 adc_code;
651 int ret;
652
653 switch (mask) {
654 case IIO_CHAN_INFO_PROCESSED:
655 ch = pm8xxx_get_channel(adc, chan->address);
656 if (!ch)
657 return -EINVAL;
658 ret = pm8xxx_read_channel(adc, ch, &adc_code);
659 if (ret)
660 return ret;
661
662 ret = qcom_vadc_scale(ch->hwchan->scale_fn_type,
663 &adc->graph[ch->calibration],
664 &ch->hwchan->prescale,
665 (ch->calibration == VADC_CALIB_ABSOLUTE),
666 adc_code, val);
667 if (ret)
668 return ret;
669
670 return IIO_VAL_INT;
671 case IIO_CHAN_INFO_RAW:
672 ch = pm8xxx_get_channel(adc, chan->address);
673 if (!ch)
674 return -EINVAL;
675 ret = pm8xxx_read_channel(adc, ch, &adc_code);
676 if (ret)
677 return ret;
678
679 *val = (int)adc_code;
680 return IIO_VAL_INT;
681 default:
682 return -EINVAL;
683 }
684 }
685
pm8xxx_fwnode_xlate(struct iio_dev * indio_dev,const struct fwnode_reference_args * iiospec)686 static int pm8xxx_fwnode_xlate(struct iio_dev *indio_dev,
687 const struct fwnode_reference_args *iiospec)
688 {
689 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
690 u8 pre_scale_mux;
691 u8 amux_channel;
692 unsigned int i;
693
694 /*
695 * First cell is prescaler or premux, second cell is analog
696 * mux.
697 */
698 if (iiospec->nargs != 2) {
699 dev_err(&indio_dev->dev, "wrong number of arguments for %pfwP need 2 got %d\n",
700 iiospec->fwnode,
701 iiospec->nargs);
702 return -EINVAL;
703 }
704 pre_scale_mux = (u8)iiospec->args[0];
705 amux_channel = (u8)iiospec->args[1];
706 dev_dbg(&indio_dev->dev, "pre scale/mux: %02x, amux: %02x\n",
707 pre_scale_mux, amux_channel);
708
709 /* We need to match exactly on the prescale/premux and channel */
710 for (i = 0; i < adc->nchans; i++)
711 if (adc->chans[i].hwchan->pre_scale_mux == pre_scale_mux &&
712 adc->chans[i].hwchan->amux_channel == amux_channel)
713 return i;
714
715 return -EINVAL;
716 }
717
pm8xxx_read_label(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,char * label)718 static int pm8xxx_read_label(struct iio_dev *indio_dev,
719 struct iio_chan_spec const *chan, char *label)
720 {
721 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
722 const struct pm8xxx_chan_info *ch;
723
724 ch = pm8xxx_get_channel(adc, chan->address);
725 if (!ch)
726 return -EINVAL;
727 return sysfs_emit(label, "%s\n", ch->label);
728 }
729
730 static const struct iio_info pm8xxx_xoadc_info = {
731 .fwnode_xlate = pm8xxx_fwnode_xlate,
732 .read_label = pm8xxx_read_label,
733 .read_raw = pm8xxx_read_raw,
734 };
735
pm8xxx_xoadc_parse_channel(struct device * dev,struct fwnode_handle * fwnode,const struct xoadc_channel * hw_channels,struct iio_chan_spec * iio_chan,struct pm8xxx_chan_info * ch)736 static int pm8xxx_xoadc_parse_channel(struct device *dev,
737 struct fwnode_handle *fwnode,
738 const struct xoadc_channel *hw_channels,
739 struct iio_chan_spec *iio_chan,
740 struct pm8xxx_chan_info *ch)
741 {
742 const char *name = fwnode_get_name(fwnode);
743 const struct xoadc_channel *hwchan;
744 u32 pre_scale_mux, amux_channel, reg[2];
745 u32 rsv, dec;
746 int ret;
747 int chid;
748
749 ret = fwnode_property_read_u32_array(fwnode, "reg", reg,
750 ARRAY_SIZE(reg));
751 if (ret) {
752 dev_err(dev, "invalid pre scale/mux or amux channel number %s\n",
753 name);
754 return ret;
755 }
756
757 pre_scale_mux = reg[0];
758 amux_channel = reg[1];
759
760 /* Find the right channel setting */
761 chid = 0;
762 hwchan = &hw_channels[0];
763 while (hwchan->datasheet_name) {
764 if (hwchan->pre_scale_mux == pre_scale_mux &&
765 hwchan->amux_channel == amux_channel)
766 break;
767 hwchan++;
768 chid++;
769 }
770 /* The sentinel does not have a name assigned */
771 if (!hwchan->datasheet_name) {
772 dev_err(dev, "could not locate channel %02x/%02x\n",
773 pre_scale_mux, amux_channel);
774 return -EINVAL;
775 }
776 ch->label = hwchan->datasheet_name;
777 fwnode_property_read_string(fwnode, "label", &ch->label);
778 ch->hwchan = hwchan;
779 /* Everyone seems to use absolute calibration except in special cases */
780 ch->calibration = VADC_CALIB_ABSOLUTE;
781 /* Everyone seems to use default ("type 2") decimation */
782 ch->decimation = VADC_DEF_DECIMATION;
783
784 if (!fwnode_property_read_u32(fwnode, "qcom,ratiometric", &rsv)) {
785 ch->calibration = VADC_CALIB_RATIOMETRIC;
786 if (rsv > XOADC_RSV_MAX) {
787 dev_err(dev, "%s too large RSV value %d\n", name, rsv);
788 return -EINVAL;
789 }
790 if (rsv == AMUX_RSV3) {
791 dev_err(dev, "%s invalid RSV value %d\n", name, rsv);
792 return -EINVAL;
793 }
794 }
795
796 /* Optional decimation, if omitted we use the default */
797 ret = fwnode_property_read_u32(fwnode, "qcom,decimation", &dec);
798 if (!ret) {
799 ret = qcom_vadc_decimation_from_dt(dec);
800 if (ret < 0) {
801 dev_err(dev, "%s invalid decimation %d\n",
802 name, dec);
803 return ret;
804 }
805 ch->decimation = ret;
806 }
807
808 iio_chan->channel = chid;
809 iio_chan->address = hwchan->amux_channel;
810 iio_chan->datasheet_name = hwchan->datasheet_name;
811 iio_chan->type = hwchan->type;
812 /* All channels are raw or processed */
813 iio_chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
814 BIT(IIO_CHAN_INFO_PROCESSED);
815 iio_chan->indexed = 1;
816
817 dev_dbg(dev,
818 "channel [PRESCALE/MUX: %02x AMUX: %02x] \"%s\" ref voltage: %d, decimation %d prescale %d/%d, scale function %d\n",
819 hwchan->pre_scale_mux, hwchan->amux_channel, ch->label,
820 ch->amux_ip_rsv, ch->decimation, hwchan->prescale.numerator,
821 hwchan->prescale.denominator, hwchan->scale_fn_type);
822
823 return 0;
824 }
825
pm8xxx_xoadc_parse_channels(struct pm8xxx_xoadc * adc)826 static int pm8xxx_xoadc_parse_channels(struct pm8xxx_xoadc *adc)
827 {
828 struct pm8xxx_chan_info *ch;
829 int ret;
830 int i;
831
832 adc->nchans = device_get_child_node_count(adc->dev);
833 if (!adc->nchans) {
834 dev_err(adc->dev, "no channel children\n");
835 return -ENODEV;
836 }
837 dev_dbg(adc->dev, "found %d ADC channels\n", adc->nchans);
838
839 adc->iio_chans = devm_kcalloc(adc->dev, adc->nchans,
840 sizeof(*adc->iio_chans), GFP_KERNEL);
841 if (!adc->iio_chans)
842 return -ENOMEM;
843
844 adc->chans = devm_kcalloc(adc->dev, adc->nchans,
845 sizeof(*adc->chans), GFP_KERNEL);
846 if (!adc->chans)
847 return -ENOMEM;
848
849 i = 0;
850 device_for_each_child_node_scoped(adc->dev, child) {
851 ch = &adc->chans[i];
852 ret = pm8xxx_xoadc_parse_channel(adc->dev, child,
853 adc->variant->channels,
854 &adc->iio_chans[i],
855 ch);
856 if (ret)
857 return ret;
858
859 i++;
860 }
861
862 /* Check for required channels */
863 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_125V);
864 if (!ch) {
865 dev_err(adc->dev, "missing 1.25V reference channel\n");
866 return -ENODEV;
867 }
868 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_INTERNAL);
869 if (!ch) {
870 dev_err(adc->dev, "missing 0.625V reference channel\n");
871 return -ENODEV;
872 }
873 ch = pm8xxx_get_channel(adc, PM8XXX_CHANNEL_MUXOFF);
874 if (!ch) {
875 dev_err(adc->dev, "missing MUXOFF reference channel\n");
876 return -ENODEV;
877 }
878
879 return 0;
880 }
881
pm8xxx_xoadc_probe(struct platform_device * pdev)882 static int pm8xxx_xoadc_probe(struct platform_device *pdev)
883 {
884 const struct xoadc_variant *variant;
885 struct pm8xxx_xoadc *adc;
886 struct iio_dev *indio_dev;
887 struct regmap *map;
888 struct device *dev = &pdev->dev;
889 int ret;
890
891 variant = device_get_match_data(dev);
892 if (!variant)
893 return -ENODEV;
894
895 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
896 if (!indio_dev)
897 return -ENOMEM;
898 platform_set_drvdata(pdev, indio_dev);
899
900 adc = iio_priv(indio_dev);
901 adc->dev = dev;
902 adc->variant = variant;
903 init_completion(&adc->complete);
904 mutex_init(&adc->lock);
905
906 ret = pm8xxx_xoadc_parse_channels(adc);
907 if (ret)
908 return ret;
909
910 map = dev_get_regmap(dev->parent, NULL);
911 if (!map) {
912 dev_err(dev, "parent regmap unavailable.\n");
913 return -ENODEV;
914 }
915 adc->map = map;
916
917 /* Bring up regulator */
918 adc->vref = devm_regulator_get(dev, "xoadc-ref");
919 if (IS_ERR(adc->vref))
920 return dev_err_probe(dev, PTR_ERR(adc->vref),
921 "failed to get XOADC VREF regulator\n");
922 ret = regulator_enable(adc->vref);
923 if (ret) {
924 dev_err(dev, "failed to enable XOADC VREF regulator\n");
925 return ret;
926 }
927
928 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
929 pm8xxx_eoc_irq, NULL, 0, variant->name, indio_dev);
930 if (ret) {
931 dev_err(dev, "unable to request IRQ\n");
932 goto out_disable_vref;
933 }
934
935 indio_dev->name = variant->name;
936 indio_dev->modes = INDIO_DIRECT_MODE;
937 indio_dev->info = &pm8xxx_xoadc_info;
938 indio_dev->channels = adc->iio_chans;
939 indio_dev->num_channels = adc->nchans;
940
941 ret = iio_device_register(indio_dev);
942 if (ret)
943 goto out_disable_vref;
944
945 ret = pm8xxx_calibrate_device(adc);
946 if (ret)
947 goto out_unreg_device;
948
949 dev_info(dev, "%s XOADC driver enabled\n", variant->name);
950
951 return 0;
952
953 out_unreg_device:
954 iio_device_unregister(indio_dev);
955 out_disable_vref:
956 regulator_disable(adc->vref);
957
958 return ret;
959 }
960
pm8xxx_xoadc_remove(struct platform_device * pdev)961 static void pm8xxx_xoadc_remove(struct platform_device *pdev)
962 {
963 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
964 struct pm8xxx_xoadc *adc = iio_priv(indio_dev);
965
966 iio_device_unregister(indio_dev);
967
968 regulator_disable(adc->vref);
969 }
970
971 static const struct xoadc_variant pm8018_variant = {
972 .name = "PM8018-XOADC",
973 .channels = pm8018_xoadc_channels,
974 };
975
976 static const struct xoadc_variant pm8038_variant = {
977 .name = "PM8038-XOADC",
978 .channels = pm8038_xoadc_channels,
979 };
980
981 static const struct xoadc_variant pm8058_variant = {
982 .name = "PM8058-XOADC",
983 .channels = pm8058_xoadc_channels,
984 .broken_ratiometric = true,
985 .prescaling = true,
986 };
987
988 static const struct xoadc_variant pm8921_variant = {
989 .name = "PM8921-XOADC",
990 .channels = pm8921_xoadc_channels,
991 .second_level_mux = true,
992 };
993
994 static const struct of_device_id pm8xxx_xoadc_id_table[] = {
995 {
996 .compatible = "qcom,pm8018-adc",
997 .data = &pm8018_variant,
998 },
999 {
1000 .compatible = "qcom,pm8038-adc",
1001 .data = &pm8038_variant,
1002 },
1003 {
1004 .compatible = "qcom,pm8058-adc",
1005 .data = &pm8058_variant,
1006 },
1007 {
1008 .compatible = "qcom,pm8921-adc",
1009 .data = &pm8921_variant,
1010 },
1011 { }
1012 };
1013 MODULE_DEVICE_TABLE(of, pm8xxx_xoadc_id_table);
1014
1015 static struct platform_driver pm8xxx_xoadc_driver = {
1016 .driver = {
1017 .name = "pm8xxx-adc",
1018 .of_match_table = pm8xxx_xoadc_id_table,
1019 },
1020 .probe = pm8xxx_xoadc_probe,
1021 .remove = pm8xxx_xoadc_remove,
1022 };
1023 module_platform_driver(pm8xxx_xoadc_driver);
1024
1025 MODULE_DESCRIPTION("PM8xxx XOADC driver");
1026 MODULE_LICENSE("GPL v2");
1027 MODULE_ALIAS("platform:pm8xxx-xoadc");
1028