xref: /linux/drivers/gpu/drm/bridge/ite-it6263.c (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright 2024 NXP
4  */
5 
6 #include <linux/bitfield.h>
7 #include <linux/bits.h>
8 #include <linux/delay.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/hdmi.h>
11 #include <linux/i2c.h>
12 #include <linux/media-bus-format.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 
18 #include <drm/display/drm_hdmi_helper.h>
19 #include <drm/display/drm_hdmi_state_helper.h>
20 #include <drm/drm_atomic.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_atomic_state_helper.h>
23 #include <drm/drm_bridge.h>
24 #include <drm/drm_bridge_connector.h>
25 #include <drm/drm_connector.h>
26 #include <drm/drm_crtc.h>
27 #include <drm/drm_edid.h>
28 #include <drm/drm_of.h>
29 #include <drm/drm_probe_helper.h>
30 
31 /* -----------------------------------------------------------------------------
32  * LVDS registers
33  */
34 
35 /* LVDS software reset registers */
36 #define LVDS_REG_05			0x05
37 #define  REG_SOFT_P_RST			BIT(1)
38 
39 /* LVDS system configuration registers */
40 /* 0x0b */
41 #define LVDS_REG_0B			0x0b
42 #define  REG_SSC_PCLK_RF		BIT(0)
43 #define  REG_LVDS_IN_SWAP		BIT(1)
44 
45 /* LVDS test pattern gen control registers */
46 /* 0x2c */
47 #define LVDS_REG_2C			0x2c
48 #define  REG_COL_DEP			GENMASK(1, 0)
49 #define  BIT8				FIELD_PREP(REG_COL_DEP, 1)
50 #define  OUT_MAP			BIT(4)
51 #define  VESA				BIT(4)
52 #define  JEIDA				0
53 #define  REG_DESSC_ENB			BIT(6)
54 #define  DMODE				BIT(7)
55 #define  DISO				BIT(7)
56 #define  SISO				0
57 
58 #define LVDS_REG_3C			0x3c
59 #define LVDS_REG_3F			0x3f
60 #define LVDS_REG_47			0x47
61 #define LVDS_REG_48			0x48
62 #define LVDS_REG_4F			0x4f
63 #define LVDS_REG_52			0x52
64 
65 /* -----------------------------------------------------------------------------
66  * HDMI registers are separated into three banks:
67  * 1) HDMI register common bank: 0x00 ~ 0x2f
68  */
69 
70 /* HDMI genernal registers */
71 #define HDMI_REG_SW_RST			0x04
72 #define  SOFTREF_RST			BIT(5)
73 #define  SOFTA_RST			BIT(4)
74 #define  SOFTV_RST			BIT(3)
75 #define  AUD_RST			BIT(2)
76 #define  HDCP_RST			BIT(0)
77 #define  HDMI_RST_ALL			(SOFTREF_RST | SOFTA_RST | SOFTV_RST | \
78 					 AUD_RST | HDCP_RST)
79 
80 #define HDMI_REG_SYS_STATUS		0x0e
81 #define  HPDETECT			BIT(6)
82 #define  TXVIDSTABLE			BIT(4)
83 
84 #define HDMI_REG_BANK_CTRL		0x0f
85 #define  REG_BANK_SEL			BIT(0)
86 
87 /* HDMI System DDC control registers */
88 #define HDMI_REG_DDC_MASTER_CTRL	0x10
89 #define  MASTER_SEL_HOST		BIT(0)
90 
91 #define HDMI_REG_DDC_HEADER		0x11
92 
93 #define HDMI_REG_DDC_REQOFF		0x12
94 #define HDMI_REG_DDC_REQCOUNT		0x13
95 #define HDMI_REG_DDC_EDIDSEG		0x14
96 
97 #define HDMI_REG_DDC_CMD		0x15
98 #define  DDC_CMD_EDID_READ		0x3
99 #define  DDC_CMD_FIFO_CLR		0x9
100 
101 #define HDMI_REG_DDC_STATUS		0x16
102 #define  DDC_DONE			BIT(7)
103 #define  DDC_NOACK			BIT(5)
104 #define  DDC_WAITBUS			BIT(4)
105 #define  DDC_ARBILOSE			BIT(3)
106 #define  DDC_ERROR			(DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE)
107 
108 #define HDMI_DDC_FIFO_BYTES		32
109 #define HDMI_REG_DDC_READFIFO		0x17
110 #define HDMI_REG_LVDS_PORT		0x1d /* LVDS input control I2C addr */
111 #define HDMI_REG_LVDS_PORT_EN		0x1e
112 #define LVDS_INPUT_CTRL_I2C_ADDR	0x33
113 
114 /* -----------------------------------------------------------------------------
115  * 2) HDMI register bank0: 0x30 ~ 0xff
116  */
117 
118 /* HDMI AFE registers */
119 #define HDMI_REG_AFE_DRV_CTRL		0x61
120 #define  AFE_DRV_PWD			BIT(5)
121 #define  AFE_DRV_RST			BIT(4)
122 
123 #define HDMI_REG_AFE_XP_CTRL		0x62
124 #define  AFE_XP_GAINBIT			BIT(7)
125 #define  AFE_XP_ER0			BIT(4)
126 #define  AFE_XP_RESETB			BIT(3)
127 
128 #define HDMI_REG_AFE_ISW_CTRL		0x63
129 
130 #define HDMI_REG_AFE_IP_CTRL		0x64
131 #define  AFE_IP_GAINBIT			BIT(7)
132 #define  AFE_IP_ER0			BIT(3)
133 #define  AFE_IP_RESETB			BIT(2)
134 
135 /* HDMI input data format registers */
136 #define HDMI_REG_INPUT_MODE		0x70
137 #define  IN_RGB				0x00
138 
139 /* HDMI general control registers */
140 #define HDMI_REG_HDMI_MODE		0xc0
141 #define  TX_HDMI_MODE			BIT(0)
142 
143 #define HDMI_REG_GCP			0xc1
144 #define  AVMUTE				BIT(0)
145 #define  HDMI_COLOR_DEPTH		GENMASK(6, 4)
146 #define  HDMI_COLOR_DEPTH_24		FIELD_PREP(HDMI_COLOR_DEPTH, 4)
147 
148 #define HDMI_REG_PKT_GENERAL_CTRL	0xc6
149 #define HDMI_REG_AVI_INFOFRM_CTRL	0xcd
150 #define  ENABLE_PKT			BIT(0)
151 #define  REPEAT_PKT			BIT(1)
152 
153 /* -----------------------------------------------------------------------------
154  * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers)
155  */
156 
157 /* AVI packet registers */
158 #define HDMI_REG_AVI_DB1		0x158
159 #define HDMI_REG_AVI_DB2		0x159
160 #define HDMI_REG_AVI_DB3		0x15a
161 #define HDMI_REG_AVI_DB4		0x15b
162 #define HDMI_REG_AVI_DB5		0x15c
163 #define HDMI_REG_AVI_CSUM		0x15d
164 #define HDMI_REG_AVI_DB6		0x15e
165 #define HDMI_REG_AVI_DB7		0x15f
166 #define HDMI_REG_AVI_DB8		0x160
167 #define HDMI_REG_AVI_DB9		0x161
168 #define HDMI_REG_AVI_DB10		0x162
169 #define HDMI_REG_AVI_DB11		0x163
170 #define HDMI_REG_AVI_DB12		0x164
171 #define HDMI_REG_AVI_DB13		0x165
172 
173 #define HDMI_AVI_DB_CHUNK1_SIZE		(HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1)
174 #define HDMI_AVI_DB_CHUNK2_SIZE		(HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1)
175 
176 /* IT6263 data sheet Rev0.8: LVDS RX supports input clock rate up to 150MHz. */
177 #define MAX_PIXEL_CLOCK_KHZ		150000
178 
179 /* IT6263 programming guide Ver0.90: PCLK_HIGH for TMDS clock over 80MHz. */
180 #define HIGH_PIXEL_CLOCK_KHZ		80000
181 
182 /*
183  * IT6263 data sheet Rev0.8: HDMI TX supports link speeds of up to 2.25Gbps
184  * (link clock rate of 225MHz).
185  */
186 #define MAX_HDMI_TMDS_CHAR_RATE_HZ	225000000
187 
188 struct it6263 {
189 	struct device *dev;
190 	struct i2c_client *hdmi_i2c;
191 	struct i2c_client *lvds_i2c;
192 	struct regmap *hdmi_regmap;
193 	struct regmap *lvds_regmap;
194 	struct drm_bridge bridge;
195 	struct drm_bridge *next_bridge;
196 	int lvds_data_mapping;
197 	bool lvds_dual_link;
198 	bool lvds_link12_swap;
199 };
200 
bridge_to_it6263(struct drm_bridge * bridge)201 static inline struct it6263 *bridge_to_it6263(struct drm_bridge *bridge)
202 {
203 	return container_of(bridge, struct it6263, bridge);
204 }
205 
it6263_hdmi_writeable_reg(struct device * dev,unsigned int reg)206 static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned int reg)
207 {
208 	switch (reg) {
209 	case HDMI_REG_SW_RST:
210 	case HDMI_REG_BANK_CTRL:
211 	case HDMI_REG_DDC_MASTER_CTRL:
212 	case HDMI_REG_DDC_HEADER:
213 	case HDMI_REG_DDC_REQOFF:
214 	case HDMI_REG_DDC_REQCOUNT:
215 	case HDMI_REG_DDC_EDIDSEG:
216 	case HDMI_REG_DDC_CMD:
217 	case HDMI_REG_LVDS_PORT:
218 	case HDMI_REG_LVDS_PORT_EN:
219 	case HDMI_REG_AFE_DRV_CTRL:
220 	case HDMI_REG_AFE_XP_CTRL:
221 	case HDMI_REG_AFE_ISW_CTRL:
222 	case HDMI_REG_AFE_IP_CTRL:
223 	case HDMI_REG_INPUT_MODE:
224 	case HDMI_REG_HDMI_MODE:
225 	case HDMI_REG_GCP:
226 	case HDMI_REG_PKT_GENERAL_CTRL:
227 	case HDMI_REG_AVI_INFOFRM_CTRL:
228 	case HDMI_REG_AVI_DB1:
229 	case HDMI_REG_AVI_DB2:
230 	case HDMI_REG_AVI_DB3:
231 	case HDMI_REG_AVI_DB4:
232 	case HDMI_REG_AVI_DB5:
233 	case HDMI_REG_AVI_CSUM:
234 	case HDMI_REG_AVI_DB6:
235 	case HDMI_REG_AVI_DB7:
236 	case HDMI_REG_AVI_DB8:
237 	case HDMI_REG_AVI_DB9:
238 	case HDMI_REG_AVI_DB10:
239 	case HDMI_REG_AVI_DB11:
240 	case HDMI_REG_AVI_DB12:
241 	case HDMI_REG_AVI_DB13:
242 		return true;
243 	default:
244 		return false;
245 	}
246 }
247 
it6263_hdmi_readable_reg(struct device * dev,unsigned int reg)248 static bool it6263_hdmi_readable_reg(struct device *dev, unsigned int reg)
249 {
250 	if (it6263_hdmi_writeable_reg(dev, reg))
251 		return true;
252 
253 	switch (reg) {
254 	case HDMI_REG_SYS_STATUS:
255 	case HDMI_REG_DDC_STATUS:
256 	case HDMI_REG_DDC_READFIFO:
257 		return true;
258 	default:
259 		return false;
260 	}
261 }
262 
it6263_hdmi_volatile_reg(struct device * dev,unsigned int reg)263 static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned int reg)
264 {
265 	switch (reg) {
266 	case HDMI_REG_SW_RST:
267 	case HDMI_REG_SYS_STATUS:
268 	case HDMI_REG_DDC_STATUS:
269 	case HDMI_REG_DDC_READFIFO:
270 		return true;
271 	default:
272 		return false;
273 	}
274 }
275 
276 static const struct regmap_range_cfg it6263_hdmi_range_cfg = {
277 	.range_min = 0x00,
278 	.range_max = HDMI_REG_AVI_DB13,
279 	.selector_reg = HDMI_REG_BANK_CTRL,
280 	.selector_mask = REG_BANK_SEL,
281 	.selector_shift = 0,
282 	.window_start = 0x00,
283 	.window_len = 0x100,
284 };
285 
286 static const struct regmap_config it6263_hdmi_regmap_config = {
287 	.name = "it6263-hdmi",
288 	.reg_bits = 8,
289 	.val_bits = 8,
290 	.writeable_reg = it6263_hdmi_writeable_reg,
291 	.readable_reg = it6263_hdmi_readable_reg,
292 	.volatile_reg = it6263_hdmi_volatile_reg,
293 	.max_register = HDMI_REG_AVI_DB13,
294 	.ranges = &it6263_hdmi_range_cfg,
295 	.num_ranges = 1,
296 	.cache_type = REGCACHE_MAPLE,
297 };
298 
it6263_lvds_writeable_reg(struct device * dev,unsigned int reg)299 static bool it6263_lvds_writeable_reg(struct device *dev, unsigned int reg)
300 {
301 	switch (reg) {
302 	case LVDS_REG_05:
303 	case LVDS_REG_0B:
304 	case LVDS_REG_2C:
305 	case LVDS_REG_3C:
306 	case LVDS_REG_3F:
307 	case LVDS_REG_47:
308 	case LVDS_REG_48:
309 	case LVDS_REG_4F:
310 	case LVDS_REG_52:
311 		return true;
312 	default:
313 		return false;
314 	}
315 }
316 
it6263_lvds_readable_reg(struct device * dev,unsigned int reg)317 static bool it6263_lvds_readable_reg(struct device *dev, unsigned int reg)
318 {
319 	return it6263_lvds_writeable_reg(dev, reg);
320 }
321 
it6263_lvds_volatile_reg(struct device * dev,unsigned int reg)322 static bool it6263_lvds_volatile_reg(struct device *dev, unsigned int reg)
323 {
324 	return reg == LVDS_REG_05;
325 }
326 
327 static const struct regmap_config it6263_lvds_regmap_config = {
328 	.name = "it6263-lvds",
329 	.reg_bits = 8,
330 	.val_bits = 8,
331 	.writeable_reg = it6263_lvds_writeable_reg,
332 	.readable_reg = it6263_lvds_readable_reg,
333 	.volatile_reg = it6263_lvds_volatile_reg,
334 	.max_register = LVDS_REG_52,
335 	.cache_type = REGCACHE_MAPLE,
336 };
337 
338 static const char * const it6263_supplies[] = {
339 	"ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2",
340 	"avcc", "anvdd", "apvdd"
341 };
342 
it6263_parse_dt(struct it6263 * it)343 static int it6263_parse_dt(struct it6263 *it)
344 {
345 	struct device *dev = it->dev;
346 	struct device_node *port0, *port1;
347 	int ret = 0;
348 
349 	it->lvds_data_mapping = drm_of_lvds_get_data_mapping(dev->of_node);
350 	if (it->lvds_data_mapping < 0) {
351 		dev_err(dev, "%pOF: invalid or missing %s DT property: %d\n",
352 			dev->of_node, "data-mapping", it->lvds_data_mapping);
353 		return it->lvds_data_mapping;
354 	}
355 
356 	it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
357 	if (IS_ERR(it->next_bridge))
358 		return dev_err_probe(dev, PTR_ERR(it->next_bridge),
359 				     "failed to get next bridge\n");
360 
361 	port0 = of_graph_get_port_by_id(dev->of_node, 0);
362 	port1 = of_graph_get_port_by_id(dev->of_node, 1);
363 	if (port0 && port1) {
364 		int order;
365 
366 		it->lvds_dual_link = true;
367 		order = drm_of_lvds_get_dual_link_pixel_order_sink(port0, port1);
368 		if (order < 0) {
369 			dev_err(dev,
370 				"failed to get dual link pixel order: %d\n",
371 				order);
372 			ret = order;
373 		} else if (order == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
374 			it->lvds_link12_swap = true;
375 		}
376 	} else if (port1) {
377 		ret = -EINVAL;
378 		dev_err(dev, "single input LVDS port1 is not supported\n");
379 	} else if (!port0) {
380 		ret = -EINVAL;
381 		dev_err(dev, "no input LVDS port\n");
382 	}
383 
384 	of_node_put(port0);
385 	of_node_put(port1);
386 
387 	return ret;
388 }
389 
it6263_hw_reset(struct gpio_desc * reset_gpio)390 static inline void it6263_hw_reset(struct gpio_desc *reset_gpio)
391 {
392 	if (!reset_gpio)
393 		return;
394 
395 	gpiod_set_value_cansleep(reset_gpio, 0);
396 	fsleep(1000);
397 	gpiod_set_value_cansleep(reset_gpio, 1);
398 	/* The chip maker says the low pulse should be at least 40ms. */
399 	fsleep(40000);
400 	gpiod_set_value_cansleep(reset_gpio, 0);
401 	/* addtional time to wait the high voltage to be stable */
402 	fsleep(5000);
403 }
404 
it6263_lvds_set_i2c_addr(struct it6263 * it)405 static inline int it6263_lvds_set_i2c_addr(struct it6263 *it)
406 {
407 	int ret;
408 
409 	ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT,
410 			   LVDS_INPUT_CTRL_I2C_ADDR << 1);
411 	if (ret)
412 		return ret;
413 
414 	return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, BIT(0));
415 }
416 
it6263_lvds_reset(struct it6263 * it)417 static inline void it6263_lvds_reset(struct it6263 *it)
418 {
419 	/* AFE PLL reset */
420 	regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0);
421 	fsleep(1000);
422 	regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0));
423 
424 	/* software pixel clock domain reset */
425 	regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST,
426 			  REG_SOFT_P_RST);
427 	fsleep(1000);
428 	regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0);
429 	fsleep(10000);
430 }
431 
it6263_is_input_bus_fmt_valid(int input_fmt)432 static inline bool it6263_is_input_bus_fmt_valid(int input_fmt)
433 {
434 	switch (input_fmt) {
435 	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
436 	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
437 		return true;
438 	}
439 	return false;
440 }
441 
it6263_lvds_set_interface(struct it6263 * it)442 static inline void it6263_lvds_set_interface(struct it6263 *it)
443 {
444 	u8 fmt;
445 
446 	/* color depth */
447 	regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);
448 
449 	if (it->lvds_data_mapping == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG)
450 		fmt = VESA;
451 	else
452 		fmt = JEIDA;
453 
454 	/* output mapping */
455 	regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, fmt);
456 
457 	if (it->lvds_dual_link) {
458 		regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO);
459 		regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1));
460 	} else {
461 		regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO);
462 		regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0);
463 	}
464 }
465 
it6263_lvds_set_afe(struct it6263 * it)466 static inline void it6263_lvds_set_afe(struct it6263 *it)
467 {
468 	regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa);
469 	regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02);
470 	regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa);
471 	regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02);
472 	regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11);
473 
474 	regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF,
475 			  REG_SSC_PCLK_RF);
476 	regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0);
477 	regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB,
478 			  REG_DESSC_ENB);
479 }
480 
it6263_lvds_sys_cfg(struct it6263 * it)481 static inline void it6263_lvds_sys_cfg(struct it6263 *it)
482 {
483 	regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP,
484 			  it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0);
485 }
486 
it6263_lvds_config(struct it6263 * it)487 static inline void it6263_lvds_config(struct it6263 *it)
488 {
489 	it6263_lvds_reset(it);
490 	it6263_lvds_set_interface(it);
491 	it6263_lvds_set_afe(it);
492 	it6263_lvds_sys_cfg(it);
493 }
494 
it6263_hdmi_config(struct it6263 * it)495 static inline void it6263_hdmi_config(struct it6263 *it)
496 {
497 	regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL);
498 	regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB);
499 	regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH,
500 			  HDMI_COLOR_DEPTH_24);
501 }
502 
it6263_detect(struct it6263 * it)503 static enum drm_connector_status it6263_detect(struct it6263 *it)
504 {
505 	unsigned int val;
506 
507 	regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val);
508 	if (val & HPDETECT)
509 		return connector_status_connected;
510 	else
511 		return connector_status_disconnected;
512 }
513 
it6263_read_edid(void * data,u8 * buf,unsigned int block,size_t len)514 static int it6263_read_edid(void *data, u8 *buf, unsigned int block, size_t len)
515 {
516 	struct it6263 *it = data;
517 	struct regmap *regmap = it->hdmi_regmap;
518 	unsigned int start = (block % 2) * EDID_LENGTH;
519 	unsigned int segment = block >> 1;
520 	unsigned int count, val;
521 	int ret;
522 
523 	regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST);
524 	regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1);
525 	regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment);
526 
527 	while (len) {
528 		/* clear DDC FIFO */
529 		regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR);
530 
531 		ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS,
532 					       val, val & DDC_DONE,
533 					       2000, 10000);
534 		if (ret) {
535 			dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret);
536 			return ret;
537 		}
538 
539 		count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len;
540 
541 		/* fire the read command */
542 		regmap_write(regmap, HDMI_REG_DDC_REQOFF, start);
543 		regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count);
544 		regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ);
545 
546 		start += count;
547 		len -= count;
548 
549 		ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val,
550 					       val & (DDC_DONE | DDC_ERROR),
551 					       20000, 250000);
552 		if (ret && !(val & DDC_ERROR)) {
553 			dev_err(it->dev, "failed to read EDID:%d\n", ret);
554 			return ret;
555 		}
556 
557 		if (val & DDC_ERROR) {
558 			dev_err(it->dev, "DDC error\n");
559 			return -EIO;
560 		}
561 
562 		/* cache to buffer */
563 		for (; count > 0; count--) {
564 			regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val);
565 			*(buf++) = val;
566 		}
567 	}
568 
569 	return 0;
570 }
571 
572 static void
it6263_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)573 it6263_bridge_atomic_disable(struct drm_bridge *bridge,
574 			     struct drm_bridge_state *old_bridge_state)
575 {
576 	struct it6263 *it = bridge_to_it6263(bridge);
577 
578 	regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE);
579 	regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0);
580 	regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL,
581 		     AFE_DRV_RST | AFE_DRV_PWD);
582 }
583 
584 static void
it6263_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)585 it6263_bridge_atomic_enable(struct drm_bridge *bridge,
586 			    struct drm_bridge_state *old_bridge_state)
587 {
588 	struct drm_atomic_state *state = old_bridge_state->base.state;
589 	struct it6263 *it = bridge_to_it6263(bridge);
590 	const struct drm_crtc_state *crtc_state;
591 	struct regmap *regmap = it->hdmi_regmap;
592 	const struct drm_display_mode *mode;
593 	struct drm_connector *connector;
594 	bool is_stable = false;
595 	struct drm_crtc *crtc;
596 	unsigned int val;
597 	bool pclk_high;
598 	int i, ret;
599 
600 	connector = drm_atomic_get_new_connector_for_encoder(state,
601 							     bridge->encoder);
602 	crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
603 	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
604 	mode = &crtc_state->adjusted_mode;
605 
606 	regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE);
607 
608 	drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
609 
610 	/* HDMI AFE setup */
611 	pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ;
612 	regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST);
613 	if (pclk_high)
614 		regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
615 			     AFE_XP_GAINBIT | AFE_XP_RESETB);
616 	else
617 		regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
618 			     AFE_XP_ER0 | AFE_XP_RESETB);
619 	regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10);
620 	if (pclk_high)
621 		regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
622 			     AFE_IP_GAINBIT | AFE_IP_RESETB);
623 	else
624 		regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
625 			     AFE_IP_ER0 | AFE_IP_RESETB);
626 
627 	/* HDMI software video reset */
628 	regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST);
629 	fsleep(1000);
630 	regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0);
631 
632 	/* reconfigure LVDS and retry several times in case video is instable */
633 	for (i = 0; i < 3; i++) {
634 		ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val,
635 					       val & TXVIDSTABLE,
636 					       20000, 500000);
637 		if (!ret) {
638 			is_stable = true;
639 			break;
640 		}
641 
642 		it6263_lvds_config(it);
643 	}
644 
645 	if (!is_stable)
646 		dev_warn(it->dev, "failed to wait for video stable\n");
647 
648 	/* HDMI AFE reset release and power up */
649 	regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0);
650 
651 	regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0);
652 
653 	regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT | REPEAT_PKT);
654 }
655 
656 static enum drm_mode_status
it6263_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)657 it6263_bridge_mode_valid(struct drm_bridge *bridge,
658 			 const struct drm_display_info *info,
659 			 const struct drm_display_mode *mode)
660 {
661 	unsigned long long rate;
662 
663 	rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
664 	if (rate == 0)
665 		return MODE_NOCLOCK;
666 
667 	return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, rate);
668 }
669 
it6263_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)670 static int it6263_bridge_attach(struct drm_bridge *bridge,
671 				enum drm_bridge_attach_flags flags)
672 {
673 	struct it6263 *it = bridge_to_it6263(bridge);
674 	struct drm_connector *connector;
675 	int ret;
676 
677 	ret = drm_bridge_attach(bridge->encoder, it->next_bridge, bridge,
678 				flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
679 	if (ret < 0)
680 		return ret;
681 
682 	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
683 		return 0;
684 
685 	connector = drm_bridge_connector_init(bridge->dev, bridge->encoder);
686 	if (IS_ERR(connector)) {
687 		ret = PTR_ERR(connector);
688 		dev_err(it->dev, "failed to initialize bridge connector: %d\n",
689 			ret);
690 		return ret;
691 	}
692 
693 	drm_connector_attach_encoder(connector, bridge->encoder);
694 
695 	return 0;
696 }
697 
it6263_bridge_detect(struct drm_bridge * bridge)698 static enum drm_connector_status it6263_bridge_detect(struct drm_bridge *bridge)
699 {
700 	struct it6263 *it = bridge_to_it6263(bridge);
701 
702 	return it6263_detect(it);
703 }
704 
705 static const struct drm_edid *
it6263_bridge_edid_read(struct drm_bridge * bridge,struct drm_connector * connector)706 it6263_bridge_edid_read(struct drm_bridge *bridge,
707 			struct drm_connector *connector)
708 {
709 	struct it6263 *it = bridge_to_it6263(bridge);
710 
711 	return drm_edid_read_custom(connector, it6263_read_edid, it);
712 }
713 
714 static u32 *
it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)715 it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
716 					struct drm_bridge_state *bridge_state,
717 					struct drm_crtc_state *crtc_state,
718 					struct drm_connector_state *conn_state,
719 					u32 output_fmt,
720 					unsigned int *num_input_fmts)
721 {
722 	struct it6263 *it = bridge_to_it6263(bridge);
723 	u32 *input_fmts;
724 
725 	*num_input_fmts = 0;
726 
727 	if (!it6263_is_input_bus_fmt_valid(it->lvds_data_mapping))
728 		return NULL;
729 
730 	input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
731 	if (!input_fmts)
732 		return NULL;
733 
734 	input_fmts[0] = it->lvds_data_mapping;
735 	*num_input_fmts = 1;
736 
737 	return input_fmts;
738 }
739 
740 static enum drm_mode_status
it6263_hdmi_tmds_char_rate_valid(const struct drm_bridge * bridge,const struct drm_display_mode * mode,unsigned long long tmds_rate)741 it6263_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
742 				 const struct drm_display_mode *mode,
743 				 unsigned long long tmds_rate)
744 {
745 	if (mode->clock > MAX_PIXEL_CLOCK_KHZ)
746 		return MODE_CLOCK_HIGH;
747 
748 	if (tmds_rate > MAX_HDMI_TMDS_CHAR_RATE_HZ)
749 		return MODE_CLOCK_HIGH;
750 
751 	return MODE_OK;
752 }
753 
it6263_hdmi_clear_infoframe(struct drm_bridge * bridge,enum hdmi_infoframe_type type)754 static int it6263_hdmi_clear_infoframe(struct drm_bridge *bridge,
755 				       enum hdmi_infoframe_type type)
756 {
757 	struct it6263 *it = bridge_to_it6263(bridge);
758 
759 	if (type == HDMI_INFOFRAME_TYPE_AVI)
760 		regmap_write(it->hdmi_regmap, HDMI_REG_AVI_INFOFRM_CTRL, 0);
761 	else
762 		dev_dbg(it->dev, "unsupported HDMI infoframe 0x%x\n", type);
763 
764 	return 0;
765 }
766 
it6263_hdmi_write_infoframe(struct drm_bridge * bridge,enum hdmi_infoframe_type type,const u8 * buffer,size_t len)767 static int it6263_hdmi_write_infoframe(struct drm_bridge *bridge,
768 				       enum hdmi_infoframe_type type,
769 				       const u8 *buffer, size_t len)
770 {
771 	struct it6263 *it = bridge_to_it6263(bridge);
772 	struct regmap *regmap = it->hdmi_regmap;
773 
774 	if (type != HDMI_INFOFRAME_TYPE_AVI) {
775 		dev_dbg(it->dev, "unsupported HDMI infoframe 0x%x\n", type);
776 		return 0;
777 	}
778 
779 	/* write the first AVI infoframe data byte chunk(DB1-DB5) */
780 	regmap_bulk_write(regmap, HDMI_REG_AVI_DB1,
781 			  &buffer[HDMI_INFOFRAME_HEADER_SIZE],
782 			  HDMI_AVI_DB_CHUNK1_SIZE);
783 
784 	/* write the second AVI infoframe data byte chunk(DB6-DB13) */
785 	regmap_bulk_write(regmap, HDMI_REG_AVI_DB6,
786 			  &buffer[HDMI_INFOFRAME_HEADER_SIZE +
787 				  HDMI_AVI_DB_CHUNK1_SIZE],
788 			  HDMI_AVI_DB_CHUNK2_SIZE);
789 
790 	/* write checksum */
791 	regmap_write(regmap, HDMI_REG_AVI_CSUM, buffer[3]);
792 
793 	regmap_write(regmap, HDMI_REG_AVI_INFOFRM_CTRL, ENABLE_PKT | REPEAT_PKT);
794 
795 	return 0;
796 }
797 
798 static const struct drm_bridge_funcs it6263_bridge_funcs = {
799 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
800 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
801 	.atomic_reset = drm_atomic_helper_bridge_reset,
802 	.attach = it6263_bridge_attach,
803 	.mode_valid = it6263_bridge_mode_valid,
804 	.atomic_disable = it6263_bridge_atomic_disable,
805 	.atomic_enable = it6263_bridge_atomic_enable,
806 	.detect = it6263_bridge_detect,
807 	.edid_read = it6263_bridge_edid_read,
808 	.atomic_get_input_bus_fmts = it6263_bridge_atomic_get_input_bus_fmts,
809 	.hdmi_tmds_char_rate_valid = it6263_hdmi_tmds_char_rate_valid,
810 	.hdmi_clear_infoframe = it6263_hdmi_clear_infoframe,
811 	.hdmi_write_infoframe = it6263_hdmi_write_infoframe,
812 };
813 
it6263_probe(struct i2c_client * client)814 static int it6263_probe(struct i2c_client *client)
815 {
816 	struct device *dev = &client->dev;
817 	struct gpio_desc *reset_gpio;
818 	struct it6263 *it;
819 	int ret;
820 
821 	it = devm_kzalloc(dev, sizeof(*it), GFP_KERNEL);
822 	if (!it)
823 		return -ENOMEM;
824 
825 	it->dev = dev;
826 	it->hdmi_i2c = client;
827 
828 	it->hdmi_regmap = devm_regmap_init_i2c(client,
829 					       &it6263_hdmi_regmap_config);
830 	if (IS_ERR(it->hdmi_regmap))
831 		return dev_err_probe(dev, PTR_ERR(it->hdmi_regmap),
832 				     "failed to init I2C regmap for HDMI\n");
833 
834 	reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
835 	if (IS_ERR(reset_gpio))
836 		return dev_err_probe(dev, PTR_ERR(reset_gpio),
837 				     "failed to get reset gpio\n");
838 
839 	ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it6263_supplies),
840 					     it6263_supplies);
841 	if (ret)
842 		return dev_err_probe(dev, ret, "failed to get power supplies\n");
843 
844 	ret = it6263_parse_dt(it);
845 	if (ret)
846 		return ret;
847 
848 	it6263_hw_reset(reset_gpio);
849 
850 	ret = it6263_lvds_set_i2c_addr(it);
851 	if (ret)
852 		return dev_err_probe(dev, ret, "failed to set I2C addr\n");
853 
854 	it->lvds_i2c = devm_i2c_new_dummy_device(dev, client->adapter,
855 						 LVDS_INPUT_CTRL_I2C_ADDR);
856 	if (IS_ERR(it->lvds_i2c))
857 		return dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c),
858 				     "failed to allocate I2C device for LVDS\n");
859 
860 	it->lvds_regmap = devm_regmap_init_i2c(it->lvds_i2c,
861 					       &it6263_lvds_regmap_config);
862 	if (IS_ERR(it->lvds_regmap))
863 		return dev_err_probe(dev, PTR_ERR(it->lvds_regmap),
864 				     "failed to init I2C regmap for LVDS\n");
865 
866 	it6263_lvds_config(it);
867 	it6263_hdmi_config(it);
868 
869 	i2c_set_clientdata(client, it);
870 
871 	it->bridge.funcs = &it6263_bridge_funcs;
872 	it->bridge.of_node = dev->of_node;
873 	/* IT6263 chip doesn't support HPD interrupt. */
874 	it->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
875 			 DRM_BRIDGE_OP_HDMI;
876 	it->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
877 	it->bridge.vendor = "ITE";
878 	it->bridge.product = "IT6263";
879 
880 	return devm_drm_bridge_add(dev, &it->bridge);
881 }
882 
883 static const struct of_device_id it6263_of_match[] = {
884 	{ .compatible = "ite,it6263", },
885 	{ }
886 };
887 MODULE_DEVICE_TABLE(of, it6263_of_match);
888 
889 static const struct i2c_device_id it6263_i2c_ids[] = {
890 	{ "it6263" },
891 	{ }
892 };
893 MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids);
894 
895 static struct i2c_driver it6263_driver = {
896 	.probe = it6263_probe,
897 	.driver = {
898 		.name = "it6263",
899 		.of_match_table = it6263_of_match,
900 	},
901 	.id_table = it6263_i2c_ids,
902 };
903 module_i2c_driver(it6263_driver);
904 
905 MODULE_DESCRIPTION("ITE Tech. Inc. IT6263 LVDS/HDMI bridge");
906 MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
907 MODULE_LICENSE("GPL");
908