1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
4 *
5 * Authors:
6 * Peter Pan <peterpandong@micron.com>
7 */
8 #ifndef __LINUX_MTD_SPINAND_H
9 #define __LINUX_MTD_SPINAND_H
10
11 #include <linux/mutex.h>
12 #include <linux/bitops.h>
13 #include <linux/device.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi-mem.h>
18
19 /**
20 * Standard SPI NAND flash operations
21 */
22
23 #define SPINAND_RESET_1S_0_0_OP \
24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \
25 SPI_MEM_OP_NO_ADDR, \
26 SPI_MEM_OP_NO_DUMMY, \
27 SPI_MEM_OP_NO_DATA)
28
29 #define SPINAND_WR_EN_DIS_1S_0_0_OP(enable) \
30 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \
31 SPI_MEM_OP_NO_ADDR, \
32 SPI_MEM_OP_NO_DUMMY, \
33 SPI_MEM_OP_NO_DATA)
34
35 #define SPINAND_READID_1S_1S_1S_OP(naddr, ndummy, buf, len) \
36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
37 SPI_MEM_OP_ADDR(naddr, 0, 1), \
38 SPI_MEM_OP_DUMMY(ndummy, 1), \
39 SPI_MEM_OP_DATA_IN(len, buf, 1))
40
41 #define SPINAND_SET_FEATURE_1S_1S_1S_OP(reg, valptr) \
42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
43 SPI_MEM_OP_ADDR(1, reg, 1), \
44 SPI_MEM_OP_NO_DUMMY, \
45 SPI_MEM_OP_DATA_OUT(1, valptr, 1))
46
47 #define SPINAND_GET_FEATURE_1S_1S_1S_OP(reg, valptr) \
48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \
49 SPI_MEM_OP_ADDR(1, reg, 1), \
50 SPI_MEM_OP_NO_DUMMY, \
51 SPI_MEM_OP_DATA_IN(1, valptr, 1))
52
53 #define SPINAND_BLK_ERASE_1S_1S_0_OP(addr) \
54 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \
55 SPI_MEM_OP_ADDR(3, addr, 1), \
56 SPI_MEM_OP_NO_DUMMY, \
57 SPI_MEM_OP_NO_DATA)
58
59 #define SPINAND_PAGE_READ_1S_1S_0_OP(addr) \
60 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \
61 SPI_MEM_OP_ADDR(3, addr, 1), \
62 SPI_MEM_OP_NO_DUMMY, \
63 SPI_MEM_OP_NO_DATA)
64
65 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
66 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
67 SPI_MEM_OP_ADDR(2, addr, 1), \
68 SPI_MEM_OP_DUMMY(ndummy, 1), \
69 SPI_MEM_OP_DATA_IN(len, buf, 1), \
70 SPI_MEM_OP_MAX_FREQ(freq))
71
72 #define SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
73 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
74 SPI_MEM_OP_ADDR(2, addr, 1), \
75 SPI_MEM_OP_DUMMY(ndummy, 1), \
76 SPI_MEM_OP_DATA_IN(len, buf, 1), \
77 SPI_MEM_OP_MAX_FREQ(freq))
78
79 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
80 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
81 SPI_MEM_OP_ADDR(3, addr, 1), \
82 SPI_MEM_OP_DUMMY(ndummy, 1), \
83 SPI_MEM_OP_DATA_IN(len, buf, 1), \
84 SPI_MEM_OP_MAX_FREQ(freq))
85
86 #define SPINAND_PAGE_READ_FROM_CACHE_FAST_3A_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
87 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
88 SPI_MEM_OP_ADDR(3, addr, 1), \
89 SPI_MEM_OP_DUMMY(ndummy, 1), \
90 SPI_MEM_OP_DATA_IN(len, buf, 1), \
91 SPI_MEM_OP_MAX_FREQ(freq))
92
93 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_1D_OP(addr, ndummy, buf, len, freq) \
94 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \
95 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
96 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
97 SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \
98 SPI_MEM_OP_MAX_FREQ(freq))
99
100 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(addr, ndummy, buf, len, freq) \
101 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
102 SPI_MEM_OP_ADDR(2, addr, 1), \
103 SPI_MEM_OP_DUMMY(ndummy, 1), \
104 SPI_MEM_OP_DATA_IN(len, buf, 2), \
105 SPI_MEM_OP_MAX_FREQ(freq))
106
107 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_2S_OP(addr, ndummy, buf, len, freq) \
108 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
109 SPI_MEM_OP_ADDR(3, addr, 1), \
110 SPI_MEM_OP_DUMMY(ndummy, 1), \
111 SPI_MEM_OP_DATA_IN(len, buf, 2), \
112 SPI_MEM_OP_MAX_FREQ(freq))
113
114 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_2D_OP(addr, ndummy, buf, len, freq) \
115 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3d, 1), \
116 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
117 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
118 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
119 SPI_MEM_OP_MAX_FREQ(freq))
120
121 #define SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(addr, ndummy, buf, len, freq) \
122 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
123 SPI_MEM_OP_ADDR(2, addr, 2), \
124 SPI_MEM_OP_DUMMY(ndummy, 2), \
125 SPI_MEM_OP_DATA_IN(len, buf, 2), \
126 SPI_MEM_OP_MAX_FREQ(freq))
127
128 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_2S_2S_OP(addr, ndummy, buf, len, freq) \
129 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
130 SPI_MEM_OP_ADDR(3, addr, 2), \
131 SPI_MEM_OP_DUMMY(ndummy, 2), \
132 SPI_MEM_OP_DATA_IN(len, buf, 2), \
133 SPI_MEM_OP_MAX_FREQ(freq))
134
135 #define SPINAND_PAGE_READ_FROM_CACHE_1S_2D_2D_OP(addr, ndummy, buf, len, freq) \
136 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \
137 SPI_MEM_DTR_OP_ADDR(2, addr, 2), \
138 SPI_MEM_DTR_OP_DUMMY(ndummy, 2), \
139 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
140 SPI_MEM_OP_MAX_FREQ(freq))
141
142 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(addr, ndummy, buf, len, freq) \
143 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
144 SPI_MEM_OP_ADDR(2, addr, 1), \
145 SPI_MEM_OP_DUMMY(ndummy, 1), \
146 SPI_MEM_OP_DATA_IN(len, buf, 4), \
147 SPI_MEM_OP_MAX_FREQ(freq))
148
149 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_4S_OP(addr, ndummy, buf, len, freq) \
150 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
151 SPI_MEM_OP_ADDR(3, addr, 1), \
152 SPI_MEM_OP_DUMMY(ndummy, 1), \
153 SPI_MEM_OP_DATA_IN(len, buf, 4), \
154 SPI_MEM_OP_MAX_FREQ(freq))
155
156 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_4D_OP(addr, ndummy, buf, len, freq) \
157 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \
158 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
159 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
160 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
161 SPI_MEM_OP_MAX_FREQ(freq))
162
163 #define SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(addr, ndummy, buf, len, freq) \
164 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
165 SPI_MEM_OP_ADDR(2, addr, 4), \
166 SPI_MEM_OP_DUMMY(ndummy, 4), \
167 SPI_MEM_OP_DATA_IN(len, buf, 4), \
168 SPI_MEM_OP_MAX_FREQ(freq))
169
170 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_4S_4S_OP(addr, ndummy, buf, len, freq) \
171 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
172 SPI_MEM_OP_ADDR(3, addr, 4), \
173 SPI_MEM_OP_DUMMY(ndummy, 4), \
174 SPI_MEM_OP_DATA_IN(len, buf, 4), \
175 SPI_MEM_OP_MAX_FREQ(freq))
176
177 #define SPINAND_PAGE_READ_FROM_CACHE_1S_4D_4D_OP(addr, ndummy, buf, len, freq) \
178 SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \
179 SPI_MEM_DTR_OP_ADDR(2, addr, 4), \
180 SPI_MEM_DTR_OP_DUMMY(ndummy, 4), \
181 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
182 SPI_MEM_OP_MAX_FREQ(freq))
183
184 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_8S_OP(addr, ndummy, buf, len, freq) \
185 SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1), \
186 SPI_MEM_OP_ADDR(2, addr, 1), \
187 SPI_MEM_OP_DUMMY(ndummy, 1), \
188 SPI_MEM_OP_DATA_IN(len, buf, 8), \
189 SPI_MEM_OP_MAX_FREQ(freq))
190
191 #define SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(addr, ndummy, buf, len, freq) \
192 SPI_MEM_OP(SPI_MEM_OP_CMD(0xcb, 1), \
193 SPI_MEM_OP_ADDR(2, addr, 8), \
194 SPI_MEM_OP_DUMMY(ndummy, 8), \
195 SPI_MEM_OP_DATA_IN(len, buf, 8), \
196 SPI_MEM_OP_MAX_FREQ(freq))
197
198 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(addr, ndummy, buf, len, freq) \
199 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9d, 1), \
200 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
201 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
202 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \
203 SPI_MEM_OP_MAX_FREQ(freq))
204
205 #define SPINAND_PROG_EXEC_1S_1S_0_OP(addr) \
206 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
207 SPI_MEM_OP_ADDR(3, addr, 1), \
208 SPI_MEM_OP_NO_DUMMY, \
209 SPI_MEM_OP_NO_DATA)
210
211 #define SPINAND_PROG_LOAD_1S_1S_1S_OP(reset, addr, buf, len) \
212 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \
213 SPI_MEM_OP_ADDR(2, addr, 1), \
214 SPI_MEM_OP_NO_DUMMY, \
215 SPI_MEM_OP_DATA_OUT(len, buf, 1))
216
217 #define SPINAND_PROG_LOAD_1S_1S_4S_OP(reset, addr, buf, len) \
218 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
219 SPI_MEM_OP_ADDR(2, addr, 1), \
220 SPI_MEM_OP_NO_DUMMY, \
221 SPI_MEM_OP_DATA_OUT(len, buf, 4))
222
223 #define SPINAND_PROG_LOAD_1S_1S_8S_OP(addr, buf, len) \
224 SPI_MEM_OP(SPI_MEM_OP_CMD(0x82, 1), \
225 SPI_MEM_OP_ADDR(2, addr, 1), \
226 SPI_MEM_OP_NO_DUMMY, \
227 SPI_MEM_OP_DATA_OUT(len, buf, 8))
228
229 #define SPINAND_PROG_LOAD_1S_8S_8S_OP(reset, addr, buf, len) \
230 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0xc2 : 0xc4, 1), \
231 SPI_MEM_OP_ADDR(2, addr, 8), \
232 SPI_MEM_OP_NO_DUMMY, \
233 SPI_MEM_OP_DATA_OUT(len, buf, 8))
234
235 /**
236 * Standard SPI NAND flash commands
237 */
238 #define SPINAND_CMD_PROG_LOAD_X4 0x32
239 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34
240
241 /* feature register */
242 #define REG_BLOCK_LOCK 0xa0
243 #define BL_ALL_UNLOCKED 0x00
244
245 /* configuration register */
246 #define REG_CFG 0xb0
247 #define CFG_OTP_ENABLE BIT(6)
248 #define CFG_ECC_ENABLE BIT(4)
249 #define CFG_QUAD_ENABLE BIT(0)
250
251 /* status register */
252 #define REG_STATUS 0xc0
253 #define STATUS_BUSY BIT(0)
254 #define STATUS_ERASE_FAILED BIT(2)
255 #define STATUS_PROG_FAILED BIT(3)
256 #define STATUS_ECC_MASK GENMASK(5, 4)
257 #define STATUS_ECC_NO_BITFLIPS (0 << 4)
258 #define STATUS_ECC_HAS_BITFLIPS (1 << 4)
259 #define STATUS_ECC_UNCOR_ERROR (2 << 4)
260
261 struct spinand_op;
262 struct spinand_device;
263
264 #define SPINAND_MAX_ID_LEN 5
265 /*
266 * For erase, write and read operation, we got the following timings :
267 * tBERS (erase) 1ms to 4ms
268 * tPROG 300us to 400us
269 * tREAD 25us to 100us
270 * In order to minimize latency, the min value is divided by 4 for the
271 * initial delay, and dividing by 20 for the poll delay.
272 * For reset, 5us/10us/500us if the device is respectively
273 * reading/programming/erasing when the RESET occurs. Since we always
274 * issue a RESET when the device is IDLE, 5us is selected for both initial
275 * and poll delay.
276 */
277 #define SPINAND_READ_INITIAL_DELAY_US 6
278 #define SPINAND_READ_POLL_DELAY_US 5
279 #define SPINAND_RESET_INITIAL_DELAY_US 5
280 #define SPINAND_RESET_POLL_DELAY_US 5
281 #define SPINAND_WRITE_INITIAL_DELAY_US 75
282 #define SPINAND_WRITE_POLL_DELAY_US 15
283 #define SPINAND_ERASE_INITIAL_DELAY_US 250
284 #define SPINAND_ERASE_POLL_DELAY_US 50
285
286 #define SPINAND_WAITRDY_TIMEOUT_MS 400
287
288 /**
289 * struct spinand_id - SPI NAND id structure
290 * @data: buffer containing the id bytes. Currently 4 bytes large, but can
291 * be extended if required
292 * @len: ID length
293 */
294 struct spinand_id {
295 u8 data[SPINAND_MAX_ID_LEN];
296 int len;
297 };
298
299 enum spinand_readid_method {
300 SPINAND_READID_METHOD_OPCODE,
301 SPINAND_READID_METHOD_OPCODE_ADDR,
302 SPINAND_READID_METHOD_OPCODE_DUMMY,
303 };
304
305 /**
306 * struct spinand_devid - SPI NAND device id structure
307 * @id: device id of current chip
308 * @len: number of bytes in device id
309 * @method: method to read chip id
310 * There are 3 possible variants:
311 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
312 * after read_id opcode.
313 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
314 * read_id opcode + 1-byte address.
315 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
316 * read_id opcode + 1 dummy byte.
317 */
318 struct spinand_devid {
319 const u8 *id;
320 const u8 len;
321 const enum spinand_readid_method method;
322 };
323
324 /**
325 * struct manufacurer_ops - SPI NAND manufacturer specific operations
326 * @init: initialize a SPI NAND device
327 * @cleanup: cleanup a SPI NAND device
328 *
329 * Each SPI NAND manufacturer driver should implement this interface so that
330 * NAND chips coming from this vendor can be initialized properly.
331 */
332 struct spinand_manufacturer_ops {
333 int (*init)(struct spinand_device *spinand);
334 void (*cleanup)(struct spinand_device *spinand);
335 };
336
337 /**
338 * struct spinand_manufacturer - SPI NAND manufacturer instance
339 * @id: manufacturer ID
340 * @name: manufacturer name
341 * @devid_len: number of bytes in device ID
342 * @chips: supported SPI NANDs under current manufacturer
343 * @nchips: number of SPI NANDs available in chips array
344 * @ops: manufacturer operations
345 */
346 struct spinand_manufacturer {
347 u8 id;
348 char *name;
349 const struct spinand_info *chips;
350 const size_t nchips;
351 const struct spinand_manufacturer_ops *ops;
352 };
353
354 /* SPI NAND manufacturers */
355 extern const struct spinand_manufacturer alliancememory_spinand_manufacturer;
356 extern const struct spinand_manufacturer ato_spinand_manufacturer;
357 extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
358 extern const struct spinand_manufacturer foresee_spinand_manufacturer;
359 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
360 extern const struct spinand_manufacturer macronix_spinand_manufacturer;
361 extern const struct spinand_manufacturer micron_spinand_manufacturer;
362 extern const struct spinand_manufacturer paragon_spinand_manufacturer;
363 extern const struct spinand_manufacturer skyhigh_spinand_manufacturer;
364 extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
365 extern const struct spinand_manufacturer winbond_spinand_manufacturer;
366 extern const struct spinand_manufacturer xtx_spinand_manufacturer;
367
368 /**
369 * struct spinand_op_variants - SPI NAND operation variants
370 * @ops: the list of variants for a given operation
371 * @nops: the number of variants
372 *
373 * Some operations like read-from-cache/write-to-cache have several variants
374 * depending on the number of IO lines you use to transfer data or address
375 * cycles. This structure is a way to describe the different variants supported
376 * by a chip and let the core pick the best one based on the SPI mem controller
377 * capabilities.
378 */
379 struct spinand_op_variants {
380 const struct spi_mem_op *ops;
381 unsigned int nops;
382 };
383
384 #define SPINAND_OP_VARIANTS(name, ...) \
385 const struct spinand_op_variants name = { \
386 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \
387 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \
388 sizeof(struct spi_mem_op), \
389 }
390
391 /**
392 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
393 * chip
394 * @get_status: get the ECC status. Should return a positive number encoding
395 * the number of corrected bitflips if correction was possible or
396 * -EBADMSG if there are uncorrectable errors. I can also return
397 * other negative error codes if the error is not caused by
398 * uncorrectable bitflips
399 * @ooblayout: the OOB layout used by the on-die ECC implementation
400 */
401 struct spinand_ecc_info {
402 int (*get_status)(struct spinand_device *spinand, u8 status);
403 const struct mtd_ooblayout_ops *ooblayout;
404 };
405
406 #define SPINAND_HAS_QE_BIT BIT(0)
407 #define SPINAND_HAS_CR_FEAT_BIT BIT(1)
408 #define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2)
409 #define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3)
410 #define SPINAND_NO_RAW_ACCESS BIT(4)
411
412 /**
413 * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
414 * @status: status of the last wait operation that will be used in case
415 * ->get_status() is not populated by the spinand device.
416 */
417 struct spinand_ondie_ecc_conf {
418 u8 status;
419 };
420
421 /**
422 * struct spinand_otp_layout - structure to describe the SPI NAND OTP area
423 * @npages: number of pages in the OTP
424 * @start_page: start page of the user/factory OTP area.
425 */
426 struct spinand_otp_layout {
427 unsigned int npages;
428 unsigned int start_page;
429 };
430
431 /**
432 * struct spinand_fact_otp_ops - SPI NAND OTP methods for factory area
433 * @info: get the OTP area information
434 * @read: read from the SPI NAND OTP area
435 */
436 struct spinand_fact_otp_ops {
437 int (*info)(struct spinand_device *spinand, size_t len,
438 struct otp_info *buf, size_t *retlen);
439 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
440 size_t *retlen, u8 *buf);
441 };
442
443 /**
444 * struct spinand_user_otp_ops - SPI NAND OTP methods for user area
445 * @info: get the OTP area information
446 * @lock: lock an OTP region
447 * @erase: erase an OTP region
448 * @read: read from the SPI NAND OTP area
449 * @write: write to the SPI NAND OTP area
450 */
451 struct spinand_user_otp_ops {
452 int (*info)(struct spinand_device *spinand, size_t len,
453 struct otp_info *buf, size_t *retlen);
454 int (*lock)(struct spinand_device *spinand, loff_t from, size_t len);
455 int (*erase)(struct spinand_device *spinand, loff_t from, size_t len);
456 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
457 size_t *retlen, u8 *buf);
458 int (*write)(struct spinand_device *spinand, loff_t from, size_t len,
459 size_t *retlen, const u8 *buf);
460 };
461
462 /**
463 * struct spinand_fact_otp - SPI NAND OTP grouping structure for factory area
464 * @layout: OTP region layout
465 * @ops: OTP access ops
466 */
467 struct spinand_fact_otp {
468 const struct spinand_otp_layout layout;
469 const struct spinand_fact_otp_ops *ops;
470 };
471
472 /**
473 * struct spinand_user_otp - SPI NAND OTP grouping structure for user area
474 * @layout: OTP region layout
475 * @ops: OTP access ops
476 */
477 struct spinand_user_otp {
478 const struct spinand_otp_layout layout;
479 const struct spinand_user_otp_ops *ops;
480 };
481
482 /**
483 * struct spinand_info - Structure used to describe SPI NAND chips
484 * @model: model name
485 * @devid: device ID
486 * @flags: OR-ing of the SPINAND_XXX flags
487 * @memorg: memory organization
488 * @eccreq: ECC requirements
489 * @eccinfo: on-die ECC info
490 * @op_variants: operations variants
491 * @op_variants.read_cache: variants of the read-cache operation
492 * @op_variants.write_cache: variants of the write-cache operation
493 * @op_variants.update_cache: variants of the update-cache operation
494 * @select_target: function used to select a target/die. Required only for
495 * multi-die chips
496 * @configure_chip: Align the chip configuration with the core settings
497 * @set_cont_read: enable/disable continuous cached reads
498 * @fact_otp: SPI NAND factory OTP info.
499 * @user_otp: SPI NAND user OTP info.
500 * @read_retries: the number of read retry modes supported
501 * @set_read_retry: enable/disable read retry for data recovery
502 *
503 * Each SPI NAND manufacturer driver should have a spinand_info table
504 * describing all the chips supported by the driver.
505 */
506 struct spinand_info {
507 const char *model;
508 struct spinand_devid devid;
509 u32 flags;
510 struct nand_memory_organization memorg;
511 struct nand_ecc_props eccreq;
512 struct spinand_ecc_info eccinfo;
513 struct {
514 const struct spinand_op_variants *read_cache;
515 const struct spinand_op_variants *write_cache;
516 const struct spinand_op_variants *update_cache;
517 } op_variants;
518 int (*select_target)(struct spinand_device *spinand,
519 unsigned int target);
520 int (*configure_chip)(struct spinand_device *spinand);
521 int (*set_cont_read)(struct spinand_device *spinand,
522 bool enable);
523 struct spinand_fact_otp fact_otp;
524 struct spinand_user_otp user_otp;
525 unsigned int read_retries;
526 int (*set_read_retry)(struct spinand_device *spinand,
527 unsigned int read_retry);
528 };
529
530 #define SPINAND_ID(__method, ...) \
531 { \
532 .id = (const u8[]){ __VA_ARGS__ }, \
533 .len = sizeof((u8[]){ __VA_ARGS__ }), \
534 .method = __method, \
535 }
536
537 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
538 { \
539 .read_cache = __read, \
540 .write_cache = __write, \
541 .update_cache = __update, \
542 }
543
544 #define SPINAND_ECCINFO(__ooblayout, __get_status) \
545 .eccinfo = { \
546 .ooblayout = __ooblayout, \
547 .get_status = __get_status, \
548 }
549
550 #define SPINAND_SELECT_TARGET(__func) \
551 .select_target = __func
552
553 #define SPINAND_CONFIGURE_CHIP(__configure_chip) \
554 .configure_chip = __configure_chip
555
556 #define SPINAND_CONT_READ(__set_cont_read) \
557 .set_cont_read = __set_cont_read
558
559 #define SPINAND_FACT_OTP_INFO(__npages, __start_page, __ops) \
560 .fact_otp = { \
561 .layout = { \
562 .npages = __npages, \
563 .start_page = __start_page, \
564 }, \
565 .ops = __ops, \
566 }
567
568 #define SPINAND_USER_OTP_INFO(__npages, __start_page, __ops) \
569 .user_otp = { \
570 .layout = { \
571 .npages = __npages, \
572 .start_page = __start_page, \
573 }, \
574 .ops = __ops, \
575 }
576
577 #define SPINAND_READ_RETRY(__read_retries, __set_read_retry) \
578 .read_retries = __read_retries, \
579 .set_read_retry = __set_read_retry
580
581 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
582 __flags, ...) \
583 { \
584 .model = __model, \
585 .devid = __id, \
586 .memorg = __memorg, \
587 .eccreq = __eccreq, \
588 .op_variants = __op_variants, \
589 .flags = __flags, \
590 __VA_ARGS__ \
591 }
592
593 struct spinand_dirmap {
594 struct spi_mem_dirmap_desc *wdesc;
595 struct spi_mem_dirmap_desc *rdesc;
596 struct spi_mem_dirmap_desc *wdesc_ecc;
597 struct spi_mem_dirmap_desc *rdesc_ecc;
598 };
599
600 /**
601 * struct spinand_device - SPI NAND device instance
602 * @base: NAND device instance
603 * @spimem: pointer to the SPI mem object
604 * @lock: lock used to serialize accesses to the NAND
605 * @id: NAND ID as returned by READ_ID
606 * @flags: NAND flags
607 * @op_templates: various SPI mem op templates
608 * @op_templates.read_cache: read cache op template
609 * @op_templates.write_cache: write cache op template
610 * @op_templates.update_cache: update cache op template
611 * @select_target: select a specific target/die. Usually called before sending
612 * a command addressing a page or an eraseblock embedded in
613 * this die. Only required if your chip exposes several dies
614 * @cur_target: currently selected target/die
615 * @eccinfo: on-die ECC information
616 * @cfg_cache: config register cache. One entry per die
617 * @databuf: bounce buffer for data
618 * @oobbuf: bounce buffer for OOB data
619 * @scratchbuf: buffer used for everything but page accesses. This is needed
620 * because the spi-mem interface explicitly requests that buffers
621 * passed in spi_mem_op be DMA-able, so we can't based the bufs on
622 * the stack
623 * @manufacturer: SPI NAND manufacturer information
624 * @configure_chip: Align the chip configuration with the core settings
625 * @cont_read_possible: Field filled by the core once the whole system
626 * configuration is known to tell whether continuous reads are
627 * suitable to use or not in general with this chip/configuration.
628 * A per-transfer check must of course be done to ensure it is
629 * actually relevant to enable this feature.
630 * @set_cont_read: Enable/disable the continuous read feature
631 * @priv: manufacturer private data
632 * @fact_otp: SPI NAND factory OTP info.
633 * @user_otp: SPI NAND user OTP info.
634 * @read_retries: the number of read retry modes supported
635 * @set_read_retry: Enable/disable the read retry feature
636 */
637 struct spinand_device {
638 struct nand_device base;
639 struct spi_mem *spimem;
640 struct mutex lock;
641 struct spinand_id id;
642 u32 flags;
643
644 struct {
645 const struct spi_mem_op *read_cache;
646 const struct spi_mem_op *write_cache;
647 const struct spi_mem_op *update_cache;
648 } op_templates;
649
650 struct spinand_dirmap *dirmaps;
651
652 int (*select_target)(struct spinand_device *spinand,
653 unsigned int target);
654 unsigned int cur_target;
655
656 struct spinand_ecc_info eccinfo;
657
658 u8 *cfg_cache;
659 u8 *databuf;
660 u8 *oobbuf;
661 u8 *scratchbuf;
662 const struct spinand_manufacturer *manufacturer;
663 void *priv;
664
665 int (*configure_chip)(struct spinand_device *spinand);
666 bool cont_read_possible;
667 int (*set_cont_read)(struct spinand_device *spinand,
668 bool enable);
669
670 const struct spinand_fact_otp *fact_otp;
671 const struct spinand_user_otp *user_otp;
672
673 unsigned int read_retries;
674 int (*set_read_retry)(struct spinand_device *spinand,
675 unsigned int retry_mode);
676 };
677
678 /**
679 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
680 * @mtd: MTD instance
681 *
682 * Return: the SPI NAND device attached to @mtd.
683 */
mtd_to_spinand(struct mtd_info * mtd)684 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
685 {
686 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
687 }
688
689 /**
690 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
691 * @spinand: SPI NAND device
692 *
693 * Return: the MTD device embedded in @spinand.
694 */
spinand_to_mtd(struct spinand_device * spinand)695 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
696 {
697 return nanddev_to_mtd(&spinand->base);
698 }
699
700 /**
701 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
702 * @nand: NAND object
703 *
704 * Return: the SPI NAND device embedding @nand.
705 */
nand_to_spinand(struct nand_device * nand)706 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
707 {
708 return container_of(nand, struct spinand_device, base);
709 }
710
711 /**
712 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
713 * @spinand: SPI NAND device
714 *
715 * Return: the NAND device embedded in @spinand.
716 */
717 static inline struct nand_device *
spinand_to_nand(struct spinand_device * spinand)718 spinand_to_nand(struct spinand_device *spinand)
719 {
720 return &spinand->base;
721 }
722
723 /**
724 * spinand_set_of_node - Attach a DT node to a SPI NAND device
725 * @spinand: SPI NAND device
726 * @np: DT node
727 *
728 * Attach a DT node to a SPI NAND device.
729 */
spinand_set_of_node(struct spinand_device * spinand,struct device_node * np)730 static inline void spinand_set_of_node(struct spinand_device *spinand,
731 struct device_node *np)
732 {
733 nanddev_set_of_node(&spinand->base, np);
734 }
735
736 int spinand_match_and_init(struct spinand_device *spinand,
737 const struct spinand_info *table,
738 unsigned int table_size,
739 enum spinand_readid_method rdid_method);
740
741 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
742 int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val);
743 int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val);
744 int spinand_write_enable_op(struct spinand_device *spinand);
745 int spinand_select_target(struct spinand_device *spinand, unsigned int target);
746
747 int spinand_wait(struct spinand_device *spinand, unsigned long initial_delay_us,
748 unsigned long poll_delay_us, u8 *s);
749
750 int spinand_read_page(struct spinand_device *spinand,
751 const struct nand_page_io_req *req);
752
753 int spinand_write_page(struct spinand_device *spinand,
754 const struct nand_page_io_req *req);
755
756 size_t spinand_otp_page_size(struct spinand_device *spinand);
757 size_t spinand_fact_otp_size(struct spinand_device *spinand);
758 size_t spinand_user_otp_size(struct spinand_device *spinand);
759
760 int spinand_fact_otp_read(struct spinand_device *spinand, loff_t ofs,
761 size_t len, size_t *retlen, u8 *buf);
762 int spinand_user_otp_read(struct spinand_device *spinand, loff_t ofs,
763 size_t len, size_t *retlen, u8 *buf);
764 int spinand_user_otp_write(struct spinand_device *spinand, loff_t ofs,
765 size_t len, size_t *retlen, const u8 *buf);
766
767 int spinand_set_mtd_otp_ops(struct spinand_device *spinand);
768
769 #endif /* __LINUX_MTD_SPINAND_H */
770