| /linux/arch/m68k/ifpsp060/ |
| H A D | pfpsp.sa | 1 dc.l $60ff0000,$17400000,$60ff0000,$15f40000
2 dc.l $60ff0000,$02b60000,$60ff0000,$04700000
3 dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000
4 dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000
5 dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f
10 dc.l $00044e74,$00042f00,$203afef2,$487b0930
[all …]
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| H A D | fplsp.sa | 1 dc.l $60ff0000,$238e0000,$60ff0000,$24200000
2 dc.l $60ff0000,$24b60000,$60ff0000,$11060000
3 dc.l $60ff0000,$11980000,$60ff0000,$122e0000
4 dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000
5 dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000
6 dc.l $60ff0000,$13400000,$60ff0000,$13d60000
7 dc.l $60ff0000,$05ae0000,$60ff0000,$06400000
8 dc.l $60ff0000,$06d60000,$60ff0000,$213e0000
9 dc.l $60ff0000,$21d00000,$60ff0000,$22660000
10 dc.l $60ff0000,$16160000,$60ff0000,$16a80000
[all …]
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| H A D | itest.sa | 1 dc.l $60ff0000,$005c5465,$7374696e,$67203638
2 dc.l $30363020,$49535020,$73746172,$7465643a
3 dc.l $0a007061,$73736564,$0a002066,$61696c65
4 dc.l $640a0000,$4a80660e,$487affe8,$61ff0000
5 dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f
6 dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56
7 dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c
8 dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff
9 dc.l $00004f58,$588f61ff,$000000f0,$61ffffff
10 dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff
[all …]
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| H A D | ftest.sa | 1 dc.l $60ff0000,$00d40000,$60ff0000,$016c0000
2 dc.l $60ff0000,$01a80000,$54657374,$696e6720
3 dc.l $36383036,$30204650,$53502073,$74617274
4 dc.l $65643a0a,$00546573,$74696e67,$20363830
5 dc.l $36302046,$50535020,$756e696d,$706c656d
6 dc.l $656e7465,$6420696e,$73747275,$6374696f
7 dc.l $6e207374,$61727465,$643a0a00,$54657374
8 dc.l $696e6720,$36383036,$30204650,$53502065
9 dc.l $78636570,$74696f6e,$20656e61,$626c6564
10 dc.l $20737461,$72746564,$3a0a0070,$61737365
[all …]
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| H A D | ilsp.sa | 1 dc.l $60ff0000,$01fe0000,$60ff0000,$02080000
2 dc.l $60ff0000,$04900000,$60ff0000,$04080000
3 dc.l $60ff0000,$051e0000,$60ff0000,$053c0000
4 dc.l $60ff0000,$055a0000,$60ff0000,$05740000
5 dc.l $60ff0000,$05940000,$60ff0000,$05b40000
6 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
7 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
8 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
9 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
10 dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
[all …]
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| /linux/drivers/tty/ |
| H A D | nozomi.c | 315 struct nozomi *dc; member
463 static void nozomi_setup_memory(struct nozomi *dc) in nozomi_setup_memory() argument
465 void __iomem *offset = dc->base_addr + dc->config_table.dl_start; in nozomi_setup_memory()
472 dc->port[PORT_MDM].dl_addr[CH_A] = offset; in nozomi_setup_memory()
473 dc->port[PORT_MDM].dl_addr[CH_B] = in nozomi_setup_memory()
474 (offset += dc->config_table.dl_mdm_len1); in nozomi_setup_memory()
475 dc->port[PORT_MDM].dl_size[CH_A] = in nozomi_setup_memory()
476 dc->config_table.dl_mdm_len1 - buff_offset; in nozomi_setup_memory()
477 dc->port[PORT_MDM].dl_size[CH_B] = in nozomi_setup_memory()
478 dc->config_table.dl_mdm_len2 - buff_offset; in nozomi_setup_memory()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.h | 31 void dcn20_log_color_state(struct dc *dc,
38 struct dc *dc,
41 struct dc *dc,
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
45 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
49 void dcn20_program_output_csc(struct dc *dc,
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
59 struct dc *dc,
[all …]
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| H A D | dcn20_hwseq.c | 74 void dcn20_log_color_state(struct dc *dc, in dcn20_log_color_state() argument
77 struct dc_context *dc_ctx = dc->ctx; in dcn20_log_color_state()
78 struct resource_pool *pool = dc->res_pool; in dcn20_log_color_state()
150 dc->caps.color.dpp.input_lut_shared, in dcn20_log_color_state()
151 dc->caps.color.dpp.icsc, in dcn20_log_color_state()
152 dc->caps.color.dpp.dgam_ram, in dcn20_log_color_state()
153 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn20_log_color_state()
154 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn20_log_color_state()
155 dc->caps.color.dpp.dgam_rom_caps.gamma2_2, in dcn20_log_color_state()
156 dc->caps.color.dpp.dgam_rom_caps.pq, in dcn20_log_color_state()
[all …]
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| /linux/drivers/md/ |
| H A D | dm-delay.c | 59 struct delay_c *dc = timer_container_of(dc, t, delay_timer); in handle_delayed_timer() local
61 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
64 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
66 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
69 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
71 return !!dc->worker; in delay_is_fast()
86 static void flush_delayed_bios(struct delay_c *dc, bool flush_all) in flush_delayed_bios() argument
95 mutex_lock(&dc->process_bios_lock); in flush_delayed_bios()
96 spin_lock(&dc->delayed_bios_lock); in flush_delayed_bios()
97 list_replace_init(&dc->delayed_bios, &local_list); in flush_delayed_bios()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer_private.h | 76 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
77 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
78 void (*init_pipes)(struct dc *dc, struct dc_state *context);
79 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
80 void (*plane_atomic_disconnect)(struct dc *dc,
83 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
84 bool (*set_input_transfer_func)(struct dc *dc,
87 bool (*set_output_transfer_func)(struct dc *dc,
90 void (*power_down)(struct dc *dc);
93 bool (*enable_display_power_gating)(struct dc *dc,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.h | 14 struct dc;
36 void dcn401_init_hw(struct dc *dc);
40 bool dcn401_set_output_transfer_func(struct dc *dc,
43 void dcn401_trigger_3dlut_dma_load(struct dc *dc,
50 struct dc *dc);
52 void dcn401_populate_mcm_luts(struct dc *dc,
64 bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);
66 void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,
69 void dcn401_prepare_bandwidth(struct dc *dc,
73 struct dc *dc,
[all …]
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| H A D | dcn401_hwseq.c | 47 dc->ctx->logger
54 void dcn401_initialize_min_clocks(struct dc *dc) in dcn401_initialize_min_clocks() argument
56 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
59 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
60 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
61 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
62 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000; in dcn401_initialize_min_clocks()
63 if (dc->debug.disable_boot_optimizations) { in dcn401_initialize_min_clocks()
64 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; in dcn401_initialize_min_clocks()
71 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); in dcn401_initialize_min_clocks()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.h | 31 struct dc;
44 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
46 void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
48 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
53 bool dcn32_set_input_transfer_func(struct dc *dc,
60 bool dcn32_set_output_transfer_func(struct dc *dc,
64 void dcn32_init_hw(struct dc *dc);
66 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
68 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
70 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 76 static void enable_memory_low_power(struct dc *dc)
78 struct dce_hwseq *hws = dc->hwseq;
81 if (dc->debug.enable_mem_low_power.bits.dmcu) {
83 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
89 if (dc->debug.enable_mem_low_power.bits.optc) {
94 if (dc->debug.enable_mem_low_power.bits.vga) {
99 if (dc->debug.enable_mem_low_power.bits.mpc &&
100 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)
101 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
103 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd…
[all …]
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| H A D | dcn35_hwseq.h | 32 struct dc;
34 void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
48 void dcn35_init_hw(struct dc *dc);
54 void dcn35_power_down_on_boot(struct dc *dc);
56 bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
58 void dcn35_z10_restore(const struct dc *dc);
60 void dcn35_init_pipes(struct dc *dc, struct dc_state *context);
61 void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
62 void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
64 void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
[all …]
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| /linux/drivers/scsi/esas2r/ |
| H A D | esas2r_disc.c | 291 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_queue_event() local
298 dc->disc_evt |= disc_evt; in esas2r_disc_queue_event()
314 struct esas2r_disc_context *dc = &a->disc_ctx; in esas2r_disc_start_port() local
326 if (dc->disc_evt) { in esas2r_disc_start_port()
352 esas2r_trace("disc_evt: %d", dc->disc_evt); in esas2r_disc_start_port()
354 dc->flags = 0; in esas2r_disc_start_port()
357 dc->flags |= DCF_POLLED; in esas2r_disc_start_port()
359 rq->interrupt_cx = dc; in esas2r_disc_start_port()
363 if (dc->disc_evt & DCDE_DEV_SCAN) { in esas2r_disc_start_port()
364 dc->disc_evt &= ~DCDE_DEV_SCAN; in esas2r_disc_start_port()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 459 struct dc;
464 bool (*get_dcc_compression_cap)(const struct dc *dc,
467 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
727 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
728 dm_get_timestamp(dc->ctx) : 0
731 if (dc->debug.bw_val_profile.enable) \
732 dc->debug.bw_val_profile.total_count++
735 if (dc->debug.bw_val_profile.enable) { \
737 voltage_level_tick = dm_get_timestamp(dc->ctx); \
738 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
[all …]
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| /linux/drivers/clk/mvebu/ |
| H A D | dove-divider.c | 51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
74 if (dc->divider_table) { in dove_calc_divider()
77 for (i = 0; dc->divider_table[i]; i++) in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn10/ |
| H A D | dcn10_fpu.c | 127 void dcn10_resource_construct_fp(struct dc *dc) in dcn10_resource_construct_fp() argument
130 if (dc->ctx->dce_version == DCN_VERSION_1_01) { in dcn10_resource_construct_fp()
131 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; in dcn10_resource_construct_fp()
132 struct dcn_ip_params *dcn_ip = dc->dcn_ip; in dcn10_resource_construct_fp()
133 struct display_mode_lib *dml = &dc->dml; in dcn10_resource_construct_fp()
140 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { in dcn10_resource_construct_fp()
141 dc->dcn_soc->urgent_latency = 3; in dcn10_resource_construct_fp()
142 dc->debug.disable_dmcu = true; in dcn10_resource_construct_fp()
143 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; in dcn10_resource_construct_fp()
146 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; in dcn10_resource_construct_fp()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_vm_helper.c | 37 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config) in dc_setup_system_context() argument
42 if (dc->hwss.init_sys_ctx) { in dc_setup_system_context()
43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
48 memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config)); in dc_setup_system_context()
49 dc->vm_pa_config.valid = true; in dc_setup_system_context()
50 dc->dml2_options.gpuvm_enable = true; in dc_setup_system_context()
51 dc_z10_save_init(dc); in dc_setup_system_context()
57 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid) in dc_setup_vm_context() argument
59 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid); in dc_setup_vm_context()
62 int dc_get_vmid_use_vector(struct dc *dc) in dc_get_vmid_use_vector() argument
[all …]
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| /linux/drivers/md/bcache/ |
| H A D | writeback.h | 78 static inline bool bcache_dev_stripe_dirty(struct cached_dev *dc, in bcache_dev_stripe_dirty() argument
82 int stripe = offset_to_stripe(&dc->disk, offset); in bcache_dev_stripe_dirty()
88 if (atomic_read(dc->disk.stripe_sectors_dirty + stripe)) in bcache_dev_stripe_dirty()
91 if (nr_sectors <= dc->disk.stripe_size) in bcache_dev_stripe_dirty()
94 nr_sectors -= dc->disk.stripe_size; in bcache_dev_stripe_dirty()
102 static inline bool should_writeback(struct cached_dev *dc, struct bio *bio, in should_writeback() argument
105 unsigned int in_use = dc->disk.c->gc_stats.in_use; in should_writeback()
108 test_bit(BCACHE_DEV_DETACHING, &dc->disk.flags) || in should_writeback()
115 if (dc->partial_stripes_expensive && in should_writeback()
116 bcache_dev_stripe_dirty(dc, bio->bi_iter.bi_sector, in should_writeback()
[all …]
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| /linux/drivers/gpu/ipu-v3/ |
| H A D | ipu-dc.c | 109 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority) in dc_link_event() argument
113 reg = readl(dc->base + DC_RL_CH(event)); in dc_link_event()
116 writel(reg, dc->base + DC_RL_CH(event)); in dc_link_event()
119 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand, in dc_write_tmpl() argument
122 struct ipu_dc_priv *priv = dc->priv; in dc_write_tmpl()
160 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, in ipu_dc_init_sync() argument
163 struct ipu_dc_priv *priv = dc->priv; in ipu_dc_init_sync()
168 dc->di = ipu_di_get_num(di); in ipu_dc_init_sync()
186 if (dc->di) in ipu_dc_init_sync()
192 dc_link_event(dc, DC_EVT_NL, addr, 3); in ipu_dc_init_sync()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 227 void dcn35_update_bw_bounding_box_fpu(struct dc *dc, in dcn35_update_bw_bounding_box_fpu() argument
234 dc->scratch.update_bw_bounding_box.clock_limits; in dcn35_update_bw_bounding_box_fpu()
240 dc->res_pool->res_cap->num_timing_generator; in dcn35_update_bw_bounding_box_fpu()
241 dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn35_update_bw_bounding_box_fpu()
321 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn35_update_bw_bounding_box_fpu()
324 != dc->debug.dram_clock_change_latency_ns in dcn35_update_bw_bounding_box_fpu()
325 && dc->debug.dram_clock_change_latency_ns) { in dcn35_update_bw_bounding_box_fpu()
327 dc->debug.dram_clock_change_latency_ns / 1000.0; in dcn35_update_bw_bounding_box_fpu()
330 if (dc->bb_overrides.dram_clock_change_latency_ns > 0) in dcn35_update_bw_bounding_box_fpu()
332 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; in dcn35_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 261 void dcn351_update_bw_bounding_box_fpu(struct dc *dc, in dcn351_update_bw_bounding_box_fpu() argument
268 dc->scratch.update_bw_bounding_box.clock_limits; in dcn351_update_bw_bounding_box_fpu()
274 dc->res_pool->res_cap->num_timing_generator; in dcn351_update_bw_bounding_box_fpu()
275 dcn3_51_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn351_update_bw_bounding_box_fpu()
355 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; in dcn351_update_bw_bounding_box_fpu()
358 != dc->debug.dram_clock_change_latency_ns in dcn351_update_bw_bounding_box_fpu()
359 && dc->debug.dram_clock_change_latency_ns) { in dcn351_update_bw_bounding_box_fpu()
361 dc->debug.dram_clock_change_latency_ns / 1000.0; in dcn351_update_bw_bounding_box_fpu()
364 if (dc->bb_overrides.dram_clock_change_latency_ns > 0) in dcn351_update_bw_bounding_box_fpu()
366 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; in dcn351_update_bw_bounding_box_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 50 dc->ctx->logger
133 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn201_update_plane_addr() argument
138 struct dce_hwseq *hws = dc->hwseq; in dcn201_update_plane_addr()
165 struct dc *dc, in dcn201_init_blank() argument
168 struct dce_hwseq *hws = dc->hwseq; in dcn201_init_blank()
177 color_space_to_black_color(dc, color_space, &black_color); in dcn201_init_blank()
186 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
187 opp = dc->res_pool->opps[opp_id_src0]; in dcn201_init_blank()
224 void dcn201_init_hw(struct dc *dc) in dcn201_init_hw() argument
227 struct dce_hwseq *hws = dc->hwseq; in dcn201_init_hw()
[all …]
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