Home
last modified time | relevance | path

Searched refs:outb (Results 1 – 25 of 87) sorted by relevance

1234

/titanic_54/usr/src/grub/grub-0.97/netboot/
H A Dns8390.c120 outb(src & 0xff, eth_asic_base + WD_GP2);
121 outb(src >> 8, eth_asic_base + WD_GP2);
123 outb(D8390_COMMAND_RD2 |
125 outb(cnt, eth_nic_base + D8390_P0_RBCR0);
126 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
127 outb(src, eth_nic_base + D8390_P0_RSAR0);
128 outb(src>>8, eth_nic_base + D8390_P0_RSAR1);
129 outb(D8390_COMMAND_RD0 |
133 outb(src & 0xff, eth_asic_base + _3COM_DALSB);
134 outb(src >> 8, eth_asic_base + _3COM_DAMSB);
[all …]
H A Dvia-rhine.c748 outb (byMIICRbak & 0x7f, byMIICR); in ReadMII()
751 outb (byMIIIndex, byMIIAD); in ReadMII()
754 outb (inb (byMIICR) | 0x40, byMIICR); in ReadMII()
768 outb (byMIIAdrbak, byMIIAD); in ReadMII()
769 outb (byMIICRbak, byMIICR); in ReadMII()
789 outb (byMIICRbak & 0x7f, byMIICR); in WriteMII()
791 outb (byMIISetByte, byMIIAD); in WriteMII()
794 outb (inb (byMIICR) | 0x40, byMIICR); in WriteMII()
824 outb (inb (byMIICR) | 0x20, byMIICR); in WriteMII()
835 outb (byMIIAdrbak & 0x7f, byMIIAD); in WriteMII()
[all …]
H A Drtl8139.c206 outb(0x00, nic->ioaddr + Config1); in rtl8139_probe()
263 outb(EE_ENB & ~EE_CS, ee_addr); in read_eeprom()
264 outb(EE_ENB, ee_addr); in read_eeprom()
270 outb(EE_ENB | dataval, ee_addr); in read_eeprom()
272 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); in read_eeprom()
275 outb(EE_ENB, ee_addr); in read_eeprom()
279 outb(EE_ENB | EE_SHIFT_CLK, ee_addr); in read_eeprom()
282 outb(EE_ENB, ee_addr); in read_eeprom()
287 outb(~EE_CS, ee_addr); in read_eeprom()
314 outb(CmdReset, nic->ioaddr + ChipCmd); in rtl_reset()
[all …]
H A Di386_timer.c29 outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB); in __load_timer2()
31 outb(TIMER2_SEL|WORD_ACCESS|MODE0|BINARY_COUNT, TIMER_MODE_PORT); in __load_timer2()
33 outb(ticks & 0xFF, TIMER2_PORT); in __load_timer2()
35 outb(ticks >> 8, TIMER2_PORT); in __load_timer2()
/titanic_54/usr/src/uts/common/io/
H A Dpic.c42 (void) outb(MCMD_PORT, PIC_ICW1BASE|PIC_NEEDICW4); in picsetup()
45 (void) outb(MIMR_PORT, PIC_VECTBASE); in picsetup()
48 (void) outb(MIMR_PORT, 1 << MASTERLINE); in picsetup()
51 (void) outb(MIMR_PORT, PIC_86MODE); in picsetup()
54 (void) outb(MIMR_PORT, 0xFF); in picsetup()
57 (void) outb(MCMD_PORT, PIC_READISR); in picsetup()
61 (void) outb(SCMD_PORT, PIC_ICW1BASE|PIC_NEEDICW4); in picsetup()
64 outb(SIMR_PORT, PIC_VECTBASE + 8); in picsetup()
67 outb(SIMR_PORT, MASTERLINE); in picsetup()
70 outb(SIMR_PORT, PIC_86MODE); in picsetup()
[all …]
H A Di8237A.c195 outb(chan_addr[chnl].mask_reg, (chnl & 3) | DMA_SETMSK); in d37A_dma_disable()
214 outb(chan_addr[chnl].mask_reg, chnl & 3); in d37A_dma_enable()
297 outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM | EISA_CMOK); in dEISA_setchain()
302 outb(chan_addr[chnl].scm_reg, chnl); in dEISA_setchain()
389 outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM); in d37A_prog_chan()
472 outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM); in d37A_dma_swsetup()
496 outb(chan_addr[chnl].reqt_reg, DMA_SETMSK | chnl); /* set request bit */ in d37A_dma_swstart()
515 outb(chan_addr[chnl].reqt_reg, chnl & 3); /* reset request bit */ in d37A_dma_stop()
607 outb(chan_addr[chnl].mode_reg, mode); in d37A_set_mode()
645 outb(chan_addr[chnl].emode_reg, emode); in d37A_set_mode()
[all …]
/titanic_54/usr/src/grub/grub-0.97/stage2/
H A Dhercules.c40 outb (unsigned short port, unsigned char value) in outb() function
50 outb (HERCULES_INDEX_REG, 0x0f); in herc_set_cursor()
51 outb (0x80, 0); in herc_set_cursor()
52 outb (HERCULES_DATA_REG, offset & 0xFF); in herc_set_cursor()
53 outb (0x80, 0); in herc_set_cursor()
55 outb (HERCULES_INDEX_REG, 0x0e); in herc_set_cursor()
56 outb (0x80, 0); in herc_set_cursor()
57 outb (HERCULES_DATA_REG, offset >> 8); in herc_set_cursor()
58 outb (0x80, 0); in herc_set_cursor()
177 outb (HERCULES_INDEX_REG, 0x0a); in hercules_setcursor()
[all …]
H A Dserial.c81 outb (unsigned short port, unsigned char value) in outb() function
111 outb (serial_hw_port + UART_TX, c); in serial_hw_put()
117 outb (0x80, 0); in serial_hw_delay()
146 outb (port + UART_IER, 0); in serial_hw_init()
149 outb (port + UART_LCR, UART_DLAB); in serial_hw_init()
162 outb (port + UART_DLL, div & 0xFF); in serial_hw_init()
163 outb (port + UART_DLH, div >> 8); in serial_hw_init()
167 outb (port + UART_LCR, status); in serial_hw_init()
170 outb (port + UART_FCR, UART_ENABLE_FIFO); in serial_hw_init()
173 outb (port + UART_MCR, UART_ENABLE_MODEM); in serial_hw_init()
/titanic_54/usr/src/uts/i86pc/io/
H A Dtodpc_subr.c361 outb(RTC_ADDR, RTC_D); /* check if clock valid */ in todpc_rtcget()
369 outb(RTC_ADDR, RTC_A); /* check if update in progress */ in todpc_rtcget()
377 outb(RTC_ADDR, i); in todpc_rtcget()
380 outb(RTC_ADDR, century); /* do century */ in todpc_rtcget()
384 outb(RTC_ADDR, day_alrm); in todpc_rtcget()
388 outb(RTC_ADDR, mon_alrm); in todpc_rtcget()
392 outb(RTC_ADDR, 0); /* re-read Seconds register */ in todpc_rtcget()
422 outb(RTC_ADDR, RTC_B); in todpc_rtcput()
424 outb(RTC_ADDR, RTC_B); in todpc_rtcput()
425 outb(RTC_DATA, reg | RTC_SET); /* allow time set now */ in todpc_rtcput()
[all …]
H A Dmicrofind.c65 outb(PITCTL_PORT, PIT_C0 | PIT_LOADMODE | PIT_SQUAREMODE); in microfind_pit_reprogram_for_bios()
70 outb(PITCTR0_PORT, 0); in microfind_pit_reprogram_for_bios()
71 outb(PITCTR0_PORT, 0); in microfind_pit_reprogram_for_bios()
94 outb(PITCTL_PORT, PIT_LOADMODE); in microfind_pit_delta()
99 outb(PITCTR0_PORT, 0xff); in microfind_pit_delta()
100 outb(PITCTR0_PORT, 0xff); in microfind_pit_delta()
111 outb(PITCTL_PORT, PIT_READBACK | PIT_READBACKC0); in microfind_pit_delta()
/titanic_54/usr/src/uts/i86pc/ml/
H A Dcpr_wakecode.s287 outb (%dx)
293 outb (%dx)
316 outb (%dx)
322 outb (%dx)
333 outb (%dx)
339 outb (%dx)
357 outb (%dx)
363 outb (%dx)
388 outb (%dx)
394 outb (%dx)
[all …]
H A Dlocore.s371 outb $MCMD_PORT
383 outb $MIMR_PORT
435 outb $CYRIX_CRI
484 outb $CYRIX_CRI
487 outb $CYRIX_CRD
493 outb $CYRIX_CRI
501 outb $CYRIX_CRI
504 outb $CYRIX_CRD
519 outb $CYRIX_CRI
543 outb $CYRIX_CRI
[all …]
/titanic_54/usr/src/uts/i86pc/os/
H A Dpci_neptune.c61 outb(PCI_CSE_PORT, PCI_MECH2_CONFIG_ENABLE); in pci_check_neptune()
62 outb(PCI_FORW_PORT, 0); in pci_check_neptune()
76 outb(PCI_CSE_PORT, oldstatus); in pci_check_neptune()
81 outb(PCI_CSE_PORT, oldstatus); in pci_check_neptune()
101 outb(PCI_PMC, neptune_BIOS_cfg_method | 1); in pci_check_neptune()
107 outb(PCI_PMC, neptune_BIOS_cfg_method); in pci_check_neptune()
111 outb(PCI_PMC, neptune_BIOS_cfg_method); in pci_check_neptune()
122 outb(PCI_PMC, neptune_BIOS_cfg_method | 1); in pci_neptune_enable()
135 outb(PCI_PMC, neptune_BIOS_cfg_method); in pci_neptune_disable()
H A Dgraphics.c39 extern void outb(int, uchar_t);
58 outb(0x3c4, 2); in mapmask()
59 outb(0x3c5, plane); in mapmask()
65 outb(0x3ce, 8); in bitmask()
66 outb(0x3cf, value); in bitmask()
H A Dpci_mech2.c58 outb(PCI_CSE_PORT, in pci_mech2_config_enable()
60 outb(PCI_FORW_PORT, bus); in pci_mech2_config_enable()
68 outb(PCI_CSE_PORT, oldstatus); in pci_mech2_config_restore()
129 outb(PCI_CADDR2(device, reg), val); in pci_mech2_putb()
/titanic_54/usr/src/boot/sys/boot/common/
H A Disapnp.c41 #define outb(x,y) (archsw.arch_isaoutb((x),(y))) macro
63 outb (_PNP_ADDRESS, d); in isapnp_write()
64 outb (_PNP_WRITE_DATA, r); in isapnp_write()
77 outb(_PNP_ADDRESS, 0); in isapnp_send_Initiation_LFSR()
78 outb(_PNP_ADDRESS, 0); /* yes, we do need it twice! */ in isapnp_send_Initiation_LFSR()
81 outb(_PNP_ADDRESS, cur); in isapnp_send_Initiation_LFSR()
85 outb(_PNP_ADDRESS, cur); in isapnp_send_Initiation_LFSR()
98 outb(_PNP_ADDRESS, SERIAL_ISOLATION); in isapnp_get_serial()
132 outb(_PNP_ADDRESS, STATUS); in isapnp_get_resource_info()
142 outb(_PNP_ADDRESS, RESOURCE_DATA); in isapnp_get_resource_info()
[all …]
/titanic_54/usr/src/uts/i86pc/dboot/
H A Ddboot_asm.s41 outb(int port, uint8_t value)
71 ENTRY(outb)
74 outb (%dx)
76 SET_SIZE(outb)
118 ENTRY_NP(outb)
121 outb (%dx)
123 SET_SIZE(outb)
/titanic_54/usr/src/boot/sys/boot/i386/libi386/
H A Drelocater_tramp.S155 outb %al,$0x20 # master,
156 outb %al,$0xa0 # slave
158 outb %al,$0x21 # master
160 outb %al,$0xa1 # slave
162 outb %al,$0x21 # master
164 outb %al,$0xa1 # slave
166 outb %al,$0x21 # master,
167 outb %al,$0xa1 # slave
169 outb %al,$0xa1 # IMR
171 outb %al,$0x21 # IMR
[all …]
H A Dcomconsole.c246 outb(sp->ioaddr + com_data, (u_char)c); in comc_putchar()
574 outb(sp->ioaddr + com_cfcr, CFCR_DLAB | sp->lcr); in comc_setup()
575 outb(sp->ioaddr + com_dlbl, COMC_BPS(sp->speed) & 0xff); in comc_setup()
576 outb(sp->ioaddr + com_dlbh, COMC_BPS(sp->speed) >> 8); in comc_setup()
577 outb(sp->ioaddr + com_cfcr, sp->lcr); in comc_setup()
578 outb(sp->ioaddr + com_mcr, in comc_setup()
601 outb(sp->ioaddr + com_cfcr, CFCR_DLAB | cfcr); in comc_getspeed()
606 outb(sp->ioaddr + com_cfcr, cfcr); in comc_getspeed()
/titanic_54/usr/src/uts/i86pc/boot/
H A Dboot_console.c163 outb(port + ISR, 0x20); in serial_init()
168 outb(port + DAT+7, 0x04); /* clear status */ in serial_init()
169 outb(port + ISR, 0x40); /* set to bank 2 */ in serial_init()
170 outb(port + MCR, 0x08); /* IMD */ in serial_init()
171 outb(port + DAT, 0x21); /* FMD */ in serial_init()
172 outb(port + ISR, 0x00); /* set to bank 0 */ in serial_init()
180 outb(port + FIFOR, 0x00); /* clear */ in serial_init()
181 outb(port + FIFOR, FIFO_ON); /* enable */ in serial_init()
182 outb(port + FIFOR, FIFO_ON|FIFORXFLSH); /* reset */ in serial_init()
183 outb(port + FIFOR, in serial_init()
[all …]
H A Dboot_vga.c168 outb(VGA_COLOR_CRTC_INDEX, index); in vga_set_crtc()
169 outb(VGA_COLOR_CRTC_DATA, val); in vga_set_crtc()
175 outb(VGA_COLOR_CRTC_INDEX, index); in vga_get_crtc()
/titanic_54/usr/src/uts/intel/io/
H A Dpit_beep.c268 outb(PITCTL_PORT, PIT_C2 | PIT_READMODE | PIT_RATEMODE); in pit_beep_freq()
269 outb(PITCTR2_PORT, counter & 0xff); in pit_beep_freq()
270 outb(PITCTR2_PORT, counter >> 8); in pit_beep_freq()
278 outb(PITAUX_PORT, inb(PITAUX_PORT) | (PITAUX_OUT2 | PITAUX_GATE2)); in pit_beep_on()
286 outb(PITAUX_PORT, inb(PITAUX_PORT) & ~(PITAUX_OUT2 | PITAUX_GATE2)); in pit_beep_off()
/titanic_54/usr/src/uts/i86pc/io/psm/
H A Duppc.c268 outb(PITCTL_PORT, (PIT_C0|PIT_NDIVMODE|PIT_READMODE)); in uppc_clkinit()
269 outb(PITCTR0_PORT, (uchar_t)clkticks); in uppc_clkinit()
270 outb(PITCTR0_PORT, (uchar_t)(clkticks>>8)); in uppc_clkinit()
575 outb(SIMR_PORT, sp->smask); in pic_restore_state()
576 outb(MIMR_PORT, sp->mmask); in pic_restore_state()
965 outb(MCMD_PORT, PIC_NSEOI); in uppc_intr_enter()
967 outb(SCMD_PORT, PIC_NSEOI); in uppc_intr_enter()
972 outb(MCMD_PORT, PIC_NSEOI); in uppc_intr_enter()
978 outb(MCMD_PORT, PIC_NSEOI); in uppc_intr_enter()
979 outb(SCMD_PORT, PIC_SEOI_LVL7); in uppc_intr_enter()
[all …]
/titanic_54/usr/src/boot/sys/boot/i386/gptzfsboot/
H A Dsio.S32 outb %al,(%dx) # and DLAB
38 outb %al,(%dx) # DLAB
41 outb %al,(%dx) # DTR
67 outb %al,(%dx) # Write character
/titanic_54/usr/src/uts/i86pc/io/pcplusmp/
H A Dapic_common.c449 outb(CMOS_ADDR, SSB); in apic_cpu_send_SIPI()
450 outb(CMOS_DATA, BIOS_SHUTDOWN); in apic_cpu_send_SIPI()
1186 outb(CMOS_ADDR, SSB); in apic_shutdown()
1187 outb(CMOS_DATA, 0); in apic_shutdown()
1194 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); in apic_shutdown()
1195 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_PIC); in apic_shutdown()
1228 outb(CMOS_ADDR, RTC_REGA); in apic_shutdown()
1230 outb(CMOS_DATA, (byte | EXT_BANK)); in apic_shutdown()
1232 outb(CMOS_ADDR, PFR_REG); in apic_shutdown()
1242 outb(CMOS_DATA, byte); in apic_shutdown()
[all …]

1234