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Searched refs:uint32_t (Results 1 – 25 of 2537) sorted by relevance

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/titanic_52/usr/src/uts/common/sys/ib/adapters/hermon/
H A Dhermon_hw.h106 uint32_t in_param0;
107 uint32_t in_param1;
108 uint32_t input_modifier;
109 uint32_t out_param0;
110 uint32_t out_param1;
111 uint32_t token;
112 uint32_t cmd;
139 uint32_t rsrv0[4];
141 uint32_t log_max_scqs :4;
142 uint32_t
3914 uint32_t uint32_t :8; global() member
3943 uint32_t uint32_t :8; global() member
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/titanic_52/usr/src/uts/common/io/hxge/
H A Dhxge_peu_hw.h198 uint32_t value;
201 uint32_t device_id:16;
202 uint32_t vendor_id:16;
204 uint32_t vendor_id:16;
205 uint32_t device_id:16;
255 uint32_t value;
258 uint32_t det_par_err:1;
259 uint32_t sig_serr:1;
260 uint32_t rcv_mstr_abrt:1;
261 uint32_t rcv_tgt_abr
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H A Dhxge_rdc_hw.h97 uint32_t rsrvd:32;
98 uint32_t rsrvd_l:12;
99 uint32_t handle:20;
101 uint32_t handle:20;
102 uint32_t rsrvd_l:12;
103 uint32_t rsrvd:32;
144 uint32_t rsrvd:32;
145 uint32_t enable:1;
146 uint32_t reset:1;
147 uint32_t qs
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H A Dhxge_tdc_hw.h89 uint32_t rsrvd:32;
90 uint32_t rsrvd_l:12;
91 uint32_t page_handle:20;
93 uint32_t page_handle:20;
94 uint32_t rsrvd_l:12;
95 uint32_t rsrvd:32;
150 uint32_t len:11;
151 uint32_t rsrvd:5;
152 uint32_t enable:1;
153 uint32_t rese
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H A Dhxge_vmac_hw.h72 uint32_t rsrvd:32;
73 uint32_t rsrvd_l:23;
74 uint32_t rx_reset:1;
75 uint32_t rsrvd1:7;
76 uint32_t tx_reset:1;
78 uint32_t tx_reset:1;
79 uint32_t rsrvd1:7;
80 uint32_t rx_reset:1;
81 uint32_t rsrvd_l:23;
82 uint32_t rsrv
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H A Dhxge_pfc_hw.h83 uint32_t rsrvd:28;
84 uint32_t parity:4;
85 uint32_t member:32;
87 uint32_t member:32;
88 uint32_t parity:4;
89 uint32_t rsrvd:28;
113 uint32_t rsrvd:32;
114 uint32_t rsrvd_l:18;
115 uint32_t par_en:1;
116 uint32_t vali
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/titanic_52/usr/src/uts/common/sys/ib/adapters/tavor/
H A Dtavor_hw.h89 uint32_t in_param0;
90 uint32_t in_param1;
91 uint32_t input_modifier;
92 uint32_t out_param0;
93 uint32_t out_param1;
94 uint32_t token;
95 uint32_t cmd;
120 uint32_t rsrv0[4];
121 uint32_t log_max_ee :5;
122 uint32_t
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/titanic_52/usr/src/uts/common/io/nge/
H A Dnge_chip.h57 uint32_t conf_val;
59 uint32_t unit_id:5;
60 uint32_t resv5_23:19;
61 uint32_t aux_val:3;
62 uint32_t resv27:1;
63 uint32_t msi_off:1;
64 uint32_t msix_off:1; /* mcp55 only */
65 uint32_t resv30_31:2;
73 uint32_t msi_mask_conf_val;
75 uint32_t vec0_of
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/titanic_52/usr/src/uts/common/sys/fibre-channel/fca/oce/
H A Doce_hw_eth.h86 uint32_t rsvd0;
89 uint32_t last_seg_udp_len:14;
90 uint32_t rsvd1:18;
93 uint32_t lso_mss:14;
94 uint32_t num_wqe:5;
95 uint32_t rsvd4:2;
96 uint32_t vlan:1;
97 uint32_t lso:1;
98 uint32_t tcpcs:1;
99 uint32_t udpc
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H A Doce_hw.h160 uint32_t lo;
162 uint32_t hi;
166 uint32_t dw0;
169 uint32_t winselect:2;
170 uint32_t hostintr:1;
171 uint32_t pfnum:3;
172 uint32_t vf_cev_int_line_en:1;
173 uint32_t winaddr:23;
174 uint32_t membarwinen:1;
176 uint32_t membarwine
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/titanic_52/usr/src/uts/intel/sys/
H A Dmc_amd.h308 uint32_t _val32;
310 uint32_t RQRte:4; /* 3:0 */
311 uint32_t reserved1:4; /* 7:4 */
312 uint32_t RPRte:4; /* 11:8 */
313 uint32_t reserved2:4; /* 15:12 */
314 uint32_t BCRte:4; /* 19:16 */
315 uint32_t reserved3:12; /* 31:20 */
323 uint32_t _val32;
325 uint32_t NodeId:3; /* 2:0 */
326 uint32_t reserved
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/titanic_52/usr/src/uts/common/sys/fibre-channel/fca/emlxs/
H A Demlxs_mbox.h239 uint32_t ldflag:1; /* Set in SRAM descriptor */
240 uint32_t ldcount:7; /* For use by program load */
241 uint32_t kernel:4; /* Kernel ID */
242 uint32_t kver:4; /* Kernel compatibility version */
243 uint32_t SMver:4; /* Sequence Manager version */
245 uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */
246 uint32_t BIUtype:4; /* PCI = 0 */
247 uint32_t BIUver:4; /* BIU version, 0 if none */
250 uint32_t BIUver:4; /* BIU version, 0 if none */
251 uint32_t BIUtyp
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H A Demlxs_queue.h41 uint32_t CQId: 16;
42 uint32_t MinorCode: 12;
43 uint32_t MajorCode: 3;
44 uint32_t Valid: 1;
47 uint32_t Valid: 1;
48 uint32_t MajorCode: 3;
49 uint32_t MinorCode: 12;
50 uint32_t CQId: 16;
57 uint32_t word;
73 uint32_t CmdSpecifi
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/titanic_52/usr/src/uts/common/sys/nxge/
H A Dnxge_txdma_hw.h77 uint32_t hdw;
81 uint32_t res1_1:31;
82 uint32_t mode32:1;
84 uint32_t mode32:1;
85 uint32_t res1_1:31;
89 uint32_t hdw;
114 uint32_t sop:1;
115 uint32_t mark:1;
116 uint32_t num_ptr:4;
117 uint32_t res
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H A Dnxge_zcp_hw.h81 uint32_t hdw;
85 uint32_t rsrvd:28;
86 uint32_t reset_cfifo3:1;
87 uint32_t reset_cfifo2:1;
88 uint32_t reset_cfifo1:1;
89 uint32_t reset_cfifo0:1;
91 uint32_t reset_cfifo0:1;
92 uint32_t reset_cfifo1:1;
93 uint32_t reset_cfifo2:1;
94 uint32_t reset_cfifo
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H A Dnxge_rxdma_hw.h48 uint32_t hdw;
52 uint32_t res1_1:16;
53 uint32_t cnt:16;
55 uint32_t cnt:16;
56 uint32_t res1_1:16;
60 uint32_t hdw;
87 uint32_t hdw;
91 uint32_t res1_1:27;
92 uint32_t rdc:5;
94 uint32_t rd
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H A Dnxge_txc_hw.h47 uint32_t hdw;
51 uint32_t res:8;
52 uint32_t port_dma_list:24;
54 uint32_t port_dma_list:24;
55 uint32_t res:8;
59 uint32_t hdw;
68 uint32_t hdw;
72 uint32_t res:16;
73 uint32_t port_dma_list:16;
75 uint32_t port_dma_lis
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H A Dnxge_fflp_hw.h69 uint32_t hdw;
73 uint32_t rsrvd:14;
74 uint32_t parity1:1;
75 uint32_t parity0:1;
76 uint32_t vpr3:1;
77 uint32_t vlanrdctbln3:3;
78 uint32_t vpr2:1;
79 uint32_t vlanrdctbln2:3;
80 uint32_t vpr1:1;
81 uint32_t vlanrdctbln
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H A Dnxge_mac_hw.h305 uint32_t msw; /* Most significant word */
306 uint32_t lsw; /* Least significant word */
308 uint32_t lsw; /* Least significant word */
309 uint32_t msw; /* Most significant word */
314 uint32_t w1;
318 uint32_t rsrvd : 22;
319 uint32_t hdx_ctrl2 : 1;
320 uint32_t no_fcs : 1;
321 uint32_t hdx_ctrl : 7;
322 uint32_t txmac_enabl
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H A Dnxge_hw.h62 typedef uint32_t dc_map_t;
67 typedef uint32_t lg_map_t;
92 uint32_t hdw;
96 uint32_t tas:1;
97 uint32_t res2:13;
98 uint32_t funcid:2;
99 uint32_t sr:16;
101 uint32_t sr:16;
102 uint32_t funcid:2;
103 uint32_t res
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/titanic_52/usr/src/uts/sun4u/sys/
H A Dsbbcreg.h41 uint32_t pad[3];
48 uint32_t devid; /* 0x0.0000 All, device ID */
50 uint32_t devtemp; /* 0x0.0010 All */
52 uint32_t incon_scratch; /* 0x0.0020 All */
54 uint32_t incon_tstl1; /* 0x0.0030 AR and SDC */
56 uint32_t incon_tsterr; /* 0x0.0040 AR and SDC */
58 uint32_t device_conf; /* 0x0.0050 All, device configuration */
60 uint32_t device_rstcntl; /* 0x0.0060 SBBC,AR,dev reset control */
62 uint32_t device_rststat; /* 0x0.0070 All, device reset status */
64 uint32_t device_errsta
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/titanic_52/usr/src/uts/common/io/iwk/
H A Diwk_calibration.h380 uint32_t dw;
673 uint32_t tx_on_a;
674 uint32_t tx_on_b;
675 uint32_t exec_time;
676 uint32_t probe_time;
677 uint32_t reserved1;
678 uint32_t reserved2;
682 uint32_t burst_check;
683 uint32_t burst_count;
684 uint32_t reserve
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/titanic_52/usr/src/uts/common/sys/
H A Dmd5_consts.h38 #define MD5_CONST_0 (uint32_t)0xd76aa478
39 #define MD5_CONST_1 (uint32_t)0xe8c7b756
40 #define MD5_CONST_2 (uint32_t)0x242070db
41 #define MD5_CONST_3 (uint32_t)0xc1bdceee
42 #define MD5_CONST_4 (uint32_t)0xf57c0faf
43 #define MD5_CONST_5 (uint32_t)0x4787c62a
44 #define MD5_CONST_6 (uint32_t)0xa8304613
45 #define MD5_CONST_7 (uint32_t)0xfd469501
46 #define MD5_CONST_8 (uint32_t)0x698098d8
47 #define MD5_CONST_9 (uint32_t)
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/titanic_52/usr/src/common/bignum/i386/
H A Dbignum_i386.c48 extern uint32_t big_mul_set_vec_sse2(uint32_t *, uint32_t *, int, uint32_t);
49 extern uint32_t big_mul_add_vec_sse2(uint32_t *, uint32_t *, int, uint32_t);
50 extern void big_mul_vec_sse2(uint32_t *, uint32_t *, in
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/titanic_52/usr/src/uts/common/sys/ib/clients/of/rdma/
H A Dib_user_verbs.h121 uint32_t event_type; /* enum ib_event_type */
122 uint32_t reserved;
130 * All commands from userspace should start with a uint32_t command field
138 uint32_t command;
149 uint32_t async_fd;
150 uint32_t num_comp_vectors;
164 uint32_t vendor_id;
165 uint32_t vendor_part_id;
166 uint32_t hw_ver;
167 uint32_t max_q
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