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Searched refs:reg (Results 1 – 25 of 810) sorted by relevance

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/titanic_51/usr/src/uts/common/io/
H A Dvgasubr.c79 vga_get_hardware_settings(struct vgaregmap *reg, int *width, int *height) in vga_get_hardware_settings() argument
81 *width = (GET_HORIZ_END(reg)+1)*8; in vga_get_hardware_settings()
82 *height = GET_VERT_END(reg)+1; in vga_get_hardware_settings()
83 if (GET_VERT_X2(reg)) *height *= 2; in vga_get_hardware_settings()
86 #define PUTB(reg, off, v) ddi_put8(reg->handle, reg->addr + (off), v) argument
87 #define GETB(reg, off) ddi_get8(reg->handle, reg argument
90 vga_get_reg(struct vgaregmap * reg,int indexreg) vga_get_reg() argument
96 vga_set_reg(struct vgaregmap * reg,int indexreg,int v) vga_set_reg() argument
102 vga_get_crtc(struct vgaregmap * reg,int i) vga_get_crtc() argument
108 vga_set_crtc(struct vgaregmap * reg,int i,int v) vga_set_crtc() argument
114 vga_get_seq(struct vgaregmap * reg,int i) vga_get_seq() argument
120 vga_set_seq(struct vgaregmap * reg,int i,int v) vga_set_seq() argument
126 vga_get_grc(struct vgaregmap * reg,int i) vga_get_grc() argument
132 vga_set_grc(struct vgaregmap * reg,int i,int v) vga_set_grc() argument
138 vga_get_atr(struct vgaregmap * reg,int i) vga_get_atr() argument
153 vga_set_atr(struct vgaregmap * reg,int i,int v) vga_set_atr() argument
165 vga_set_indexed(struct vgaregmap * reg,int indexreg,int datareg,unsigned char index,unsigned char val) vga_set_indexed() argument
177 vga_get_indexed(struct vgaregmap * reg,int indexreg,int datareg,unsigned char index) vga_get_indexed() argument
193 vga_put_cmap(struct vgaregmap * reg,int index,unsigned char r,unsigned char g,unsigned char b) vga_put_cmap() argument
208 vga_get_cmap(struct vgaregmap * reg,int index,unsigned char * r,unsigned char * g,unsigned char * b) vga_get_cmap() argument
223 vga_dump_regs(struct vgaregmap * reg,int maxseq,int maxcrtc,int maxatr,int maxgrc) vga_dump_regs() argument
[all...]
H A Dsock_conf.c71 smod_register(const smod_reg_t *reg) in smod_register() argument
79 if (reg->smod_version != SOCKMOD_VERSION || in smod_register()
80 reg->smod_dc_version != SOCK_DC_VERSION || in smod_register()
81 reg->smod_uc_version != SOCK_UC_VERSION) { in smod_register()
84 reg->smod_name); in smod_register()
90 if ((smodp = smod_find(reg->smod_name)) != NULL) { in smod_register()
97 smodp = smod_create(reg->smod_name); in smod_register()
98 smodp->smod_version = reg->smod_version; in smod_register()
103 ASSERT(reg->__smod_priv != NULL); in smod_register()
105 reg in smod_register()
[all...]
/titanic_51/usr/src/uts/intel/io/intel_nhm/
H A Dintel_nhm.h62 #define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \ argument
63 0x4c, reg);
65 #define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \ argument
66 reg);
102 #define MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \ argument
103 ((reg) & (1 << (8 + (channel))) != 0)
104 #define MC_CONTROL_ECCEN(reg) (((reg) >> 1) & 1) argument
105 #define MC_CONTROL_CLOSED_PAGE(reg) ((reg) argument
106 MC_CONTROL_DIVBY3(reg) global() argument
113 CHANNEL_DISABLED(reg,channel) global() argument
126 RANKOFFSET(reg) global() argument
127 DIMMPRESENT(reg) global() argument
128 NUMBANK(reg) global() argument
129 NUMRANK(reg) global() argument
130 NUMROW(reg) global() argument
131 NUMCOL(reg) global() argument
133 DIMMSIZE(reg) global() argument
139 DIVBY3(reg) global() argument
140 REMOVE_6(reg) global() argument
141 REMOVE_7(reg) global() argument
142 REMOVE_8(reg) global() argument
143 CH_ADDRESS_OFFSET(reg) global() argument
145 CH_ADDRESS_SOFFSET(reg) global() argument
158 RIR_LIMIT(reg) global() argument
162 RIR_OFFSET(reg) global() argument
163 RIR_SOFFSET(reg) global() argument
165 RIR_DIMM_RANK(reg) global() argument
166 RIR_RANK(reg) global() argument
167 RIR_DIMM(reg) global() argument
182 RAS_LOCKSTEP_ENABLE(reg) global() argument
183 RAS_MIRROR_MEM_ENABLE(reg) global() argument
187 REDUNDANCY_LOSS(reg) global() argument
191 SPAREING_IN_PROGRESS(reg) global() argument
192 SPAREING_COMPLETE(reg) global() argument
197 SSR_MODE(reg) global() argument
209 MAX_DIMM_CLK_RATIO(reg) global() argument
311 CHANNEL_MAP(reg,channel,write) global() argument
[all...]
H A Dnhm_pci_cfg.c45 pci_regspec_t reg; in nhm_pci_cfg_setup() local
48 reg.pci_phys_mid = 0; in nhm_pci_cfg_setup()
49 reg.pci_phys_low = 0; in nhm_pci_cfg_setup()
50 reg.pci_size_hi = 0; in nhm_pci_cfg_setup()
51 reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */ in nhm_pci_cfg_setup()
55 reg.pci_phys_hi = ((SOCKET_BUS(i)) in nhm_pci_cfg_setup()
60 DDI_MAJOR_T_UNKNOWN, dip, "reg", in nhm_pci_cfg_setup()
61 (int *)&reg, sizeof (reg)/sizeof (int)) != in nhm_pci_cfg_setup()
64 "cannot create reg propert in nhm_pci_cfg_setup()
108 nhm_pci_getb(int bus,int dev,int func,int reg,int * interpose) nhm_pci_getb() argument
117 nhm_pci_getw(int bus,int dev,int func,int reg,int * interpose) nhm_pci_getw() argument
126 nhm_pci_getl(int bus,int dev,int func,int reg,int * interpose) nhm_pci_getl() argument
135 nhm_pci_putb(int bus,int dev,int func,int reg,uint8_t val) nhm_pci_putb() argument
144 nhm_pci_putw(int bus,int dev,int func,int reg,uint16_t val) nhm_pci_putw() argument
153 nhm_pci_putl(int bus,int dev,int func,int reg,uint32_t val) nhm_pci_putl() argument
[all...]
/titanic_51/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_dcb_82599.c121 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599() local
130 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82599()
131 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); in ixgbe_dcb_config_rx_arbiter_82599()
139 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599()
141 reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); in ixgbe_dcb_config_rx_arbiter_82599()
143 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); in ixgbe_dcb_config_rx_arbiter_82599()
149 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82599()
151 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; in ixgbe_dcb_config_rx_arbiter_82599()
154 reg |= IXGBE_RTRPT4C_LSP; in ixgbe_dcb_config_rx_arbiter_82599()
156 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); in ixgbe_dcb_config_rx_arbiter_82599()
179 u32 reg, max_credits; ixgbe_dcb_config_tx_desc_arbiter_82599() local
225 u32 reg; ixgbe_dcb_config_tx_data_arbiter_82599() local
285 u32 i, j, fcrtl, reg; ixgbe_dcb_config_pfc_82599() local
372 u32 reg = 0; ixgbe_dcb_config_tc_stats_82599() local
498 u32 reg; ixgbe_dcb_config_82599() local
[all...]
H A Dixgbe_dcb_82598.c121 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
126 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598()
127 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598()
129 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598()
131 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598()
133 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598()
135 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598()
137 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598()
144 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598()
147 reg | in ixgbe_dcb_config_rx_arbiter_82598()
177 u32 reg, max_credits; ixgbe_dcb_config_tx_desc_arbiter_82598() local
221 u32 reg; ixgbe_dcb_config_tx_data_arbiter_82598() local
264 u32 fcrtl, reg; ixgbe_dcb_config_pfc_82598() local
316 u32 reg = 0; ixgbe_dcb_config_tc_stats_82598() local
[all...]
/titanic_51/usr/src/uts/common/io/mii/
H A Dmii_marvell.c151 uint16_t reg; in mvphy_reset_88e3016() local
156 reg = phy_read(ph, MVPHY_PSC); in mvphy_reset_88e3016()
158 reg |= MV_PSC_AUTO_MDIX; in mvphy_reset_88e3016()
159 reg &= ~(MV_PSC_EN_DETECT | MV_PSC_DIS_SCRAMBLER); in mvphy_reset_88e3016()
160 reg |= MV_PSC_LPNP; in mvphy_reset_88e3016()
165 phy_write(ph, MVPHY_PSC, reg); in mvphy_reset_88e3016()
184 uint16_t reg; in mvphy_loop_88e3016() local
193 reg = phy_read(ph, MII_CONTROL); in mvphy_loop_88e3016()
194 reg |= MII_CONTROL_RESET; in mvphy_loop_88e3016()
195 phy_write(ph, MII_CONTROL, reg); in mvphy_loop_88e3016()
210 uint16_t reg; mvphy_reset_88e3082() local
227 uint16_t reg; mvphy_reset_88e1149() local
289 uint16_t reg; mvphy_reset_88e1116() local
324 uint16_t reg; mvphy_reset_88e1118() local
340 uint16_t reg; mvphy_reset_88e1111() local
362 uint16_t reg, page; mvphy_reset_88e1112() local
397 uint16_t reg; mvphy_reset_88e1011() local
420 uint16_t reg; mvphy_reset() local
[all...]
/titanic_51/usr/src/uts/common/io/i40e/
H A Di40e_intr.c213 uint32_t reg; in i40e_intr_adminq_enable() local
215 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | in i40e_intr_adminq_enable()
218 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg); in i40e_intr_adminq_enable()
226 uint32_t reg; in i40e_intr_adminq_disable() local
228 reg = I40E_ITR_INDEX_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; in i40e_intr_adminq_disable()
229 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg); in i40e_intr_adminq_disable()
242 uint32_t reg; in i40e_intr_io_enable() local
246 reg = I40E_PFINT_DYN_CTLN_INTENA_MASK | in i40e_intr_io_enable()
249 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vector - 1), reg); in i40e_intr_io_enable()
255 uint32_t reg; in i40e_intr_io_disable() local
278 uint32_t reg; i40e_intr_io_enable_all() local
306 uint32_t reg; i40e_intr_io_disable_all() local
333 uint32_t reg; i40e_intr_io_clear_cause() local
340 uint32_t reg; i40e_intr_io_clear_cause() local
357 uint32_t reg; i40e_intr_chip_fini() local
387 uint32_t reg; i40e_set_lnklstn() local
406 uint32_t reg; i40e_set_rqctl() local
428 uint32_t reg; i40e_set_tqctl() local
495 uint32_t reg; i40e_intr_init_queue_shared() local
529 uint32_t reg; i40e_intr_rx_queue_enable() local
550 uint32_t reg; i40e_intr_rx_queue_disable() local
573 uint32_t reg; i40e_intr_chip_init() local
701 uint32_t reg; i40e_intr_other_work() local
777 uint32_t reg; i40e_intr_notx() local
[all...]
/titanic_51/usr/src/uts/intel/io/intel_nb5000/
H A Dnb_pci_cfg.c49 pci_regspec_t reg; in nb_pci_cfg_setup() local
52 reg.pci_phys_hi = 16 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=16, Func=0 */ in nb_pci_cfg_setup()
53 reg.pci_phys_mid = 0; in nb_pci_cfg_setup()
54 reg.pci_phys_low = 0; in nb_pci_cfg_setup()
55 reg.pci_size_hi = 0; in nb_pci_cfg_setup()
56 reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */ in nb_pci_cfg_setup()
59 if (ddi_prop_update_int_array(DDI_MAJOR_T_UNKNOWN, dip, "reg", in nb_pci_cfg_setup()
60 (int *)&reg, sizeof (reg)/sizeof (int)) != DDI_PROP_SUCCESS) in nb_pci_cfg_setup()
62 "nb_pci_cfg_setup: cannot create reg propert in nb_pci_cfg_setup()
149 nb_pci_getb(int bus,int dev,int func,int reg,int * interpose) nb_pci_getb() argument
158 nb_pci_getw(int bus,int dev,int func,int reg,int * interpose) nb_pci_getw() argument
167 nb_pci_getl(int bus,int dev,int func,int reg,int * interpose) nb_pci_getl() argument
176 nb_pci_putb(int bus,int dev,int func,int reg,uint8_t val) nb_pci_putb() argument
185 nb_pci_putw(int bus,int dev,int func,int reg,uint16_t val) nb_pci_putw() argument
194 nb_pci_putl(int bus,int dev,int func,int reg,uint32_t val) nb_pci_putl() argument
[all...]
/titanic_51/usr/src/uts/i86pc/sys/
H A Dpci_cfgspace_impl.h41 extern uint8_t pci_mech1_getb(int bus, int dev, int func, int reg);
42 extern uint16_t pci_mech1_getw(int bus, int dev, int func, int reg);
43 extern uint32_t pci_mech1_getl(int bus, int dev, int func, int reg);
44 extern void pci_mech1_putb(int bus, int dev, int func, int reg, uint8_t val);
45 extern void pci_mech1_putw(int bus, int dev, int func, int reg, uint16_t val);
46 extern void pci_mech1_putl(int bus, int dev, int func, int reg, uint32_t val);
52 extern uint8_t pci_mech1_amd_getb(int bus, int dev, int func, int reg);
53 extern uint16_t pci_mech1_amd_getw(int bus, int dev, int func, int reg);
54 extern uint32_t pci_mech1_amd_getl(int bus, int dev, int func, int reg);
55 extern void pci_mech1_amd_putb(int bus, int dev, int func, int reg,
[all...]
/titanic_51/usr/src/uts/common/io/cxgbe/t4nex/
H A Dadapter.c26 t4_read_reg(struct adapter *sc, uint32_t reg) in t4_read_reg() argument
29 return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg))); in t4_read_reg()
33 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) in t4_write_reg() argument
36 ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val); in t4_write_reg()
40 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) in t4_os_pci_read_cfg1() argument
42 *val = pci_config_get8(sc->pci_regh, reg); in t4_os_pci_read_cfg1()
46 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) in t4_os_pci_write_cfg1() argument
48 pci_config_put8(sc->pci_regh, reg, val); in t4_os_pci_write_cfg1()
52 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) in t4_os_pci_read_cfg2() argument
54 *val = pci_config_get16(sc->pci_regh, reg); in t4_os_pci_read_cfg2()
58 t4_os_pci_write_cfg2(struct adapter * sc,int reg,uint16_t val) t4_os_pci_write_cfg2() argument
64 t4_os_pci_read_cfg4(struct adapter * sc,int reg,uint32_t * val) t4_os_pci_read_cfg4() argument
70 t4_os_pci_write_cfg4(struct adapter * sc,int reg,uint32_t val) t4_os_pci_write_cfg4() argument
76 t4_read_reg64(struct adapter * sc,uint32_t reg) t4_read_reg64() argument
83 t4_write_reg64(struct adapter * sc,uint32_t reg,uint64_t val) t4_write_reg64() argument
[all...]
/titanic_51/usr/src/uts/common/io/audio/drv/audio1575/
H A Daudio1575.h395 #define GET8(reg) \ argument
396 ddi_get8(statep->regsh, (void *)(statep->regsp + (reg)))
398 #define GET16(reg) \ argument
399 ddi_get16(statep->regsh, (void *)(statep->regsp + (reg)))
401 #define GET32(reg) \ argument
402 ddi_get32(statep->regsh, (void *)(statep->regsp + (reg)))
404 #define PUT8(reg, val) \ argument
405 ddi_put8(statep->regsh, (void *)(statep->regsp + (reg)), (val))
407 #define PUT16(reg, val) \ argument
408 ddi_put16(statep->regsh, (void *)(statep->regsp + (reg)), (va
410 PUT32(reg,val) global() argument
413 SET8(reg,bit) global() argument
414 SET16(reg,bit) global() argument
415 SET32(reg,bit) global() argument
416 CLR8(reg,bit) global() argument
417 CLR16(reg,bit) global() argument
418 CLR32(reg,bit) global() argument
[all...]
/titanic_51/usr/src/uts/common/sys/
H A Dvgasubr.h42 extern int vga_get_reg(struct vgaregmap *reg, int i);
43 extern void vga_set_reg(struct vgaregmap *reg, int i, int v);
44 extern int vga_get_crtc(struct vgaregmap *reg, int i);
45 extern void vga_set_crtc(struct vgaregmap *reg, int i, int v);
46 extern int vga_get_seq(struct vgaregmap *reg, int i);
47 extern void vga_set_seq(struct vgaregmap *reg, int i, int v);
48 extern int vga_get_grc(struct vgaregmap *reg, int i);
49 extern void vga_set_grc(struct vgaregmap *reg, int i, int v);
50 extern int vga_get_atr(struct vgaregmap *reg, int i);
51 extern void vga_set_atr(struct vgaregmap *reg, in
[all...]
/titanic_51/usr/src/cmd/rcm_daemon/common/
H A Dmpxio_rcm.c163 phci_list_t *reg; in rcm_mod_fini() local
172 reg = reg_list; in rcm_mod_fini()
173 while (reg) { in rcm_mod_fini()
174 next = reg->next; in rcm_mod_fini()
175 free(reg->phci.path); in rcm_mod_fini()
176 free(reg); in rcm_mod_fini()
177 reg = next; in rcm_mod_fini()
245 phci_list_t *reg; in mpxio_unregister() local
251 for (reg = reg_list; reg ! in mpxio_unregister()
274 phci_list_t *reg; mpxio_getinfo() local
514 phci_list_t *reg; lookup_phci() local
656 phci_list_t *reg; refresh_regs() local
[all...]
/titanic_51/usr/src/uts/i86pc/os/
H A Dpci_mech1.c41 * 5.3.1.2: dev=31 func=7 reg=0 means a special cycle. We don't want to
48 pci_mech1_getb(int bus, int device, int function, int reg) in pci_mech1_getb() argument
57 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_getb()
58 val = inb(PCI_CONFDATA | (reg & 0x3)); in pci_mech1_getb()
64 pci_mech1_getw(int bus, int device, int function, int reg) in pci_mech1_getw() argument
74 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_getw()
75 val = inw(PCI_CONFDATA | (reg & 0x2)); in pci_mech1_getw()
81 pci_mech1_getl(int bus, int device, int function, int reg) in pci_mech1_getl() argument
91 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_getl()
98 pci_mech1_putb(int bus, int device, int function, int reg, uint8_ argument
112 pci_mech1_putw(int bus,int device,int function,int reg,uint16_t val) pci_mech1_putw() argument
126 pci_mech1_putl(int bus,int device,int function,int reg,uint32_t val) pci_mech1_putl() argument
[all...]
/titanic_51/usr/src/cmd/fm/modules/common/fabric-xlate/
H A Dfx_fire.c42 * <pci error status reg>
43 * <pci bridge status reg>
139 uint64_t reg; in fab_xlate_fire_ce() local
155 if (nvlist_lookup_uint64(erpt, "tlu-cess", &reg) == 0) { in fab_xlate_fire_ce()
156 data->pcie_ce_status = (uint32_t)reg | (uint32_t)(reg >> 32); in fab_xlate_fire_ce()
167 uint64_t reg; in fab_xlate_fire_ue() local
195 if (nvlist_lookup_uint64(erpt, "tlu-uess", &reg) == 0) { in fab_xlate_fire_ue()
196 data->pcie_ue_status = (uint32_t)reg | (uint32_t)(reg >> 3 in fab_xlate_fire_ue()
258 uint64_t reg; fab_xlate_fire_oe() local
319 uint64_t reg; fab_xlate_fire_dmc() local
[all...]
/titanic_51/usr/src/lib/libc/sparc/gen/
H A Dmakectxt.c57 greg_t *reg; in makecontext() local
64 reg = ucp->uc_mcontext.gregs; in makecontext()
65 reg[REG_PC] = (greg_t)func; in makecontext()
66 reg[REG_nPC] = reg[REG_PC] + 0x4; in makecontext()
96 *tsp++ = reg[REG_O0 + argno] = va_arg(ap, long); in makecontext()
103 reg[REG_SP] = (greg_t)sp - STACK_BIAS; /* sp (when done) */ in makecontext()
104 reg[REG_O7] = (greg_t)resumecontext - 8; /* return pc */ in makecontext()
110 greg_t *reg; in __makecontext_v2() local
117 reg in __makecontext_v2()
[all...]
/titanic_51/usr/src/lib/libc/sparcv9/gen/
H A Dmakectxt.c57 greg_t *reg; in makecontext() local
64 reg = ucp->uc_mcontext.gregs; in makecontext()
65 reg[REG_PC] = (greg_t)func; in makecontext()
66 reg[REG_nPC] = reg[REG_PC] + 0x4; in makecontext()
96 *tsp++ = reg[REG_O0 + argno] = va_arg(ap, long); in makecontext()
103 reg[REG_SP] = (greg_t)sp - STACK_BIAS; /* sp (when done) */ in makecontext()
104 reg[REG_O7] = (greg_t)resumecontext - 8; /* return pc */ in makecontext()
110 greg_t *reg; in __makecontext_v2() local
117 reg in __makecontext_v2()
[all...]
/titanic_51/usr/src/uts/common/io/igb/
H A De1000_osdep.h113 #define E1000_WRITE_REG(hw, reg, value) \ argument
115 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), (value))
117 #define E1000_READ_REG(hw, reg) \ argument
119 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg))
121 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ argument
123 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)), \
126 #define E1000_READ_REG_ARRAY(hw, reg, offset) \ argument
128 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)))
130 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \ argument
131 E1000_WRITE_REG_ARRAY(a, reg, offse
132 E1000_READ_REG_ARRAY_DWORD(a,reg,offset) global() argument
136 E1000_READ_FLASH_REG(hw,reg) global() argument
140 E1000_READ_FLASH_REG16(hw,reg) global() argument
144 E1000_WRITE_FLASH_REG(hw,reg,value) global() argument
148 E1000_WRITE_FLASH_REG16(hw,reg,value) global() argument
200 E1000_WRITE_REG_IO(a,reg,val) global() argument
[all...]
/titanic_51/usr/src/uts/common/io/e1000g/
H A De1000_osdep.h123 #define E1000_WRITE_REG(hw, reg, value) \ argument
127 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), \
132 e1000_translate_register_82542(reg)), \
136 #define E1000_READ_REG(hw, reg) (\ argument
139 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg)) : \
142 e1000_translate_register_82542(reg))))
144 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ argument
149 reg + ((offset) << 2)),\
154 e1000_translate_register_82542(reg) + \
158 #define E1000_READ_REG_ARRAY(hw, reg, offse argument
169 E1000_WRITE_REG_ARRAY_DWORD(a,reg,offset,value) global() argument
171 E1000_READ_REG_ARRAY_DWORD(a,reg,offset) global() argument
175 E1000_READ_FLASH_REG(hw,reg) global() argument
179 E1000_READ_FLASH_REG16(hw,reg) global() argument
183 E1000_WRITE_FLASH_REG(hw,reg,value) global() argument
187 E1000_WRITE_FLASH_REG16(hw,reg,value) global() argument
233 E1000_WRITE_REG_IO(a,reg,val) global() argument
[all...]
/titanic_51/usr/src/lib/libdtrace/common/
H A Ddt_regset.c78 int reg; in dt_regset_assert_free() local
80 for (reg = 0; reg < drp->dr_size; reg++) { in dt_regset_assert_free()
81 if (BT_TEST(drp->dr_bitmap, reg) != 0) { in dt_regset_assert_free()
82 dt_dprintf("%%r%d was left allocated\n", reg); in dt_regset_assert_free()
110 int reg; in dt_regset_alloc() local
114 reg = (int)((wx << BT_ULSHIFT) | bx); in dt_regset_alloc()
115 BT_SET(drp->dr_bitmap, reg); in dt_regset_alloc()
116 return (reg); in dt_regset_alloc()
127 dt_regset_free(dt_regset_t * drp,int reg) dt_regset_free() argument
[all...]
/titanic_51/usr/src/boot/sys/boot/fdt/dts/powerpc/
H A Dp3041si.dtsi108 reg = <0>;
117 reg = <1>;
125 reg = <2>;
133 reg = <3>;
152 reg = <0x0 0x1000>;
156 reg = <0x1000 0x1000 0x1000000 0x8000>;
160 reg = <0x2000 0x1000>;
164 reg = <0x8000 0x1000 0xB0000 0x1000>;
168 reg = <0x9000 0x1000>;
172 reg
[all...]
H A Dp2041si.dtsi107 reg = <0>;
116 reg = <1>;
124 reg = <2>;
132 reg = <3>;
151 reg = <0x0 0x1000>;
155 reg = <0x1000 0x1000 0x1000000 0x8000>;
159 reg = <0x2000 0x1000>;
163 reg = <0x8000 0x1000 0xB0000 0x1000>;
167 reg = <0x9000 0x1000>;
171 reg
[all...]
/titanic_51/usr/src/uts/intel/brand/common/
H A Dbrand_asm.h147 * reg - a register to read the variable into, or
153 #define GET_V(sp, pcnt, var, reg) \ argument
154 mov V_OFFSET(pcnt, var)(sp), reg
156 #define SET_V(sp, pcnt, var, reg) \ argument
157 mov reg, V_OFFSET(pcnt, var)(sp)
159 #define GET_PROCP(sp, pcnt, reg) \ argument
160 GET_V(sp, pcnt, V_LWP, reg); /* get lwp pointer */ \
161 mov LWP_PROCP(reg), reg /* get proc pointer */
163 #define GET_P_BRAND_DATA(sp, pcnt, reg) \ argument
194 CHECK_FOR_NATIVE(reg) global() argument
[all...]
/titanic_51/usr/src/boot/sys/boot/fdt/dts/arm/
H A Dimx6.dtsi43 reg = <0x0>;
70 reg = <0x00a01000 0x00001000
76 reg = <0x00a00200 0x100
84 reg = <0xa02000 0x1000>;
95 reg = <0x02000000 0x00100000>;
101 reg = <0x020c4000 0x4000>;
108 reg = <0x020D8000 0x100>;
113 reg = <0x020ec000 0x4000>;
121 reg = <0x020c8000 0x1000>;
128 reg
[all...]

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