| /titanic_50/usr/src/cmd/mdb/intel/amd64/kmdb/ |
| H A D | kmdb_asmutil.s | 87 wrmsr(uint32_t addr, uint64_t *valp)
92 ENTRY(wrmsr)
96 wrmsr
98 SET_SIZE(wrmsr)
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| /titanic_50/usr/src/uts/i86pc/os/cpupm/ |
| H A D | turbo.c | 111 wrmsr(IA32_MPERF_MSR, 0); in update_turbo_info()
112 wrmsr(IA32_APERF_MSR, 0); in update_turbo_info()
144 wrmsr(IA32_MPERF_MSR, 0); in reset_turbo_info()
145 wrmsr(IA32_APERF_MSR, 0); in reset_turbo_info()
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| H A D | cpupm_intel.c | 163 wrmsr(IA32_ENERGY_PERF_BIAS_MSR, epb_value); in cpupm_iepb_set_policy()
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| H A D | pwrnow.c | 98 wrmsr(PWRNOW_PERF_CTL_MSR, reg); in write_ctrl()
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| /titanic_50/usr/src/uts/i86pc/ml/ |
| H A D | bios_call_src.s | 140 wrmsr
148 wrmsr
156 wrmsr
240 wrmsr
361 wrmsr
425 wrmsr
430 wrmsr
435 wrmsr
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| H A D | mpcore.s | 172 wrmsr
282 wrmsr
295 wrmsr
298 wrmsr
324 wrmsr
426 wrmsr
517 wrmsr
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| H A D | fb_swtch_src.s | 132 wrmsr
135 wrmsr
138 wrmsr
247 wrmsr
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| H A D | cpr_wakecode.s | 383 wrmsr
671 wrmsr
696 / restore %fsbase %gsbase %kgbase registers using wrmsr instruction
704 wrmsr
712 wrmsr
717 wrmsr
1089 wrmsr
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| H A D | syscall_asm.s | 676 wrmsr
687 wrmsr
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| /titanic_50/usr/src/uts/i86pc/os/ |
| H A D | mp_startup.c | 193 wrmsr(MSR_AMD_STAR, in init_cpu_syscall()
195 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); in init_cpu_syscall()
196 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); in init_cpu_syscall()
202 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); in init_cpu_syscall()
239 wrmsr(MSR_INTC_SEP_ESP, 0); in init_cpu_syscall()
240 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); in init_cpu_syscall()
1211 wrmsr(MSR_AMD_DE_CFG, in workaround_errata()
1677 (void) wrmsr(REG_TSC, 0UL); in mp_startup_common()
1708 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); in mp_startup_common()
2043 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); in cpu_sep_enable()
[all …]
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| H A D | mach_kdi.c | 167 wrmsr(MSR_AMD_GSBASE, (uint64_t)cpu); in boot_kdi_tmpinit()
174 wrmsr(MSR_AMD_GSBASE, (uint64_t)old); in boot_kdi_tmpfini()
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| H A D | mlsetup.c | 208 (void) wrmsr(REG_TSC, 0UL); in mlsetup()
271 (void) wrmsr(MSR_AMD_TSCAUX, 0); in mlsetup()
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| H A D | xpv_platform.c | 168 wrmsr(cp.cp_ebx, msrval); in xen_hvm_init()
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| H A D | pci_mech1_amd.c | 75 wrmsr(MSR_AMD_NB_CFG, rdmsr(MSR_AMD_NB_CFG) | AMD_GH_NB_CFG_EN_ECS); in pci_check_amd_ioecs()
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| H A D | microcode.c | 758 wrmsr(ucode->write_msr, (uintptr_t)uusp->ucodep); in ucode_write()
789 wrmsr(ucode->write_msr, (uintptr_t)ucodefp); in ucode_load_amd()
852 wrmsr(ucode->write_msr, (uintptr_t)ucodefp->uf_body); in ucode_load_intel()
900 wrmsr(MSR_INTC_UCODE_REV, 0); in ucode_read_rev_intel()
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| /titanic_50/usr/src/uts/i86pc/io/pcplusmp/ |
| H A D | apic_regops.c | 177 wrmsr((REG_X2APIC_BASE_MSR + (msr >> 2)), tmp); in local_x2apic_write()
195 wrmsr((REG_X2APIC_BASE_MSR + (APIC_INT_CMD1 >> 2)), in local_x2apic_write_int_cmd()
265 wrmsr(REG_APIC_BASE_MSR, apic_base_msr); in apic_enable_x2apic()
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| H A D | apic_timer.c | 311 wrmsr(IA32_DEADLINE_TSC_MSR, 1ULL << 63); in deadline_timer_enable()
342 wrmsr(IA32_DEADLINE_TSC_MSR, ticks); in deadline_timer_reprogram()
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| /titanic_50/usr/src/uts/intel/ia32/os/ |
| H A D | desctbls.c | 695 wrmsr(MSR_AMD_GSBASE, (uint64_t)&cpus[0]); in init_gdt()
707 wrmsr(MSR_AMD_FSBASE, 0x200000000ul); in init_gdt()
708 wrmsr(MSR_AMD_KGSBASE, 0x200000000ul); in init_gdt()
1340 wrmsr(MSR_AMD_LSTAR, (uintptr_t)brand_sys_syscall); in brand_interpositioning_enable()
1341 wrmsr(MSR_AMD_CSTAR, (uintptr_t)brand_sys_syscall32); in brand_interpositioning_enable()
1348 wrmsr(MSR_INTC_SEP_EIP, (uintptr_t)brand_sys_sysenter); in brand_interpositioning_enable()
1384 wrmsr(MSR_AMD_LSTAR, (uintptr_t)sys_syscall); in brand_interpositioning_disable()
1385 wrmsr(MSR_AMD_CSTAR, (uintptr_t)sys_syscall32); in brand_interpositioning_disable()
1392 wrmsr(MSR_INTC_SEP_EIP, (uintptr_t)sys_sysenter); in brand_interpositioning_disable()
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| H A D | sundep.c | 562 wrmsr(MSR_AMD_GSBASE, kgsbase); in update_sregs()
591 wrmsr(MSR_AMD_KGSBASE, pcb->pcb_gsbase); in update_sregs()
615 wrmsr(MSR_AMD_FSBASE, pcb->pcb_fsbase); in update_sregs()
662 wrmsr(MSR_AMD_GSBASE, kgsbase); in reset_sregs()
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| /titanic_50/usr/src/uts/intel/pcbe/ |
| H A D | p4_pcbe.c | 953 wrmsr(p4_ctrs[i].pc_caddr, cfgs[i]->p4_rawpic); in p4_pcbe_program()
954 wrmsr(p4_escrs[cfgs[i]->p4_escr_ndx].pe_addr, escr); in p4_pcbe_program()
968 wrmsr(p4_ctrs[i].pc_ctladdr, cccr); in p4_pcbe_program()
974 wrmsr(p4_ctrs[i].pc_caddr, cfgs[i]->p4_rawpic); in p4_pcbe_program()
975 wrmsr(p4_escrs[cfgs[i]->p4_escr_ndx].pe_addr, in p4_pcbe_program()
982 wrmsr(p4_ctrs[i].pc_ctladdr, in p4_pcbe_program()
994 wrmsr(p4_ctrs[i].pc_ctladdr, 0ULL); in p4_pcbe_allstop()
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| H A D | opteron_pcbe.c | 859 wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel); in opt_pcbe_program()
860 wrmsr(opd.opd_picf(i), cfgs[i]->opt_rawpic); in opt_pcbe_program()
864 wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel | in opt_pcbe_program()
875 wrmsr(opd.opd_pesf(i), 0ULL); in opt_pcbe_allstop()
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| /titanic_50/usr/src/cmd/mdb/intel/kmdb/ |
| H A D | kmdb_asmutil.h | 42 extern void wrmsr(uint32_t, uint64_t *);
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| /titanic_50/usr/src/uts/i86pc/dboot/ |
| H A D | dboot_grub.s | 249 wrmsr
266 wrmsr
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| /titanic_50/usr/src/uts/intel/kdi/amd64/ |
| H A D | kdi_asm.s | 100 wrmsr
217 wrmsr; \
239 wrmsr; \
330 wrmsr
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| /titanic_50/usr/src/grub/grub-0.97/netboot/ |
| H A D | cpu.h | 198 #define wrmsr(msr,val1,val2) \ macro
|