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/titanic_50/usr/src/uts/common/io/chxge/com/
H A Dch_subr.c240 u32 tp_cause = t1_read_reg_4(adapter, in fpga_slow_intr() local
243 if (tp_cause & FPGA_TP_INTERRUPT_MC5) in fpga_slow_intr()
248 tp_cause); in fpga_slow_intr()