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Searched refs:simulation (Results 1 – 18 of 18) sorted by relevance

/titanic_50/usr/src/cmd/fm/scripts/
H A Dfmsim.ksh178 echo "\t-d set the simulation root directory to the given location"
183 echo "\t-o set fmd(1M) option to specified value during simulation"
184 echo "\t-s set up simulation world but do not actually run simulation"
188 echo "\t-w wait for a keypress after simulation completes"
189 echo "\t-x delete simulation world if simulation is successful"
194 echo "fmsim: creating simulation world $simroot ... \c"
/titanic_50/usr/src/cmd/cdrw/
H A Dmain.h42 extern int simulation;
H A Dmain.c52 int simulation = 0; variable
311 simulation++; in main()
H A Dmisc_scsi.c1048 if (simulation) in write_init()
1064 if (simulation && in write_init()
1083 if (!prepare_for_write(target, mode, simulation, keep_disc_open)) { in write_init()
1127 if (!simulation) { in write_fini()
H A Dcopycd.c390 if (simulation && (device_type == DVD_PLUS_W || in copy_cd()
463 if (simulation && (end_tno != 1)) { in copy_cd()
H A Dwrite_audio.c135 if (simulation && (nfiles != 1)) { in write_audio()
H A Dwrite_image.c68 if (simulation && (device_type == DVD_PLUS_W || in write_image()
H A Dtransport.c182 simulation))) in uscsi()
H A Dtrackio.c160 if (simulation) in write_to_cd()
175 if ((retry == 0) && (simulation == 0)) { in write_to_cd()
/titanic_50/usr/src/lib/librstp/common/
H A DREADME.files13 o The second is a simulation of virtual RSTP bridge. It
/titanic_50/usr/src/grub/grub-0.97/
H A Dconfigure.ac544 AC_ARG_ENABLE(serial-speed-simulation,
545 [ --enable-serial-speed-simulation
H A DINSTALL245 `--enable-serial-speed-simulation'
H A DNEWS188 `--enable-serial-speed-simulation', which is useful when you want to
H A Dconfigure908 --enable-serial-speed-simulation
/titanic_50/usr/src/uts/common/avs/ns/sdbc/
H A DCACHE_SPEC.txt332 simulation.
/titanic_50/usr/src/cmd/filesync/
H A DREADME226 simulation and bit-map display.
/titanic_50/usr/src/cmd/fm/eversholt/files/i386/i86pc/
H A Damd64.esc631 * Ereports for all of these can be generated by error simulation and
/titanic_50/usr/src/uts/intel/io/acpica/
H A Dchanges.txt1896 expands the simulation of operation regions by supporting regions that
7235 simulation
12067 Added a sleep simulation command to the AML debugger to test sleep code.