Home
last modified time | relevance | path

Searched refs:sc_scd_base (Results 1 – 6 of 6) sorted by relevance

/titanic_50/usr/src/uts/common/io/iwk/
H A Diwk2_var.h176 uint32_t sc_scd_base; member
H A Diwk2.c2284 sc->sc_scd_base = iwk_reg_read(sc, SCD_SRAM_BASE_ADDR); in iwk_ucode_alive()
2287 for (base = sc->sc_scd_base + SCD_CONTEXT_DATA_OFFSET, i = 0; in iwk_ucode_alive()
2292 for (base = sc->sc_scd_base + SCD_TX_STTS_BITMAP_OFFSET; in iwk_ucode_alive()
2297 for (base = sc->sc_scd_base + SCD_TRANSLATE_TBL_OFFSET; in iwk_ucode_alive()
2309 iwk_mem_write(sc, sc->sc_scd_base + in iwk_ucode_alive()
2312 iwk_mem_write(sc, sc->sc_scd_base + in iwk_ucode_alive()
/titanic_50/usr/src/uts/common/io/iwp/
H A Diwp_var.h202 uint32_t sc_scd_base; member
H A Diwp.c4920 sc->sc_scd_base = iwp_reg_read(sc, IWP_SCD_SRAM_BASE_ADDR); in iwp_alive_common()
4922 for (base = sc->sc_scd_base + IWP_SCD_CONTEXT_DATA_OFFSET; in iwp_alive_common()
4923 base < sc->sc_scd_base + IWP_SCD_TX_STTS_BITMAP_OFFSET; in iwp_alive_common()
4928 for (; base < sc->sc_scd_base + IWP_SCD_TRANSLATE_TBL_OFFSET; in iwp_alive_common()
4948 iwp_mem_write(sc, sc->sc_scd_base + in iwp_alive_common()
4950 iwp_mem_write(sc, sc->sc_scd_base + in iwp_alive_common()
/titanic_50/usr/src/uts/common/io/iwh/
H A Diwh_var.h184 uint32_t sc_scd_base; member
H A Diwh.c5307 sc->sc_scd_base = iwh_reg_read(sc, IWH_SCD_SRAM_BASE_ADDR); in iwh_alive_common()
5309 for (base = sc->sc_scd_base + IWH_SCD_CONTEXT_DATA_OFFSET; in iwh_alive_common()
5310 base < sc->sc_scd_base + IWH_SCD_TX_STTS_BITMAP_OFFSET; in iwh_alive_common()
5315 for (; base < sc->sc_scd_base + IWH_SCD_TRANSLATE_TBL_OFFSET; in iwh_alive_common()
5335 iwh_mem_write(sc, sc->sc_scd_base + in iwh_alive_common()
5337 iwh_mem_write(sc, sc->sc_scd_base + in iwh_alive_common()