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Searched refs:rx_rings (Results 1 – 18 of 18) sorted by relevance

/titanic_50/usr/src/uts/common/io/fibre-channel/fca/oce/
H A Doce_intr.c64 nreqd = dev->rx_rings + 1; in oce_setup_intr()
132 dev->rx_rings = nallocd - 1; in oce_setup_intr()
134 dev->rx_rings = 1; in oce_setup_intr()
H A Doce_queue.c1138 dev->rss_enable = (dev->rx_rings > 1) ? B_TRUE : B_FALSE; in oce_init_txrx()
1156 for (qid = 1; qid < dev->rx_rings; qid++) { in oce_init_txrx()
1261 if (dev->rx_rings <= 1) { in oce_dev_rss_ready()
1263 "Rx rings = %d, Not enabling RSS", dev->rx_rings); in oce_dev_rss_ready()
1287 dev->rx_rings = 1; in oce_dev_rss_ready()
H A Doce_main.c422 for (qid = 0; qid < dev->rx_rings; qid++) { in oce_detach()
631 dev->rx_rings = oce_get_prop(dev, (char *)rx_rings_name, in oce_get_params()
/titanic_50/usr/src/uts/common/io/igb/
H A Digb_main.c1044 rx_ring = &igb->rx_rings[i]; in igb_init_driver_settings()
1088 rx_ring = &igb->rx_rings[i]; in igb_init_locks()
1126 rx_ring = &igb->rx_rings[i]; in igb_destroy_locks()
1607 mutex_enter(&igb->rx_rings[i].rx_lock); in igb_reset()
1652 mutex_exit(&igb->rx_rings[i].rx_lock); in igb_reset()
1664 mutex_exit(&igb->rx_rings[i].rx_lock); in igb_reset()
1839 mutex_enter(&igb->rx_rings[i].rx_lock); in igb_start()
1879 mutex_exit(&igb->rx_rings[i].rx_lock); in igb_start()
1887 mutex_exit(&igb->rx_rings[i].rx_lock); in igb_start()
1917 mutex_enter(&igb->rx_rings[i].rx_lock); in igb_stop()
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H A Digb_stat.c68 igb->rx_rings[i].stat_frame_error; in igb_update_stats()
70 igb->rx_rings[i].stat_cksum_error; in igb_update_stats()
72 igb->rx_rings[i].stat_exceed_pkt; in igb_update_stats()
H A Digb_buf.c136 rx_ring = &igb->rx_rings[i]; in igb_alloc_dma()
183 rx_ring = &igb->rx_rings[i]; in igb_free_dma()
H A Digb_sw.h591 igb_rx_ring_t *rx_rings; /* Array of rx rings */ member
H A Digb_gld.c775 rx_ring = &igb->rx_rings[i]; in igb_get_rx_ring_index()
820 rx_ring = &igb->rx_rings[global_index]; in igb_fill_ring()
/titanic_50/usr/src/uts/common/io/ixgbe/
H A Dixgbe_main.c1141 rx_ring = &ixgbe->rx_rings[i]; in ixgbe_init_driver_settings()
1193 rx_ring = &ixgbe->rx_rings[i]; in ixgbe_init_locks()
1228 rx_ring = &ixgbe->rx_rings[i]; in ixgbe_destroy_locks()
1823 mutex_enter(&ixgbe->rx_rings[i].rx_lock); in ixgbe_start()
1879 mutex_exit(&ixgbe->rx_rings[i].rx_lock); in ixgbe_start()
1887 mutex_exit(&ixgbe->rx_rings[i].rx_lock); in ixgbe_start()
1915 mutex_enter(&ixgbe->rx_rings[i].rx_lock); in ixgbe_stop()
1936 mutex_exit(&ixgbe->rx_rings[i].rx_lock); in ixgbe_stop()
2010 mac_ring_intr_set(ixgbe->rx_rings[i].ring_handle, NULL); in ixgbe_intr_adjust()
2125 mac_ring_intr_set(ixgbe->rx_rings[i].ring_handle, in ixgbe_intr_adjust()
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H A Dixgbe_debug.c76 hw_index = ixgbe->rx_rings[j].hw_index; in ixgbe_dump_interrupt()
463 hw_index = ixgbe->rx_rings[i].hw_index; in ixgbe_dump_regs()
H A Dixgbe_stat.c67 ixgbe->rx_rings[i].stat_frame_error; in ixgbe_update_stats()
69 ixgbe->rx_rings[i].stat_cksum_error; in ixgbe_update_stats()
71 ixgbe->rx_rings[i].stat_exceed_pkt; in ixgbe_update_stats()
H A Dixgbe_buf.c134 rx_ring = &ixgbe->rx_rings[i]; in ixgbe_alloc_dma()
180 rx_ring = &ixgbe->rx_rings[i]; in ixgbe_free_dma()
H A Dixgbe_sw.h654 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ member
/titanic_50/usr/src/uts/common/io/bge/
H A Dbge_chip2.c2589 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) in bge_chip_id_init()
2590 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; in bge_chip_id_init()
2637 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; in bge_chip_id_init()
2707 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; in bge_chip_id_init()
2724 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; in bge_chip_id_init()
2741 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; in bge_chip_id_init()
2759 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; in bge_chip_id_init()
2782 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; in bge_chip_id_init()
2800 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; in bge_chip_id_init()
2839 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; in bge_chip_id_init()
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H A Dbge_main2.c348 for (ring = 0; ring < bgep->chipid.rx_rings; ++ring) in bge_reinit_rings()
1299 for (i = 0; i < MIN(bgep->chipid.rx_rings, MAC_ADDRESS_REGS_MAX); i++)
1726 ASSERT(rg_index >= 0 && rg_index < MIN(bgep->chipid.rx_rings,
1767 ASSERT(rg_index >= 0 && rg_index < MIN(bgep->chipid.rx_rings,
1813 MIN(bgep->chipid.rx_rings, MAC_ADDRESS_REGS_MAX);
2661 uint32_t rx_rings = bgep->chipid.rx_rings; local
2676 rxdescsize = rx_rings*bgep->chipid.recv_slots;
2738 ASSERT((rxdescsize % rx_rings) == 0);
2739 for (split = 0; split < rx_rings; ++split) {
2740 err = bge_alloc_dma_mem(bgep, rxdescsize/rx_rings,
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H A Dbge_recv2.c420 for (index = 0; index < bgep->chipid.rx_rings; index++) { in bge_receive()
H A Dbge_impl.h646 uint32_t rx_rings; /* from bge.conf */ member
/titanic_50/usr/src/uts/common/sys/fibre-channel/fca/oce/
H A Doce_impl.h276 uint32_t rx_rings; member