xref: /titanic_50/usr/src/grub/grub-0.97/netboot/eepro100.c (revision 1b8adde7ba7d5e04395c141c5400dc2cffd7d809)
1 /*
2  * eepro100.c -- This file implements the eepro100 driver for etherboot.
3  *
4  *
5  * Copyright (C) AW Computer Systems.
6  * written by R.E.Wolff -- R.E.Wolff@BitWizard.nl
7  *
8  *
9  * AW Computer Systems is contributing to the free software community
10  * by paying for this driver and then putting the result under GPL.
11  *
12  * If you need a Linux device driver, please contact BitWizard for a
13  * quote.
14  *
15  *
16  * This program is free software; you can redistribute it and/or
17  * modify it under the terms of the GNU General Public License as
18  * published by the Free Software Foundation; either version 2, or (at
19  * your option) any later version.
20  *
21  * This program is distributed in the hope that it will be useful, but
22  * WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
24  * General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with this program; if not, write to the Free Software
28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29  *
30  *
31  *              date       version  by   what
32  *  Written:    May 29 1997  V0.10  REW  Initial revision.
33  * changes:     May 31 1997  V0.90  REW  Works!
34  *              Jun 1  1997  V0.91  REW  Cleanup
35  *              Jun 2  1997  V0.92  REW  Add some code documentation
36  *              Jul 25 1997  V1.00  REW  Tested by AW to work in a PROM
37  *                                       Cleanup for publication
38  *
39  * This is the etherboot intel etherexpress Pro/100B driver.
40  *
41  * It was written from scratch, with Donald Beckers eepro100.c kernel
42  * driver as a guideline. Mostly the 82557 related definitions and the
43  * lower level routines have been cut-and-pasted into this source.
44  *
45  * The driver was finished before Intel got the NDA out of the closet.
46  * I still don't have the docs.
47  * */
48 
49 /* Philosophy of this driver.
50  *
51  * Probing:
52  *
53  * Using the pci.c functions of the Etherboot code, the 82557 chip is detected.
54  * It is verified that the BIOS initialized everything properly and if
55  * something is missing it is done now.
56  *
57  *
58  * Initialization:
59  *
60  *
61  * The chip is then initialized to "know" its ethernet address, and to
62  * start recieving packets. The Linux driver has a whole transmit and
63  * recieve ring of buffers. This is neat if you need high performance:
64  * you can write the buffers asynchronously to the chip reading the
65  * buffers and transmitting them over the network.  Performance is NOT
66  * an issue here. We can boot a 400k kernel in about two
67  * seconds. (Theory: 0.4 seconds). Booting a system is going to take
68  * about half a minute anyway, so getting 10 times closer to the
69  * theoretical limit is going to make a difference of a few percent.
70  *
71  *
72  * Transmitting and recieving.
73  *
74  * We have only one transmit descriptor. It has two buffer descriptors:
75  * one for the header, and the other for the data.
76  * We have only one receive buffer. The chip is told to recieve packets,
77  * and suspend itself once it got one. The recieve (poll) routine simply
78  * looks at the recieve buffer to see if there is already a packet there.
79  * if there is, the buffer is copied, and the reciever is restarted.
80  *
81  * Caveats:
82  *
83  * The Etherboot framework moves the code to the 48k segment from
84  * 0x94000 to 0xa0000. There is just a little room between the end of
85  * this driver and the 0xa0000 address. If you compile in too many
86  * features, this will overflow.
87  * The number under "hex" in the output of size that scrolls by while
88  * compiling should be less than 8000. Maybe even the stack is up there,
89  * so that you need even more headroom.
90  */
91 
92 /* The etherboot authors seem to dislike the argument ordering in
93  * outb macros that Linux uses. I disklike the confusion that this
94  * has caused even more.... This file uses the Linux argument ordering.  */
95 /* Sorry not us. It's inherited code from FreeBSD. [The authors] */
96 
97 #include "etherboot.h"
98 #include "nic.h"
99 #include "pci.h"
100 #include "timer.h"
101 
102 static int ioaddr;
103 
104 typedef unsigned char  u8;
105 typedef   signed char  s8;
106 typedef unsigned short u16;
107 typedef   signed short s16;
108 typedef unsigned int   u32;
109 typedef   signed int   s32;
110 
111 enum speedo_offsets {
112   SCBStatus = 0, SCBCmd = 2,      /* Rx/Command Unit command and status. */
113   SCBPointer = 4,                 /* General purpose pointer. */
114   SCBPort = 8,                    /* Misc. commands and operands.  */
115   SCBflash = 12, SCBeeprom = 14,  /* EEPROM and flash memory control. */
116   SCBCtrlMDI = 16,                /* MDI interface control. */
117   SCBEarlyRx = 20,                /* Early receive byte count. */
118 };
119 
120 enum SCBCmdBits {
121 	SCBMaskCmdDone=0x8000, SCBMaskRxDone=0x4000, SCBMaskCmdIdle=0x2000,
122 	SCBMaskRxSuspend=0x1000, SCBMaskEarlyRx=0x0800, SCBMaskFlowCtl=0x0400,
123 	SCBTriggerIntr=0x0200, SCBMaskAll=0x0100,
124 	/* The rest are Rx and Tx commands. */
125 	CUStart=0x0010, CUResume=0x0020, CUStatsAddr=0x0040, CUShowStats=0x0050,
126 	CUCmdBase=0x0060,	/* CU Base address (set to zero) . */
127 	CUDumpStats=0x0070, /* Dump then reset stats counters. */
128 	RxStart=0x0001, RxResume=0x0002, RxAbort=0x0004, RxAddrLoad=0x0006,
129 	RxResumeNoResources=0x0007,
130 };
131 
132 static int do_eeprom_cmd(int cmd, int cmd_len);
133 void hd(void *where, int n);
134 
135 /***********************************************************************/
136 /*                       I82557 related defines                        */
137 /***********************************************************************/
138 
139 /* Serial EEPROM section.
140    A "bit" grungy, but we work our way through bit-by-bit :->. */
141 /*  EEPROM_Ctrl bits. */
142 #define EE_SHIFT_CLK    0x01    /* EEPROM shift clock. */
143 #define EE_CS           0x02    /* EEPROM chip select. */
144 #define EE_DATA_WRITE   0x04    /* EEPROM chip data in. */
145 #define EE_DATA_READ    0x08    /* EEPROM chip data out. */
146 #define EE_WRITE_0      0x4802
147 #define EE_WRITE_1      0x4806
148 #define EE_ENB          (0x4800 | EE_CS)
149 
150 /* The EEPROM commands include the alway-set leading bit. */
151 #define EE_READ_CMD     6
152 
153 /* The SCB accepts the following controls for the Tx and Rx units: */
154 #define  CU_START       0x0010
155 #define  CU_RESUME      0x0020
156 #define  CU_STATSADDR   0x0040
157 #define  CU_SHOWSTATS   0x0050  /* Dump statistics counters. */
158 #define  CU_CMD_BASE    0x0060  /* Base address to add to add CU commands. */
159 #define  CU_DUMPSTATS   0x0070  /* Dump then reset stats counters. */
160 
161 #define  RX_START       0x0001
162 #define  RX_RESUME      0x0002
163 #define  RX_ABORT       0x0004
164 #define  RX_ADDR_LOAD   0x0006
165 #define  RX_RESUMENR    0x0007
166 #define INT_MASK        0x0100
167 #define DRVR_INT        0x0200          /* Driver generated interrupt. */
168 
169 enum phy_chips { NonSuchPhy=0, I82553AB, I82553C, I82503, DP83840, S80C240,
170                                          S80C24, PhyUndefined, DP83840A=10, };
171 
172 /* Commands that can be put in a command list entry. */
173 enum commands {
174   CmdNOp = 0,
175   CmdIASetup = 1,
176   CmdConfigure = 2,
177   CmdMulticastList = 3,
178   CmdTx = 4,
179   CmdTDR = 5,
180   CmdDump = 6,
181   CmdDiagnose = 7,
182 
183   /* And some extra flags: */
184   CmdSuspend = 0x4000,      /* Suspend after completion. */
185   CmdIntr = 0x2000,         /* Interrupt after completion. */
186   CmdTxFlex = 0x0008,       /* Use "Flexible mode" for CmdTx command. */
187 };
188 
189 /* How to wait for the command unit to accept a command.
190    Typically this takes 0 ticks. */
wait_for_cmd_done(int cmd_ioaddr)191 static inline void wait_for_cmd_done(int cmd_ioaddr)
192 {
193   int wait = 0;
194   int delayed_cmd;
195 
196   do
197     if (inb(cmd_ioaddr) == 0) return;
198   while(++wait <= 100);
199   delayed_cmd = inb(cmd_ioaddr);
200   do
201     if (inb(cmd_ioaddr) == 0) break;
202   while(++wait <= 10000);
203   printf("Command %2.2x was not immediately accepted, %d ticks!\n",
204       delayed_cmd, wait);
205 }
206 
207 /* Elements of the dump_statistics block. This block must be lword aligned. */
208 static struct speedo_stats {
209         u32 tx_good_frames;
210         u32 tx_coll16_errs;
211         u32 tx_late_colls;
212         u32 tx_underruns;
213         u32 tx_lost_carrier;
214         u32 tx_deferred;
215         u32 tx_one_colls;
216         u32 tx_multi_colls;
217         u32 tx_total_colls;
218         u32 rx_good_frames;
219         u32 rx_crc_errs;
220         u32 rx_align_errs;
221         u32 rx_resource_errs;
222         u32 rx_overrun_errs;
223         u32 rx_colls_errs;
224         u32 rx_runt_errs;
225         u32 done_marker;
226 } lstats;
227 
228 /* A speedo3 TX buffer descriptor with two buffers... */
229 static struct TxFD {
230 	volatile s16 status;
231 	s16 command;
232 	u32 link;          /* void * */
233 	u32 tx_desc_addr;  /* (almost) Always points to the tx_buf_addr element. */
234 	s32 count;         /* # of TBD (=2), Tx start thresh., etc. */
235 	/* This constitutes two "TBD" entries: hdr and data */
236 	u32 tx_buf_addr0;  /* void *, header of frame to be transmitted.  */
237 	s32 tx_buf_size0;  /* Length of Tx hdr. */
238 	u32 tx_buf_addr1;  /* void *, data to be transmitted.  */
239 	s32 tx_buf_size1;  /* Length of Tx data. */
240 } txfd;
241 
242 struct RxFD {               /* Receive frame descriptor. */
243 	volatile s16 status;
244 	s16 command;
245 	u32 link;                 /* struct RxFD * */
246 	u32 rx_buf_addr;          /* void * */
247 	u16 count;
248 	u16 size;
249 	char packet[1518];
250 };
251 
252 static struct RxFD rxfd;
253 #define ACCESS(x) x.
254 
255 static int congenb = 0;         /* Enable congestion control in the DP83840. */
256 static int txfifo = 8;          /* Tx FIFO threshold in 4 byte units, 0-15 */
257 static int rxfifo = 8;          /* Rx FIFO threshold, default 32 bytes. */
258 static int txdmacount = 0;      /* Tx DMA burst length, 0-127, default 0. */
259 static int rxdmacount = 0;      /* Rx DMA length, 0 means no preemption. */
260 
261 /* I don't understand a byte in this structure. It was copied from the
262  * Linux kernel initialization for the eepro100. -- REW */
263 static struct ConfCmd {
264   s16 status;
265   s16 command;
266   u32 link;
267   unsigned char data[22];
268 } confcmd = {
269   0, 0, 0, /* filled in later */
270   {22, 0x08, 0, 0,  0, 0x80, 0x32, 0x03,  1, /* 1=Use MII  0=Use AUI */
271    0, 0x2E, 0,  0x60, 0,
272    0xf2, 0x48,   0, 0x40, 0xf2, 0x80,        /* 0x40=Force full-duplex */
273    0x3f, 0x05, }
274 };
275 
276 /***********************************************************************/
277 /*                       Locally used functions                        */
278 /***********************************************************************/
279 
280 /* Support function: mdio_write
281  *
282  * This probably writes to the "physical media interface chip".
283  * -- REW
284  */
285 
mdio_write(int phy_id,int location,int value)286 static int mdio_write(int phy_id, int location, int value)
287 {
288 	int val, boguscnt = 64*4;         /* <64 usec. to complete, typ 27 ticks */
289 
290 	outl(0x04000000 | (location<<16) | (phy_id<<21) | value,
291 	     ioaddr + SCBCtrlMDI);
292 	do {
293 		udelay(16);
294 
295 		val = inl(ioaddr + SCBCtrlMDI);
296 		if (--boguscnt < 0) {
297 			printf(" mdio_write() timed out with val = %X.\n", val);
298 			break;
299 		}
300 	} while (! (val & 0x10000000));
301 	return val & 0xffff;
302 }
303 
304 /* Support function: mdio_read
305  *
306  * This probably reads a register in the "physical media interface chip".
307  * -- REW
308  */
mdio_read(int phy_id,int location)309 static int mdio_read(int phy_id, int location)
310 {
311 	int val, boguscnt = 64*4;               /* <64 usec. to complete, typ 27 ticks */
312 	outl(0x08000000 | (location<<16) | (phy_id<<21), ioaddr + SCBCtrlMDI);
313 	do {
314 		udelay(16);
315 
316 		val = inl(ioaddr + SCBCtrlMDI);
317 
318 		if (--boguscnt < 0) {
319 			printf( " mdio_read() timed out with val = %X.\n", val);
320 			break;
321 		}
322 	} while (! (val & 0x10000000));
323 	return val & 0xffff;
324 }
325 
326 /* The fixes for the code were kindly provided by Dragan Stancevic
327    <visitor@valinux.com> to strictly follow Intel specifications of EEPROM
328    access timing.
329    The publicly available sheet 64486302 (sec. 3.1) specifies 1us access
330    interval for serial EEPROM.  However, it looks like that there is an
331    additional requirement dictating larger udelay's in the code below.
332    2000/05/24  SAW */
do_eeprom_cmd(int cmd,int cmd_len)333 static int do_eeprom_cmd(int cmd, int cmd_len)
334 {
335 	unsigned retval = 0;
336 	long ee_addr = ioaddr + SCBeeprom;
337 
338 	outw(EE_ENB, ee_addr); udelay(2);
339 	outw(EE_ENB | EE_SHIFT_CLK, ee_addr); udelay(2);
340 
341 	/* Shift the command bits out. */
342 	do {
343 		short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
344 		outw(dataval, ee_addr); udelay(2);
345 		outw(dataval | EE_SHIFT_CLK, ee_addr); udelay(2);
346 		retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0);
347 	} while (--cmd_len >= 0);
348 	outw(EE_ENB, ee_addr); udelay(2);
349 
350 	/* Terminate the EEPROM access. */
351 	outw(EE_ENB & ~EE_CS, ee_addr);
352 	return retval;
353 }
354 
355 #if 0
356 static inline void whereami (const char *str)
357 {
358   printf ("%s\n", str);
359   sleep (2);
360 }
361 #else
362 #define whereami(s)
363 #endif
364 
eepro100_irq(struct nic * nic __unused,irq_action_t action __unused)365 static void eepro100_irq(struct nic *nic __unused, irq_action_t action __unused)
366 {
367   switch ( action ) {
368   case DISABLE :
369     break;
370   case ENABLE :
371     break;
372   case FORCE :
373     break;
374   }
375 }
376 
377 /* function: eepro100_transmit
378  * This transmits a packet.
379  *
380  * Arguments: char d[6]:          destination ethernet address.
381  *            unsigned short t:   ethernet protocol type.
382  *            unsigned short s:   size of the data-part of the packet.
383  *            char *p:            the data for the packet.
384  * returns:   void.
385  */
386 
eepro100_transmit(struct nic * nic,const char * d,unsigned int t,unsigned int s,const char * p)387 static void eepro100_transmit(struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p)
388 {
389 	struct eth_hdr {
390 		unsigned char dst_addr[ETH_ALEN];
391 		unsigned char src_addr[ETH_ALEN];
392 		unsigned short type;
393 	} hdr;
394 	unsigned short status;
395 	int s1, s2;
396 
397 	status = inw(ioaddr + SCBStatus);
398 	/* Acknowledge all of the current interrupt sources ASAP. */
399 	outw(status & 0xfc00, ioaddr + SCBStatus);
400 
401 #ifdef	DEBUG
402 	printf ("transmitting type %hX packet (%d bytes). status = %hX, cmd=%hX\n",
403 		t, s, status, inw (ioaddr + SCBCmd));
404 #endif
405 
406 	memcpy (&hdr.dst_addr, d, ETH_ALEN);
407 	memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN);
408 
409 	hdr.type = htons (t);
410 
411 	txfd.status = 0;
412 	txfd.command = CmdSuspend | CmdTx | CmdTxFlex;
413 	txfd.link   = virt_to_bus (&txfd);
414 	txfd.count   = 0x02208000;
415 	txfd.tx_desc_addr = virt_to_bus(&txfd.tx_buf_addr0);
416 
417 	txfd.tx_buf_addr0 = virt_to_bus (&hdr);
418 	txfd.tx_buf_size0 = sizeof (hdr);
419 
420 	txfd.tx_buf_addr1 = virt_to_bus (p);
421 	txfd.tx_buf_size1 = s;
422 
423 #ifdef	DEBUG
424 	printf ("txfd: \n");
425 	hd (&txfd, sizeof (txfd));
426 #endif
427 
428 	outl(virt_to_bus(&txfd), ioaddr + SCBPointer);
429 	outw(INT_MASK | CU_START, ioaddr + SCBCmd);
430 	wait_for_cmd_done(ioaddr + SCBCmd);
431 
432 	s1 = inw (ioaddr + SCBStatus);
433 	load_timer2(10*TICKS_PER_MS);		/* timeout 10 ms for transmit */
434 	while (!txfd.status && timer2_running())
435 		/* Wait */;
436 	s2 = inw (ioaddr + SCBStatus);
437 
438 #ifdef	DEBUG
439 	printf ("s1 = %hX, s2 = %hX.\n", s1, s2);
440 #endif
441 }
442 
443 /*
444  * Sometimes the receiver stops making progress.  This routine knows how to
445  * get it going again, without losing packets or being otherwise nasty like
446  * a chip reset would be.  Previously the driver had a whole sequence
447  * of if RxSuspended, if it's no buffers do one thing, if it's no resources,
448  * do another, etc.  But those things don't really matter.  Separate logic
449  * in the ISR provides for allocating buffers--the other half of operation
450  * is just making sure the receiver is active.  speedo_rx_soft_reset does that.
451  * This problem with the old, more involved algorithm is shown up under
452  * ping floods on the order of 60K packets/second on a 100Mbps fdx network.
453  */
454 static void
speedo_rx_soft_reset(void)455 speedo_rx_soft_reset(void)
456 {
457   wait_for_cmd_done(ioaddr + SCBCmd);
458 	/*
459 	* Put the hardware into a known state.
460 	*/
461 	outb(RX_ABORT, ioaddr + SCBCmd);
462 
463 	ACCESS(rxfd)rx_buf_addr = 0xffffffff;
464 
465   wait_for_cmd_done(ioaddr + SCBCmd);
466 
467 	outb(RX_START, ioaddr + SCBCmd);
468 }
469 
470 /* function: eepro100_poll / eth_poll
471  * This recieves a packet from the network.
472  *
473  * Arguments: none
474  *
475  * returns:   1 if a packet was recieved.
476  *            0 if no pacet was recieved.
477  * side effects:
478  *            returns the packet in the array nic->packet.
479  *            returns the length of the packet in nic->packetlen.
480  */
481 
eepro100_poll(struct nic * nic,int retrieve)482 static int eepro100_poll(struct nic *nic, int retrieve)
483 {
484   unsigned int status;
485   status = inw(ioaddr + SCBStatus);
486 
487 	if (!ACCESS(rxfd)status)
488 		return 0;
489 
490 	/* There is a packet ready */
491 	if ( ! retrieve ) return 1;
492 
493   /*
494    * The chip may have suspended reception for various reasons.
495    * Check for that, and re-prime it should this be the case.
496    */
497   switch ((status >> 2) & 0xf) {
498   case 0: /* Idle */
499     break;
500   case 1:	/* Suspended */
501   case 2:	/* No resources (RxFDs) */
502   case 9:	/* Suspended with no more RBDs */
503   case 10: /* No resources due to no RBDs */
504   case 12: /* Ready with no RBDs */
505     speedo_rx_soft_reset();
506     break;
507   case 3:  case 5:  case 6:  case 7:  case 8:
508   case 11:  case 13:  case 14:  case 15:
509     /* these are all reserved values */
510     break;
511   }
512 
513 	/* Ok. We got a packet. Now restart the reciever.... */
514 	ACCESS(rxfd)status = 0;
515 	ACCESS(rxfd)command = 0xc000;
516 	outl(virt_to_bus(&(ACCESS(rxfd)status)), ioaddr + SCBPointer);
517 	outw(INT_MASK | RX_START, ioaddr + SCBCmd);
518 	wait_for_cmd_done(ioaddr + SCBCmd);
519 
520 #ifdef	DEBUG
521 	printf ("Got a packet: Len = %d.\n", ACCESS(rxfd)count & 0x3fff);
522 #endif
523 	nic->packetlen =  ACCESS(rxfd)count & 0x3fff;
524 	memcpy (nic->packet, ACCESS(rxfd)packet, nic->packetlen);
525 #ifdef	DEBUG
526 	hd (nic->packet, 0x30);
527 #endif
528 	return 1;
529 }
530 
531 /* function: eepro100_disable
532  * resets the card. This is used to allow Etherboot or Linux
533  * to probe the card again from a "virginal" state....
534  * Arguments: none
535  *
536  * returns:   void.
537  */
eepro100_disable(struct dev * dev __unused)538 static void eepro100_disable(struct dev *dev __unused)
539 {
540 /* from eepro100_reset */
541 	outl(0, ioaddr + SCBPort);
542 /* from eepro100_disable */
543 	/* See if this PartialReset solves the problem with interfering with
544 	   kernel operation after Etherboot hands over. - Ken 20001102 */
545 	outl(2, ioaddr + SCBPort);
546 
547 	/* The following is from the Intel e100 driver.
548 	 * This hopefully solves the problem with hanging hard DOS images. */
549 
550 	/* wait for the reset to take effect */
551 	udelay(20);
552 
553 	/* Mask off our interrupt line -- it is unmasked after reset */
554 	{
555 		u16 intr_status;
556 		/* Disable interrupts on our PCI board by setting the mask bit */
557 		outw(INT_MASK, ioaddr + SCBCmd);
558 		intr_status = inw(ioaddr + SCBStatus);
559 		/* ack and clear intrs */
560 		outw(intr_status, ioaddr + SCBStatus);
561 		inw(ioaddr + SCBStatus);
562 	}
563 }
564 
565 /* exported function: eepro100_probe / eth_probe
566  * initializes a card
567  *
568  * side effects:
569  *            leaves the ioaddress of the 82557 chip in the variable ioaddr.
570  *            leaves the 82557 initialized, and ready to recieve packets.
571  */
572 
eepro100_probe(struct dev * dev,struct pci_device * p)573 static int eepro100_probe(struct dev *dev, struct pci_device *p)
574 {
575 	struct nic *nic = (struct nic *)dev;
576 	unsigned short sum = 0;
577 	int i;
578 	int read_cmd, ee_size;
579 	int options;
580 	int rx_mode;
581 
582 	/* we cache only the first few words of the EEPROM data
583 	   be careful not to access beyond this array */
584 	unsigned short eeprom[16];
585 
586 	if (p->ioaddr == 0)
587 		return 0;
588 	ioaddr = p->ioaddr & ~3; /* Mask the bit that says "this is an io addr" */
589 	nic->ioaddr = ioaddr;
590 
591 	adjust_pci_device(p);
592 
593 	/* Copy IRQ from PCI information */
594 	/* nic->irqno = pci->irq; */
595 	nic->irqno = 0;
596 
597 	if ((do_eeprom_cmd(EE_READ_CMD << 24, 27) & 0xffe0000)
598 		== 0xffe0000) {
599 		ee_size = 0x100;
600 		read_cmd = EE_READ_CMD << 24;
601 	} else {
602 		ee_size = 0x40;
603 		read_cmd = EE_READ_CMD << 22;
604 	}
605 
606 	for (i = 0, sum = 0; i < ee_size; i++) {
607 		unsigned short value = do_eeprom_cmd(read_cmd | (i << 16), 27);
608 		if (i < (int)(sizeof(eeprom)/sizeof(eeprom[0])))
609 			eeprom[i] = value;
610 		sum += value;
611 	}
612 
613 	for (i=0;i<ETH_ALEN;i++) {
614 		nic->node_addr[i] =  (eeprom[i/2] >> (8*(i&1))) & 0xff;
615 	}
616 	printf ("Ethernet addr: %!\n", nic->node_addr);
617 
618 	if (sum != 0xBABA)
619 		printf("eepro100: Invalid EEPROM checksum %#hX, "
620 		       "check settings before activating this device!\n", sum);
621 	outl(0, ioaddr + SCBPort);
622 	udelay (10000);
623 	whereami ("Got eeprom.");
624 
625 	/* Base = 0 */
626 	outl(0, ioaddr + SCBPointer);
627 	outw(INT_MASK | RX_ADDR_LOAD, ioaddr + SCBCmd);
628 	wait_for_cmd_done(ioaddr + SCBCmd);
629 	whereami ("set rx base addr.");
630 
631 	outl(virt_to_bus(&lstats), ioaddr + SCBPointer);
632 	outw(INT_MASK | CU_STATSADDR, ioaddr + SCBCmd);
633 	wait_for_cmd_done(ioaddr + SCBCmd);
634 	whereami ("set stats addr.");
635 
636 	/* INIT RX stuff. */
637 	ACCESS(rxfd)status  = 0x0001;
638 	ACCESS(rxfd)command = 0x0000;
639 	ACCESS(rxfd)link    = virt_to_bus(&(ACCESS(rxfd)status));
640 	ACCESS(rxfd)rx_buf_addr = virt_to_bus(&nic->packet);
641 	ACCESS(rxfd)count   = 0;
642 	ACCESS(rxfd)size    = 1528;
643 
644 	outl(virt_to_bus(&(ACCESS(rxfd)status)), ioaddr + SCBPointer);
645 	outw(INT_MASK | RX_START, ioaddr + SCBCmd);
646 	wait_for_cmd_done(ioaddr + SCBCmd);
647 
648 	whereami ("started RX process.");
649 
650 	/* Start the reciever.... */
651 	ACCESS(rxfd)status = 0;
652 	ACCESS(rxfd)command = 0xc000;
653 	outl(virt_to_bus(&(ACCESS(rxfd)status)), ioaddr + SCBPointer);
654 	outw(INT_MASK | RX_START, ioaddr + SCBCmd);
655 
656 	/* INIT TX stuff. */
657 
658 	/* Base = 0 */
659 	outl(0, ioaddr + SCBPointer);
660 	outw(INT_MASK | CU_CMD_BASE, ioaddr + SCBCmd);
661 	wait_for_cmd_done(ioaddr + SCBCmd);
662 
663 	whereami ("set TX base addr.");
664 
665 	txfd.command      = (CmdIASetup);
666 	txfd.status       = 0x0000;
667 	txfd.link         = virt_to_bus (&confcmd);
668 
669 	{
670 		char *t = (char *)&txfd.tx_desc_addr;
671 
672 		for (i=0;i<ETH_ALEN;i++)
673 			t[i] = nic->node_addr[i];
674 	}
675 
676 #ifdef	DEBUG
677 	printf ("Setup_eaddr:\n");
678 	hd (&txfd, 0x20);
679 #endif
680 	/*      options = 0x40; */ /* 10mbps half duplex... */
681 	options = 0x00;            /* Autosense */
682 
683 #ifdef PROMISC
684 	rx_mode = 3;
685 #elif ALLMULTI
686 	rx_mode = 1;
687 #else
688 	rx_mode = 0;
689 #endif
690 
691 	if (   ((eeprom[6]>>8) & 0x3f) == DP83840
692 	       || ((eeprom[6]>>8) & 0x3f) == DP83840A) {
693 		int mdi_reg23 = mdio_read(eeprom[6] & 0x1f, 23) | 0x0422;
694 		if (congenb)
695 			mdi_reg23 |= 0x0100;
696 		printf("  DP83840 specific setup, setting register 23 to %hX.\n",
697 		       mdi_reg23);
698 		mdio_write(eeprom[6] & 0x1f, 23, mdi_reg23);
699 	}
700 	whereami ("Done DP8340 special setup.");
701 	if (options != 0) {
702 		mdio_write(eeprom[6] & 0x1f, 0,
703 			   ((options & 0x20) ? 0x2000 : 0) |    /* 100mbps? */
704 			   ((options & 0x10) ? 0x0100 : 0)); /* Full duplex? */
705 		whereami ("set mdio_register.");
706 	}
707 
708 	confcmd.command  = CmdSuspend | CmdConfigure;
709 	confcmd.status   = 0x0000;
710 	confcmd.link     = virt_to_bus (&txfd);
711 	confcmd.data[1]  = (txfifo << 4) | rxfifo;
712 	confcmd.data[4]  = rxdmacount;
713 	confcmd.data[5]  = txdmacount + 0x80;
714 	confcmd.data[15] = (rx_mode & 2) ? 0x49: 0x48;
715 	confcmd.data[19] = (options & 0x10) ? 0xC0 : 0x80;
716 	confcmd.data[21] = (rx_mode & 1) ? 0x0D: 0x05;
717 
718 	outl(virt_to_bus(&txfd), ioaddr + SCBPointer);
719 	outw(INT_MASK | CU_START, ioaddr + SCBCmd);
720 	wait_for_cmd_done(ioaddr + SCBCmd);
721 
722 	whereami ("started TX thingy (config, iasetup).");
723 
724 	load_timer2(10*TICKS_PER_MS);
725 	while (!txfd.status && timer2_running())
726 		/* Wait */;
727 
728 	/* Read the status register once to disgard stale data */
729 	mdio_read(eeprom[6] & 0x1f, 1);
730 	/* Check to see if the network cable is plugged in.
731 	 * This allows for faster failure if there is nothing
732 	 * we can do.
733 	 */
734 	if (!(mdio_read(eeprom[6] & 0x1f, 1) & (1 << 2))) {
735 		printf("Valid link not established\n");
736 		eepro100_disable(dev);
737 		return 0;
738 	}
739 
740 	dev->disable  = eepro100_disable;
741 	nic->poll     = eepro100_poll;
742 	nic->transmit = eepro100_transmit;
743 	nic->irq      = eepro100_irq;
744 	return 1;
745 }
746 
747 /*********************************************************************/
748 
749 #ifdef	DEBUG
750 
751 /* Hexdump a number of bytes from memory... */
hd(void * where,int n)752 void hd (void *where, int n)
753 {
754 	int i;
755 
756 	while (n > 0) {
757 		printf ("%X ", where);
758 		for (i=0;i < ( (n>16)?16:n);i++)
759 			printf (" %hhX", ((char *)where)[i]);
760 		printf ("\n");
761 		n -= 16;
762 		where += 16;
763 	}
764 }
765 #endif
766 
767 static struct pci_id eepro100_nics[] = {
768 PCI_ROM(0x8086, 0x1029, "id1029",        "Intel EtherExpressPro100 ID1029"),
769 PCI_ROM(0x8086, 0x1030, "id1030",        "Intel EtherExpressPro100 ID1030"),
770 PCI_ROM(0x8086, 0x1031, "82801cam",      "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
771 PCI_ROM(0x8086, 0x1032, "eepro100-1032", "Intel PRO/100 VE Network Connection"),
772 PCI_ROM(0x8086, 0x1033, "eepro100-1033", "Intel PRO/100 VM Network Connection"),
773 PCI_ROM(0x8086, 0x1034, "eepro100-1034", "Intel PRO/100 VM Network Connection"),
774 PCI_ROM(0x8086, 0x1035, "eepro100-1035", "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
775 PCI_ROM(0x8086, 0x1036, "eepro100-1036", "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
776 PCI_ROM(0x8086, 0x1037, "eepro100-1037", "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
777 PCI_ROM(0x8086, 0x1038, "id1038",        "Intel PRO/100 VM Network Connection"),
778 PCI_ROM(0x8086, 0x1039, "82562et",       "Intel PRO100 VE 82562ET"),
779 PCI_ROM(0x8086, 0x103a, "id103a",        "Intel Corporation 82559 InBusiness 10/100"),
780 PCI_ROM(0x8086, 0x103b, "82562etb",      "Intel PRO100 VE 82562ETB"),
781 PCI_ROM(0x8086, 0x103c, "eepro100-103c", "Intel PRO/100 VM Network Connection"),
782 PCI_ROM(0x8086, 0x103d, "eepro100-103d", "Intel PRO/100 VE Network Connection"),
783 PCI_ROM(0x8086, 0x103e, "eepro100-103e", "Intel PRO/100 VM Network Connection"),
784 PCI_ROM(0x8086, 0x1059, "82551qm",       "Intel PRO/100 M Mobile Connection"),
785 PCI_ROM(0x8086, 0x1209, "82559er",       "Intel EtherExpressPro100 82559ER"),
786 PCI_ROM(0x8086, 0x1227, "82865",         "Intel 82865 EtherExpress PRO/100A"),
787 PCI_ROM(0x8086, 0x1228, "82556",         "Intel 82556 EtherExpress PRO/100 Smart"),
788 PCI_ROM(0x8086, 0x1229, "eepro100",      "Intel EtherExpressPro100"),
789 PCI_ROM(0x8086, 0x2449, "82562em",       "Intel EtherExpressPro100 82562EM"),
790 PCI_ROM(0x8086, 0x2459, "82562-1",       "Intel 82562 based Fast Ethernet Connection"),
791 PCI_ROM(0x8086, 0x245d, "82562-2",       "Intel 82562 based Fast Ethernet Connection"),
792 PCI_ROM(0x8086, 0x1050, "82562ez",       "Intel 82562EZ Network Connection"),
793 PCI_ROM(0x8086, 0x5200, "eepro100-5200", "Intel EtherExpress PRO/100 Intelligent Server"),
794 PCI_ROM(0x8086, 0x5201, "eepro100-5201", "Intel EtherExpress PRO/100 Intelligent Server"),
795 };
796 
797 /* Cards with device ids 0x1030 to 0x103F, 0x2449, 0x2459 or 0x245D might need
798  * a workaround for hardware bug on 10 mbit half duplex (see linux driver eepro100.c)
799  * 2003/03/17 gbaum */
800 
801 
802 struct pci_driver eepro100_driver = {
803 	.type      = NIC_DRIVER,
804 	.name      = "EEPRO100",
805 	.probe     = eepro100_probe,
806 	.ids       = eepro100_nics,
807 	.id_count  = sizeof(eepro100_nics)/sizeof(eepro100_nics[0]),
808 	.class     = 0
809 };
810