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Searched refs:rir (Results 1 – 3 of 3) sorted by relevance

/titanic_50/usr/src/uts/intel/io/intel_nhm/
H A Dmem_addr.c46 rir_t rir[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER] variable
298 if (caddr >= base && caddr < rir[node][channel][i].limit) { in channel_addr_to_dimm()
302 rir[node][channel][i].way[way].offset * in channel_addr_to_dimm()
304 rir[node][channel][i].interleave) & in channel_addr_to_dimm()
309 rir[node][channel][i].way[way].offset * in channel_addr_to_dimm()
311 rir[node][channel][i].interleave) & in channel_addr_to_dimm()
314 rank = rir[node][channel][i].way[way].rank; in channel_addr_to_dimm()
318 base = rir[node][channel][i].limit; in channel_addr_to_dimm()
432 if (rir[node][channel][i].way[way].dimm_rank == rank) { in dimm_to_addr()
433 rlimit = rir[node][channel][i].way[way].rlimit; in dimm_to_addr()
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H A Dmem_addr.h64 extern rir_t rir[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]
H A Dintel_nhm.h293 typedef struct rir { struct