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Searched refs:reg_offset (Results 1 – 24 of 24) sorted by relevance

/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_hw_access.c1393 u32_t reg_offset = 0; in lm_set_mac_in_nig() local
1424 reg_offset = (PORT_ID(pdev)? NIG_REG_LLH1_FUNC_MEM: NIG_REG_LLH0_FUNC_MEM) + 8*offset; in lm_set_mac_in_nig()
1428 …reg_offset = (PORT_ID(pdev)? NIG_REG_P1_LLH_FUNC_MEM2: NIG_REG_P0_LLH_FUNC_MEM2) + 8*(offset - MAX… in lm_set_mac_in_nig()
1434 REG_WR_DMAE_LEN(pdev, reg_offset, wb_data, ARRSIZE(wb_data)); in lm_set_mac_in_nig()
1443 …reg_offset = (PORT_ID(pdev)? NIG_REG_LLH1_FUNC_MEM_ENABLE : NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*offs… in lm_set_mac_in_nig()
1447 …reg_offset = (PORT_ID(pdev)? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE : NIG_REG_P0_LLH_FUNC_MEM2_ENABLE) + … in lm_set_mac_in_nig()
1449 REG_WR(pdev, reg_offset, enable_mac); in lm_set_mac_in_nig()
1636 u32_t reg_wait_verify_val(struct _lm_device_t * pdev, u32_t reg_offset, u32_t excpected_val, u32_t … in reg_wait_verify_val() argument
1645 val=REG_RD(pdev,reg_offset); in reg_wait_verify_val()
1649 val=REG_RD(pdev,reg_offset); in reg_wait_verify_val()
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H A Dlm_power.c64 u32_t reg_offset = 0 ; in init_nwuf_57710() local
161 reg_offset = ( offset / 8 ) - 1 ; // 0 - 15 in init_nwuf_57710()
162 val = (reg_offset*sizeof(u64_t)) ; in init_nwuf_57710()
H A Dlm_hw_attn.c205 u32_t reg_offset; /* the register offset */ in disable_blocks_attention() member
440 offset = init_mask_values_arr[mask_idx].reg_offset; in disable_blocks_attention()
/titanic_50/usr/src/uts/sun4u/io/i2c/clients/
H A Dpca9556.c183 int reg_offset, num_of_ports; in pca9556_resume() local
203 reg_offset = 2; in pca9556_resume()
206 reg_offset = 1; in pca9556_resume()
235 reg = reg + reg_offset; in pca9556_resume()
420 int reg_offset, num_of_ports; in pca9556_suspend() local
445 reg_offset = 2; in pca9556_suspend()
448 reg_offset = 1; in pca9556_suspend()
500 reg = reg + reg_offset; in pca9556_suspend()
/titanic_50/usr/src/uts/common/io/chxge/com/
H A Despi.c50 int ch_addr, int reg_offset, u32 wr_data) in tricn_write() argument
55 V_REGISTER_OFFSET(reg_offset) | in tricn_write()
72 int ch_addr, int reg_offset, u8 *rd_data)
78 V_REGISTER_OFFSET(reg_offset) |
/titanic_50/usr/src/uts/sun4u/io/
H A Dpic16f747.c375 RF_IND_ADDR, pic_nodes[node].reg_offset); in pic_ioctl()
399 RF_IND_ADDR, pic_nodes[node].reg_offset); in pic_ioctl()
415 RF_IND_ADDR, pic_nodes[node].reg_offset); in pic_ioctl()
/titanic_50/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_mbx.c597 u32 reg_offset = (vf_number < 32) ? 0 : 1; in ixgbe_check_for_rst_pf() local
606 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset)); in ixgbe_check_for_rst_pf()
611 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset)); in ixgbe_check_for_rst_pf()
619 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift)); in ixgbe_check_for_rst_pf()
/titanic_50/usr/src/uts/sun4u/sys/
H A Dpic16f747.h109 uint8_t reg_offset; /* indirect register offset */ member
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/
H A Dlm.h1202 u32_t reg_offset,
1209 u32_t reg_offset,
1217 u32_t reg_offset,
1224 u32_t reg_offset,
H A Dlm5710.h4081 static __inline u32_t _reg_rd(struct _lm_device_t * pdev, u32_t reg_offset) in _reg_rd() argument
4084 LM_BAR_RD32_OFFSET(pdev, BAR_0, reg_offset, &val); in _reg_rd()
4130 static __inline u32_t _reg_rd(struct _lm_device_t * pdev, u32_t reg_offset) in _reg_rd() argument
4134 LM_BAR_RD32_OFFSET(pdev, BAR_0, reg_offset, &val); in _reg_rd()
4135 LOG_REG_RD(pdev, (reg_offset), val); in _reg_rd()
4142 static __inline u32_t _vf_reg_rd(struct _lm_device_t * pdev, u32_t reg_offset) in _vf_reg_rd() argument
4145 LM_BAR_RD32_OFFSET(pdev, BAR_0, reg_offset, &val); in _vf_reg_rd()
4146 LOG_REG_RD(pdev, (reg_offset), val); in _vf_reg_rd()
4171 static __inline u32_t _reg_rd(struct _lm_device_t * pdev, u32_t reg_offset) in _reg_rd() argument
4175 LM_BAR_RD32_OFFSET(pdev, BAR_0, reg_offset, &val); in _reg_rd()
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/titanic_50/usr/src/uts/common/io/nxge/
H A Dnxge_hw.c879 uint64_t reg_offset; in nxge_rxdma_channel_put64() local
889 reg_offset = reg_base + DMC_OFFSET(channel); in nxge_rxdma_channel_put64()
890 NXGE_PIO_WRITE64(handle, reg_addrp, reg_offset, reg_data); in nxge_rxdma_channel_put64()
900 uint64_t reg_offset; in nxge_rxdma_channel_get64() local
910 reg_offset = reg_base + DMC_OFFSET(channel); in nxge_rxdma_channel_get64()
914 return (NXGE_PIO_READ64(handle, reg_addrp, reg_offset)); in nxge_rxdma_channel_get64()
/titanic_50/usr/src/cmd/fm/modules/common/fabric-xlate/
H A Dfabric-xlate.h140 uint32_t reg_offset; /* sts reg for ereport table offset */ member
H A Dfx_subr.c192 ((uint32_t)data + tbl->reg_offset)); in fab_send_erpt()
194 reg = *((uint32_t *)((uint32_t)data + tbl->reg_offset)); in fab_send_erpt()
H A Dfx_fabric.c835 fab_master_err_tbl[n].reg_offset = offsetof(fab_data_t, reg); \
/titanic_50/usr/src/uts/i86pc/io/gfx_private/
H A Dgfxp_vgatext.c331 off_t reg_offset; in gfxp_vgatext_attach() local
370 &reg_offset); in gfxp_vgatext_attach()
392 &reg_offset); in gfxp_vgatext_attach()
421 (caddr_t *)&softc->regs.addr, reg_offset, VGA_REG_SIZE, in gfxp_vgatext_attach()
/titanic_50/usr/src/uts/intel/io/vgatext/
H A Dvgatext.c441 off_t reg_offset; in vgatext_attach() local
491 &reg_offset); in vgatext_attach()
511 &reg_offset); in vgatext_attach()
539 (caddr_t *)&softc->regs.addr, reg_offset, VGA_REG_SIZE, in vgatext_attach()
/titanic_50/usr/src/uts/sun4u/daktari/io/
H A Dhpc3130_dak.c763 char *reg_offset; in hpc3130_do_attach() local
876 reg_offset = s; in hpc3130_do_attach()
884 j = hpc3130_atoi(reg_offset); in hpc3130_do_attach()
914 hpc3130_atoi(reg_offset); in hpc3130_do_attach()
932 ste->callback_info.offset = hpc3130_atoi(reg_offset); in hpc3130_do_attach()
/titanic_50/usr/src/uts/common/io/arn/
H A Darn_main.c250 arn_iowrite32(struct ath_hal *ah, uint32_t reg_offset, uint32_t val) in arn_iowrite32() argument
256 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset)), val); in arn_iowrite32()
260 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset)), val); in arn_iowrite32()
265 arn_ioread32(struct ath_hal *ah, uint32_t reg_offset) in arn_ioread32() argument
272 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset))); in arn_ioread32()
276 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset))); in arn_ioread32()
H A Darn_core.h1012 arn_iowrite32(struct ath_hal *ah, uint32_t reg_offset, uint32_t val);
1014 arn_ioread32(struct ath_hal *ah, uint32_t reg_offset);
/titanic_50/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c3003 pcicfg_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) in pcicfg_update_reg_prop() argument
3039 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset); in pcicfg_update_reg_prop()
3041 if (reg_offset == PCI_CONF_ROM) { in pcicfg_update_reg_prop()
3070 DEBUG3("updating BAR@off %x with %x,%x\n", reg_offset, hiword, size); in pcicfg_update_reg_prop()
3085 uint32_t base, uint32_t base_hi, uint_t reg_offset) in pcicfg_update_assigned_prop_value() argument
3118 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset); in pcicfg_update_assigned_prop_value()
3122 if (reg_offset == PCI_CONF_ROM) { in pcicfg_update_assigned_prop_value()
3152 DEBUG3("updating BAR@off %x with %x,%x\n", reg_offset, hiword, size); in pcicfg_update_assigned_prop_value()
/titanic_50/usr/src/uts/common/io/e1000api/
H A De1000_82575.c2277 u32 reg_val, reg_offset; in e1000_vmdq_set_anti_spoofing_pf() local
2281 reg_offset = E1000_DTXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2285 reg_offset = E1000_TXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2291 reg_val = E1000_READ_REG(hw, reg_offset); in e1000_vmdq_set_anti_spoofing_pf()
2303 E1000_WRITE_REG(hw, reg_offset, reg_val); in e1000_vmdq_set_anti_spoofing_pf()
/titanic_50/usr/src/uts/sun4/io/
H A Dpcicfg.c3178 pcicfg_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) in pcicfg_update_reg_prop() argument
3214 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset); in pcicfg_update_reg_prop()
3216 if (reg_offset == PCI_CONF_ROM) { in pcicfg_update_reg_prop()
3305 uint32_t base, uint32_t base_hi, uint_t reg_offset) in pcicfg_update_assigned_prop_value() argument
3338 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset); in pcicfg_update_assigned_prop_value()
3342 if (reg_offset == PCI_CONF_ROM) { in pcicfg_update_assigned_prop_value()
3373 DEBUG3("updating BAR@off %x with %x,%x\n", reg_offset, hiword, size); in pcicfg_update_assigned_prop_value()
/titanic_50/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c203 uint_t reg_offset);
3503 cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) argument
3539 reg_offset);
3541 if (reg_offset == PCI_CONF_ROM) {
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/
H A Decore_sp_verbs.c1095 u32 reg_offset = PORT_ID(pdev) ? NIG_REG_LLH1_FUNC_MEM : in ecore_set_mac_in_nig() local
1109 reg_offset += 8*index; in ecore_set_mac_in_nig()
1115 REG_WR_DMAE_LEN(pdev, reg_offset, wb_data, 2); in ecore_set_mac_in_nig()