Searched refs:reg_begin (Results 1 – 5 of 5) sorted by relevance
217 uint64_t reg_begin, reg_end, reg_sz; in px_xlate_reg() local221 reg_begin = (uint64_t)px_rp->pci_phys_mid << 32 | px_rp->pci_phys_low; in px_xlate_reg()224 if (reg_begin > PCI_CONF_HDR_SIZE) in px_xlate_reg()228 reg_begin += px_rp->pci_phys_hi << 4; in px_xlate_reg()230 reg_end = reg_begin + reg_sz - 1; in px_xlate_reg()242 if (reg_begin >= rng_begin && reg_end <= rng_end) in px_xlate_reg()248 addr = reg_begin - rng_begin + ((uint64_t)rng_p->parent_high << 32 | in px_xlate_reg()
52 extern int px_search_ranges(px_t *px_p, uint32_t space_type, uint32_t reg_begin,
195 uint32_t reg_end, reg_begin = pcmu_rp->pci_phys_low; in pcmu_xlate_reg() local201 if (reg_begin > PCI_CONF_HDR_SIZE) { in pcmu_xlate_reg()205 reg_begin += pcmu_rp->pci_phys_hi; in pcmu_xlate_reg()207 reg_end = reg_begin + sz - 1; in pcmu_xlate_reg()219 if (reg_begin >= rng_begin && reg_end <= rng_end) { in pcmu_xlate_reg()227 new_rp->regspec_addr = reg_begin - rng_begin + rng_p->parent_low; in pcmu_xlate_reg()
218 uint32_t reg_end, reg_begin = pci_rp->pci_phys_low; in pci_xlate_reg() local224 if (reg_begin > PCI_CONF_HDR_SIZE) in pci_xlate_reg()227 reg_begin += pci_rp->pci_phys_hi; in pci_xlate_reg()229 reg_end = reg_begin + sz - 1; in pci_xlate_reg()240 if (reg_begin >= rng_begin && reg_end <= rng_end) in pci_xlate_reg()246 new_rp->regspec_addr = reg_begin - rng_begin + rng_p->parent_low; in pci_xlate_reg()
378 uint32_t reg_begin, rng_begin; in niumx_map() local428 reg_begin = reg_p->addr_low; in niumx_map()430 if (reg_begin < rng_begin || (reg_begin + (reg_p->size_low - 1)) > in niumx_map()438 p_regspec.regspec_addr = reg_begin - rng_begin + rng_p->parent_lo; in niumx_map()