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Searched refs:reg32 (Results 1 – 8 of 8) sorted by relevance

/titanic_50/usr/src/uts/common/io/arn/
H A Darn_phy.c44 uint32_t reg32 = 0; in ath9k_hw_set_channel() local
98 reg32 = in ath9k_hw_set_channel()
102 REG_WRITE(ah, AR_PHY(0x37), reg32); in ath9k_hw_set_channel()
116 uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ath9k_hw_ar9280_set_channel() local
123 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ath9k_hw_ar9280_set_channel()
124 reg32 &= 0xc0000000; in ath9k_hw_ar9280_set_channel()
169 reg32 = reg32 | in ath9k_hw_ar9280_set_channel()
173 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ath9k_hw_ar9280_set_channel()
183 ath9k_phy_modify_rx_buffer(uint32_t *rfBuf, uint32_t reg32, in ath9k_phy_modify_rx_buffer() argument
189 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); in ath9k_phy_modify_rx_buffer()
H A Darn_eeprom.c1042 uint32_t reg32, regOffset, regChainOffset; in ath9k_hw_set_def_power_cal_table() local
1124 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | in ath9k_hw_set_def_power_cal_table()
1128 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_def_power_cal_table()
1133 reg32)); in ath9k_hw_set_def_power_cal_table()
1170 uint32_t reg32, regOffset, regChainOffset; in ath9k_hw_set_4k_power_cal_table() local
1240 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | in ath9k_hw_set_4k_power_cal_table()
1244 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_4k_power_cal_table()
1249 reg32)); in ath9k_hw_set_4k_power_cal_table()
/titanic_50/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_api.c13534 uint32_t *reg32; in ql_24xx_binary_fw_dump() local
13577 reg32 = (uint32_t *)((caddr_t)ha->iobase + 0xF0); in ql_24xx_binary_fw_dump()
13578 WRT_REG_DWORD(ha, reg32, 0xB0000000); in ql_24xx_binary_fw_dump()
13579 reg32 = (uint32_t *)((caddr_t)ha->iobase + 0xFC); in ql_24xx_binary_fw_dump()
13580 fw->shadow_reg[0] = RD_REG_DWORD(ha, reg32); in ql_24xx_binary_fw_dump()
13582 reg32 = (uint32_t *)((caddr_t)ha->iobase + 0xF0); in ql_24xx_binary_fw_dump()
13583 WRT_REG_DWORD(ha, reg32, 0xB0100000); in ql_24xx_binary_fw_dump()
13584 reg32 = (uint32_t *)((caddr_t)ha->iobase + 0xFC); in ql_24xx_binary_fw_dump()
13585 fw->shadow_reg[1] = RD_REG_DWORD(ha, reg32); in ql_24xx_binary_fw_dump()
13587 reg32 = (uint32_t *)((caddr_t)ha->iobase + 0xF0); in ql_24xx_binary_fw_dump()
[all …]
/titanic_50/usr/src/uts/common/io/pciex/
H A Dpcie.c1360 uint32_t reg32, tmp32; in pcie_enable_errors() local
1408 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_UCE_SERV)) != in pcie_enable_errors()
1414 reg32); in pcie_enable_errors()
1418 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_UCE_MASK)) != in pcie_enable_errors()
1424 reg32); in pcie_enable_errors()
1428 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_CTL)) != in pcie_enable_errors()
1430 tmp32 = reg32 | pcie_ecrc_value; in pcie_enable_errors()
1432 PCIE_DBG_AER(dip, bus_p, "AER CTL", 32, PCIE_AER_CTL, reg32); in pcie_enable_errors()
1440 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_SUCE_SERV)) != in pcie_enable_errors()
1446 reg32); in pcie_enable_errors()
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/titanic_50/usr/src/uts/common/os/
H A Dbrand.c511 brand_common_reg32_t reg32; in brand_solaris_cmd() local
513 if (copyin((void *)arg1, &reg32, sizeof (reg32)) != 0) in brand_solaris_cmd()
515 reg.sbr_version = reg32.sbr_version; in brand_solaris_cmd()
516 reg.sbr_handler = (caddr_t)(uintptr_t)reg32.sbr_handler; in brand_solaris_cmd()
/titanic_50/usr/src/cmd/ptools/pflags/
H A Dpflags.c572 prgregset32_t reg32; in dumpregs32() local
575 prgregset_n_to_32(reg, reg32); in dumpregs32()
579 regname32[i], reg32[i]); in dumpregs32()
/titanic_50/usr/src/uts/common/io/sata/adapters/nv_sata/
H A Dnv_sata.c576 uint32_t reg32; in nv_attach() local
829 reg32 = pci_config_get32(pci_conf_handle, NV_SATA_CFG_20); in nv_attach()
831 if ((reg32 & NV_BAR5_SPACE_EN) != NV_BAR5_SPACE_EN) { in nv_attach()
833 reg32 | NV_BAR5_SPACE_EN); in nv_attach()
2559 uint32_t reg32; in mcp5x_reg_init() local
2566 reg32 = pci_config_get32(pci_conf_handle, in mcp5x_reg_init()
2569 reg32 | NV_40BIT_PRD); in mcp5x_reg_init()
2579 reg32 = pci_config_get32(pci_conf_handle, in mcp5x_reg_init()
2582 reg32 & 0xffff0000); in mcp5x_reg_init()
2602 uint32_t reg32; in ck804_reg_init() local
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/titanic_50/usr/src/grub/grub-0.97/netboot/
H A Dtg3.c405 uint32_t reg32, phy9_orig; in tg3_phy_reset_5703_4_5() local
419 tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32); in tg3_phy_reset_5703_4_5()
420 reg32 |= 0x3000; in tg3_phy_reset_5703_4_5()
421 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
459 tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32); in tg3_phy_reset_5703_4_5()
460 reg32 &= ~0x3000; in tg3_phy_reset_5703_4_5()
461 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()