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Searched refs:rd32 (Results 1 – 5 of 5) sorted by relevance

/titanic_50/usr/src/uts/common/io/i40e/
H A Di40e_osdep.h174 #define rd32(hw, reg) \ macro
178 #define I40E_READ_REG rd32
185 #define i40e_flush(hw) (void) rd32(hw, I40E_GLGEN_STAT)
/titanic_50/usr/src/uts/common/io/i40e/core/
H A Di40e_lan_hmc.c136 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
139 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ); in i40e_init_lan_hmc()
156 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
162 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ); in i40e_init_lan_hmc()
179 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX); in i40e_init_lan_hmc()
185 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ); in i40e_init_lan_hmc()
202 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX); in i40e_init_lan_hmc()
208 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ); in i40e_init_lan_hmc()
H A Di40e_adminq.c314 reg = rd32(hw, hw->aq.asq.bal); in i40e_config_asq_regs()
346 reg = rd32(hw, hw->aq.arq.bal); in i40e_config_arq_regs()
701 while (rd32(hw, hw->aq.asq.head) != ntc) { in i40e_clean_asq()
703 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in i40e_clean_asq()
738 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in i40e_asq_done()
778 val = rd32(hw, hw->aq.asq.head); in i40e_asq_send_command()
998 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); in i40e_clean_arq_element()
H A Di40e_common.c376 return !!(rd32(hw, hw->aq.asq.len) & in i40e_check_asq_alive()
987 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) in i40e_init_shared_code()
990 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> in i40e_init_shared_code()
992 func_rid = rd32(hw, I40E_PF_FUNC_RID); in i40e_init_shared_code()
1130 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_pre_tx_queue_cfg()
1275 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & in i40e_pf_reset()
1282 reg = rd32(hw, I40E_GLGEN_RSTAT); in i40e_pf_reset()
1294 reg = rd32(hw, I40E_GLNVM_ULD); in i40e_pf_reset()
1315 reg = rd32(hw, I40E_PFGEN_CTRL); in i40e_pf_reset()
1319 reg = rd32(hw, I40E_PFGEN_CTRL); in i40e_pf_reset()
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H A Di40e_nvm.c71 gens = rd32(hw, I40E_GLNVM_GENS); in i40e_init_nvm()
78 fla = rd32(hw, I40E_GLNVM_FLA); in i40e_init_nvm()
115 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_acquire_nvm()
130 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_acquire_nvm()
198 srctl = rd32(hw, I40E_GLNVM_SRCTL); in i40e_poll_sr_srctl_done_bit()
291 sr_reg = rd32(hw, I40E_GLNVM_SRDATA); in i40e_read_nvm_word_srctl()
1221 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_nvmupd_state_writing()