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Searched refs:r15 (Results 1 – 25 of 29) sorted by relevance

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/titanic_50/usr/src/uts/i86pc/ml/
H A Dsyscall_asm_amd64.s178 movq %gs:CPU_RTMP_RSP, %r15 /* grab the intr. stack pointer */ ;\
179 pushq (%r15) /* push the return address */
183 movq %r15, %gs:CPU_RTMP_R15 /* save %r15 */ ;\
184 movq %gs:CPU_THREAD, %r15 /* load the thread pointer */ ;\
185 movq T_STACK(%r15), %rsp /* switch to the kernel stack */ ;\
191 movq T_LWP(%r15), %r15 /* load the lwp pointer */ ;\
192 pushq %r15 /* push the lwp pointer */ ;\
193 movq LWP_PROCP(%r15), %r15 /* load the proc pointer */ ;\
194 movq P_BRAND(%r15), %r15 /* load the brand pointer */ ;\
195 movq B_MACHOPS(%r15), %r15 /* load the machops pointer */ ;\
[all …]
H A Dbios_call_src.s94 movq %r15, save_r15
192 xorq %r15, %r15
475 movq save_r15, %r15
H A Dlocore.s1136 movq %r15, %rsi
1176 movq %r15, CPUC_DTRACE_ILLVAL(%rax)
1499 movq %gs:CPU_THREAD, %r15
1500 movq T_STACK(%r15), %rsp /* switch to the thread stack */
1513 movq %gs:CPU_THREAD, %r15
1514 movq T_STACK(%r15), %rsp /* switch to the thread stack */
1548 cmpq %r15, P_AGENTTP(%rdx)
H A Dfb_swtch_src.s152 xorq %r15, %r15
H A Dcpr_wakecode.s124 movq %r15, WC_R15(%rdi)
780 movq WC_R15(%rbx), %r15
/titanic_50/usr/src/uts/intel/kdi/amd64/
H A Dkdi_asm.s124 movq %r15, REG_OFF(KDIREG_R15)(base); \
146 movq REG_OFF(KDIREG_R15)(%rdi), %r15; \
176 leaq kdi_drreg(%rip), %r15; \
178 movq DR_CTL(%r15), %rsi; \
186 movq DRADDR_OFF(0)(%r15), %rsi; \
189 movq DRADDR_OFF(1)(%r15), %rsi; \
192 movq DRADDR_OFF(2)(%r15), %rsi; \
195 movq DRADDR_OFF(3)(%r15), %rsi; \
508 movq %rax, %r15 /* save cpusave area ptr */
511 movq %rax, KRS_DRCTL(%r15)
[all …]
/titanic_50/usr/src/uts/i86xpv/sys/
H A Dmachprivregs.h340 pushq %r15; \
343 movq %gs:CPU_THREAD, %r15; \
344 movq T_LWP(%r15), %r15; \
345 testb $0x1, PCB_RUPDATE(%r15); \
348 1: popq %r15
/titanic_50/usr/src/common/bignum/amd64/
H A Dbignum_amd64_asm.s443 pushq %r15
450 movq %rdx, %r15 / tlen = len
451 decq %r15 / tlen = len - 1
454 movq %r15, %rdx / arg3 = tlen
457 movq %rax, 0(%r13, %r15, 8) / tr[tlen] = cy
459 decq %r15 / --tlen
466 movq %r15, %rdx / arg3 = tlen
469 movq %rax, 0(%r13, %r15, 8) / tr[tlen] = cy
/titanic_50/usr/src/lib/libc/amd64/unwind/
H A Dunwind_frame.s55 movq %r15,120(%rdi)
78 movq 120(%rax),%r15
/titanic_50/usr/src/cmd/mdb/intel/amd64/libstand/
H A Dsetjmp.s76 movq %r15, 32(%rdi)
108 movq 32(%rdi), %r15
/titanic_50/usr/src/lib/libc/amd64/gen/
H A Dsetjmp.s61 movq %r15, 32(%rdi)
83 movq 32(%rdi), %r15
/titanic_50/usr/src/uts/intel/ia32/ml/
H A Dswtch.s98 movq %r15, T_R15(thread_t); \
123 movq T_R15(scratch_reg), %r15
249 LOADCPU(%r15) /* %r15 = CPU */
250 movq CPU_THREAD(%r15), %r13 /* %r13 = curthread */
281 movq CPU_IDLE_THREAD(%r15), %rax /* idle thread pointer */
287 movq %rax, CPU_THREAD(%r15)
H A Dfloat.s234 pushq %r15
241 movq $4, %r15
249 subq $1, %r15
252 popq %r15
H A Dexception.s174 movq %rax, %r15 /* %db6 -> %r15 */
179 movq %db6, %r15
1068 movq %gs:CPU_VCPU_INFO, %r15
1069 movq VCPU_INFO_ARCH_CR2(%r15), %r15 /* vcpu[].arch.cr2 */
1078 movq %cr2, %r15
H A Dmodstubs.s176 movq %r15, (%rsp) /* (caller saved) */
177 movq %rax, %r15 /* stash the fcnname_info pointer */
188 movq %r15, %rdi
192 movq 0x18(%r15), %rax
222 call *(%r15) /* call the stub fn(arg, ..) */
226 movq %r15, %rdi
231 popq %r15
/titanic_50/usr/src/common/crypto/sha2/amd64/
H A Dsha512-x86_64.pl89 ($T1,$a0,$a1,$a2)=("%r12","%r13","%r14","%r15");
232 push %r15
313 pop %r15
/titanic_50/usr/src/uts/common/xen/public/arch-x86/
H A Dxen-x86_64.h157 uint64_t r15; member
225 unsigned long r15; member
/titanic_50/usr/src/common/crypto/md5/amd64/
H A Dmd5_amd64.pl178 push %r15
294 pop %r15
/titanic_50/usr/src/uts/intel/amd64/sys/
H A Dprivregs.h152 movq %r15, REGOFF_R15(%rsp); \
196 movq REGOFF_R15(%rsp), %r15
/titanic_50/usr/src/uts/intel/brand/common/
H A Dbrand_asm.h81 #define SCR_REG %r15
/titanic_50/usr/src/lib/libc/amd64/threads/
H A Dasm_subr.s125 movq %r15, REGOFF(REG_R15) (%rsp)
/titanic_50/usr/src/lib/brand/shared/brand/amd64/
H A Dhandler.s79 movq %r15, EH_LOCALS_GREG(REG_R15)(%rbp)
/titanic_50/usr/src/cmd/sgs/libconv/common/
H A Ddwarf.msg188 @ MSG_REG_R15 "r15"
H A Dcorenote.msg305 @ MSG_REG_SPARC_O7 "[ r15/o7 ]"
332 @ MSG_REG_AMD64_R15 "[ r15 ]"
/titanic_50/usr/src/uts/i86xpv/ml/
H A Dpanic_asm.s127 movq %r15, REGOFF_R15(%rsp)

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